# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-dp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip DW DisplayPort Transmitter

maintainers:
  - Andy Yan <andy.yan@rock-chips.com>

description: |
  The Rockchip RK3588 SoC integrates the Synopsys DesignWare DPTX controller
  which is compliant with the DisplayPort Specification Version 1.4 with the
  following features:

  * DisplayPort 1.4a
  * Main Link: 1/2/4 lanes
  * Main Link Support 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps
  * AUX channel 1Mbps
  * Single Stream Transport(SST)
  * Multistream Transport (MST)
  * Type-C support (alternate mode)
  * HDCP 2.2, HDCP 1.3
  * Supports up to 8/10 bits per color component
  * Supports RBG, YCbCr4:4:4, YCbCr4:2:2, YCbCr4:2:0
  * Pixel clock up to 594MHz
  * I2S, SPDIF audio interface

allOf:
  - $ref: /schemas/sound/dai-common.yaml#

properties:
  compatible:
    enum:
      - rockchip,rk3588-dp

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: Peripheral/APB bus clock
      - description: DisplayPort AUX clock
      - description: HDCP clock
      - description: I2S interface clock
      - description: SPDIF interfce clock

  clock-names:
    items:
      - const: apb
      - const: aux
      - const: hdcp
      - const: i2s
      - const: spdif

  phys:
    maxItems: 1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: Video port for RGB/YUV input.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: Video port for DP output.

    required:
      - port@0
      - port@1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  "#sound-dai-cells":
    const: 0

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - interrupts
  - phys
  - ports
  - resets

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/rockchip,rk3588-cru.h>
    #include <dt-bindings/phy/phy.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/power/rk3588-power.h>
    #include <dt-bindings/reset/rockchip,rk3588-cru.h>

    soc {
      #address-cells = <2>;
      #size-cells = <2>;

      dp@fde50000 {
        compatible = "rockchip,rk3588-dp";
        reg = <0x0 0xfde50000 0x0 0x4000>;
        interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>;
        clocks = <&cru PCLK_DP0>, <&cru CLK_AUX16M_0>,
        <&cru CLK_DP0>, <&cru MCLK_I2S4_8CH_TX>,
        <&cru MCLK_SPDIF2_DP0>;
        clock-names = "apb", "aux", "hdcp", "i2s", "spdif";
        assigned-clocks = <&cru CLK_AUX16M_0>;
        assigned-clock-rates = <16000000>;
        resets = <&cru SRST_DP0>;
        phys = <&usbdp_phy0 PHY_TYPE_DP>;
        power-domains = <&power RK3588_PD_VO0>;
        #sound-dai-cells = <0>;


        ports {
          #address-cells = <1>;
          #size-cells = <0>;

          port@0 {
            reg = <0>;

            dp0_in_vp2: endpoint {
              remote-endpoint = <&vp2_out_dp0>;
            };
          };

          port@1 {
            reg = <1>;

            dp0_out_con0: endpoint {
              remote-endpoint = <&dp_con0_in>;
            };
          };
        };
      };
    };
