# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/qcom,wcd937x-sdw.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SoundWire Slave devices on WCD9370/WCD9375

maintainers:
  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

description: |
  Qualcomm WCD9370/WCD9375 Codec is a standalone Hi-Fi audio codec IC.
  It has RX and TX Soundwire slave devices. This bindings is for the
  slave devices.

properties:
  compatible:
    const: sdw20217010a00

  reg:
    maxItems: 1

  qcom,tx-port-mapping:
    description: |
      Specifies static port mapping between device and host tx ports.
      In the order of the device port index which are adc1_port, adc23_port,
      dmic03_mbhc_port, dmic46_port.
      Supports maximum 4 tx soundwire ports.

      WCD9370 TX Port 1 (ADC1)               <=> SWR2 Port 2
      WCD9370 TX Port 2 (ADC2, 3)            <=> SWR2 Port 2
      WCD9370 TX Port 3 (DMIC0,1,2,3 & MBHC) <=> SWR2 Port 3
      WCD9370 TX Port 4 (DMIC4,5,6,7)        <=> SWR2 Port 4

    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 4
    maxItems: 4
    items:
      enum: [1, 2, 3, 4]

  qcom,rx-port-mapping:
    description: |
      Specifies static port mapping between device and host rx ports.
      In the order of device port index which are hph_port, clsh_port,
      comp_port, lo_port, dsd port.
      Supports maximum 5 rx soundwire ports.

      WCD9370 RX Port 1 (HPH_L/R)       <==>    SWR1 Port 1 (HPH_L/R)
      WCD9370 RX Port 2 (CLSH)          <==>    SWR1 Port 2 (CLSH)
      WCD9370 RX Port 3 (COMP_L/R)      <==>    SWR1 Port 3 (COMP_L/R)
      WCD9370 RX Port 4 (LO)            <==>    SWR1 Port 4 (LO)
      WCD9370 RX Port 5 (DSD_L/R)       <==>    SWR1 Port 5 (DSD)

    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 5
    maxItems: 5
    items:
      enum: [1, 2, 3, 4, 5]

  qcom,tx-channel-mapping:
    description: |
      Specifies static channel mapping between slave and master tx port
      channels.
      In the order of slave port channels which is adc1, adc2, adc3,
      dmic0, dmic1, mbhc, dmic2, dmic3, dmci4, dmic5, dmic6, dmic7.
    $ref: /schemas/types.yaml#/definitions/uint8-array
    minItems: 12
    maxItems: 12
    additionalItems: false
    items:
      enum:
        - 1  # WCD9370_SWRM_CH1
        - 2  # WCD9370_SWRM_CH2
        - 3  # WCD9370_SWRM_CH3
        - 4  # WCD9370_SWRM_CH4

  qcom,rx-channel-mapping:
    description: |
      Specifies static channels mapping between slave and master rx port
      channels.
      In the order of slave port channels, which is
      hph_l, hph_r, clsh, comp_l, comp_r, lo, dsd_r, dsd_l.
    $ref: /schemas/types.yaml#/definitions/uint8-array
    minItems: 8
    maxItems: 8
    additionalItems: false
    items:
      enum:
        - 1  # WCD9370_SWRM_CH1
        - 2  # WCD9370_SWRM_CH2
        - 3  # WCD9370_SWRM_CH3
        - 4  # WCD9370_SWRM_CH4

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    soundwire@3210000 {
        reg = <0x03210000 0x2000>;
        #address-cells = <2>;
        #size-cells = <0>;
        wcd937x_rx: codec@0,4 {
            compatible = "sdw20217010a00";
            reg = <0 4>;
            qcom,rx-port-mapping = <1 2 3 4 5>;
            qcom,rx-channel-mapping = /bits/ 8 <1 2 1 1 2 1 1 2>;
        };
    };

    soundwire@3230000 {
        reg = <0x03230000 0x2000>;
        #address-cells = <2>;
        #size-cells = <0>;
        wcd937x_tx: codec@0,3 {
            compatible = "sdw20217010a00";
            reg = <0 3>;
            qcom,tx-port-mapping = <2 2 3 4>;
            qcom,tx-channel-mapping = /bits/ 8 <1 2 1 1 2 3 3 4 1 2 3 4>;
        };
    };

...