// SPDX-License-Identifier: GPL-2.0-only and MIT

/*
 * Copyright 2024 NXP
 */

lvds0_subsys: bus@56240000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x56240000 0x0 0x56240000 0x10000>;

	qm_lvds0_lis_lpcg: qxp_mipi1_lis_lpcg: clock-controller@56243000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x56243000 0x4>;
		#clock-cells = <1>;
		clock-output-names = "lvds0_lis_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_MIPI_1>;
	};

	qm_lvds0_pwm_lpcg: qxp_mipi1_pwm_lpcg: clock-controller@5624300c {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5624300c 0x4>;
		#clock-cells = <1>;
		clock-output-names = "lvds0_pwm_lpcg_clk",
				     "lvds0_pwm_lpcg_ipg_clk",
				     "lvds0_pwm_lpcg_32k_clk";
		power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
	};

	qm_lvds0_i2c0_lpcg: qxp_mipi1_i2c0_lpcg: clock-controller@56243010 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x56243010 0x4>;
		#clock-cells = <1>;
		clock-output-names = "lvds0_i2c0_lpcg_clk",
				     "lvds0_i2c0_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
	};

	qm_pwm_lvds0: qxp_pwm_mipi_lvds1: pwm@56244000 {
		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
		reg = <0x56244000 0x1000>;
		clock-names = "ipg", "per";
		assigned-clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <24000000>;
		#pwm-cells = <3>;
		power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
		status = "disabled";
	};

	qm_i2c0_lvds0: qxp_i2c0_mipi_lvds1: i2c@56246000 {
		compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
		reg = <0x56246000 0x1000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <8>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <24000000>;
		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
		status = "disabled";
	};
};