// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright 2024 Variscite Ltd. * * Author: Tarang Raval */ /dts-v1/; #include #include #include #include "imx8mp.dtsi" / { model = "Variscite VAR-SOM-MX8M Plus module"; chosen { stdout-path = &uart2; }; gpio-leds { compatible = "gpio-leds"; led-0 { function = LED_FUNCTION_POWER; gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; memory@40000000 { device_type = "memory"; reg = <0x0 0x40000000 0 0xc0000000>, <0x1 0x00000000 0 0xc0000000>; }; reg_usdhc2_vmmc: regulator-usdhc2-vmmc { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; enable-active-high; startup-delay-us = <100>; off-on-delay-us = <12000>; }; reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { compatible = "regulator-gpio"; regulator-name = "VSD_VSEL"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; states = <3300000 0x0 1800000 0x1>; vin-supply = <&ldo5>; }; reg_phy_supply: regulator-phy-supply { compatible = "regulator-fixed"; regulator-name = "phy-supply"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-enable-ramp-delay = <20000>; gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-always-on; }; reg_phy_vddio: regulator-phy-vddio { compatible = "regulator-fixed"; regulator-name = "vddio-1v8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; }; &A53_0 { cpu-supply = <&buck2>; }; &A53_1 { cpu-supply = <&buck2>; }; &A53_2 { cpu-supply = <&buck2>; }; &A53_3 { cpu-supply = <&buck2>; }; &eqos { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos>; /* * The required RGMII TX and RX 2ns delays are implemented directly * in hardware via passive delay elements on the SOM PCB. * No delay configuration is needed in software via PHY driver. */ phy-mode = "rgmii"; phy-handle = <ðphy0>; status = "okay"; mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; ethphy0: ethernet-phy@4 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <4>; reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; reset-deassert-us = <100000>; vddio-supply = <®_phy_vddio>; leds { #address-cells = <1>; #size-cells = <0>; led@0 { reg = <0>; color = ; function = LED_FUNCTION_LAN; linux,default-trigger = "netdev"; }; led@1 { reg = <1>; color = ; function = LED_FUNCTION_LAN; linux,default-trigger = "netdev"; }; }; }; }; }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; pmic@25 { compatible = "nxp,pca9450c"; reg = <0x25>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio5>; interrupts = <4 IRQ_TYPE_LEVEL_LOW>; regulators { buck1: BUCK1 { regulator-name = "BUCK1"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <2187500>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; }; buck2: BUCK2 { regulator-name = "BUCK2"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <2187500>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; nxp,dvs-run-voltage = <950000>; nxp,dvs-standby-voltage = <850000>; }; buck4: BUCK4 { regulator-name = "BUCK4"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; buck5: BUCK5 { regulator-name = "BUCK5"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; buck6: BUCK6 { regulator-name = "BUCK6"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; ldo1: LDO1 { regulator-name = "LDO1"; regulator-min-microvolt = <1600000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; ldo2: LDO2 { regulator-name = "LDO2"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1150000>; regulator-boot-on; regulator-always-on; }; ldo3: LDO3 { regulator-name = "LDO3"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; ldo4: LDO4 { regulator-name = "LDO4"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; }; ldo5: LDO5 { regulator-name = "LDO5"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; }; }; }; }; &i2c3 { clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; /* GPIO expander */ pca9534: gpio@20 { compatible = "nxp,pca9534"; reg = <0x20>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pca9534>; gpio-controller; #gpio-cells = <2>; interrupt-parent = <&gpio1>; interrupts = <15 IRQ_TYPE_EDGE_FALLING>; wakeup-source; usb3-sata-sel-hog { gpio-hog; gpios = <4 0>; output-low; line-name = "usb3_sata_sel"; }; }; }; /* Console */ &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; status = "okay"; }; /* SD-card */ &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; cd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; vmmc-supply = <®_usdhc2_vmmc>; vqmmc-supply = <®_usdhc2_vqmmc>; bus-width = <4>; status = "okay"; }; /* eMMC */ &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; pinctrl-1 = <&pinctrl_usdhc3_100mhz>; pinctrl-2 = <&pinctrl_usdhc3_200mhz>; bus-width = <8>; non-removable; status = "okay"; }; &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; fsl,ext-reset-output; status = "okay"; }; &iomuxc { pinctrl_eqos: eqosgrp { fsl,pins = < MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x10 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x150 >; }; pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MP_IOMUXC_SD1_DATA4__I2C1_SCL 0x400001c2 MX8MP_IOMUXC_SD1_DATA5__I2C1_SDA 0x400001c2 >; }; pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 >; }; pinctrl_pca9534: pca9534grp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0xc0 >; }; pinctrl_pmic: pmicgrp { fsl,pins = < MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1c0 >; }; pinctrl_uart2: uart2grp { fsl,pins = < MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40 >; }; pinctrl_usdhc2_gpio: usdhc2-gpiogrp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x1c4 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0xc0 >; }; pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 >; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 >; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 >; }; pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 >; }; pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { fsl,pins = < MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 >; }; pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = < MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 >; }; pinctrl_wdog: wdoggrp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 >; }; };