// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2025 PHYTEC Messtechnik GmbH
 * Author: Primoz Fiser <primoz.fiser@norik.com>
 */

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>
#include "imx93-pinfunc.h"

&{/} {
	usdhc3_pwrseq: usdhc3-pwrseq {
		compatible = "mmc-pwrseq-simple";
		reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>;
	};
};

&lpuart5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart5>;
	status = "okay";

	bluetooth {
		compatible = "nxp,88w8987-bt";
	};
};

/*
 * NOTE: When uSDHC3 port is multiplexed on GPIO_IO[27:22] pads, it only
 * supports 50 MHz mode, due to introduction of potential variations in
 * trace impedance, drive strength, and timing skew. Refer to i.MX 93
 * Application Processors Data Sheet, Rev. 3, page 60 for more details.
 */
&usdhc3 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wlbt>;
	pinctrl-1 = <&pinctrl_usdhc3_sleep>, <&pinctrl_wlbt>;
	mmc-pwrseq = <&usdhc3_pwrseq>;
	bus-width = <4>;
	keep-power-in-suspend;
	non-removable;
	wakeup-source;
	status = "okay";
};

&iomuxc {
	pinctrl_uart5: uart5grp {
		fsl,pins = <
			MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX	0x31e
			MX93_PAD_DAP_TDI__LPUART5_RX		0x31e
			MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B	0x31e
			MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B	0x31e
		>;
	};

	/* need to config the SION for data and cmd pad, refer to ERR052021 */
	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX93_PAD_GPIO_IO22__USDHC3_CLK		0x179e
			MX93_PAD_SD3_CMD__USDHC3_CMD 		0x4000178e
			MX93_PAD_SD3_DATA0__USDHC3_DATA0	0x4000138e
			MX93_PAD_SD3_DATA1__USDHC3_DATA1	0x4000138e
			MX93_PAD_SD3_DATA2__USDHC3_DATA2	0x4000138e
			MX93_PAD_SD3_DATA3__USDHC3_DATA3	0x4000138e
		>;
	};

	pinctrl_usdhc3_sleep: usdhc3sleepgrp {
		fsl,pins = <
			MX93_PAD_GPIO_IO22__USDHC3_CLK		0x31e
			MX93_PAD_SD3_CMD__USDHC3_CMD 		0x31e
			MX93_PAD_SD3_DATA0__USDHC3_DATA0	0x31e
			MX93_PAD_SD3_DATA1__USDHC3_DATA1	0x31e
			MX93_PAD_SD3_DATA2__USDHC3_DATA2	0x31e
			MX93_PAD_SD3_DATA3__USDHC3_DATA3	0x31e
		>;
	};

	pinctrl_wlbt: wlbtgrp {
		fsl,pins = <
			MX93_PAD_CCM_CLKO2__GPIO3_IO27		0x31e	/* WAKE_DEV */
			MX93_PAD_CCM_CLKO3__GPIO4_IO28		0x31e	/* WAKE_HOST */
			MX93_PAD_CCM_CLKO4__GPIO4_IO29		0x31e	/* PDn */
		>;
	};
};