// SPDX-License-Identifier: (GPL-2.0-or-later OR X11)
/*
 * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
 * D-82229 Seefeld, Germany.
 * Author: Alexander Stein
 */

/ {
	memory@80000000 {
		device_type = "memory";
		reg = <0x00000000 0x80000000 0 0x40000000>;
	};

	reg_1v8: regulator-1v8 {
		compatible = "regulator-fixed";
		regulator-name = "V_1V8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	reg_3v3: regulator-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "V_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/*
		 * global autoconfigured region for contiguous allocations
		 * must not exceed memory size and region
		 */
		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0 0x20000000>;
			alloc-ranges = <0 0x96000000 0 0x30000000>;
			linux,cma-default;
		};
	};
};

/* TQMa8Xx only uses industrial grade, reduce trip points accordingly */
&cpu_alert0 {
	temperature = <95000>;
};

&cpu_crit0 {
	temperature = <100000>;
};
/* end of temperature grade adjustments */

&flexspi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexspi0>;
	status = "okay";

	flash0: flash@0 {
		reg = <0>;
		compatible = "jedec,spi-nor";
		spi-max-frequency = <66000000>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;
		};
	};
};

/* TODO GPU */

&i2c1 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_lpi2c1>;
	pinctrl-1 = <&pinctrl_lpi2c1gpio>;
	scl-gpios = <&lsio_gpio1 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&lsio_gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	se97: temperature-sensor@1b {
		compatible = "nxp,se97b", "jedec,jc-42.4-temp";
		reg = <0x1b>;
	};

	pcf85063: rtc@51 {
		compatible = "nxp,pcf85063a";
		reg = <0x51>;
		quartz-load-femtofarads = <7000>;
	};

	at24c02: eeprom@53 {
		compatible = "nxp,se97b", "atmel,24c02";
		reg = <0x53>;
		pagesize = <16>;
		read-only;
		vcc-supply = <&reg_3v3>;
	};

	m24c64: eeprom@57 {
		compatible = "atmel,24c64";
		reg = <0x57>;
		pagesize = <32>;
		vcc-supply = <&reg_3v3>;
	};
};

&mu_m0 {
	status = "okay";
};

&mu1_m0 {
	status = "okay";
};

&thermal_zones {
	pmic_thermal: pmic-thermal {
		polling-delay-passive = <250>;
		polling-delay = <2000>;
		thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;

		trips {
			pmic_alert0: trip0 {
				temperature = <110000>;
				hysteresis = <2000>;
				type = "passive";
			};

			pmic_crit0: trip1 {
				temperature = <125000>;
				hysteresis = <2000>;
				type = "critical";
			};
		};

		cooling-maps {
			map0 {
				trip = <&pmic_alert0>;
				cooling-device =
					<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
					<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
					<&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
					<&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
			};
		};
	};
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	vqmmc-supply = <&reg_1v8>;
	vmmc-supply = <&reg_3v3>;
	bus-width = <8>;
	non-removable;
	no-sdio;
	no-sd;
	status = "okay";
};

&vpu {
	compatible = "nxp,imx8qxp-vpu";
	status = "okay";
};

&vpu_core0 {
	memory-region = <&decoder_boot>, <&decoder_rpc>;
	status = "okay";
};

&vpu_core1 {
	memory-region = <&encoder_boot>, <&encoder_rpc>;
	status = "okay";
};

&iomuxc {
	pinctrl_flexspi0: flexspi0grp {
		fsl,pins = <
			IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0	0x0600004d
			IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1	0x0600004d
			IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2	0x0600004d
			IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3	0x0600004d
			IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS	0x0600004d
			IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B	0x0600004d
			IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK	0x0600004d
			IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK	0x0600004d
			IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0	0x0600004d
			IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1	0x0600004d
			IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2	0x0600004d
			IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3	0x0600004d
			IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS	0x0600004d
			IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B	0x0600004d
			IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B	0x0600004d
		>;
	};

	pinctrl_lpi2c1: lpi2c1grp {
		fsl,pins = <
			IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL	0x06000021
			IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA	0x06000021
		>;
	};

	pinctrl_lpi2c1gpio: lpi2c1gpiogrp {
		fsl,pins = <
			IMX8QXP_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27	0x06000021
			IMX8QXP_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28	0x06000021
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK	0x06000041
			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD	0x00000021
			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
			IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
			IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
			IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
			IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
			IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
		fsl,pins = <
			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK	0x06000040
			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD	0x00000020
			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
			IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
			IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
			IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
			IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
			IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000040
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
		fsl,pins = <
			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK	0x06000040
			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD	0x00000020
			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
			IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
			IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
			IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
			IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
			IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000040
		>;
	};
};