// SPDX-License-Identifier: GPL-2.0-only OR MIT #include #include #include #include #include / { compatible = "mediatek,mt7988a"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a73"; reg = <0x0>; device_type = "cpu"; enable-method = "psci"; clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, <&topckgen CLK_TOP_XTAL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@1 { compatible = "arm,cortex-a73"; reg = <0x1>; device_type = "cpu"; enable-method = "psci"; clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, <&topckgen CLK_TOP_XTAL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@2 { compatible = "arm,cortex-a73"; reg = <0x2>; device_type = "cpu"; enable-method = "psci"; clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, <&topckgen CLK_TOP_XTAL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster0_opp>; }; cpu3: cpu@3 { compatible = "arm,cortex-a73"; reg = <0x3>; device_type = "cpu"; enable-method = "psci"; clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, <&topckgen CLK_TOP_XTAL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster0_opp>; }; cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared; opp-800000000 { opp-hz = /bits/ 64 <800000000>; opp-microvolt = <850000>; }; opp-1100000000 { opp-hz = /bits/ 64 <1100000000>; opp-microvolt = <850000>; }; opp-1500000000 { opp-hz = /bits/ 64 <1500000000>; opp-microvolt = <850000>; }; opp-1800000000 { opp-hz = /bits/ 64 <1800000000>; opp-microvolt = <900000>; }; }; }; oscillator-40m { compatible = "fixed-clock"; clock-frequency = <40000000>; #clock-cells = <0>; clock-output-names = "clkxtal"; }; pmu { compatible = "arm,cortex-a73-pmu"; interrupt-parent = <&gic>; interrupts = ; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */ secmon@43000000 { reg = <0 0x43000000 0 0x50000>; no-map; }; }; soc { compatible = "simple-bus"; ranges; #address-cells = <2>; #size-cells = <2>; gic: interrupt-controller@c000000 { compatible = "arm,gic-v3"; reg = <0 0x0c000000 0 0x40000>, /* GICD */ <0 0x0c080000 0 0x200000>, /* GICR */ <0 0x0c400000 0 0x2000>, /* GICC */ <0 0x0c410000 0 0x1000>, /* GICH */ <0 0x0c420000 0 0x2000>; /* GICV */ interrupt-parent = <&gic>; interrupts = ; interrupt-controller; #interrupt-cells = <3>; }; infracfg: clock-controller@10001000 { compatible = "mediatek,mt7988-infracfg", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; topckgen: clock-controller@1001b000 { compatible = "mediatek,mt7988-topckgen", "syscon"; reg = <0 0x1001b000 0 0x1000>; #clock-cells = <1>; }; watchdog: watchdog@1001c000 { compatible = "mediatek,mt7988-wdt"; reg = <0 0x1001c000 0 0x1000>; interrupts = ; #reset-cells = <1>; }; apmixedsys: clock-controller@1001e000 { compatible = "mediatek,mt7988-apmixedsys"; reg = <0 0x1001e000 0 0x1000>; #clock-cells = <1>; }; pio: pinctrl@1001f000 { compatible = "mediatek,mt7988-pinctrl"; reg = <0 0x1001f000 0 0x1000>, <0 0x11c10000 0 0x1000>, <0 0x11d00000 0 0x1000>, <0 0x11d20000 0 0x1000>, <0 0x11e00000 0 0x1000>, <0 0x11f00000 0 0x1000>, <0 0x1000b000 0 0x1000>; reg-names = "gpio", "iocfg_tr", "iocfg_br", "iocfg_rb", "iocfg_lb", "iocfg_tl", "eint"; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pio 0 0 84>; interrupt-controller; interrupts = ; interrupt-parent = <&gic>; #interrupt-cells = <2>; pcie0_pins: pcie0-pins { mux { function = "pcie"; groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", "pcie_wake_n0_0"; }; }; pcie1_pins: pcie1-pins { mux { function = "pcie"; groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", "pcie_wake_n1_0"; }; }; pcie2_pins: pcie2-pins { mux { function = "pcie"; groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", "pcie_wake_n2_0"; }; }; pcie3_pins: pcie3-pins { mux { function = "pcie"; groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", "pcie_wake_n3_0"; }; }; }; pwm: pwm@10048000 { compatible = "mediatek,mt7988-pwm"; reg = <0 0x10048000 0 0x1000>; clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>, <&infracfg CLK_INFRA_66M_PWM_HCK>, <&infracfg CLK_INFRA_66M_PWM_CK1>, <&infracfg CLK_INFRA_66M_PWM_CK2>, <&infracfg CLK_INFRA_66M_PWM_CK3>, <&infracfg CLK_INFRA_66M_PWM_CK4>, <&infracfg CLK_INFRA_66M_PWM_CK5>, <&infracfg CLK_INFRA_66M_PWM_CK6>, <&infracfg CLK_INFRA_66M_PWM_CK7>, <&infracfg CLK_INFRA_66M_PWM_CK8>; clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6", "pwm7", "pwm8"; #pwm-cells = <2>; status = "disabled"; }; mcusys: mcusys@100e0000 { compatible = "mediatek,mt7988-mcusys", "syscon"; reg = <0 0x100e0000 0 0x1000>; #clock-cells = <1>; }; serial0: serial@11000000 { compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; reg = <0 0x11000000 0 0x100>; interrupts = ; interrupt-names = "uart", "wakeup"; clocks = <&topckgen CLK_TOP_UART_SEL>, <&infracfg CLK_INFRA_52M_UART0_CK>; clock-names = "baud", "bus"; status = "disabled"; }; serial@11000100 { compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; reg = <0 0x11000100 0 0x100>; interrupts = ; interrupt-names = "uart", "wakeup"; clocks = <&topckgen CLK_TOP_UART_SEL>, <&infracfg CLK_INFRA_52M_UART1_CK>; clock-names = "baud", "bus"; status = "disabled"; }; serial@11000200 { compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; reg = <0 0x11000200 0 0x100>; interrupts = ; interrupt-names = "uart", "wakeup"; clocks = <&topckgen CLK_TOP_UART_SEL>, <&infracfg CLK_INFRA_52M_UART2_CK>; clock-names = "baud", "bus"; status = "disabled"; }; i2c0: i2c@11003000 { compatible = "mediatek,mt7981-i2c"; reg = <0 0x11003000 0 0x1000>, <0 0x10217080 0 0x80>; interrupts = ; clock-div = <1>; clocks = <&infracfg CLK_INFRA_I2C_BCK>, <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; clock-names = "main", "dma"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c1: i2c@11004000 { compatible = "mediatek,mt7981-i2c"; reg = <0 0x11004000 0 0x1000>, <0 0x10217100 0 0x80>; interrupts = ; clock-div = <1>; clocks = <&infracfg CLK_INFRA_I2C_BCK>, <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; clock-names = "main", "dma"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c2: i2c@11005000 { compatible = "mediatek,mt7981-i2c"; reg = <0 0x11005000 0 0x1000>, <0 0x10217180 0 0x80>; interrupts = ; clock-div = <1>; clocks = <&infracfg CLK_INFRA_I2C_BCK>, <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; clock-names = "main", "dma"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; lvts: lvts@1100a000 { compatible = "mediatek,mt7988-lvts-ap"; #thermal-sensor-cells = <1>; reg = <0 0x1100a000 0 0x1000>; clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>; interrupts = ; resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>; nvmem-cells = <&lvts_calibration>; nvmem-cell-names = "lvts-calib-data-1"; }; usb@11190000 { compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; reg = <0 0x11190000 0 0x2e00>, <0 0x11193e00 0 0x0100>; reg-names = "mac", "ippc"; interrupts = ; clocks = <&infracfg CLK_INFRA_USB_SYS>, <&infracfg CLK_INFRA_USB_REF>, <&infracfg CLK_INFRA_66M_USB_HCK>, <&infracfg CLK_INFRA_133M_USB_HCK>, <&infracfg CLK_INFRA_USB_XHCI>; clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; status = "disabled"; }; ssusb1: usb@11200000 { compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; reg = <0 0x11200000 0 0x2e00>, <0 0x11203e00 0 0x0100>; reg-names = "mac", "ippc"; interrupts = ; clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>, <&infracfg CLK_INFRA_USB_CK_P1>, <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>, <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>, <&infracfg CLK_INFRA_USB_XHCI_CK_P1>; clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; phys = <&tphyu2port0 PHY_TYPE_USB2>, <&tphyu3port0 PHY_TYPE_USB3>; status = "disabled"; }; mmc0: mmc@11230000 { compatible = "mediatek,mt7988-mmc"; reg = <0 0x11230000 0 0x1000>, <0 0x11D60000 0 0x1000>; interrupts = ; clocks = <&infracfg CLK_INFRA_MSDC400>, <&infracfg CLK_INFRA_MSDC2_HCK>, <&infracfg CLK_INFRA_66M_MSDC_0_HCK>, <&infracfg CLK_INFRA_133M_MSDC_0_HCK>; assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>, <&topckgen CLK_TOP_EMMC_400M_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>, <&apmixedsys CLK_APMIXED_MSDCPLL>; clock-names = "source", "hclk", "axi_cg", "ahb_cg"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; pcie2: pcie@11280000 { compatible = "mediatek,mt7986-pcie", "mediatek,mt8192-pcie"; device_type = "pci"; #address-cells = <3>; #size-cells = <2>; reg = <0 0x11280000 0 0x2000>; reg-names = "pcie-mac"; linux,pci-domain = <3>; interrupts = ; bus-range = <0x00 0xff>; ranges = <0x81000000 0x00 0x20000000 0x00 0x20000000 0x00 0x00200000>, <0x82000000 0x00 0x20200000 0x00 0x20200000 0x00 0x07e00000>; clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>, <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>, <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>, <&infracfg CLK_INFRA_133M_PCIE_CK_P2>; clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; pinctrl-names = "default"; pinctrl-0 = <&pcie2_pins>; status = "disabled"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &pcie_intc2 0>, <0 0 0 2 &pcie_intc2 1>, <0 0 0 3 &pcie_intc2 2>, <0 0 0 4 &pcie_intc2 3>; pcie_intc2: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller; }; }; pcie3: pcie@11290000 { compatible = "mediatek,mt7986-pcie", "mediatek,mt8192-pcie"; device_type = "pci"; #address-cells = <3>; #size-cells = <2>; reg = <0 0x11290000 0 0x2000>; reg-names = "pcie-mac"; linux,pci-domain = <2>; interrupts = ; bus-range = <0x00 0xff>; ranges = <0x81000000 0x00 0x28000000 0x00 0x28000000 0x00 0x00200000>, <0x82000000 0x00 0x28200000 0x00 0x28200000 0x00 0x07e00000>; clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>, <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>, <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>, <&infracfg CLK_INFRA_133M_PCIE_CK_P3>; clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; pinctrl-names = "default"; pinctrl-0 = <&pcie3_pins>; status = "disabled"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &pcie_intc3 0>, <0 0 0 2 &pcie_intc3 1>, <0 0 0 3 &pcie_intc3 2>, <0 0 0 4 &pcie_intc3 3>; pcie_intc3: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller; }; }; pcie0: pcie@11300000 { compatible = "mediatek,mt7986-pcie", "mediatek,mt8192-pcie"; device_type = "pci"; #address-cells = <3>; #size-cells = <2>; reg = <0 0x11300000 0 0x2000>; reg-names = "pcie-mac"; linux,pci-domain = <0>; interrupts = ; bus-range = <0x00 0xff>; ranges = <0x81000000 0x00 0x30000000 0x00 0x30000000 0x00 0x00200000>, <0x82000000 0x00 0x30200000 0x00 0x30200000 0x00 0x07e00000>; clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>, <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>, <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>, <&infracfg CLK_INFRA_133M_PCIE_CK_P0>; clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; pinctrl-names = "default"; pinctrl-0 = <&pcie0_pins>; status = "disabled"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &pcie_intc0 0>, <0 0 0 2 &pcie_intc0 1>, <0 0 0 3 &pcie_intc0 2>, <0 0 0 4 &pcie_intc0 3>; pcie_intc0: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller; }; }; pcie1: pcie@11310000 { compatible = "mediatek,mt7986-pcie", "mediatek,mt8192-pcie"; device_type = "pci"; #address-cells = <3>; #size-cells = <2>; reg = <0 0x11310000 0 0x2000>; reg-names = "pcie-mac"; linux,pci-domain = <1>; interrupts = ; bus-range = <0x00 0xff>; ranges = <0x81000000 0x00 0x38000000 0x00 0x38000000 0x00 0x00200000>, <0x82000000 0x00 0x38200000 0x00 0x38200000 0x00 0x07e00000>; clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>, <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>, <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>, <&infracfg CLK_INFRA_133M_PCIE_CK_P1>; clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; pinctrl-names = "default"; pinctrl-0 = <&pcie1_pins>; status = "disabled"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &pcie_intc1 0>, <0 0 0 2 &pcie_intc1 1>, <0 0 0 3 &pcie_intc1 2>, <0 0 0 4 &pcie_intc1 3>; pcie_intc1: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller; }; }; tphy: t-phy@11c50000 { compatible = "mediatek,mt7986-tphy", "mediatek,generic-tphy-v2"; #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; tphyu2port0: usb-phy@11c50000 { reg = <0 0x11c50000 0 0x700>; clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>; clock-names = "ref"; #phy-cells = <1>; }; tphyu3port0: usb-phy@11c50700 { reg = <0 0x11c50700 0 0x900>; clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>; clock-names = "ref"; #phy-cells = <1>; }; }; clock-controller@11f40000 { compatible = "mediatek,mt7988-xfi-pll"; reg = <0 0x11f40000 0 0x1000>; resets = <&watchdog 16>; #clock-cells = <1>; }; efuse@11f50000 { compatible = "mediatek,mt7988-efuse", "mediatek,efuse"; reg = <0 0x11f50000 0 0x1000>; #address-cells = <1>; #size-cells = <1>; lvts_calibration: calib@918 { reg = <0x918 0x28>; }; }; clock-controller@15000000 { compatible = "mediatek,mt7988-ethsys", "syscon"; reg = <0 0x15000000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; clock-controller@15031000 { compatible = "mediatek,mt7988-ethwarp"; reg = <0 0x15031000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; }; thermal-zones { cpu_thermal: cpu-thermal { polling-delay-passive = <1000>; polling-delay = <1000>; thermal-sensors = <&lvts 0>; trips { cpu_trip_crit: crit { temperature = <125000>; hysteresis = <2000>; type = "critical"; }; }; }; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = , , , ; }; };