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HMHHDHMHHDHMHHD5HpHHHDH`HHHD|HpHHHD;HhHHHDH`HHHDHHHHDHHHHDMH`HHHDHHHHDHHHHDkHHHHD HMHHDHMHHDH@MHHDTHHHHDHHHHD+HHHHDHM-!MH HH HHMHHDKHpHHHDHhHHHDHpHHHDHpMHHDeHhHHHDH`HHHDxHHHHDHMHHDHMHHDXHMHHD+HMHHDHMHHDHMHHD]H@MHHDAYxwAYxAYxH=H HHƒ~ HHHIHƒHHMtHoHHH xarch/x86/events/intel/core.c%d %lu perfevents: irq loop stuck! 6core: %s PMU driver: c sapphire_rapidsgranite_rapidspantherlake_hybridlunarlake_hybridgeneric_arch_v2+core2corearrowlake_h_hybridmeteorlake_hybridalderlake_hybridicelakeskylakeknights-landingbroadwellhaswellivybridgesandybridgewestmeredarkmontcrestmontgracemontTremontgoldmont_plusgoldmontsilvermontbonnellnehalemgeneric_arch_v1generic_arch_v5+Intelc AnyThread deprecated, cCore events, cCore2 events, cNehalem events, cAtom events, cSilvermont events, cGoldmont events, 4cGoldmont plus events, cTremont events, cGracemont events, cCrestmont events, cDarkmont events, cWestmere events, cSandyBridge events, cIvyBridge events, cHaswell events, cBroadwell events, event=0xd,umask=0x1,cmask=1cSkylake events, cIcelake events, cSapphire Rapids events, cGranite Rapids events, cAlderlake Hybrid events, cMeteorlake Hybrid events, cPantherlake Hybrid events, cLunarlake Hybrid events, cArrowLake-H Hybrid events, %sc%d-deep LBR, cfull-width counters, cpu_atomcpu_corecpu_lowpowercpusformateventssnoop_rspfrontendldlatoffcore_rspin_tx_cpin_txtx-capacity-writeevent=0x54,umask=0x2tx-capacity-readevent=0x54,umask=0x80cycles-ctevent=0x3c,in_tx=1,in_tx_cp=1cycles-tevent=0x3c,in_tx=1tx-conflictevent=0x54,umask=0x1tx-abortevent=0xc9,umask=0x4tx-commitevent=0xc9,umask=0x2tx-startevent=0xc9,umask=0x1mem-storesmem-loadsmem-loads-auxevent=0x03,umask=0x82topdown-be-boundtopdown-fe-boundtopdown-bad-spectopdown-retiringtopdown-mem-boundevent=0x00,umask=0x87topdown-fetch-latevent=0x00,umask=0x86topdown-br-mispredictevent=0x00,umask=0x85topdown-heavy-opsevent=0x00,umask=0x84slotsevent=0x00,umask=0x4capsacr_maskallow_tsx_force_abortpmu_namebranch_counter_widthbranch_counter_nrbranchesfreeze_on_smievent=0xcd,umask=0x2el-capacity-writeel-capacity-readel-conflictel-capacityel-abortevent=0xc8,umask=0x4el-commitevent=0xc8,umask=0x2el-startevent=0xc8,umask=0x1tx-capacityevent=0xd0,umask=0x82event=0xcd,umask=0x1,ldlat=3cpu cyclesinstructionsbus cyclescache referencescache missesbranch instructionsbranch missesumaskmetrics_cleareqcmaskinvanypcedgeeventevent=0xa4,umask=0x02event=0xc2,umask=0x02event=0x9c,umask=0x01event=0x73,umask=0x0event=0x72,umask=0x0event=0xd0,umask=0x6event=0xd0,umask=0x5,ldlat=3event=0x74,umask=0x0event=0x73,umask=0x6event=0xc2,umask=0x0event=0x71,umask=0x0topdown-slots-issuedevent=0x0etopdown-slots-retiredevent=0xc2topdown-recovery-bubblesevent=0xca,umask=0x02topdown-fetch-bubblesevent=0x9ctopdown-total-slots.scale3topdown-total-slotsevent=0x3cevent=0xc2,umask=0x10topdown-fetch-bubbles.scale2event=0xca,umask=0x50event=0x00,umask=0x83event=0x00,umask=0x82event=0x00,umask=0x81event=0x00,umask=0x80event=0xd,umask=0x3,cmask=1event=0x9c,umask=0x1event=0xc2,umask=0x2event=0xe,umask=0x1event=0x3c,umask=0x0,any=1event=0x3c,umask=0x0event=0x0b,umask=0x10,ldlat=3s d E - z   n n    ;   a  4core: CPUID marked event: '%s' unavailable 4core: PEBS disabled due to CPU errata 6core: CPU erratum AAJ80 worked around 6core: PMU erratum BJ122, BV98, HSD29 worked around, HT is on 6core: PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off 3hw perf events %d > max(%d), clipping!3hw perf events fixed %d > max(%d), clipping!6core: PEBS enabled due to microcode update 6core: PEBS disabled due to CPU errata, please upgrade microcode 6core: clearing PMU state on CPU#%d 4core: Failed to disable the event with invalid index %d 4core: Failed to enable the event with invalid index %d cunsupported CPU family %d model %d cKnights Landing/Mill events, event=0xd,umask=0x1,cmask=1,any=1cgeneric architected perfmon, cgeneric architected perfmon v1, event=0xd0,umask=0x6;event=0xcd,umask=0x2;event=0xd0,umask=0x6event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3;event=0xd0,umask=0x5,ldlat=3event=0xd0,umask=0x6;event=0xcd,umask=0x2event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3event=0xa4,umask=0x02;event=0x00,umask=0x83;event=0x74,umask=0x0event=0x9c,umask=0x01;event=0x00,umask=0x82;event=0x71,umask=0x0event=0x73,umask=0x0;event=0x00,umask=0x81;event=0x73,umask=0x0event=0xc2,umask=0x02;event=0x00,umask=0x80;event=0xc2,umask=0x0event=0xa4,umask=0x02;event=0x00,umask=0x83event=0x9c,umask=0x01;event=0x00,umask=0x82event=0xc2,umask=0x02;event=0x00,umask=0x80event=0x74,umask=0x0;event=0x00,umask=0x83event=0x71,umask=0x0;event=0x00,umask=0x82event=0x73,umask=0x0;event=0x00,umask=0x81event=0xc2,umask=0x0;event=0x00,umask=0x80topdown-recovery-bubbles.scaleevent=0xd,umask=0x3,cmask=1,any=1uSuOHHHHHHHHHHHHHCCCC*(-@- <EF?7? =#GVV V V O U!UUN|^|>NN?00???66ЁЂЁЂI66006ЁЂЁЂ6006@!@")O)A*O*A@!@"@@AAN)O)A*O*A@A Q QNN@A   00p p 0p0 Q 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"@ "H "P !"XH!"`!"h!"p!"x7"0R"@0m" 0"0(" "0"@ 0"`!0" 0 # 0 #!0;#!0V##0t#`#0# #0#"0#"0#%0$`%08$ %0X$$0~$$0$`$0$.0$@.0$.0$"6%;%e%%%%%%% &,&F&Y&o&w&&&&&&&& ''!'2'A' X'(m'v'''''''''( (*(5(B(J(\(v(((((()))&)7)C)Q)j)|)))))))**.*@*[*c*|*******+-+<+R+l+++++++,,3,J,c,z,,,,,,--(-C-SCX-r-@UN-U-----^-..3.`E.p9T.h....... 6 ./8/W/c/o//////0'0<0a0x00000 1+1L1n111112&282Y2p222223"3/3G3X3y333333424Q4r4444444515P5p55core.cintel_pmu_topdown_event_update__initcall__kmod_core__751_7841_fixup_ht_bug4fixup_ht_bugintel_pmu_event_mapintel_perfmon_event_mapintel_pmu_disable_all__icl_update_topdown_eventintel_pebs_aliases_core2intel_pebs_aliases_snbadl_get_hybrid_cpu_typehsw_limit_periodnhm_limit_periodintel_ht_bugintel_start_schedulingintel_commit_schedulingintel_stop_schedulingexra_is_visiblehybrid_events_is_visiblehybrid_td_is_visibleintel_pmu_v6_addr_offsetdyn_constraintintel_guest_get_msrs__intel_shared_reg_get_constraintsintel_pmu_filterhybrid_tsx_is_visiblehybrid_format_is_visibleupdate_saved_topdown_regsintel_arch_events_quirkintel_arch_events_mapintel_clovertown_quirkintel_nehalem_quirkintel_pmu_set_periodshow_sysctl_tfabranch_counter_width_showbranches_showintel_hybrid_get_attr_cpusset_sysctl_tfaupdate_tfa_schedfreeze_on_smi_storefreeze_on_smi_mutexflip_smm_bitfreeze_on_smi_showacr_mask_showmetrics_clear_showeq_showumask2_showfrontend_showldlat_showoffcore_rsp_showin_tx_cp_showin_tx_showcmask_showinv_showany_showpc_showedge_showumask_showevent_showbranch_counter_nr_showintel_pmu_aux_output_matchintel_pmu_sched_taskintel_pmu_cpu_dyingcore_pmu_enable_eventintel_pmu_check_counters_maskintel_pmu_assign_eventintel_check_pebs_isolationisolation_ucodesintel_pebs_aliases_ivbintel_pebs_aliases_sklbdw_limit_periodlbr_is_visibledefault_is_visibledev_attr_allow_tsx_force_abortmem_is_visibleevent_attr_mem_ld_auxevtsel_ext_is_visibleintel_pmu_updateintel_pmu_check_event_constraints.part.0glc_limit_periodintel_snb_check_microcodepebs_ucodesintel_sandybridge_quirksnoop_rsp_showintel_pmu_check_periodacr_is_visibleintel_pmu_bts_configcore_pmu_hw_configintel_pebs_isolation_quirkintel_put_event_constraintscore_guest_get_msrsintel_pmu_add_eventintel_pmu_del_eventupdate_pmu_capintel_pmu_hw_config.part.0intel_pmu_hw_confighsw_hw_configadl_hw_configarl_h_hw_configintel_tfa_commit_schedulingx86_pmu_disable_event__intel_pmu_enable_all.constprop.0intel_tfa_pmu_enable_all__intel_pmu_snapshot_branch_stackintel_pmu_snapshot_arch_branch_stackintel_pmu_enable_allintel_pmu_read_eventintel_pmu_config_acrintel_pmu_enable_acrintel_pmu_nhm_enable_allnhm_magic.1icl_set_topdown_event_periodcore_pmu_enable_allhandle_pmi_commonintel_pmu_handle_irqwarned.0intel_pmu_disable_eventcheck_msrintel_pmu_cpu_startingintel_pmu_enable_eventintel_get_event_constraintshsw_get_event_constraintscounter2_constraintcmt_get_event_constraintsfixed0_constraintCSWTCH.572fixed0_counter0_1_constrainttnt_get_event_constraintsfixed0_counter0_constraintglp_get_event_constraintsicl_get_event_constraintstfa_get_event_constraintsglc_get_event_constraintsmtl_get_event_constraintscounters_1_7_constraintarl_h_get_event_constraintsadl_get_event_constraintsintel_pmu_cpu_prepareintel_pmu_cpu_deadintel_arch3_formats_attr__quirk.11westmere_hw_cache_event_idsnehalem_hw_cache_extra_regsintel_westmere_event_constraintsintel_westmere_extra_regsempty_attrsnhm_mem_events_attrsnhm_format_attrintel_core_event_constraintsintel_arch_formats_attratom_hw_cache_event_idsintel_gen_event_constraintspmu_name_strgroup_format_extra_sklnehalem_hw_cache_event_idsintel_nehalem_event_constraintsintel_nehalem_extra_regs__quirk.9snb_hw_cache_event_ids__quirk.8__quirk.7snb_hw_cache_extra_regsintel_snbep_extra_regsintel_snb_extra_regsintel_snb_event_constraintssnb_mem_events_attrssnb_events_attrscore2_hw_cache_event_idsintel_core2_event_constraintsglp_hw_cache_event_idstnt_events_attrstnt_hw_cache_extra_regsslm_format_attrintel_slm_event_constraintsintel_tnt_extra_regsskl_hw_cache_event_ids__quirk.2skl_hw_cache_extra_regsevent_attr_td_recovery_bubbleshsw_format_attrintel_skl_event_constraintsintel_skl_extra_regshsw_tsx_events_attrshsw_mem_events_attrshsw_events_attrsskl_format_attrintel_skt_event_constraintsintel_cmt_extra_regsgrt_mem_attrsskt_events_attrscmt_format_attricl_events_attrsicl_td_events_attrsicl_tsx_events_attrsintel_icl_event_constraintsintel_icl_extra_regsintel_hybrid_pmu_type_mapglp_hw_cache_extra_regsintel_glm_extra_regsevent_attr_td_total_slots_scale_glmglm_events_attrsintel_glc_extra_regsglc_hw_cache_event_idsglc_hw_cache_extra_regsintel_glc_event_constraintsglc_tsx_events_attrsglc_events_attrsglc_td_events_attrsslm_hw_cache_event_idsknl_hw_cache_extra_regsintel_knl_extra_regsslm_hw_cache_extra_regsslm_events_attrsintel_slm_extra_regshsw_hw_cache_event_idshsw_hw_cache_extra_regs__quirk.3intel_bdw_event_constraints__quirk.5__quirk.4intel_hsw_event_constraints__quirk.6intel_ivb_event_constraintshybrid_group_events_tdhybrid_attr_updatehybrid_group_events_memhybrid_group_events_tsxhybrid_group_format_extraintel_v1_event_constraintsmtl_hybrid_extra_attrmtl_hybrid_extra_attr_rtmintel_lnc_event_constraintsintel_lnc_extra_regsintel_grt_event_constraintsintel_grt_extra_regsadl_hybrid_tsx_attrsmtl_hybrid_mem_attrslnl_hybrid_events_attrsadl_hybrid_extra_attradl_hybrid_extra_attr_rtmadl_hybrid_mem_attrsadl_hybrid_events_attrsintel_rwc_extra_regscmt_even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