ELF>@@@/.HcHff.SeHH10HH/r'[11HH/s[f.IIHЃw HAHHIHMuI9s L)IILEIIIHhHH 11-111Ҿ1HƉ1LƉfDSHHH9t'HHt ftpH1[1 0C1)0&HǃHHǃ1[11)11 H¹ H 00H)HH 0d1Hƿ)P1Hƿ 뿐U HAWAVAUIATSHHHt$8Ld$@LeH%(H$x1HeHHL5eHkE1H#D$8HeHP H#HH!HD$8>HD$8s9HLP LLHP I7L!t$8L9sA7HD$8N0HD$8-HH D$8HD$8HD$4?HHD$(HcD$4Ht$(AL4HsdLAl3LtBHD$@IHD$PHD$HALLLL$4HcH?w#HHH#D$8tHD$4?QH$xeH+%(HeD[A\A]A^A_]HHH5LX01AAH¹H 0x1Hƿd1L.LHL1A0Idž11HHAWAVAUATUSHH?eHAHLHcLtI$sTHDuFAeL=AuyIhIAxH @L!HH 0FKHcH?w"LHHH#tHÃ?oH[]A\A]A^A_1HƉAHL zHtL$ L$L$ L$LDH 0-3IHH 01HƉ1LƉff.AWAVAUATIUSH0eHD5LDD$AADt$A|$D$u |$XALJeHH10HH/2H H ISMtNeALDDH 0ptLLl2H H IMu|$aD$A |$*H0[]A\A]A^A_1Lu=eHL,HIILD$LT$H[eHHD$ D$(e5HLT$LD$AHHIʼnÃLt$E1l$LHD5DHt A DD017HD5Ht 1AC .DD01KHcHw$HH#EHtLDAiLt$LD$l$AHHÃE1MIHHK HHt85Ht$Ht 1|$DD01KHcHwHHI#E%t HÃ~H\$ HtHHC=^HD$(zt1L[@IHHgD`AADt$NIHH-`D$1L11HH/UK7|$@@IHLxHHIEIIHHLpHp2H HH HڹH 010"F%Dw ?H HHH*HIHHHHH*HIHIIH H H+HHHHHEHHHHGJHHH*HHIIH*IIHHH HHHD: K<-=HHH*HHH*HHHIHHHHHH-8IIHHI HHH H HH+HHHHEHHHH7 V'Z/\JHH*IHHH*HH HHHHHIHIIsiA  1O HH*HHHH*HIIHIIH HH+HHHHEHHHHHHHHHHHH\^1H HHH*HHHHH*HH HH+HHHHEHHHHHH t4Hu( HHHHIHIII:#H HH*IIIHH*IHHHHH HHHH(zL~HHH*HHIIH*IIHHH HHHvH  eo !HIH|v1dju H ./ mHI HHHH f  HHHHHHHH*HHH*HHHu H<H HHIHIH+IHHHEJ 8%HH%HHHH=L 1ALcHcֻIHih HEMHpLxD@L8L`HhHHǂHǂLǂHǂLPA!Q`HcHwHHH҉уHH-HHHHHH+HLh HHHEH f  HHHHHHHHxHHHHHHH)H)PHHHHxHHHHHHH)H)PHHHHHu H<HHHHWHHH HHxL-L%HHHL(LHH)H)PHHHxLLIHLLLHH)H)PHSHHǀ"HHHHHHu H<HHZHHH LHHf  HHxL(HHLHH)H)PHHHxLLHLHH)H)PHHHǀHHrHH)HHu H<IHHǂ(IIIH HHf  HH*HHH*HHHHHu H<HHHHIIIHI>3Wy(J{ ADHL-HL%H-HYHHHH E2H H HH,SdH= HHHHHH=L1LcDJIHih HEMHpLxD@L8H`HhHHǂHǂLǂHǂLPA9Q`HcHHHH҉уIct H= HHpHHHDH=L1LcDJIHih HEMHpLxD@L8H`HhHHǂHǂLǂHǂLPAQ`HcHwkHHt\H҉уwPIc1H޿EHHIHiHH-HHHHHH+HLh HHHEH f  HHHHHHHHHxHHHHHHH)H)PH|HHHxHHHHHHH)H)PHHHHHu H<H H HHTH H kH=HHH H H H=H HHDž HDž DžHDžHDž HHf  oHH HxHHHH HHH)H)PHHH HxHHHH HHH)H)PHHHǀ~HH+ HH HHu H<IH IHIIHH-HHHHHH+HLh HHHEH f  HHHHHHHHxHHHHHHH)H)PH HHHxHHHHHHH)H)PHF HH HHu H< HH HH~ HHH HHf   HH HxHHHH HHH)H)PH HH HxHHHH HHH)H)PHS HHǀ" HH HH HHu H<HHHHIHIIIHQH= HH5HHH H=L1LcDJIHih HEMHpLxD@L8H`HhHHǂHǂLǂHǂLPAM Q`HcH,HHH҉у Ic HHf  HH*HHH*HHHHu H<HIHIHIIHHHHH-HHHHHH+HLh HHHEH f  HHHHHHHHxHHHHHHH)H)PHHHHxHHHHHHH)H)PHGHHHHu H<HHDž HHf  HH HxHHHH HHH)H)PH0HH HxHHHH HHH)H)PHHHǀHHrHHHHu H<IHHǂXIIIHHIH)HHHHHHH*IHHHHH*H H=>HHHHHDH HHHH*IHHH*HH HHHHHHHXHHHDHXHHHDkHHHHHD>HPHHHD{HHHHHDNHHHHDHHHHDHHHHD]HMHHDHMHHDH`MHHDFHXHHHDHPHHHDH(MHHDHxMHHDHXHHHDHHHHHDfHXHHHD%HPHHHDHHHHHDHHHHDHHHHD7HHHHDHMHHDHMHHDiHMHHDHHHHDHHHHD~HMMH HHH ZHMHHDHMHHDH`MHHDqHMHHDH MHHD{HMHHDNHxMHHDHMHHDAQ`A&Q`AQ`AQ`HHH *HHƒ~ HHHIHƒHH.Mxl1vUNOHHHarch/x86/events/intel/core.c%d %lu perfevents: irq loop stuck! 6core: %s PMU driver: c sapphire_rapidsgranite_rapidsgeneric_arch_v2+core2corearrowlake_h_hybridlunarlake_hybridmeteorlake_hybridalderlake_hybridicelakeskylakeknights-landingbroadwellhaswellivybridgesandybridgewestmerecrestmontgracemontTremontgoldmont_plusgoldmontsilvermontbonnellnehalemgeneric_arch_v1generic_arch_v5+Intelc AnyThread deprecated, cCore events, cCore2 events, cNehalem events, cAtom events, cSilvermont events, cGoldmont events, 4cGoldmont plus events, cTremont events, cGracemont events, cCrestmont events, cWestmere events, cSandyBridge events, cIvyBridge events, cHaswell events, cBroadwell events, event=0xd,umask=0x1,cmask=1cSkylake events, cIcelake events, cSapphire Rapids events, cGranite Rapids events, cAlderlake Hybrid events, cMeteorlake Hybrid events, cLunarlake Hybrid events, cArrowLake-H Hybrid events, %sc%d-deep LBR, cfull-width counters, cpu_atomcpu_corecpu_lowpowercpusformateventssnoop_rspfrontendldlatoffcore_rspin_tx_cpin_txtx-capacity-writeevent=0x54,umask=0x2tx-capacity-readevent=0x54,umask=0x80cycles-ctevent=0x3c,in_tx=1,in_tx_cp=1cycles-tevent=0x3c,in_tx=1tx-conflictevent=0x54,umask=0x1tx-abortevent=0xc9,umask=0x4tx-commitevent=0xc9,umask=0x2tx-startevent=0xc9,umask=0x1mem-storesmem-loadsmem-loads-auxevent=0x03,umask=0x82topdown-be-boundtopdown-fe-boundtopdown-bad-spectopdown-retiringtopdown-mem-boundevent=0x00,umask=0x87topdown-fetch-latevent=0x00,umask=0x86topdown-br-mispredictevent=0x00,umask=0x85topdown-heavy-opsevent=0x00,umask=0x84slotsevent=0x00,umask=0x4capsallow_tsx_force_abortpmu_namebranch_counter_widthbranch_counter_nrbranchesfreeze_on_smievent=0xcd,umask=0x2el-capacity-writeel-capacity-readel-conflictel-capacityel-abortevent=0xc8,umask=0x4el-commitevent=0xc8,umask=0x2el-startevent=0xc8,umask=0x1tx-capacityevent=0xd0,umask=0x82event=0xcd,umask=0x1,ldlat=3cpu cyclesinstructionsbus cyclescache referencescache missesbranch instructionsbranch missesumaskmetrics_cleareqcmaskinvanypcedgeeventevent=0x73,umask=0x0event=0x72,umask=0x0event=0xd0,umask=0x6event=0xd0,umask=0x5,ldlat=3event=0x74,umask=0x0event=0x73,umask=0x6event=0xc2,umask=0x0event=0x71,umask=0x0topdown-slots-issuedevent=0x0etopdown-slots-retiredevent=0xc2topdown-recovery-bubblesevent=0xca,umask=0x02topdown-fetch-bubblesevent=0x9ctopdown-total-slots.scale3topdown-total-slotsevent=0x3cevent=0xc2,umask=0x10topdown-fetch-bubbles.scale2event=0xca,umask=0x50event=0x00,umask=0x83event=0x00,umask=0x82event=0x00,umask=0x81event=0x00,umask=0x80event=0xd,umask=0x3,cmask=1event=0x9c,umask=0x1event=0xc2,umask=0x2event=0xe,umask=0x1event=0x3c,umask=0x0,any=1event=0x3c,umask=0x0event=0x0b,umask=0x10,ldlat=3     X `  L L   l   a ?  4core: PEBS disabled due to CPU errata 6core: CPU erratum AAJ80 worked around 4core: CPUID marked event: '%s' unavailable 6core: PMU erratum BJ122, BV98, HSD29 worked around, HT is on 6core: PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off 3hw perf events %d > max(%d), clipping!3hw perf events fixed %d > max(%d), clipping!6core: PEBS enabled due to microcode update 6core: PEBS disabled due to CPU errata, please upgrade microcode 6core: clearing PMU state on CPU#%d 4core: Failed to disable the event with invalid index %d 4core: Failed to enable the event with invalid index %d cKnights Landing/Mill events, event=0xd,umask=0x1,cmask=1,any=1cgeneric architected perfmon, cgeneric architected perfmon v1, event=0xd0,umask=0x6;event=0xcd,umask=0x2;event=0xd0,umask=0x6event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3;event=0xd0,umask=0x5,ldlat=3event=0xd0,umask=0x6;event=0xcd,umask=0x2event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3event=0xa4,umask=0x02;event=0x00,umask=0x83;event=0x74,umask=0x0event=0x9c,umask=0x01;event=0x00,umask=0x82;event=0x71,umask=0x0event=0x73,umask=0x0;event=0x00,umask=0x81;event=0x73,umask=0x0event=0xc2,umask=0x02;event=0x00,umask=0x80;event=0xc2,umask=0x0event=0xa4,umask=0x02;event=0x00,umask=0x83event=0x9c,umask=0x01;event=0x00,umask=0x82event=0xc2,umask=0x02;event=0x00,umask=0x80event=0x74,umask=0x0;event=0x00,umask=0x83event=0x71,umask=0x0;event=0x00,umask=0x82event=0x73,umask=0x0;event=0x00,umask=0x81event=0xc2,umask=0x0;event=0x00,umask=0x80topdown-recovery-bubbles.scaleevent=0xd,umask=0x3,cmask=1,any=1uSuOHHHHHHHHHHCCCC*(-@- <EF?7? =#GVV V V O U!UUN|^|>NN?00???66ЁЂЁЂI66006ЁЂЁЂ6006@!@")O)A*O*A@!@"@@AAN)O)A*O*A@A Q QNN@A   00p p 0p0 Q QNN   @?@?@@ЁQЂЁЂI`QQNЁЂI??00?00????ЁQЂЁЂI ????? ?Ё$Ђ$****ЁЂ**'(')??v6v6*+ @*?+? @*?+?@????????y9<<s @<<<< @      @< <Hy     <H    <Q`c <@ABCHNQc<<.O.A<GCC: (Debian 12.2.0-14) 12.2.0GNU 66CW(@Po@f]0>>-0 1R. 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/03/@]/~//////040U0t00000001/1@1_11111112core.c__initcall__kmod_core__673_7479_fixup_ht_bug4fixup_ht_bugintel_pmu_event_mapintel_perfmon_event_mapintel_pmu_disable_all__icl_update_topdown_eventintel_pebs_aliases_core2intel_pebs_aliases_snbadl_get_hybrid_cpu_typehsw_limit_periodnhm_limit_periodintel_ht_bugintel_start_schedulingintel_commit_schedulingintel_stop_schedulingexra_is_visiblehybrid_events_is_visiblehybrid_td_is_visibleintel_pmu_v6_addr_offsetdyn_constraintintel_guest_get_msrs__intel_shared_reg_get_constraintsintel_pmu_filterintel_clovertown_quirkintel_nehalem_quirkintel_pmu_updateintel_pmu_set_periodshow_sysctl_tfabranch_counter_width_showbranches_showintel_hybrid_get_attr_cpusset_sysctl_tfaupdate_tfa_schedfreeze_on_smi_storefreeze_on_smi_mutexflip_smm_bitfreeze_on_smi_showmetrics_clear_showeq_showumask2_showfrontend_showldlat_showoffcore_rsp_showin_tx_cp_showin_tx_showcmask_showinv_showany_showpc_showedge_showumask_showevent_showbranch_counter_nr_showhybrid_tsx_is_visiblehybrid_format_is_visibleintel_arch_events_quirkintel_arch_events_mapupdate_saved_topdown_regsintel_pmu_aux_output_matchintel_pmu_swap_task_ctxintel_pmu_sched_taskintel_pmu_read_eventintel_pmu_del_eventintel_pmu_add_eventintel_pmu_cpu_dyingcore_pmu_enable_eventintel_pmu_check_counters_maskintel_pmu_assign_eventintel_check_pebs_isolationisolation_ucodesintel_pebs_aliases_ivbintel_pebs_aliases_sklbdw_limit_periodlbr_is_visibledefault_is_visibledev_attr_allow_tsx_force_abortmem_is_visibleevent_attr_mem_ld_auxevtsel_ext_is_visibleintel_pmu_check_event_constraints.part.0glc_limit_periodintel_snb_check_microcodepebs_ucodesintel_sandybridge_quirkintel_pmu_hw_config.part.0snoop_rsp_showintel_pmu_check_periodintel_pmu_bts_configcore_pmu_hw_configintel_pmu_hw_configintel_pebs_isolation_quirkintel_put_event_constraintscore_guest_get_msrshsw_hw_configadl_hw_configarl_h_hw_configx86_pmu_disable_event__intel_pmu_enable_all.constprop.0__intel_pmu_snapshot_branch_stackintel_pmu_snapshot_arch_branch_stackintel_pmu_enable_allintel_tfa_pmu_enable_allintel_tfa_commit_schedulingintel_pmu_nhm_enable_allnhm_magic.1icl_set_topdown_event_periodhandle_pmi_commoncore_pmu_enable_allintel_pmu_handle_irqwarned.0intel_pmu_disable_eventcheck_msrintel_pmu_cpu_startingintel_pmu_enable_eventintel_get_event_constraintshsw_get_event_constraintscounter2_constraintcmt_get_event_constraintsfixed0_constraintCSWTCH.474fixed0_counter0_1_constrainttnt_get_event_constraintsfixed0_counter0_constraintglp_get_event_constraintsicl_get_event_constraintstfa_get_event_constraintsglc_get_event_constraintsmtl_get_event_constraintscounters_1_7_constraintarl_h_get_event_constraintsadl_get_event_constraintsintel_pmu_cpu_prepareintel_pmu_cpu_deadintel_arch3_formats_attr__quirk.11westmere_hw_cache_event_idsnehalem_hw_cache_extra_regsintel_westmere_event_constraintsintel_westmere_extra_regsempty_attrsnhm_mem_events_attrsnhm_format_attrintel_core_event_constraintsintel_arch_formats_attrsnb_hw_cache_event_ids__quirk.8__quirk.7snb_hw_cache_extra_regsintel_snbep_extra_regsintel_snb_extra_regsintel_snb_event_constraintssnb_mem_events_attrssnb_events_attrsnehalem_hw_cache_event_idsintel_nehalem_event_constraintsintel_nehalem_extra_regs__quirk.9atom_hw_cache_event_idsintel_gen_event_constraintspmu_name_strgroup_format_extra_sklcore2_hw_cache_event_idsintel_core2_event_constraintshsw_hw_cache_event_ids__quirk.5__quirk.4hsw_hw_cache_extra_regshsw_tsx_events_attrshsw_mem_events_attrshsw_events_attrsintel_hsw_event_constraintshsw_format_attrslm_hw_cache_event_idsslm_hw_cache_extra_regsslm_events_attrsslm_format_attrintel_slm_event_constraintsintel_slm_extra_regs__quirk.3intel_bdw_event_constraintsglm_hw_cache_event_idsglm_hw_cache_extra_regsintel_glm_extra_regsglm_events_attrsskl_hw_cache_event_idsskl_hw_cache_extra_regsicl_events_attrsicl_td_events_attrsskl_format_attricl_tsx_events_attrsintel_icl_event_constraintsintel_icl_extra_regs__quirk.2event_attr_td_recovery_bubblesintel_skl_event_constraintsintel_skl_extra_regsglp_hw_cache_event_idstnt_events_attrstnt_hw_cache_extra_regsintel_tnt_extra_regsknl_hw_cache_extra_regsintel_knl_extra_regsintel_glc_extra_regsglc_hw_cache_event_idsglc_hw_cache_extra_regsintel_glc_event_constraintsglc_tsx_events_attrsglc_events_attrsglc_td_events_attrsintel_hybrid_pmu_type_mapmtl_hybrid_extra_attrmtl_hybrid_extra_attr_rtmintel_lnc_event_constraintsintel_lnc_extra_regsintel_grt_event_constraintsintel_grt_extra_regsintel_skt_event_constraintsintel_cmt_extra_regsadl_hybrid_tsx_attrsarl_h_hybrid_mem_attrsarl_h_hybrid_events_attrsgrt_mem_attrshybrid_group_events_tdhybrid_attr_updatehybrid_group_events_memhybrid_group_events_tsxhybrid_group_format_extraintel_v1_event_constraintsadl_hybrid_extra_attradl_hybrid_extra_attr_rtmadl_hybrid_mem_attrsadl_hybrid_events_attrsmtl_hybrid_mem_attrslnl_hybrid_events_attrscmt_events_attrscmt_format_attrintel_rwc_extra_regs__quirk.10__quirk.6intel_ivb_event_constraintsglp_hw_cache_extra_regsevent_attr_td_total_slots_scale_glmintel_v5_gen_event_constraintscounter1_constraint__UNIQUE_ID___addressable_fixup_ht_bug674group_caps_gengroup_caps_lbrgroup_format_evtsel_extgroup_defaulthybrid_group_cpusintel_hybrid_cpus_attrsdev_attr_cpusformat_attr_hybrid_offcore_rspformat_attr_hybrid_ldlatformat_attr_hybrid_frontendformat_attr_hybrid_snoop_rspformat_attr_hybrid_in_txformat_attr_hybrid_in_tx_cpevent_attr_tx_start_adlevent_attr_tx_abort_adlevent_attr_tx_commit_adlevent_attr_tx_capacity_read_adlevent_attr_tx_capacity_write_adlevent_attr_tx_conflict_adlevent_attr_cycles_t_adlevent_attr_cycles_ct_adlevent_attr_mem_ld_arl_hevent_attr_mem_st_arl_hevent_attr_mem_ld_adlevent_attr_mem_st_adlevent_attr_mem_ld_aux_adlevent_attr_slots_adlevent_attr_td_retiring_arl_hevent_attr_td_bad_spec_arl_hevent_attr_td_fe_bound_arl_hevent_attr_td_be_bound_arl_hevent_attr_td_heavy_ops_adlevent_attr_td_br_mis_adlevent_attr_td_fetch_lat_adlevent_attr_td_mem_bound_adlevent_attr_td_retiring_lnlevent_attr_td_bad_spec_adlevent_attr_td_fe_bound_lnlevent_attr_td_be_bound_lnlevent_attr_td_retiring_adlevent_attr_td_fe_bound_adlevent_attr_td_be_bound_adlintel_pmu_attrsformat_evtsel_ext_attrslbr_attrsintel_pmu_caps_attrsdev_attr_freeze_on_smidev_attr_pmu_namedev_attr_branchesdev_attr_branch_counter_nrdev_attr_branch_counter_widthevent_attr_tx_startevent_attr_tx_abortevent_attr_tx_commitevent_attr_tx_capacity_readevent_attr_tx_capacity_writeevent_attr_tx_conflictevent_attr_cycles_tevent_attr_cycles_ctevent_attr_slotsevent_attr_td_retiringevent_attr_td_bad_specevent_attr_td_fe_boundevent_attr_td_be_boundevent_attr_td_heavy_opsevent_attr_td_br_mispredictevent_attr_td_fetch_latevent_attr_td_mem_boundevent_attr_mem_ld_hswevent_attr_mem_st_sprevent_attr_el_startevent_attr_el_abortevent_attr_el_commitevent_attr_el_capacity_readevent_attr_el_capacity_writeevent_attr_el_conflictevent_attr_mem_st_hswevent_attr_tx_capacityevent_attr_el_capacityevent_attr_td_slots_issuedevent_attr_td_slots_retiredevent_attr_td_fetch_bubblesevent_attr_td_total_slotsevent_attr_td_total_slots_scaleevent_attr_td_recovery_bubbles_scaleformat_attr_frontendformat_attr_offcore_rspformat_attr_ldlatformat_attr_snoop_rspformat_attr_in_txformat_attr_in_tx_cpformat_attr_eventformat_attr_umaskformat_attr_edgeformat_attr_pcformat_attr_anyformat_attr_invformat_attr_cmaskformat_attr_umask2format_attr_eqformat_attr_metrics_clear__UNIQUE_ID___addressable___SCK__intel_pmu_update_topdown_event605.12__UNIQUE_ID___addressable___SCK__intel_pmu_update_topdown_event604.13__UNIQUE_ID___addressable___SCK__intel_pmu_set_topdown_event_period603.14__UNIQUE_ID___addressable___SCK__x86_pmu_set_period602.15__UNIQUE_ID___addressable___SCK__x86_pmu_update601.16__UNIQUE_ID___addressable___SCK__intel_pmu_update_topdown_event600.17__UNIQUE_ID___addressable___SCK__x86_pmu_set_period599.18__UNIQUE_ID___addressable___SCK__x86_pmu_update598.19event_attr_td_fe_bound_tntevent_attr_td_retiring_cmtevent_attr_td_bad_spec_cmtevent_attr_td_be_bound_tntevent_attr_mem_ld_grtevent_attr_mem_st_grtevent_attr_td_retiring_tntevent_attr_td_bad_spec_tntevent_attr_td_total_slots_glmevent_attr_td_fetch_bubbles_glmevent_attr_td_recovery_bubbles_glmevent_attr_td_slots_issued_glmevent_attr_td_slots_retired_glmevent_attr_td_total_slots_slmevent_attr_td_total_slots_scale_slmevent_attr_td_fetch_bubbles_slmevent_attr_td_fetch_bubbles_scale_slmevent_attr_td_slots_issued_slmevent_attr_td_slots_retired_slmevent_attr_mem_ld_snbevent_attr_mem_st_snbevent_attr_mem_ld_nhm__UNIQUE_ID___addressable___SCK__apic_call_write532.20.LC0__SCT__intel_pmu_set_topdown_event_periodx86_perf_event_set_period__SCT__intel_pmu_update_topdown_eventx86_perf_event_update__x86_return_thunkthis_cpu_offcpu_hw_events__tracepoint_write_msrintel_pmu_pebs_disable_allintel_pmu_lbr_disable_alldo_trace_write_msrintel_pmu_disable_btsx86_pmuboot_cpu_dataperf_is_hybrid_raw_spin_unlock_irqrestore_raw_spin_lock_irqsaveemptyconstraint_raw_spin_unlock_raw_spin_lockintel_event_sysfs_showx86_event_sysfs_showsnprintfnr_cpu_idsbitmap_print_to_pagebufkstrtoboolcpus_read_lock__cpu_online_maskon_each_cpu_cond_maskcpus_read_unlock__stack_chk_failkstrtoullmutex_lockmutex_unlocksprintfcpu_info__per_cpu_offset__max_smt_threadskfree_find_next_bitis_intel_pt_eventintel_pmu_lbr_swap_task_ctxintel_pmu_pebs_sched_taskintel_pmu_lbr_sched_taskperf_pmu_disableperf_pmu_enableintel_pmu_auto_reload_readintel_pmu_lbr_delintel_pmu_pebs_delintel_pmu_pebs_addintel_pmu_lbr_addfini_debug_store_on_cpux86_pmu_enable_event__warn_printkperf_report_aux_output_idx86_match_min_microcode_rev__sw_hweight64pcpu_hotx86_get_pmuperf_pmu_reschedmsr_set_bitmsr_clear_bit__x86_indirect_thunk_raxsysctl_perf_event_paranoidcapablesecurity_perf_event_openintel_pmu_setup_lbr_filterx86_add_exclusivehw_perf_lbr_event_destroyx86_pmu_hw_config__x86_indirect_thunk_r10intel_pmu_lbr_enable_allintel_pmu_enable_btsintel_pmu_lbr_readmemcpyintel_pmu_pebs_enable_all__tracepoint_read_msrdo_trace_read_msr__tracepoint_rdpmcdo_trace_rdpmc__SCT__x86_pmu_update__SCT__x86_pmu_set_periodperf_event_update_userpageirq_statperf_event_overflowintel_pt_interruptx86_pmu_stopintel_pmu_lbr_save_brstackintel_bts_disable_localintel_pmu_drain_bts_bufferintel_bts_interruptintel_bts_enable_local__x86_indirect_thunk_rdx__SCT__apic_call_writeperf_event_print_debugintel_pmu_pebs_disablelbr_from_signext_quirk_wrinit_debug_store_on_cpuintel_pmu_lbr_resetcpu_sibling_mapget_this_hybrid_cpu_typeget_this_hybrid_cpu_native_idcheck_hw_existsx86_pmu_show_pmu_capintel_pmu_pebs_enableintel_pmu_save_and_restartx86_get_event_constraintsunconstrainedvlbr_constraintintel_pebs_constraintsbts_constraintintel_cpuc_preparenuma_nodekmalloc_caches__kmalloc_cache_node_noprofintel_cpuc_finishintel_pmu_initx86_schedule_eventsintel_pmu_lbr_reset_64intel_pmu_lbr_read_64intel_pmu_lbr_saveintel_pmu_lbr_restoreintel_pmu_lbr_reset_32intel_pmu_lbr_read_32intel_ds_initintel_pmu_lbr_init_nhmintel_westmere_pebs_event_constraintsintel_pmu_pebs_data_source_nhmp6_pmu_initp4_pmu_initx86_pmu_handle_irqx86_pmu_disable_allintel_pmu_lbr_init_snbintel_snb_pebs_event_constraintsintel_nehalem_pebs_event_constraintsintel_pmu_lbr_init_atomintel_atom_pebs_event_constraintsintel_pmu_lbr_init__SCT__perf_snapshot_branch_stack__SCK__perf_snapshot_branch_stack__static_call_updateintel_pmu_lbr_init_coreintel_core2_pebs_event_constraintsintel_pmu_lbr_init_hswintel_hsw_pebs_event_constraintsintel_pmu_lbr_init_slmintel_slm_pebs_event_constraintsintel_bdw_pebs_event_constraintsintel_pmu_lbr_init_sklintel_glm_pebs_event_constraintsintel_icl_pebs_event_constraintsintel_pmu_pebs_data_source_skl__SCK__intel_pmu_update_topdown_event__SCK__intel_pmu_set_topdown_event_periodintel_skl_pebs_event_constraintsintel_pmu_lbr_init_knlintel_glc_pebs_event_constraints__kmalloc_large_noprofstatic_key_enablearl_h_latency_dataintel_lnc_pebs_event_constraintsintel_grt_pebs_event_constraintsintel_pmu_pebs_data_source_arl_hintel_pmu_pebs_data_source_grtgrt_latency_dataknc_pmu_initintel_pmu_arch_lbr_init__kmalloc_cache_noprofintel_pmu_pebs_data_source_adllnl_latency_dataintel_pmu_pebs_data_source_lnlintel_pmu_pebs_data_source_cmtcmt_latency_dataintel_pmu_pebs_data_source_mtlintel_ivb_pebs_event_constraintsevents_hybrid_sysfs_showdevice_show_stringevents_sysfs_show__SCK__x86_pmu_set_period__SCK__x86_pmu_updateevents_ht_sysfs_show__SCK__apic_call_write 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