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w+1҃HDH 1҃ uHǐI|$H_PHuHHHHH H[]A\A]A^A_DHH~uDHHkbaXHGL7NI~LwPMuL7HLHH ƃPMLuMt LIƃhHHLAI>DHHLDD$Dt$AADL'f.AWAVAUATUHSHHL?D$LD,aDIHI<$DHHDLADwCuQLeI|$LgPMHLHH t9v&t/HDH DuѾLLeHHgH@HLxAAIHHHHDHHHFHxt.HLHHH[]A\A]A^A_7LD,aDIHI>DHHDLAD%=v#`==t =u2\ ^t9=ux|$HH 1봐I|$LwPMt:HLHH sL'L7ff.@ATLUHLSHLHHH߉[]A\ATLUHSHLtHHH[]A\mLHސAWAVIAUATUHSL'HDL.Lqt ELHHh@HLHވlŅu]A$t-Apu"`ut[A$(tH[]A\A]A^A_ǃ`Nsff.ATUSH/HtOHHHHHtlH1HHH[]A\H}H_PHuHHHHH []A\H}LgPMt(HLHH ^L'fAWAVAUATIUSL?HLD,aDHHH}DHHDHAD%=`wB= =@ufLHLHLH[]A\A]A^A_=t?=u11=tHDH 1륾tվ눾끾wfAWAVAUATIUSL/HDL\HHH}\HH\HAC 1AsLD!HLHLH[]A\A]A^A_bfUHSHH?w HHHHH[]HHcH 1fDUHSHHHHHH[]@AWIAVAUATUHSHL'LAIHǁÀBI}HHLD$DLA )D$!AFOHLHHLH[]A\A]A^A_AWAVAUATIUHSH0L/eH%(HD$(1LHHHHT$HL$\HT$ HL$L\$BIHI>BHHBLAL$D!LLHHHD$(eH+%(uH0LH[]A\A]A^A_f.AWAVAUIATUSHH0L?eH%(HD$(1LLcD$ H HD$LH0HD$BlMiVUUUL$ I A)EkDHHDLD$D$L$ LDD$!C@)LHHHD$(eH+%(uH0LH[]A\A]A^A_zDHHt1@AWAVAUIATUHSH HHHAf`AEVAH IHI> HH LADuEEGAHHtHsHH 1[]A\A]A^A_AgADHAĄHHHBH9uBHtKH HL[]A\A]A^A_HPHBH9tD;uEGAHHtHvH>Hf` tH{H_PHuHHHH H []A\A]A^A_HIcH H IHI> HH LADZH IHI> HH LADH@IHI>@HH@LADDHLƉD$AAńt8EEGAHAAHtHsH H1[]A\A]A^A_HHD$wHAq EGAHHtHsH1D$D$Dt$HDt0Ls#EFAHHtHsH1H= IHǀHHf` H\$v AkHf` ADH1HA^AW.IPILHQRHHHLHI@HDHAdž`IdžIdžIdžIdžIdž IdžIdžIdž(Idž8Idž0Idž@IdžHIdžPIdžXIdžhIdžpIdžIdžIdžxAdž E1EHAfEAƆf` bIdžIdžIdžIdž`HHHf` wHILHf` DAAWAGAMAA@HD$t$HH$H $H9HL$t$HHt$H|$$H$HDAf` w $AAEM.AdžALD$f` w^D$jAuEAu;I(t,LMtIuH1AƆAELALAnDHHA f` (IdžLEAJ|$?AHH.@HLA1HAH []A\A]A^A_HD$HA}|$EEGAHHtHsHuP[1ABD87IdžIdžIdž`HEOAf` MDHD $D $1HAHPHHQIHNLRHHHi1|$tZ|$HEGAHHDIHLDHt HKHL$PHt$ H1t$YIdžLIdžIdžIdžCLLLL@HH$H $H9HL$@HHH|$@$$2|$1M.EHHIA$@LAHHLf` HIdžIdžHGIdž IIdžAIdžVHf`o%ALHHHEIIdžIdžIdžIdž`D$EO=APILHHAYAWAIDED$D$APHf` LH%HD$HAnIdžIdžIdžIdž`H}AGAAGHf` w`LA8PAGAAGHf` HH(HDHf` t EIdžH{HoPHuH/HHHH YD$HA tMIdžIdžIdžIdž`)L$H=`DH9tjIdžIdžIdžIdžIdž`EIdžIdžIdžIdžIdž`[Hf` (tbIdž`)DED$HmHf` AGADHf` IdžIdžIdžIdž`DH8IdžIdžIdžIdžIdž`1Hf` u DHoIdžIdžIdžIdž`drm_WARN_ON(!pll)%s %s: [drm] %slane_countMissing case (%s == %ld) drm_WARN_ON(n_entries < 1)port_clockenableddisabled[ENCODER:%d:%s] [CRTC:%d:%s] drm_WARN_ON(ret)disablecrtc_state->pipe_bpppipepll->info->ididclockpin_assignmenttmp & (7 << 12)drm_WARN_ON_ONCE(!trans)drm_WARN_ON(ctl & (1 << 9))drm_WARN_ON(!wakeref)Using signal levels %08x drm_WARN_ON(is_mst)Retry FEC enabling tmpdrm_WARN_ON(!pll_active)valencoder->portTC (TC)non-legacyyeslegacynoportPort %c strap not detected Port %c already claimed VBT says port %c has lspcon DDI %c/PHY %cDDI %s%c/PHY %s%cDDI %c%s/PHY %s%c&dig_port->hdcp_mutexdrm_WARN_ON(port > PORT_I)drivers/gpu/drm/i915/display/intel_ddi.cconn_state->connector->connector_typedrm_WARN_ON(n_entries > (sizeof(index_to_dp_signal_levels) / sizeof((index_to_dp_signal_levels)[0]) + ((int)sizeof(struct {_Static_assert(!(__builtin_types_compatible_p(typeof((index_to_dp_signal_levels)), typeof(&(index_to_dp_signal_levels)[0]))), "must be array");}))))drm_WARN_ON(dig_port->aux_wakeref)drm_WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))drm_WARN_ON(dig_port->ddi_io_wakeref)[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs Failed to set FEC_READY to %s in the sink Failed to clear FEC detected flags drm_WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))[drm] *ERROR* [CONNECTOR:%d:%s] Failed to read TMDS config: %d drm_WARN_ON(!dig_port->dp.attached_connector)[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio Failed to %s MSA_TIMING_PAR_IGNORE in the sink drm_WARN_ON(master == INVALID_TRANSCODER)[drm] *ERROR* Timeout waiting for DDI BUF %c to get active [drm] *ERROR* Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c drm_WARN_ON((pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))drm_WARN_ON(!intel_tc_port_in_legacy_mode(dig_port))No pipe for [ENCODER:%d:%s] found Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x) Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b %02x) [drm] *ERROR* [ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x) [drm] *ERROR* Timeout waiting for DDI BUF %c to get idle drm_WARN_ON(transcoder_is_dsi(cpu_transcoder))drm_WARN_ON(crtc_state->limited_color_range && crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)Quirk Increase DDI disabled time drm_WARN_ON(ddi_mode == (3 << 24))%s %s: [drm] Unsupported voltage swing/pre-emphasis level: 0x%x drm_WARN_ON_ONCE(level >= n_entries)[drm] *ERROR* Invalid I_boost value %u drm_WARN_ON(port_mask & ((((1UL))) << (other_encoder->port)))[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it [drm] *ERROR* Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c [drm] *ERROR* Timed out waiting for DP idle patterns [drm] *ERROR* Timed out waiting for ACT sent [drm] *ERROR* Timeout waiting for FEC live state to get %s Failed waiting for FEC %s to get detected: %d (status %d) [drm] *ERROR* Failed to enable FEC after retries drm_WARN_ON(crtc_state->has_pch_encoder)drm_WARN_ON(is_mst && (port == PORT_A || port == PORT_E))drm_WARN_ON(is_mst && port == PORT_A)[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio drm_WARN_ON(((&_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display))->info.__runtime_info)->ip.ver) < 9)drm_WARN_ON(port < PORT_A || port > PORT_E)drm_WARN_ON(!(intel_ddi_splitter_pipe_mask(i915) & ((((1UL))) << (pipe))))%s %s: [drm] Invalid splitter configuration, dss1=0x%08x drm_WARN_ON(crtc_state->master_transcoder != INVALID_TRANSCODER && crtc_state->sync_mode_slaves_mask)%s %s: [drm] Platform does not support DSI PORT %c / PHY %c reserved by HTI VBT says port %c is not DVI/HDMI/DP compatible, respect it SNPS PHY %c failed to calibrate, proceeding anyway Forcing DDI_A_4_LANES for port A VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s  U ^ ` F     l    A     %    N "  z  l ,          C  b  5 " 2 / C = ;  U  X z     q    `@   i915.import_ns=PWMGCC: (Debian 12.2.0-14) 12.2.0GNU &0c?RR Lph @DWl:@uYuc`   /  /@ MYmP0 Gp.@vGsb`s}s0  ! $@@%T0&j&'p()\)+@-0.:@/"O0i2a4'@6P8 90;%p=?;)BEWhy ]Q`hBk+qKzj{0}AP# @&P<PSph }$  =P 0+ p> 0ZQ ,j }  + @(   * b         7 H Z p       ! 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