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=BbH3D$$ED$ADL$(HtHvPH1McMoH|$L$$H߉D$HXDAh,BlLA+hLEDD$AH;HHHHXHߋh,Bl +hLH;HHHHXHߋh,Bl +hLH;HHHHXHߋh,Bl +hLH; HHHHXHߋh,Bl +hLH; HHHHXHߋh,Bl +hLH;HHHHXHߋh,Bl +hLH;HHHB,@`HH;Dl$HHDH߃HH;DHHH߽`DD$ZHXAA@,EE~ CTd,`D$(HDH;DDHHADHHXHD`,ADH;DDHHDHHXHD`,ADH;1DHHDH HXHD`,ADH;DDHHDHHXHD`,ADH;DDHHDHHXHD`,ADH;1DHHHD AfHXHMg h,Bl0+h0H;HHHHXHߋh,B,+h0H;1҉HHH߉H<$HD$8eH+%(uOH@[]A\A]A^A_HHxHoPHuH/HHHH ff.fAWAVAUATUHSHHLwMt LIƋM&HLH)HU HLhp$f`HHzLLAHH谫Aiu)A$@4$LHHLf`t 4$1LI$HHxvA$ $H[]A\A]A^A_IEA`1L8LLLHX@,0D$t$HHD$HL$H9HL$t$HHt$H|$D$MDD$LtIwH1LLHX@,0D$t$IHI?t$1HHt$LR4$HL[]A\A]A^A_HL]4$LML}ff.fAVAUAATUSHH3EEAIHtHvH1HXHߋh,ŀH;HHHAEHXHߋh,h4ŀ+h0H;HHHAEsHXHߋh,h8ŀ+h0H;HHHAE[HXHߋh,ŀH;HHHAA'HHXHߋh,hlŀ+hhH;HHHAA'/HXIcHLr h,l0+h0H;1҉HHHHXHߋh,B,+h0H;1҉HHH߽`LHXD`,E~ CDm,`AHDH;DHHDHHXHh,H;1HHH[]A\A]A^HHxHoPHuH/HHHH 9HHxHoPHuH/HHHH QHHxHoPHuH/HHHH iHHxHoPHuH/HHHH |HHxHoPHuH/HHHH ff.SHeH%(HD$1HH$HD$ H u=HHHtUH tH tH{@H tH HX HHHuHHD$eH+%(u H[fDSHf`w1[H[onoff73infoframeexpected: found: %s %s: [drm] %sUsing %s as Y plane for %s linked->idMissing case (%s == %ld) crtc_state->pipe_bppdrm_WARN_ON(active)tmpczclkCZ clock rate: %d kHz yesnodig_port->base.portenabling pipe %c disabling pipe %c drm_WARN_ON(ret)drm_WARN_ON(disable_pipes)enableddisableddrm_WARN_ON(crtc->active)C10C20(expected %s, found %s)hw.enablehw.active(expected %i, found %i)cpu_transcodermst_master_transcoderhas_pch_encoderfdi_lanesfdi_m_nlane_countlane_lat_optim_maskdp_m_ndp_m2_n2output_typesframestart_delaymsa_timing_delayhw.pipe_mode.crtc_hdisplayhw.pipe_mode.crtc_htotalhw.pipe_mode.crtc_hblank_endhw.pipe_mode.crtc_hsync_starthw.pipe_mode.crtc_hsync_endhw.pipe_mode.crtc_vdisplayhw.pipe_mode.crtc_vsync_starthw.pipe_mode.crtc_vsync_endhw.pipe_mode.crtc_vtotalhw.pipe_mode.crtc_vblank_endhw.adjusted_mode.crtc_htotalhw.adjusted_mode.crtc_vtotalpixel_multiplier(%x) (expected %i, found %i)hw.adjusted_mode.flagsoutput_formathas_hdmi_sinklimited_color_rangehdmi_scramblinghdmi_high_tmds_clock_ratiohas_infoframeenhanced_framingfec_enablehas_audiobuffereldexpected: found: gmch_pfit.controlgmch_pfit.pgm_ratiosgmch_pfit.lvds_border_bitspch_pfit.force_thrupipe_src.x1pipe_src.x2pipe_src.y1pipe_src.y2pch_pfit.enabledpch_pfit.dst.x1pch_pfit.dst.x2pch_pfit.dst.y1pch_pfit.dst.y2scaler_state.scaler_idpixel_rategamma_modecgm_modecsc_modegamma_enablecsc_enablewgc_enablelinetimeips_linetimepre_csc_lutpost_csc_lutcsc.preoff[0]csc.preoff[1]csc.preoff[2]csc.coeff[0]csc.coeff[1]csc.coeff[2]csc.coeff[3]csc.coeff[4]csc.coeff[5]csc.coeff[6]csc.coeff[7]csc.coeff[8]csc.postoff[0]csc.postoff[1]csc.postoff[2]output_csc.preoff[0]output_csc.preoff[1]output_csc.preoff[2]output_csc.coeff[0]output_csc.coeff[1]output_csc.coeff[2]output_csc.coeff[3]output_csc.coeff[4]output_csc.coeff[5]output_csc.coeff[6]output_csc.coeff[7]output_csc.coeff[8]output_csc.postoff[0]output_csc.postoff[1]output_csc.postoff[2]has_psrhas_sel_updateenable_psr2_sel_fetchenable_psr2_su_region_ethas_panel_replaydouble_wide(expected %p, found %p)shared_dpll dpll_hw_statedpll_hw_state.cx0plldsi_pll.ctrldsi_pll.divpipe_bpphw.pipe_mode.crtc_clockhw.adjusted_mode.crtc_clockport_clockmin_voltage_levelinfoframes.enableinfoframes.gcpavispdhdmidrmdp vsc sdpvscdp as sdpas_sdpsync_mode_slaves_maskmaster_transcoderjoiner_pipesdsc.config.block_pred_enabledsc.config.convert_rgbdsc.config.simple_422dsc.config.native_422dsc.config.native_420dsc.config.vbr_enabledsc.config.line_buf_depthdsc.config.bits_per_componentdsc.config.pic_widthdsc.config.pic_heightdsc.config.slice_widthdsc.config.slice_heightdsc.config.initial_dec_delaydsc.config.initial_xmit_delaydsc.config.flatness_min_qpdsc.config.flatness_max_qpdsc.config.slice_bpg_offsetdsc.config.nfl_bpg_offsetdsc.config.initial_offsetdsc.config.final_offsetdsc.config.rc_model_sizedsc.config.slice_chunk_sizedsc.config.nsl_bpg_offsetdsc.compression_enabledsc.num_streamsdsc.compressed_bpp_x16splitter.enablesplitter.link_countsplitter.pixel_overlapvrr.enablevrr.vminvrr.vmaxvrr.fliplinevrr.pipeline_fullvrr.guardbandvrr.vsync_startvrr.vsync_end(expected %lli, found %lli)cmrr.cmrr_mcmrr.cmrr_ncmrr.enablemodesetfastset[CRTC:%d:%s] not active conn_state->max_bpcfaileddrm_WARN_ON(modeset_pipes)drm_WARN_ON(update_pipes)probing SDVOB probing HDMI on SDVOB probing SDVOC probing HDMI on SDVOC ABCDEDPDSI ADSI C%s %s: [drm] %s assertion failure (expected %s, current %s) drivers/gpu/drm/i915/display/intel_display.c[drm] *ERROR* %s assertion failure (expected %s, current %s) [CRTC:%d:%s] fastset requirement not met in %s %pV [CRTC:%d:%s] mismatch in %s %pV drm_WARN_ON(linked_plane_state->planar_linked_plane != plane)drm_WARN_ON(linked_plane_state->planar_slave == plane_state->planar_slave)Need %d free Y planes for planar YUV [CRTC:%d:%s] Full modeset due to %s drm_WARN_ON(pipe != crtc->pipe)drm_WARN_ON(expected_secondary_pipes(primary_ultrajoiner_pipes, 3) != secondary_ultrajoiner_pipes)drm_WARN_ON((primary_ultrajoiner_pipes & secondary_ultrajoiner_pipes) != 0)drm_WARN_ON((primary_uncompressed_joiner_pipes & secondary_uncompressed_joiner_pipes) != 0)drm_WARN_ON((primary_bigjoiner_pipes & secondary_bigjoiner_pipes) != 0)%s %s: [drm] Ultrajoiner pipes(%#x) should be bigjoiner pipes(%#x) %s %s: [drm] Wrong secondary ultrajoiner pipes(expected %#x, current %#x) %s %s: [drm] Uncompressed joiner pipes(%#x) and bigjoiner pipes(%#x) can't intersect %s %s: [drm] Wrong secondary bigjoiner pipes(expected %#x, current %#x) %s %s: [drm] Wrong secondary uncompressed joiner pipes(expected %#x, current %#x) %s %s: [drm] Wrong ultrajoiner secondary pipes for primary_pipe %#x (expected %#x, current %#x) %s %s: [drm] Wrong uncompressed joiner secondary pipes for primary_pipe %#x (expected %#x, current %#x) %s %s: [drm] Wrong bigjoiner secondary pipes for primary_pipe %#x (expected %#x, current %#x) %s %s: [drm] unknown pipe linked to transcoder %s drm_WARN_ON(has_edp_transcoders(enabled_transcoders) + has_dsi_transcoders(enabled_transcoders) + has_pipe_transcoders(enabled_transcoders) > 1)drm_WARN_ON(!has_dsi_transcoders(enabled_transcoders) && !is_power_of_2(enabled_transcoders))drm_WARN_ON((tmp & ((u32)(((((1UL))) << (26)) + ((int)(sizeof(struct { int:(-!!((sizeof(int) == sizeof(*(8 ? ((void *)((long)(26) * 0l)) : (int *)8))) && ((26) < 0 || (26) > 31))); })))))) == 0)%s %s: [drm] %s change in progress [CRTC:%d:%s] Odd pipe source width not supported with double wide pipe [CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS [CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s) %s %s: [drm] transcoder %s assertion failure (expected %s, current %s) [drm] *ERROR* transcoder %s assertion failure (expected %s, current %s) drm_WARN_ON(__intel_de_read(_Generic(dev_priv, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(dev_priv)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(dev_priv)), const struct intel_display *: (dev_priv), struct intel_display *: (dev_priv)), ((const i915_reg_t){ .reg = (((_Generic(dev_priv, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(dev_priv)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(dev_priv)), const struct intel_display *: (dev_priv), struct intel_display *: (dev_priv))->info.__device_info)->mmio_offset) + 0x61230) })) & ((u32)(((((1UL))) << (31)) + ((int)(sizeof(struct { int:(-!!((sizeof(int) == sizeof(*(8 ? ((void *)((long)(31) * 0l)) : (int *)8))) && ((31) < 0 || (31) > 31))); }))))))%s %s: [drm] timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x drm_WARN_ON(!IS_PLATFORM(dev_priv, INTEL_I830))%s %s: [drm] pipe_off wait timed out Disabling [PLANE:%d:%s] on [CRTC:%d:%s] %s %s: [drm] %d encoders for pipe %c drm_WARN_ON(!intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF))SSC %s by BIOS, overriding VBT which says %s drm_WARN_ON(crtc_state->limited_color_range && crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)(expected tu %i data %i/%i link %i/%i, found tu %i, data %i/%i link %i/%i)(expected 0x%08x, found 0x%08x)hw.pipe_mode.crtc_hblank_starthw.pipe_mode.crtc_vblank_starthw.adjusted_mode.crtc_hdisplayhw.adjusted_mode.crtc_hblank_starthw.adjusted_mode.crtc_hblank_endhw.adjusted_mode.crtc_hsync_starthw.adjusted_mode.crtc_hsync_endhw.adjusted_mode.crtc_vdisplayhw.adjusted_mode.crtc_vblank_starthw.adjusted_mode.crtc_vsync_starthw.adjusted_mode.crtc_vsync_endhw.adjusted_mode.crtc_vblank_endhw_state doesn't match sw_statedsc.config.scale_decrement_intervaldsc.config.scale_increment_intervaldsc.config.initial_scale_valuedsc.config.first_line_bpg_offsetdsc.config.rc_quant_incr_limit0dsc.config.rc_quant_incr_limit1dsc.config.second_line_bpg_offset[CRTC:%d:%s] modeset required [CRTC:%d:%s] async flip disallowed with joiner [PLANE:%d:%s] async flip not supported [PLANE:%d:%s] no old or new framebuffer drm_WARN_ON(intel_crtc_is_joiner_secondary(new_crtc_state))[CONNECTOR:%d:%s] Limiting display bpp to %d (EDID bpp %d, max requested bpp %d, max platform bpp %d) [CRTC:%d:%s] Link bpp limited to %d.%04d [ENCODER:%d:%s] rejecting invalid cloning configuration [ENCODER:%d:%s] config failure: %d [CRTC:%d:%s] config failure: %d [CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i drm_WARN_ON(new_crtc_state->uapi.enable)drm_WARN_ON(primary_crtc->pipe != joiner_primary_pipe(primary_crtc_state))[CRTC:%d:%s] Cannot act as joiner primary (need 0x%x as pipes, only 0x%x possible) [CRTC:%d:%s] secondary is enabled as normal CRTC, but [CRTC:%d:%s] claiming this CRTC for joiner. [CRTC:%d:%s] Used as secondary for joiner primary [CRTC:%d:%s] [CRTC:%d:%s] fastset requirement not met, forcing full modeset drm_WARN_ON(!connector_state->crtc)drm_WARN_ON(!((_Generic(to_i915(dev), const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(to_i915(dev))), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(to_i915(dev))), const struct intel_display *: (to_i915(dev)), struct intel_display *: (to_i915(dev)))->info.__device_info)->has_ddi))rejecting conflicting digital port configuration [PLANE:%d:%s] atomic driver check failed [CRTC:%d:%s] watermarks are invalid [CRTC:%d:%s] atomic driver check failed [CRTC:%d:%s] Active planes cannot be in async flip drm_WARN_ON(new_crtc_state->do_async_flip && !plane->async_flip)[PLANE:%d:%s] Modifier 0x%llx does not support async flip on display ver %d [PLANE:%d:%s] Modifier 0x%llx does not support async flip [PLANE:%d:%s] Planar formats do not support async flips [PLANE:%d:%s] Stride cannot be changed in async flip [PLANE:%d:%s] Modifier cannot be changed in async flip [PLANE:%d:%s] Pixel format cannot be changed in async flip [PLANE:%d:%s] Rotation cannot be changed in async flip [PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip [PLANES:%d:%s] Alpha value cannot be changed in async flip [PLANE:%d:%s] Pixel blend mode cannot be changed in async flip [PLANE:%d:%s] Color encoding cannot be changed in async flip [PLANE:%d:%s] Color range cannot be changed in async flip [PLANE:%d:%s] Decryption cannot be changed in async flip drm_WARN_ON(intel_crtc_needs_modeset(new_crtc_state) && intel_crtc_needs_fastset(new_crtc_state))drm_WARN_ON(adjusted_mode->flags & (1<<4))drm_WARN_ON(skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, entries, I915_MAX_PIPES, pipe))Preparing state failed with %i %s %s: [drm] Platform does not support port %c drm_WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154)enabling pipe %c due to force quirk (vco=%d dot=%d) disabling pfit, current: 0x%08x disabling pipe %c due to force quirk drm_WARN_ON(__intel_de_read(_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display)), ((const i915_reg_t){ .reg = ((_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display))->info.__device_info)->pipe_offsets[(PLANE_A)] - (_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display))->info.__device_info)->pipe_offsets[PIPE_A] + ((_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display))->info.__device_info)->mmio_offset) + (0x70180)) })) & ((u32)(((((1UL))) << (31)) + ((int)(sizeof(struct { int:(-!!((sizeof(int) == sizeof(*(8 ? ((void *)((long)(31) * 0l)) : (int *)8))) && ((31) < 0 || (31) > 31))); }))))))drm_WARN_ON(__intel_de_read(_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display)), ((const i915_reg_t){ .reg = ((_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display))->info.__device_info)->pipe_offsets[(PLANE_B)] - (_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display))->info.__device_info)->pipe_offsets[PIPE_A] + ((_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display))->info.__device_info)->mmio_offset) + (0x70180)) })) & ((u32)(((((1UL))) << (31)) + ((int)(sizeof(struct { int:(-!!((sizeof(int) == sizeof(*(8 ? ((void *)((long)(31) * 0l)) : (int *)8))) && ((31) < 0 || (31) > 31))); }))))))drm_WARN_ON(__intel_de_read(_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display)), ((const i915_reg_t){ .reg = ((_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display))->info.__device_info)->pipe_offsets[(PLANE_C)] - (_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display))->info.__device_info)->pipe_offsets[PIPE_A] + ((_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display))->info.__device_info)->mmio_offset) + (0x70180)) })) & ((u32)(((((1UL))) << (31)) + ((int)(sizeof(struct { int:(-!!((sizeof(int) == sizeof(*(8 ? ((void *)((long)(31) * 0l)) : (int *)8))) && ((31) < 0 || (31) > 31))); }))))))drm_WARN_ON(__intel_de_read(_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display)), ((const i915_reg_t){ .reg = ((_Generic((display), const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)((display))), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)((display))), const struct intel_display *: ((display)), struct intel_display *: ((display)))->info.__device_info)->cursor_offsets[((PIPE_A))] - (_Generic((display), const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)((display))), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)((display))), const struct intel_display *: ((display)), struct intel_display *: ((display)))->info.__device_info)->cursor_offsets[PIPE_A] + ((_Generic((display), const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)((display))), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)((display))), const struct intel_display *: ((display)), struct intel_display *: ((display)))->info.__device_info)->mmio_offset) + (0x70080)) })) & 0x27)drm_WARN_ON(__intel_de_read(_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display)), ((const i915_reg_t){ .reg = ((_Generic((display), const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)((display))), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)((display))), const struct intel_display *: ((display)), struct intel_display *: ((display)))->info.__device_info)->cursor_offsets[((PIPE_B))] - (_Generic((display), const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)((display))), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)((display))), const struct intel_display *: ((display)), struct intel_display *: ((display)))->info.__device_info)->cursor_offsets[PIPE_A] + ((_Generic((display), const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)((display))), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)((display))), const struct intel_display *: ((display)), struct intel_display *: ((display)))->info.__device_info)->mmio_offset) + (0x70080)) })) & 0x27)   r   8        &   5  h   ' J |     5         u q 0 C !      | } 3 Q K U _ ^  ! ! ! ! ! ! $$$$$i915.import_ns=PWMGCC: (Debian 12.2.0-14) 12.2.0GNU|)G@a} _*0  6L ej` |@PD ] 8Kgpm@z %l@Xp!#%, 87?KA> _@8jOW[h_b.wlp~P 9` R@ b`WдH0&,,(12 0@010I0[0nU@)BS\n| 1@\n  * E f       ' A R b s       % 9 P g z       > T k ~   Se  @T T   US  V9 PV!Q VJq VE PWO    pY2Y..ZUPpZUuZ+ [,`[,[( 7O`_ k_E~`+ eof 6PjPlZp!qVpqVq-+ r$@`rWZkr; ssq)?PueZ|uvPw4G\u5Nmp Pp.@RpGcІx!@/zPp,(Kp#;Md{ 9Qj6Rp #=Qe(GUlLm+Hb{gZ $5EYzY0t!0F0]@k `?Y  0& 5 L c | ; P3     !!/!M!h!!!!`!!" "7"I"qa":","""" #.#D#a#z###### $($E$a$$$$$$%%;%[%m%~%%%%%%&-&E&_&,u|&&&&& ''0'C'\'{'''8v''( (C(j((((((P;));r%)< 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sintel_vrr_set_transcoder_timingsintel_color_commit_noarmintel_crtc_planes_update_noarm__x86_indirect_thunk_r9intel_dpt_configureilk_pfit_disableintel_set_pch_fifo_underrun_reportingintel_crtc_vblank_offilk_pch_disableilk_pch_post_disableintel_phy_is_combointel_phy_is_tcintel_phy_is_snpsintel_port_to_phyintel_port_to_tcintel_encoder_to_phyintel_encoder_is_combointel_encoder_is_snpsintel_encoder_is_tcintel_encoder_to_tcintel_aux_power_domainintel_tc_port_in_tbt_alt_modeintel_display_power_legacy_aux_domainintel_display_power_tbt_aux_domainintel_modeset_get_crtc_power_domains__bitmap_andnotintel_display_power_get_in_setintel_color_prepare_commiti915_fence_context_timeoutdma_fence_wait_timeoutdma_fence_releaseintel_fb_rc_ccs_cc_planeintel_fb_bointel_bo_read_from_pageintel_dsb_prepareintel_dsb_vblank_evadeintel_color_commit_armintel_crtc_planes_update_armintel_dsb_chainintel_dsb_finishdrm_atomic_helper_wait_for_dependenciesdrm_dp_mst_atomic_wait_for_dependenciesintel_atomic_global_state_wait_for_dependenciesintel_display_power_getintel_overlay_switch_offintel_frontbuffer_flipdrm_vblank_work_flush_allintel_pmdemand_pre_plane_updateintel_sagv_pre_plane_update_raw_spin_lock_irqdrm_crtc_send_vblank_event_raw_spin_unlock_irqintel_dbuf_pre_plane_updateintel_program_dpkgc_latencyintel_wait_for_vblank_workersdrm_atomic_helper_wait_for_flip_doneintel_dsb_waitintel_color_wait_commitintel_dbuf_post_plane_updateintel_psr_post_plane_updateintel_fbc_post_updateintel_color_post_updateintel_modeset_verify_crtchsw_ips_post_updateintel_drrs_activateintel_check_cpu_fifo_underrunsintel_check_pch_fifo_underrunsintel_sagv_post_plane_updateintel_pmdemand_post_plane_updatedrm_atomic_helper_commit_hw_doneintel_atomic_global_state_commit_doneintel_runtime_pm_put_uncheckedqueue_work_onintel_dsb_wait_vblanksintel_dsb_wait_vblank_delayintel_dsb_interruptintel_optimize_watermarksintel_dp_mst_is_slave_transintel_uncore_arm_unclaimed_mmio_detectionintel_set_cdclk_post_plane_updatedrm_atomic_helper_update_legacy_modeset_stateintel_set_cdclk_pre_plane_updateintel_modeset_verify_disabledintel_modeset_put_crtc_power_domainsintel_encoder_destroydrm_encoder_cleanupkfreeintel_encoder_get_configintel_link_compute_m_nintel_dp_link_symbol_clockintel_dp_effective_data_ratedrm_dp_max_dprx_data_rateintel_panel_sanitize_sscintel_zero_m_nintel_set_m_nintel_cpu_transcoder_has_m2_n2intel_cpu_transcoder_set_m1_n1intel_cpu_transcoder_set_m2_n2intel_dmc_enable_pipeintel_enable_shared_dpllintel_dsc_enableskl_pfit_enableintel_color_modesetintel_uncompressed_joiner_enablei9xx_set_pipeconfi9xx_enable_pllintel_crtc_vblank_onvlv_enable_pllchv_enable_pllilk_set_pipeconfassert_fdi_tx_disabledassert_fdi_rx_disabledilk_pch_pre_enableilk_pch_enablebdw_get_pipe_misc_bppilk_get_lanes_requiredintel_get_m_nintel_cpu_transcoder_get_m1_n1intel_cpu_transcoder_get_m2_n2intel_crtc_get_pipe_configintel_dotclock_calculateintel_dp_link_symbol_sizeintel_crtc_dotclockintel_encoder_current_modekmalloc_caches__kmalloc_cache_noprofintel_crtc_state_allocintel_crtc_destroy_stateintel_fuzzy_clock_checkintel_pipe_config_compare__drm_printfn_dbgintel_dpll_compare_hw_stateintel_hdmi_infoframe_enabledrm_dp_vsc_sdp_logdrm_dp_as_sdp_log__drm_printfn_errintel_cx0pll_compare_hw_stateintel_cx0pll_dump_hw_stateintel_dpll_dump_hw_statedrm_print_hex_dumpintel_color_lut_equalintel_modeset_pipes_in_mask_earlyintel_atomic_get_crtc_stateintel_modeset_all_pipes_lateintel_modeset_commit_pipesdrm_atomic_state_allocdrm_atomic_commitintel_calc_active_pipesintel_atomic_add_affected_planesintel_atomic_checkintel_display_driver_check_accessintel_vrr_check_modesetdrm_atomic_helper_check_modesetintel_link_bw_init_limitsintel_link_bw_set_bpp_limit_for_pipeintel_crtc_state_dumpintel_fdi_add_affected_crtcsintel_crtc_free_hw_statedrm_mode_get_hv_timingintel_vrr_compute_config_lateintel_link_bw_atomic_checkkmemdup_noprofdrm_mode_set_crtcinfointel_release_shared_dpllsdrm_connector_list_iter_begindrm_connector_list_iter_nextdrm_connector_list_iter_endintel_dp_mst_crtc_needs_modesetintel_plane_atomic_checkintel_compute_global_watermarksintel_bw_atomic_checkintel_cdclk_atomic_checkintel_any_crtc_needs_modesetintel_modeset_calc_cdclkintel_pmdemand_atomic_checkintel_dpll_crtc_get_shared_dpllintel_color_checkintel_wm_computeskl_update_scaler_crtcintel_atomic_setup_scalershsw_ips_compute_confighsw_crtc_supports_ipsintel_atomic_get_cdclk_stateintel_psr2_sel_fetch_updateintel_fbc_atomic_checkintel_color_assert_lutsskl_watermark_ipc_enabledintel_crtc_arm_fifo_underrunintel_crtc_prepare_vblank_eventintel_dsb_commitintel_pipe_update_startintel_psr2_program_trans_man_trk_ctlintel_atomic_update_watermarksintel_pipe_update_endintel_vrr_enableskl_detach_scalers__x86_indirect_thunk_r11intel_dbuf_mbus_pre_ddb_updateskl_ddb_allocation_overlapsintel_dbuf_mbus_post_ddb_updateintel_atomic_commitintel_runtime_pm_getdrm_atomic_helper_prepare_planesdrm_atomic_helper_setup_commitdrm_atomic_helper_unprepare_planesintel_atomic_global_state_setup_commitdrm_atomic_helper_swap_stateintel_atomic_swap_global_stateintel_shared_dpll_swap_stateintel_frontbuffer_track__flush_workqueueintel_plane_destroydrm_plane_cleanupassert_port_validintel_setup_outputsintel_pps_unlock_regs_waintel_dp_is_port_edpintel_bios_is_port_presentg4x_dp_initvlv_dsi_initintel_init_pch_refclkdrm_helper_move_panel_connectors_to_headintel_crt_initintel_sdvo_initg4x_hdmi_initintel_tv_initintel_ddi_initintel_bios_for_each_encoderintel_lvds_initintel_dvo_initintel_mode_validintel_cpu_transcoder_mode_validintel_mode_valid_max_plane_sizeintel_init_display_hooksintel_initial_commitdrm_modeset_acquire_initdrm_atomic_add_affected_planesdrm_atomic_state_cleardrm_modeset_backoffdrm_modeset_drop_locksdrm_modeset_acquire_finii830_enable_pipei9xx_calc_dpll_paramsi9xx_dpll_compute_fp__const_udelayvlv_disable_plli9xx_disable_pllchv_disable_plli830_disable_pipeintel_hpd_poll_finicancel_work_syncdrm_mode_object_putcancel_delayed_work_syncintel_scanout_needs_vtd_wai9xx_get_initial_plane_configi9xx_fixup_initial_plane_configskl_get_initial_plane_configskl_fixup_initial_plane_config__SCK__tp_func_i915_reg_rw__SCK__preempt_schedule_notraceQQUQQRQ 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