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HAŃvHIA҃D$H0QƉ$H;4$IHL4$LI4$HLD$HxHWPHuHH$H$HHH hff.AWAVAUAATLXUSHH`Ƈ0H/f HH#GuGf G nG fG t 1PH@ @HH(L LHp LHIKL3u KLHLHuNHPLHIKLu KLHLPL4H0~)HHH HHc4H+0HH9|Lƃ0H[]A\A]A^A_@HHHHxLoPMuL/HLHH LHHILHIH3HtHvH1LHLHLL3L2LLAAAHILHHILHǃ8I¸m<LHƃ=D8H3HtHvH1LH'11PH@pLHHHHHHLHL3Lf` mLEHs@H;@HH@HAA tH;HtHHExhA0H;HtHHHHxLoPMt(HLHH *L/H;HtHH{@bHH;@bHH@bHAD1D8A A Aƃ=D8HXHDx,A`DH;DHHDHAD 8 AAAt AD 81LH!HH;!HH!HAAH߉t$t$~D88JHHxLoPMuL/LHH fAUATUSH/HHLJHL t6HHHǃ(uN[L]A\A]HLJPLp LHKLLH+느HHxH_PHuHHHHH [L]A\A]fATLXUHLSHc4H0HH HHxbH@uLCuEHHt6HHuIHtHv1HHHH H;0y[L]A\f.USHHLJHHp HHKHH []fDAUATUHSHHHu]H LHp HIKLu KLHLH[]A\A]H{LgPMuL'HLHH jAWAVAUATUSL'HHLJHM$p M$LM$ KLbLL@u @tbL`f wCHH#Cu f ƃ1[]A\A]A^A_ptH0HHǃPLKLLLiHO[L]A\A]A^A_=piHH;1f` wPHHXHH߾HHH 1HAUATUS1HH/ugHHuyH LHp HIKLu KLHLH[]A\A]ƃ1[]A\A]H}LgPMt(HLHH QL'fU@SHH/f` wHH#CtHP=v'[]fC tHBP=wH HHH} HHHH߾  HH[ ]fATUSf` HH/wHH#Gt,HHP=vZH[]A\fG t1HtHuH1HHHP=wH IHI<$ HHHH $HL H[]A\ ff.Sf` Hw0HH#GufG u4[puH[iH[H[[ff.USf` HwPHH#GufG uf[]H߾Ht@tH[]H߾Ht@uAtH/1HtHuH1HHH[]H[]f.AWLp AVAUIATILUSHHLHA$L E1IcHI$H HHL1HH HHLt7HHsA HHLHHLuAE9$L t[L]A\A]A^A_ff.@UHHSiHtPLt +[]HHxH_PHt/HHHH []HUHHSHtPLt +[]HHxH_PHt/HHHH []HUHHSHtPLt +X[]HHxH_PHt/HHHH /[]HfDUHHS艾HtPLt +X[]HHxH_PHt/HHHH 5[]HfDUHHSHtP Lt +X[]HHxH_PHt/HHHH A[]Hdrm_WARN_ON(power_domains->async_put_wakeref)drivers/gpu/drm/i915/display/intel_display_power.cdrm_WARN_ON(!queue_delayed_work(system_unbound_wq, &power_domains->async_put_work, msecs_to_jiffies(delay_ms)))%s %s: [drm] Use count on domain %s is already zero %s %s: [drm] Async disabling of domain %s is pending %s %s: [drm] ISP not power gated [drm] *ERROR* LCPLL not locked yet [drm] *ERROR* Switching back to LCPLL failed %s %s: [drm] CRTC for pipe %c enabled [drm] *ERROR* CRTC for pipe %c enabled %s %s: [drm] Display power well on [drm] *ERROR* Display power well on %s %s: [drm] CPU PWM1 enabled [drm] *ERROR* CPU PWM1 enabled %s %s: [drm] CPU PWM2 enabled [drm] *ERROR* CPU PWM2 enabled %s %s: [drm] PCH PWM1 enabled [drm] *ERROR* PCH PWM1 enabled %s %s: [drm] Utility pin enabled in PWM mode [drm] *ERROR* Utility pin enabled in PWM mode [drm] *ERROR* PCH GTC enabled [drm] *ERROR* Switching to FCLK failed [drm] *ERROR* LCPLL still locked [drm] *ERROR* D_COMP RCOMP still in progress drm_WARN_ON(power_domains->domain_use_count[domain] != 1)drm_WARN_ON(((__builtin_constant_p(domain) && __builtin_constant_p((uintptr_t)(power_domain_set->mask.bits) != (uintptr_t)((void *)0)) && (uintptr_t)(power_domain_set->mask.bits) != (uintptr_t)((void *)0) && __builtin_constant_p(*(const unsigned long *)(power_domain_set->mask.bits))) ? const_test_bit(domain, power_domain_set->mask.bits) : _test_bit(domain, power_domain_set->mask.bits)))drm_WARN_ON(!bitmap_subset(mask->bits, power_domain_set->mask.bits, POWER_DOMAIN_NUM))Adjusting requested max DC state (%d->%d) [drm] *ERROR* Unexpected value for enable_dc (%d) %s %s: [drm] Invalid set of dbuf slices (0x%x) requested (total dbuf slices 0x%x) %s %s: [drm] DBuf slice %d power %s timeout! drm_WARN_ON(((&_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display))->info.__runtime_info)->step) == STEP_NONE)Unknown memory configuration; disabling address buddy logic. toggling display PHY side reset %s %s: [drm] VED not power gated [drm] *ERROR* CDCLK source is not LCPLL [drm] *ERROR* LCPLL is disabled [drm] *ERROR* LCPLL not using non-SSC reference drm_WARN_ON(power_domains->init_wakeref)drm_WARN_ON(power_domains->disable_wakeref)BIOS left unused %s power well enabled, disabling it drm_WARN_ON(!domains || domains->ddi_io == POWER_DOMAIN_INVALID)drm_WARN_ON(!domains || domains->ddi_lanes == POWER_DOMAIN_INVALID)drm_WARN_ON(!domains || domains->aux_io == POWER_DOMAIN_INVALID)drm_WARN_ON(!domains || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID)drm_WARN_ON(!domains || domains->aux_tbt == POWER_DOMAIN_INVALID)%s %s: [drm] %sdomainMissing case (%s == %ld) ?Failed to write to D_COMP Current CDCLKEnabling package C8+ %s %s: [drm] SPLL enabled [drm] *ERROR* SPLL enabled %s %s: [drm] WRPLL1 enabled [drm] *ERROR* WRPLL1 enabled %s %s: [drm] WRPLL2 enabled [drm] *ERROR* WRPLL2 enabled %s %s: [drm] Panel power on [drm] *ERROR* Panel power on %s %s: [drm] PCH GTC enabled %s %s: [drm] IRQs enabled [drm] *ERROR* IRQs enabled drm_WARN_ON(!power_well)Allowed DC state mask %02x &power_domains->lockenabledisableUpdating dbuf slices to 0x%x Initial PHY_CONTROL=0x%08x Disabling package C8+ Use countPower well/domain%-25s %s %-25s %d %-23s %d DISPLAY_COREPIPE_APIPE_BPIPE_CPIPE_DPIPE_PANEL_FITTER_APIPE_PANEL_FITTER_BPIPE_PANEL_FITTER_CPIPE_PANEL_FITTER_DTRANSCODER_ATRANSCODER_BTRANSCODER_CTRANSCODER_DTRANSCODER_EDPTRANSCODER_DSI_ATRANSCODER_DSI_CTRANSCODER_VDSC_PW2PORT_DDI_LANES_APORT_DDI_LANES_BPORT_DDI_LANES_CPORT_DDI_LANES_DPORT_DDI_LANES_EPORT_DDI_LANES_FPORT_DDI_LANES_TC1PORT_DDI_LANES_TC2PORT_DDI_LANES_TC3PORT_DDI_LANES_TC4PORT_DDI_LANES_TC5PORT_DDI_LANES_TC6PORT_DDI_IO_APORT_DDI_IO_BPORT_DDI_IO_CPORT_DDI_IO_DPORT_DDI_IO_EPORT_DDI_IO_FPORT_DDI_IO_TC1PORT_DDI_IO_TC2PORT_DDI_IO_TC3PORT_DDI_IO_TC4PORT_DDI_IO_TC5PORT_DDI_IO_TC6PORT_DSIPORT_CRTPORT_OTHERVGAAUDIO_MMIOAUDIO_PLAYBACKAUX_IO_AAUX_IO_BAUX_IO_CAUX_IO_DAUX_IO_EAUX_IO_FAUX_AAUX_BAUX_CAUX_DAUX_EAUX_FAUX_USBC1AUX_USBC2AUX_USBC3AUX_USBC4AUX_USBC5AUX_USBC6AUX_TBT1AUX_TBT2AUX_TBT3AUX_TBT4AUX_TBT5AUX_TBT6GMBUSGT_IRQDC_OFFTC_COLD_OFFINITe g H D s             -  b s  # 0 M   f +  n  8"/5L#L;A 28L/5L#L;A/5L17A/5L88i915.import_ns=PWMGCC: (Debian 12.2.0-14) 12.2.0GNU6@W%  ~ 'P`r9*aRPxpH $l`H`xw   6. =E)wd0*|@+4,$ `HHJc 0 8I\n'<L\k{!*EXpy8 ? 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S r    5  < 2 =U k >J > ?  pA `B  1 PCR i y   Dd E   E " < U Gyw Gy  Hz Hz @Izintel_display_power.casync_put_domains_clear_domain__intel_display_power_is_enabledintel_display_power_grab_async_put_refqueue_async_put_domains_workintel_display_power_domain_str.part.0__intel_display_power_put_domainCSWTCH.148release_async_put_domainsintel_display_power_put_async_work__intel_display_power_get_domain.part.0intel_port_domains_for_aux_chd11_port_domainsi9xx_port_domainsd13_port_domainsd12_port_domainsassert_isp_power_gatedisp_ids.0intel_port_domains_for_portintel_pch_reset_handshakehsw_write_dcomphsw_restore_lcpllhsw_enable_pc8__key.1bxt_display_core_uninit.part.0icl_display_core_uninitbxt_display_core_initicl_display_core_initwa_1409767108_buddy_page_maskstgl_buddy_page_masks__UNIQUE_ID___addressable___SCK__preempt_schedule848.3__UNIQUE_ID___addressable___SCK__preempt_schedule846.4__UNIQUE_ID_import_ns709__UNIQUE_ID___addressable___SCK__might_resched29.5.LC2__x86_return_thunkintel_power_well_is_always_onintel_power_well_is_enabled_cached__bitmap_or_find_first_bitcancel_delayed_workintel_runtime_pm_put_raw__stack_chk_fail__msecs_to_jiffiessystem_unbound_wqqueue_delayed_work_ondev_driver_string__warn_printkintel_power_well_putintel_runtime_pm_get_noresumeintel_runtime_pm_put_uncheckedintel_runtime_pm_get_rawmutex_lockmutex_unlockintel_power_well_getpci_dev_presentvlv_iosf_sb_getvlv_punit_readvlv_iosf_sb_putintel_dmc_wl_getto_intel_uncore__x86_indirect_thunk_raxintel_dmc_wl_putsnb_pcode_write_timeout__drm_dev_dbgintel_uncore_forcewake_get__intel_wait_for_register_dev_errintel_uncore_forcewake_putintel_update_cdclkintel_cdclk_dump_configpcpu_hotlocal_clock__SCT__preempt_schedulelpt_disable_clkout_dpintel_irqs_enabled__const_udelayktime_get_raw__SCT__might_reschedusleep_range_stateintel_display_power_set_target_dc_statelookup_power_wellintel_power_well_is_enabledintel_power_well_enableintel_power_well_disableintel_display_power_getintel_runtime_pm_getintel_display_power_get_if_enabledintel_runtime_pm_get_if_in_use__intel_display_power_put_asyncintel_display_power_flush_workintel_display_power_put_uncheckedintel_display_power_get_in_setintel_display_power_get_in_set_if_enabledintel_display_power_put_mask_in_set__bitmap_subsetintel_power_domains_init__mutex_initdelayed_work_timer_fninit_timer_keyintel_display_power_map_initintel_power_domains_cleanupintel_display_power_map_cleanupgen9_dbuf_slices_update__x86_indirect_thunk_r8gen9_disable_dc_statesintel_cdclk_uninit_hwintel_pmdemand_program_dbufintel_dmc_disable_programintel_combo_phy_uninitgen9_set_dc_stateintel_cdclk_init_hwintel_enabled_dbuf_slices_maskintel_dmc_load_programintel_combo_phy_initintel_snps_phy_wait_for_calibrationintel_power_domains_init_hwintel_power_well_sync_hwintel_power_domains_driver_removecancel_delayed_work_syncintel_power_domains_sanitize_stateintel_power_well_nameintel_power_domains_enableintel_power_domains_disableintel_power_domains_suspendintel_dmc_has_payloadintel_power_domains_resumeintel_display_power_suspend_latebxt_enable_dc9__i915_to_displayintel_display_power_resume_earlygen9_sanitize_dc_statebxt_disable_dc9intel_init_pch_refclkintel_clock_gating_initintel_display_power_suspendintel_display_power_resumegen9_enable_dc5skl_enable_dc6intel_display_power_debugseq_printfintel_power_well_refcountintel_power_well_domainsintel_display_power_ddi_io_domainintel_display_power_ddi_lanes_domainintel_display_power_aux_io_domainintel_display_power_legacy_aux_domainintel_display_power_tbt_aux_domain__SCK__preempt_schedule__SCK__might_resched*+O,,-./0B1I2]34  54 h 5  "5. 1 #,!6|4 54 5079:.-';2/;;<h #y #  # #` #`= >?(@I4S H[5 # #  # #`[ Ad B} C C E 3 A% B@ CM DZ Ab Bx C A B C D% GH AP Bi Cx D A B C D A B C D A BE HU Dn ps I J K N A B C D A B1 C> DK AS Bi Cv D A B C C D MM N)A1BJCZD{MMNMON I" \.FIPABCDABC DA&B?CNDcAkBCDABCDABCD=AEB^CmDABCDABCDQ&A.BGCVDcAkBCDMMNABCDM"M,N6M=OYNt yIABCDABCDAB$C1D>AFBhHwD IABCDRSTA%B>CNDzUSABCDABC>CKDXA`BvC I IABC!D3A;BTCcD IABCCD IA <FIk pI I XI I I= BIg lI @I4 54 5"4, r45T4^ f54 54 h54 54& x.5N4X Z`54 (54 54 58:P;:XY Z[C4J T \5]:;4_K:b;j8;;9:Q;a/;4 ( 5] : , . ; / ; 0(!:>!;!]!:!;!4" h " "5d"^"4" h" "5#f7#:N#;[#8#4# # #5R$ ^$F % H%FW% ^% c%h{% i% %j% %FQ& xV&IR' W'F_': (A(B.(CQ(o[(De(Aq(B(C(D(R(A(B(C(D( ( )4.) 3)5^)4r) w)5)0)p)n)q):)X)[);*rI*pQ*s[*nm*q*:*X*[*;*r*A*B*C+C+DQ+u+A+B+C+C+D+: ,X,Z,;$,v/,wO,nn,r,u -y(-:5-X@-ZH-;^-vw-w-nV.A^.Bz.C.C.D.A.B.C.C4/Am8?}8@8:8X8X8Y8Y9 &*9F29;F9up9:}9X9Z9X9Z9;9v9w9n9x9A:B:C.:DJ:  O:It: h y:I:4:  : :5: @ :I:A:B;C;Dn;Av;B;C;D;Y<A <B#<C3<DN<r<4< <5<a<~8=:Q=;Y=8w=4~= = =5=:>Y>4>  >>FI>[>:>;?]?:A?;i?4p? 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