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(pg))), 1))drm_WARN_ON(!timeout_expected)pica power well disable timeout %s %s: [drm] Power well PICA timeout when disabledpica power well enable timeout %s %s: [drm] Power well PICA timeout when enableddrm_WARN_ON((&(display)->info.__runtime_info)->rawclk_freq == 0)drm_WARN_ON_ONCE(state & ~power_domains->allowed_dc_mask)Setting DC state from %02x to %02x [drm] *ERROR* DC state mismatch (0x%x -> 0x%x) [drm] *ERROR* Writing dc state to 0x%x failed, now 0x%x Rewrote dc state to 0x%x %d times %s forced on (bios:%d driver:%d kvmr:%d debug:%d) [drm] Timeout waiting TC uC health %s %s: [drm] Power well %d not defined for this platform [drm] *ERROR* Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x) drm_WARN_ON_ONCE(id != VLV_DISP_PW_DPIO_CMN_BC && id != CHV_DISP_PW_DPIO_CMN_D)Disabled DPIO PHY%d (PHY_CONTROL=0x%08x) [drm] *ERROR* Display PHY %d is not power up Enabled DPIO PHY%d (PHY_CONTROL=0x%08x) %s %s: [drm] Use count on power well %s is already zeroResetting DC state tracking from %02x to %02x %s %s: [drm] Power wells above platform's DC5 limit still enabled. %s %s: [drm] DC5 already programmed to be enabled. %s %s: [drm] Utility pin enabled in PWM mode %s %s: [drm] DC6 already programmed to be enabled. %s %s: [drm] DC9 already programmed to be enabled. %s %s: [drm] DC5 still not disabled to enable DC9. %s %s: [drm] Power well 2 on. %s %s: [drm] Interrupts not disabled yet. %s %s: [drm] DC5 still not disabled. drm_WARN_ON(intel_cdclk_clock_changed(&display->cdclk.hw, &cdclk_config))%s %s: [drm] Unexpected DBuf power power state (0x%08x, expected 0x%08x) Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x) Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x) %s %s: [drm] Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x) %s %s: [drm] %sdrm_WARN_ON(ctrl != state)unTC cold %sblock succeeded %s power well enable timeout failedsucceededTC cold block %s enabling %s disabling %s Enabling DC5 Enabling DC6 Enabling DC3CO Enabling DC9 Disabling DC9 Disabling DC3CO     g + y l   m   I M i n  w z ~     H PTTT\T@TDTLTTTT Ti915.import_ns=PWMGCC: (Debian 12.2.0-14+deb12u1) 12.2.0GNU 90[P"0"p"1E h P%1@V7\U t@ ? Q  Q0  & KB `}SP 1 *Hg-0"p@#XV5`!(U"lp#0%w*, /k 1z/@Qbs <v    C   1 0I ]t`":N`v 0 B X m ~        % < M l {       ) G Z d ~ +   3d 04_ 4: 4  5! 5= 6 `  6# `6 6" 6 6 7 7 8$ < S g :v  <   P?: @   +EdyCD* (E @(_ (s ( ( @( ( ( (  @(' (: (T (p @( (intel_display_power_well.ci9xx_power_well_sync_hw_noopi9xx_always_on_power_well_enabledtgl_tc_cold_off_power_well_is_enabledchv_pipe_power_well_enabledvlv_power_well_enabledi830_pipes_power_well_disablebxt_dpio_cmn_power_well_enabledbxt_dpio_cmn_power_well_disablebxt_dpio_cmn_power_well_enabletgl_tc_cold_requesttgl_tc_cold_off_power_well_disabletgl_tc_cold_off_power_well_enabletgl_tc_cold_off_power_well_sync_hwchv_set_pipe_power_well.constprop.0vlv_set_power_well.isra.0vlv_power_well_enablevlv_power_well_disablevlv_display_power_well_disableaux_ch_to_digital_port.isra.0i9xx_always_on_power_well_noopicl_aux_pw_to_phy.isra.0chv_pipe_power_well_disablegen9_wait_for_power_well_fuseshsw_wait_for_power_well_enablevlv_dpio_cmn_power_well_enablevlv_dpio_cmn_power_well_disablechv_pipe_power_well_sync_hwxelpdp_aux_power_well_disablexelpdp_aux_power_well_enablexe2lpd_pica_power_well_enabledhsw_power_well_enablexelpdp_aux_power_well_enabledi830_pipes_power_well_enablei830_pipes_power_well_sync_hwxe2lpd_pica_power_well_disablexe2lpd_pica_power_well_enablegen9_dc_off_power_well_enabledvlv_display_power_well_initchv_pipe_power_well_enablevlv_display_power_well_enablei830_pipes_power_well_enabledgen9_set_dc_state.part.0__already_done.6hsw_power_well_sync_hwhsw_power_well_requestershsw_wait_for_power_well_disablehsw_power_well_disableicl_aux_power_well_disableicl_aux_power_well_enablehsw_power_well_enabledassert_chv_phy_statuschv_dpio_cmn_power_well_disable__already_done.0chv_dpio_cmn_power_well_enable__already_done.1__already_done.5__already_done.4__already_done.3__already_done.2gen9_dc_off_power_well_disable__already_done.9__already_done.12__already_done.11__already_done.10__already_done.8__already_done.7gen9_dc_off_power_well_enableicl_ddi_power_well_regsicl_aux_power_well_regshsw_power_well_regs__UNIQUE_ID_modinfo801__UNIQUE_ID___addressable___SCK__might_resched2.13.LC2__x86_return_thunkvlv_iosf_sb_getvlv_iosf_sb_readvlv_iosf_sb_putdev_driver_string__warn_printki830_disable_pipebxt_dpio_phy_is_enabledbxt_dpio_phy_uninitbxt_dpio_phy_init__ref_stack_chk_guardintel_pcode_readmsleep_dev_err__drm_dev_dbg__stack_chk_failvlv_iosf_sb_writektime_get__SCT__might_reschedusleep_range_statevalleyview_disable_display_irqsintel_synchronize_irqvlv_pps_reset_allintel_hpd_poll_enableintel_encoder_to_phyintel_dmc_wl_getto_intel_uncore__intel_wait_for_registerintel_dmc_wl_put__const_udelay__x86_indirect_thunk_raxassert_pll_disabledintel_phy_is_tcgen8_irq_power_well_post_enableintel_vga_reset_io_memi830_enable_pipevalleyview_enable_display_irqsintel_hpd_initintel_hpd_poll_disableintel_crt_resetintel_vga_disableintel_pps_unlock_regs_waintel_dmc_update_dc6_allowed_countintel_psr_notify_dc5_dc6gen8_irq_power_well_pre_disableintel_tc_cold_requires_aux_pwintel_dkl_phy_read_dev_warnintel_pcode_write_timeoutlookup_power_wellvlv_dpio_readvlv_dpio_writeintel_power_well_enableintel_power_well_disableintel_power_well_sync_hwintel_power_well_getintel_power_well_putintel_power_well_is_enabledintel_power_well_is_enabled_cachedintel_display_power_well_is_enabledintel_power_well_is_always_onintel_power_well_nameintel_power_well_domainsintel_power_well_refcountgen9_sanitize_dc_stategen9_set_dc_stategen9_enable_dc5assert_display_rpm_heldassert_main_dmc_loadedintel_dmc_wl_enableskl_enable_dc6intel_dmc_has_payloadbxt_enable_dc9intel_irqs_enabledbxt_pps_reset_allbxt_disable_dc9gen9_disable_dc_statesintel_dmc_wl_get_noregintel_dmc_wl_put_noregintel_cdclk_get_cdclkintel_cdclk_clock_changedintel_enabled_dbuf_slices_maskintel_combo_phy_initbxt_dpio_phy_verify_stateintel_dmc_wl_disablechv_phy_powergate_chmutex_lockmutex_unlockchv_phy_powergate_lanes__drm_to_displayvlv_dig_port_to_phyvlv_dig_port_to_channelxe2lpd_pica_power_well_opsxelpdp_aux_power_well_opstgl_tc_cold_off_opsicl_ddi_power_well_opsicl_aux_power_well_opsvlv_dpio_power_well_opsvlv_dpio_cmn_power_well_opsvlv_display_power_well_opsbxt_dpio_cmn_power_well_opsgen9_dc_off_power_well_opshsw_power_well_opsi830_pipes_power_well_opschv_dpio_cmn_power_well_opschv_pipe_power_well_opsi9xx_always_on_power_well_ops__SCK__might_reschedQRRST $ ,UQTX b jUQR T  %U@RUST  UVZ[$\4 +; ,UZb v ,Z / +_kQ}R`abcaRQ)RRRj 8o]QRR#`(a4bOcValRR 8]RdZebfg d e f g i! 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