ELF>h@@USHHtHHH{HHH;u1[]fUSHHtHHH{HHH;u1[]fUSHHtHHH{HHH;u1[]fATUSHHt"IHHH{HHLH;u[1]A\ff.@ATUSHHt IHH{HLH;u[1]A\ATUSHHt IHH{HLH;u[1]A\AUATUSHHt(IDHH{HDLH;u[1]A\A]DATUSHHt"IHHH{HHLH;u[1]A\ff.@ATUSHHt"IHHH{HHLH;u[1]A\ff.@AVAUATUSHHt.IAADHH{HADDLH;u[1]A\A]A^ff.AUATUSHHt'IIHH{HLLH;u[1]A\A]fDATUSHHt"IHHH{HHLH;u[1]A\ff.@ATUSHHt"IHHH{HHLH;u[1]A\ff.@ATUSHHt"IHHH{HHLH;u[1]A\ff.@USHHtHHH{HHH;u1[]fUSHHtHHH{HHH;u1[]fUSHHtHHH{HHH;u1[]fUSHHtHHH{HHH;u1[]fUSHHtHHH{HHH;u1[]fUSHHtHHH{HHH;u1[]fUSHHtHHH{HHH;u1[]fAUATUSHHt&IAԉHH{HDLH;u[1]A\A]AUATUSHHt&IAԉHH{HDLH;u[1]A\A]AUATUSHHt&IAԉHH{HDLH;u[1]A\A]UHAWAVIAUATARSH0H}eH%(HE1HEHEH@LxPMLX-H}HG`eHHEHHGhHpHe[AZA\A]A^A_]HHL8M?-Cff.UHAWAVIAUATARSH0H}eH%(HE1HEHEH@LxPMLX-H}HG`eHHEHHGhHpHe[AZA\A]A^A_]HHL8M?-Cff.UHAWAVIAUIATARSH(eH%(HE1HEHEH@LxPM<LXAIF`eHHEHIFhHA$HUHuAAD$ljEIHHUHEI|$HfHHǀHA\$MLDHcHLADLApAAAD$ LAD$LALAD$juuLMUY^HEeH+%(u?He[AZA\A]A^A_]HHL8MA@UHAWAVIAUIATARSH(eH%(HE1HEHEH@LxPM<LXAIF`eHHEHIFhHA$HUHuAAD$ljEIHHUHEI|$HfHHǀHA\$MLDHcHLADLApAAAD$ LAD$LALAD$juuLMUY^HEeH+%(u?He[AZA\A]A^A_]HHL8MA@UHAWAVIAUIATARSH(eH%(HE1HEHEH@LxPM<LXAIF`eHHEHIFhHA$HUHuAAD$ljEIHHUHEI|$HfHHǀHA\$MLDHcHLADLApAAAD$ LAD$LALAD$juuLMUY^HEeH+%(u?He[AZA\A]A^A_]HHL8MA@UHAWAVIAUIATARSH(eH%(HE1HEHEH@L@PMZLLELEXA IE`eHHEHIEhHA,HUHuLEAADIHHUHEI LEHfHHǀHA_MLDHcHLAD LApAAG LAGLDLAGAAAGAAGjuLMUY^HEeH+%(u?He[AZA\A]A^A_]HHLM AfDUHAWAVIAUIATARSH(eH%(HE1HEHEH@L@PMXLLELEXA IE`eHHEHIEhHA,HUHuLEAADIHHUHEI LEHfHHǀHA_MLDHcHLLDLAD ApAAAG AAGAAGAAGAAGjuLMUY^HEeH+%(u?He[AZA\A]A^A_]HHLM AUHSHH@t[]E(UHHDMDE M,PHEPE$PEPE PEPH H0[]UHSHH@t[]E(UHHDMDE M,PHEPE$PEPE PEPH H0[]UHSHH@t[]UM HHDMDEHH []ff.UHSHH@t[]E(UHHDMDEM PHE$PE PEPEPH H([]@UHSHH@t[]UM HHDMDEHH []ff.UHSHH@t[]UM HHDMDEHH []ff.AVHAUATUHSH@u}H{-HDs(IDkDc$LD€{,{sD[HDDS DK HCAVAUATHASARWHVHH H8[]A\A]A^[]A\A]A^AWHAVAUATUHSH@H{,Ds(HIIDk&Dc$LD{+{ LDڀ{*sDS"HEDKCDCK AWAVHAUATASARWHVHRSRSRSRHH H`[]A\A]A^A_[]A\A]A^A_UHSHH@t[]E4UHHDMDEM PHE0PE,PE(PE$PE PEPEPH H@[]UHSHH@t[]E UHHDMDEM PHEPEPH H[]ff.UHSHH@uR}HuHHDMM HEULD5HPEHPH XZ[][]f.AUHATUSHH@t []A\A]Dm,De(DUM} U$E DE8uDMAUD)ATD]4)IHE)ASD]0E)ASEAEi =A ASARDEi =A ARQi = QHRi = RHHPEPH Hh[]A\A]AUHATUSHH@t []A\A]Dm,De(DUM} U$E DE8uDMAUD)ATD]4)IHE)ASD]0E)ASEAEi =A ASARDEi =A ARQi = QHRi = RHHPEPH Hh[]A\A]UHSHH@t[]uEHUDMM VLDHHH X[]fUHSHH@t[]uE HUDMMVLDHHH X[]fUHSHH@t[]uE HUDMMVLDHHH X[]fUHSHH@t[]uE HUDMMVLDHHH X[]fUHSHH@t[]UM HHDMDEHH []ff.UHSHH@t[]UM HHDMDEHH []ff.UHSHH@t[]EUHHDMDEM PHEPH XZ[]fUHSHH@t[]EUHHDMDEM PHEPH XZ[]fUHSHH@t[]UM HHDMDEHH []ff.UHSHH@t[]UM HHDEHH []UHSHH@t[]UM HHDEHH []UHAWAVAUIATISHPeH%(HE1HHEHEH@HEHEHXPHEEHHDpDUPM|$MLUU DMu`UIUheL5LuHJ'HUHux}IHHUHEHHfHǀEAFEAF I<$HtHA$PAVIHLHHDHcHHUHHULA^ LHcHHLA$pAAFLAFALLAFjuULMuXZHEeH+%(uZHe[A\A]A^A_]IHHH8E#A<IJfUHAWAVAUIATISHPeH%(HE1HHEHEH@HEHEHXPHEEHHDpDUPM|$MLUU DMu`UIUheL5LuHJ'HUHux}IHHUHEHHfHǀEAFEAF I<$HtHA$PAVIHLHHDHcHHUHHULA^ LHcHHLA$pAAFLAFALLAFjuULMuXZHEeH+%(uZHe[A\A]A^A_]IHHH8E#A<IJfUHAWAVAUIATISHPeH%(HE1HHEHEH@HEHEHXPHEEHHDpDUPM|$MLUU DMu`UIUheL5LuHJ'HUHux}IHHUHEHHfHǀEAFEAF I<$HtHA$PAVIHLHHDHcHHUHHULA^ LHcHHLA$pAAFLAFALLAFjuULMuXZHEeH+%(uZHe[A\A]A^A_]IHHH8E#A<IJfUHAWAAVAUATIARSH0MeH%(HE1HEHEH@LpPM#LHID$hMl$`eL-H HUHuMIHHUHEIzLUMHfHHǀHAJMLDHcHHMLLUHMދEAAD LLEz ABjAULMUY^HEeH+%(u?He[AZA\A]A^A_]IEH L0Mff.UHAWAAVAUATIARSH0MeH%(HE1HEHEH@LpPM#LHID$hMl$`eL-H HUHuMIHHUHEIzLUMHfHHǀHAJMLDHcHHMLLUHMދEAAD LLEz ABjAULMUY^HEeH+%(u?He[AZA\A]A^A_]IEH L0Mff.UHAWAVAUIATIARSH0UMeH%(HE1HEHEH@LxPM3LHID$hMt$`eL5H$HUHuMIHHUHEIzLUMHfHHǀHAJMLDHcHHMLLUHMAAD ApLL׃AAB EABEABjAVLMUY^HEeH+%(u>He[AZA\A]A^A_]IHL8MUHAWIAVAUATISHPHUeH%(HE1HHEHEH@HEHELhPHEEMLDpPDMMLUU DMt$`UIT$heL5LuH$'HUHuljEIHHUHEI~MHfHHǀHA^MANLDHcHLADA^LLHcHHH]pH߉uuFAAF HAFLALAFjuuLMUY^HEeH+%(uXHe[A\A]A^A_]IHL(M`#AcIpff.@UHAWAVAUIATISHXHUeH%(HE1HHEHEH@HEHELpPHEEMLDxp=DHe[AZA\A]A^A_]HHL0M$DUHAWAVIAUIATARSH0H}eH%(HE1HEHEH@LHPMLLMLMXA8HuHF`eHHEHHFhHrADHUHuLMAADIH"HUHEI8LMHfHHǀHA_MLDHcHLAD8LApAAG LAGDALAGAFTAGAFUAGIcpHAFAG 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HD$@eH+%(HH[A\A]A^A_]L(MtVLLLXHcHIHtm$LH4$H4$ {LLIH_IAGIff.UHAWIAVAUIATSH@ $Ld$T$LeH%(HD$81HIGHIEH@LpPMLLLHHPIHtEA_IHcHLLApAAG D$AG$AGHD$8eH+%(H@[A\A]A^A_]L0MtKLLLXHcHIHt\LLLIHjIAGIUHAWAVIAUATISH@ $Ll$T$LeH%(HD$81HID$H]IH@LxPMLLLHHP0.IHA\$I|$.HcLHID$ ID$ID$ID$$IHHLyH9t@IcpLLAD IcpALIIOHLyH9uD$LAD$,$AD$-HD$8eH+%(H@[A\A]A^A_]L8MtKLLLXHcH0IHt.LL7LIHjAD$.I|$.IfDUHAWIAVIAUATSHH@eH%(HD$81Ll$LHHCHIH@HHPHHH $HLAHHP,AA,H $HHteDcAH{,AMcLHLB ApAC LCLCIHSIWHS AWS(HD$8eH+%(H@[A\A]A^A_]HHtYHH $HLD`IcH,H $HHtAA,1HxH޺3LHH\C,H{,AHff.fUHAWIAVAUATSHH@T$Lt$LeH%(HD$81HHCHEIH@LhPMLHLD`IcHHHtmAt$LAD`DcIAAAHMcLLDl$LB AADk LCLCHD$8eH+%(H@[A\A]A^A_]L(MLAHAHPAHLHHtD`t$LDcIHAAAHMLDMc&HDAff.fUHAWIAVAUATSHH@T$Lt$LeH%(HD$81HHCHEIH@LhPMLHLD`IcHHHtmAt$LAD`DcIAAAHMcLLDl$LB AADk LCLCHD$8eH+%(H@[A\A]A^A_]L(MLAHAHPAHLHHtD`t$LDcIHAAAHMLDMc&HDAff.fUHAWAVAUIATISHH@eH%(HD$81L|$LHHCH~I$H@HHPH&HH $HLAHHP8AA8H $HHDsAH{8AMcLHLB0A$pAC LCLCAETCAEUCIc$pHADEC Ic$pHADEC$Ic$pHADEC(Ic$pHADEC,AE6C0AE8C4HD$8eH+%(H@[A\A]A^A_]HHtYHH $HLDpIcH8H $HHtAA8yHixH޺?LHH\C8H{8AHfUHAWAVAUIATISHH@eH%(HD$81L|$LHHCHIEH@HHPHFHH $HLAHHP0AA-H $HHDsAH{-AMcLHLB0ApAC LCLCIcpHADfCIcpHADDfCIcpHADDfCAD$$fCAD$&fC AD$(fC"AD$*fC$AD$,fC&AD$.fC(AD$0C*AD$1C+AD$2C,HD$8eH+%(H@[A\A]A^A_]HHtYHH $HLDpIcH0H $HHtAA-YHIxH޺7LHH\C-H{-AHnfUHAWAVIAUATSHH8eH%(HD$01ILHHCH IH@LxPMLHLAHHP AA HHtdDcAHK AMcHLLLB ApAC ACACACACHD$0eH+%(H8[A\A]A^A_]L8MtNLHLD`IcH HHtAA :HH޺'LHHgC HK AIfDUHAWAVIAUIATSH8eH%(HD$01ILHIEHIH@LxPMLLLHHPIHtRA]IMHcHHLLApAAE LAELAEHD$0eH+%(H8[A\A]A^A_]L8MtKLLLXHcHIHtOLLLIHjIMAEI ff.UHAWAVIAUIATSH8eH%(HD$01ILHIEHIH@LxPMLLLHHPIHtRA]IMHcHHLLApAAE LAELAEHD$0eH+%(H8[A\A]A^A_]L8MtKLLLXHcHIHtOLLLIHjIMAEI ff.UHAWAVIAUIATSH8eH%(HD$01ILHIEHIH@LxPMLLLHHPIHtRA]IMHcHHLLApAAE LAELAEHD$0eH+%(H8[A\A]A^A_]L8MtKLLLXHcHIHtOLLLIHjIMAEI ff.UHAWAVIAUATSHH8eH%(HD$01ILHHCH IH@LxPMLHLAHHP AA HHtfDcAHK AMcHLLLB ApAC LCLCACACHD$0eH+%(H8[A\A]A^A_]L8MtNLHLD`IcH HHtAA 8HH޺'LHHgC HK AI@UHAWAVAUIATISH8eH%(HD$01HHID$HlIEH@LxPM0LPHcH0-LHIHXMuMtLA\$IHLMLDHcHLID$ ID$ID$ID$$IHHHZH9t@LcpHHCD HcpATIHSHHZH9uApHAAD$,HD$0eH+%(udH8[A\A]A^A_]L8Mt:LHcH0-L{뛺7-ff.@UHAWAVAUIATISH8eH%(HD$01HHID$HlIEH@LxPM0LPHcH0-LHIHXMuMtLA\$IHLMLDHcHLID$ ID$ID$ID$$IHHHZH9t@LcpHHCD HcpATIHSHHZH9uApHAAD$,HD$0eH+%(udH8[A\A]A^A_]L8Mt:LHcH0-L{뛺7-ff.@AWIAVAUATIUHSHhL$Ll$0LeH%(HD$`1HD$HD$HD$ HD$(HID$HmIH@LpPM#LPp! MM Lt$ T$T$t$  LHc҉t$LH IHt$XHx MpHHcLDHLAD A\$LLHcHHHpAAD$ HAD$LAD$D$AD$HD$`eH+%(udHh[]A\A]A^A_L0M' ILzAWIAVAUIATUSHH`eH%(HD$X1H|$(HD$HD$HD$HD$ HHCHVIH@LpPM LPIĉAMMLT$T$A H|$(HHcHHHhHxD`HMLDHcHLD+kLHHcHHL(ApAC LCCH|$(HD$XeH+%(ueH`[]A\A]A^A_L0MA#IHff.@AWAVAUIATIUHSH`eH%(HD$X1H|$(HD$HD$HD$HD$ HIEHHEH@LpPMHLPp=frontbuffer_bits, REC->origin"dev %s, frontbuffer_bits=0x%08x, origin=%u", __get_str(dev), REC->frontbuffer_bits, REC->origin"dev %s, pipe %c, frame=%u, scanline=%u", __get_str(dev), REC->pipe_name, REC->frame, REC->scanline"dev %s, pipe %c, frame=%u, scanline=%u, min=%u, max=%u", __get_str(dev), REC->pipe_name, REC->frame, REC->scanline, REC->min, REC->max"dev %s, pipe %c, frame=%u, scanline=%u, min=%u, max=%u", __get_str(dev), REC->pipe_name, REC->frame, REC->scanline, REC->min, REC->max"dev %s, pipe %c, frame=%u, scanline=%u", __get_str(dev), REC->pipe_name, REC->frame, REC->scanline"dev %s, pipe %c, frame=%u, scanline=%u", __get_str(dev), REC->pipe_name, REC->frame, REC->scanline"dev %s, pipe %c, plane %s, frame=%u, scanline=%u", __get_str(dev), REC->pipe_name, __get_str(name), REC->frame, REC->scanline"dev %s, pipe %c, plane %s, frame=%u, scanline=%u", __get_str(dev), REC->pipe_name, __get_str(name), REC->frame, REC->scanline"dev %s, pipe %c, plane %s, frame=%u, scanline=%u", __get_str(dev), REC->pipe_name, __get_str(name), REC->frame, REC->scanline"dev %s, pipe %c, plane %s, frame=%u, scanline=%u", __get_str(dev), REC->pipe_name, __get_str(name), REC->frame, REC->scanline"dev %s, pipe %c, plane %s, frame=%u, scanline=%u, %d.%06ux%d.%06u%+d.%06u%+d.%06u -> %dx%d%+d%+d", __get_str(dev), REC->pipe_name, __get_str(name), REC->frame, REC->scanline, drm_rect_width((const struct drm_rect *)REC->src) >> 16, ((drm_rect_width((const struct drm_rect *)REC->src) & 0xffff) * 15625) >> 10, drm_rect_height((const struct drm_rect *)REC->src) >> 16, ((drm_rect_height((const struct drm_rect *)REC->src) & 0xffff) * 15625) >> 10, ((const struct drm_rect *)REC->src)->x1 >> 16, ((((const struct drm_rect *)REC->src)->x1 & 0xffff) * 15625) >> 10, ((const struct drm_rect *)REC->src)->y1 >> 16, ((((const struct drm_rect *)REC->src)->y1 & 0xffff) * 15625) >> 10, drm_rect_width((const struct drm_rect *)REC->dst), drm_rect_height((const struct drm_rect *)REC->dst), ((const struct drm_rect *)REC->dst)->x1, ((const struct drm_rect *)REC->dst)->y1"dev %s, pipe %c, plane %s, frame=%u, scanline=%u, %d.%06ux%d.%06u%+d.%06u%+d.%06u -> %dx%d%+d%+d", __get_str(dev), REC->pipe_name, __get_str(name), REC->frame, REC->scanline, drm_rect_width((const struct drm_rect *)REC->src) >> 16, ((drm_rect_width((const struct drm_rect *)REC->src) & 0xffff) * 15625) >> 10, drm_rect_height((const struct drm_rect *)REC->src) >> 16, ((drm_rect_height((const struct drm_rect *)REC->src) & 0xffff) * 15625) >> 10, ((const struct drm_rect *)REC->src)->x1 >> 16, ((((const struct drm_rect *)REC->src)->x1 & 0xffff) * 15625) >> 10, ((const struct drm_rect *)REC->src)->y1 >> 16, ((((const struct drm_rect *)REC->src)->y1 & 0xffff) * 15625) >> 10, drm_rect_width((const struct drm_rect *)REC->dst), drm_rect_height((const struct drm_rect *)REC->dst), ((const struct drm_rect *)REC->dst)->x1, ((const struct drm_rect *)REC->dst)->y1"dev %s, pipe %c, plane %s, frame=%u, scanline=%u, async_flip=%s", __get_str(dev), REC->pipe_name, __get_str(name), REC->frame, REC->scanline, str_yes_no(REC->async_flip)"dev %s, pipe %c, frame=%u, scanline=%u, %d/%d/%d", __get_str(dev), REC->pipe_name, REC->frame, REC->scanline, REC->sprite0_start, REC->sprite1_start, REC->fifo_size"dev %s, pipe %c, frame=%u, scanline=%u, level=%d, cxsr=%d, wm %d/%d/%d/%d, sr %d/%d", __get_str(dev), REC->pipe_name, REC->frame, REC->scanline, REC->level, REC->cxsr, REC->primary, REC->sprite0, REC->sprite1, REC->cursor, REC->sr_plane, REC->sr_cursor"dev %s, pipe %c, frame=%u, scanline=%u, wm %d/%d/%d, sr %s/%d/%d/%d, hpll %s/%d/%d/%d, fbc %s", __get_str(dev), REC->pipe_name, REC->frame, REC->scanline, REC->primary, REC->sprite, REC->cursor, str_yes_no(REC->cxsr), REC->sr_plane, REC->sr_cursor, REC->sr_fbc, str_yes_no(REC->hpll), REC->hpll_plane, REC->hpll_cursor, REC->hpll_fbc, str_yes_no(REC->fbc)"dev %s, cxsr %s->%s, pipe A: frame=%u, scanline=%u, pipe B: frame=%u, scanline=%u, pipe C: frame=%u, scanline=%u, pipe D: frame=%u, scanline=%u", __get_str(dev), str_on_off(REC->old), str_on_off(REC->new), REC->frame[0], REC->scanline[0] , REC->frame[1], REC->scanline[1] , REC->frame[2], REC->scanline[2] , REC->frame[3], REC->scanline[3]"dev %s, pch transcoder %c, frame=%u, scanline=%u", __get_str(dev), REC->pipe_name, REC->frame, REC->scanline"dev %s, pipe %c, frame=%u, scanline=%u", __get_str(dev), REC->pipe_name, REC->frame, REC->scanline"dev %s, pipe %c, frame=%u, scanline=%u crc=%08x %08x %08x %08x %08x", __get_str(dev), REC->pipe_name, REC->frame, REC->scanline, REC->crcs[0], REC->crcs[1], REC->crcs[2], REC->crcs[3], REC->crcs[4]"dev %s, pipe %c, frame=%u, scanline=%u", __get_str(dev), REC->pipe_name, REC->frame, REC->scanline"dev %s, pipe %c disable, pipe A: frame=%u, scanline=%u, pipe B: frame=%u, scanline=%u, pipe C: frame=%u, scanline=%u, pipe D: frame=%u, scanline=%u", __get_str(dev), REC->pipe_name, REC->frame[0], REC->scanline[0] , REC->frame[1], REC->scanline[1] , REC->frame[2], REC->scanline[2] , REC->frame[3], REC->scanline[3]"dev %s, pipe %c enable, pipe A: frame=%u, scanline=%u, pipe B: frame=%u, scanline=%u, pipe C: frame=%u, scanline=%u, pipe D: frame=%u, scanline=%u", __get_str(dev), REC->pipe_name, REC->frame[0], REC->scanline[0] , REC->frame[1], REC->scanline[1] , REC->frame[2], REC->scanline[2] , REC->frame[3], REC->scanline[3](null)onoffyesno__data_loc char[]devunsigned intfrontbuffer_bitsorigincharpipe_nameu32framescanlineminmaxnameint[4]srcdstboolasync_flipsprite0_startsprite1_startfifo_sizelevelcxsrprimarysprite0sprite1cursorsr_planesr_cursoru16spritesr_fbchpll_planehpll_cursorhpll_fbchpllfbcu32[I915_MAX_PIPES]oldnewu32[5]crcsdev %s, pipe %c enable, pipe A: frame=%u, scanline=%u, pipe B: frame=%u, scanline=%u, pipe C: frame=%u, scanline=%u, pipe D: frame=%u, scanline=%u dev %s, pipe %c disable, pipe A: frame=%u, scanline=%u, pipe B: frame=%u, scanline=%u, pipe C: frame=%u, scanline=%u, pipe D: frame=%u, scanline=%u dev %s, pipe %c, frame=%u, scanline=%u dev %s, pipe %c, frame=%u, scanline=%u crc=%08x %08x %08x %08x %08x dev %s, pch transcoder %c, frame=%u, scanline=%u dev %s, cxsr %s->%s, pipe A: frame=%u, scanline=%u, pipe B: frame=%u, scanline=%u, pipe C: frame=%u, scanline=%u, pipe D: frame=%u, scanline=%u dev %s, pipe %c, frame=%u, scanline=%u, wm %d/%d/%d, sr %s/%d/%d/%d, hpll %s/%d/%d/%d, fbc %s dev %s, pipe %c, frame=%u, scanline=%u, level=%d, cxsr=%d, wm %d/%d/%d/%d, sr %d/%d dev %s, pipe %c, frame=%u, scanline=%u, %d/%d/%d dev %s, pipe %c, plane %s, frame=%u, scanline=%u, async_flip=%s dev %s, pipe %c, plane %s, frame=%u, scanline=%u, %d.%06ux%d.%06u%+d.%06u%+d.%06u -> %dx%d%+d%+d dev %s, pipe %c, plane %s, frame=%u, scanline=%u dev %s, pipe %c, frame=%u, scanline=%u, min=%u, max=%u dev %s, frontbuffer_bits=0x%08x, origin=%u i915intel_frontbuffer_flushintel_frontbuffer_invalidateintel_pipe_update_endintel_pipe_update_vblank_evadedintel_pipe_update_startintel_crtc_vblank_work_endintel_crtc_vblank_work_startintel_fbc_nukeintel_fbc_deactivateintel_fbc_activateintel_plane_disable_armintel_plane_update_armintel_plane_update_noarmintel_plane_async_flipvlv_fifo_sizevlv_wmg4x_wmintel_memory_cxsrintel_pch_fifo_underrunintel_cpu_fifo_underrunintel_pipe_crcintel_crtc_flip_doneintel_pipe_disableintel_pipe_enablei915.import_ns=PWMGCC: (Debian 12.2.0-14) 12.2.0GNU` %4 %R r` p1`pUT{PlT@Tp(`x@d_pv^p^&^LP ^l T0!T!^"^ "TG"OuP#O#g0&g(g0+,A.bP0A2z@5z7L0:<4`>P*@GBjDFJPLM,OX0Q PS0UWX'0[G;]qP_ab `d.  fV  h  j 0l 0n `p6 r[ t v  4x a  4x a= ? 5x[ d{ } 5x    6x   ( 6x2 dW 0Y 7x| @d 8 7x  @ 8x @ H 8x* G PI 9xg @ X 9x ^ ` :x  ^ h:x, MpO;xc@ {x};x<xe<xU=xn35=xS`duw>x>xd?x@=?x3<Oz`1 _* @T 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A/0A/@A/PA/`A0pAintel_display_trace.cperf_trace_intel_pipe_enableperf_trace_intel_pipe_disableperf_trace_intel_crtc_flip_doneperf_trace_intel_crtc_vblank_work_startperf_trace_intel_crtc_vblank_work_endperf_trace_intel_pipe_update_startperf_trace_intel_pipe_update_vblank_evadedtrace_raw_output_intel_pipe_enabletrace_raw_output_intel_pipe_disabletrace_raw_output_intel_crtc_flip_donetrace_raw_output_intel_pipe_crctrace_raw_output_intel_cpu_fifo_underruntrace_raw_output_intel_pch_fifo_underruntrace_raw_output_intel_memory_cxsrtrace_raw_output_g4x_wmtrace_raw_output_vlv_wmtrace_raw_output_vlv_fifo_sizetrace_raw_output_intel_plane_async_fliptrace_raw_output_intel_plane_update_noarmtrace_raw_output_intel_plane_update_armtrace_raw_output_intel_plane_disable_armtrace_raw_output_intel_fbc_activatetrace_raw_output_intel_fbc_deactivatetrace_raw_output_intel_fbc_nuketrace_raw_output_intel_crtc_vblank_work_starttrace_raw_output_intel_crtc_vblank_work_endtrace_raw_output_intel_pipe_update_starttrace_raw_output_intel_pipe_update_vblank_evadedtrace_raw_output_intel_pipe_update_endtrace_raw_output_intel_frontbuffer_invalidatetrace_raw_output_intel_frontbuffer_flushperf_trace_intel_fbc_activateperf_trace_intel_fbc_deactivateperf_trace_intel_fbc_nukeperf_trace_intel_frontbuffer_flushperf_trace_intel_frontbuffer_invalidateperf_trace_intel_pipe_update_endperf_trace_intel_plane_disable_armperf_trace_intel_plane_update_armperf_trace_intel_plane_update_noarmperf_trace_intel_plane_async_flipperf_trace_vlv_fifo_sizeperf_trace_vlv_wmperf_trace_g4x_wmperf_trace_intel_memory_cxsrperf_trace_intel_pch_fifo_underrunperf_trace_intel_cpu_fifo_underrunperf_trace_intel_pipe_crctrace_event_raw_event_vlv_fifo_sizetrace_event_raw_event_intel_frontbuffer_invalidatetrace_event_raw_event_intel_frontbuffer_flushtrace_event_raw_event_intel_pipe_update_endtrace_event_raw_event_intel_memory_cxsrtrace_event_raw_event_intel_pipe_crctrace_event_raw_event_intel_cpu_fifo_underruntrace_event_raw_event_intel_pch_fifo_underruntrace_event_raw_event_vlv_wmtrace_event_raw_event_g4x_wmtrace_event_raw_event_intel_pipe_update_vblank_evadedtrace_event_raw_event_intel_crtc_flip_donetrace_event_raw_event_intel_crtc_vblank_work_endtrace_event_raw_event_intel_crtc_vblank_work_starttrace_event_raw_event_intel_pipe_update_starttrace_event_raw_event_intel_pipe_enabletrace_event_raw_event_intel_pipe_disabletrace_event_raw_event_intel_plane_async_fliptrace_event_raw_event_intel_plane_disable_armtrace_event_raw_event_intel_plane_update_noarmtrace_event_raw_event_intel_plane_update_armtrace_event_raw_event_intel_fbc_nuketrace_event_raw_event_intel_fbc_activatetrace_event_raw_event_intel_fbc_deactivate__event_intel_frontbuffer_flushprint_fmt_intel_frontbuffer_flush__event_intel_frontbuffer_invalidateprint_fmt_intel_frontbuffer_invalidate__event_intel_pipe_update_endprint_fmt_intel_pipe_update_end__event_intel_pipe_update_vblank_evadedprint_fmt_intel_pipe_update_vblank_evaded__event_intel_pipe_update_startprint_fmt_intel_pipe_update_start__event_intel_crtc_vblank_work_endprint_fmt_intel_crtc_vblank_work_end__event_intel_crtc_vblank_work_startprint_fmt_intel_crtc_vblank_work_start__event_intel_fbc_nukeprint_fmt_intel_fbc_nuke__event_intel_fbc_deactivateprint_fmt_intel_fbc_deactivate__event_intel_fbc_activateprint_fmt_intel_fbc_activate__event_intel_plane_disable_armprint_fmt_intel_plane_disable_arm__event_intel_plane_update_armprint_fmt_intel_plane_update_arm__event_intel_plane_update_noarmprint_fmt_intel_plane_update_noarm__event_intel_plane_async_flipprint_fmt_intel_plane_async_flip__event_vlv_fifo_sizeprint_fmt_vlv_fifo_size__event_vlv_wmprint_fmt_vlv_wm__event_g4x_wmprint_fmt_g4x_wm__event_intel_memory_cxsrprint_fmt_intel_memory_cxsr__event_intel_pch_fifo_underrunprint_fmt_intel_pch_fifo_underrun__event_intel_cpu_fifo_underrunprint_fmt_intel_cpu_fifo_underrun__event_intel_pipe_crcprint_fmt_intel_pipe_crc__event_intel_crtc_flip_doneprint_fmt_intel_crtc_flip_done__event_intel_pipe_disableprint_fmt_intel_pipe_disable__event_intel_pipe_enableprint_fmt_intel_pipe_enabletrace_event_fields_intel_frontbuffer_flushtrace_event_fields_intel_frontbuffer_invalidatetrace_event_fields_intel_pipe_update_endtrace_event_fields_intel_pipe_update_vblank_evadedtrace_event_fields_intel_pipe_update_starttrace_event_fields_intel_crtc_vblank_work_endtrace_event_fields_intel_crtc_vblank_work_starttrace_event_fields_intel_fbc_nuketrace_event_fields_intel_fbc_deactivatetrace_event_fields_intel_fbc_activatetrace_event_fields_intel_plane_disable_armtrace_event_fields_intel_plane_update_armtrace_event_fields_intel_plane_update_noarmtrace_event_fields_intel_plane_async_fliptrace_event_fields_vlv_fifo_sizetrace_event_fields_vlv_wmtrace_event_fields_g4x_wmtrace_event_fields_intel_memory_cxsrtrace_event_fields_intel_pch_fifo_underruntrace_event_fields_intel_cpu_fifo_underruntrace_event_fields_intel_pipe_crctrace_event_fields_intel_crtc_flip_donetrace_event_fields_intel_pipe_disabletrace_event_fields_intel_pipe_enabletrace_event_type_funcs_intel_frontbuffer_flushtrace_event_type_funcs_intel_frontbuffer_invalidatetrace_event_type_funcs_intel_pipe_update_endtrace_event_type_funcs_intel_pipe_update_vblank_evadedtrace_event_type_funcs_intel_pipe_update_starttrace_event_type_funcs_intel_crtc_vblank_work_endtrace_event_type_funcs_intel_crtc_vblank_work_starttrace_event_type_funcs_intel_fbc_nuketrace_event_type_funcs_intel_fbc_deactivatetrace_event_type_funcs_intel_fbc_activatetrace_event_type_funcs_intel_plane_disable_armtrace_event_type_funcs_intel_plane_update_armtrace_event_type_funcs_intel_plane_update_noarmtrace_event_type_funcs_intel_plane_async_fliptrace_event_type_funcs_vlv_fifo_sizetrace_event_type_funcs_vlv_wmtrace_event_type_funcs_g4x_wmtrace_event_type_funcs_intel_memory_cxsrtrace_event_type_funcs_intel_pch_fifo_underruntrace_event_type_funcs_intel_cpu_fifo_underruntrace_event_type_funcs_intel_pipe_crctrace_event_type_funcs_intel_crtc_flip_donetrace_event_type_funcs_intel_pipe_disabletrace_event_type_funcs_intel_pipe_enableevent_class_intel_frontbuffer_flushstr__i915__trace_system_nameevent_class_intel_frontbuffer_invalidateevent_class_intel_pipe_update_endevent_class_intel_pipe_update_vblank_evadedevent_class_intel_pipe_update_startevent_class_intel_crtc_vblank_work_endevent_class_intel_crtc_vblank_work_startevent_class_intel_fbc_nukeevent_class_intel_fbc_deactivateevent_class_intel_fbc_activateevent_class_intel_plane_disable_armevent_class_intel_plane_update_armevent_class_intel_plane_update_noarmevent_class_intel_plane_async_flipevent_class_vlv_fifo_sizeevent_class_vlv_wmevent_class_g4x_wmevent_class_intel_memory_cxsrevent_class_intel_pch_fifo_underrunevent_class_intel_cpu_fifo_underrunevent_class_intel_pipe_crcevent_class_intel_crtc_flip_doneevent_class_intel_pipe_disableevent_class_intel_pipe_enable__tpstrtab_intel_frontbuffer_flush__tpstrtab_intel_frontbuffer_invalidate__tpstrtab_intel_pipe_update_end__tpstrtab_intel_pipe_update_vblank_evaded__tpstrtab_intel_pipe_update_start__tpstrtab_intel_crtc_vblank_work_end__tpstrtab_intel_crtc_vblank_work_start__tpstrtab_intel_fbc_nuke__tpstrtab_intel_fbc_deactivate__tpstrtab_intel_fbc_activate__tpstrtab_intel_plane_disable_arm__tpstrtab_intel_plane_update_arm__tpstrtab_intel_plane_update_noarm__tpstrtab_intel_plane_async_flip__tpstrtab_vlv_fifo_size__tpstrtab_vlv_wm__tpstrtab_g4x_wm__tpstrtab_intel_memory_cxsr__tpstrtab_intel_pch_fifo_underrun__tpstrtab_intel_cpu_fifo_underrun__tpstrtab_intel_pipe_crc__tpstrtab_intel_crtc_flip_done__tpstrtab_intel_pipe_disable__tpstrtab_intel_pipe_enable__UNIQUE_ID_import_ns482__tracepoint_intel_pipe_enable__SCT__tp_func_intel_pipe_enable__traceiter_intel_pipe_enable__tracepoint_intel_pipe_disable__SCT__tp_func_intel_pipe_disable__traceiter_intel_pipe_disable__tracepoint_intel_crtc_flip_done__SCT__tp_func_intel_crtc_flip_done__traceiter_intel_crtc_flip_done__tracepoint_intel_pipe_crc__SCT__tp_func_intel_pipe_crc__traceiter_intel_pipe_crc__tracepoint_intel_cpu_fifo_underrun__SCT__tp_func_intel_cpu_fifo_underrun__traceiter_intel_cpu_fifo_underrun__tracepoint_intel_pch_fifo_underrun__SCT__tp_func_intel_pch_fifo_underrun__traceiter_intel_pch_fifo_underrun__tracepoint_intel_memory_cxsr__SCT__tp_func_intel_memory_cxsr__traceiter_intel_memory_cxsr__tracepoint_g4x_wm__SCT__tp_func_g4x_wm__traceiter_g4x_wm__tracepoint_vlv_wm__SCT__tp_func_vlv_wm__traceiter_vlv_wm__tracepoint_vlv_fifo_size__SCT__tp_func_vlv_fifo_size__traceiter_vlv_fifo_size__tracepoint_intel_plane_async_flip__SCT__tp_func_intel_plane_async_flip__traceiter_intel_plane_async_flip__tracepoint_intel_plane_update_noarm__SCT__tp_func_intel_plane_update_noarm__traceiter_intel_plane_update_noarm__tracepoint_intel_plane_update_arm__SCT__tp_func_intel_plane_update_arm__traceiter_intel_plane_update_arm__tracepoint_intel_plane_disable_arm__SCT__tp_func_intel_plane_disable_arm__traceiter_intel_plane_disable_arm__tracepoint_intel_fbc_activate__SCT__tp_func_intel_fbc_activate__traceiter_intel_fbc_activate__tracepoint_intel_fbc_deactivate__SCT__tp_func_intel_fbc_deactivate__traceiter_intel_fbc_deactivate__tracepoint_intel_fbc_nuke__SCT__tp_func_intel_fbc_nuke__traceiter_intel_fbc_nuke__tracepoint_intel_crtc_vblank_work_start__SCT__tp_func_intel_crtc_vblank_work_start__traceiter_intel_crtc_vblank_work_start__tracepoint_intel_crtc_vblank_work_end__SCT__tp_func_intel_crtc_vblank_work_end__traceiter_intel_crtc_vblank_work_end__tracepoint_intel_pipe_update_start__SCT__tp_func_intel_pipe_update_start__traceiter_intel_pipe_update_start__tracepoint_intel_pipe_update_vblank_evaded__SCT__tp_func_intel_pipe_update_vblank_evaded__traceiter_intel_pipe_update_vblank_evaded__tracepoint_intel_pipe_update_end__SCT__tp_func_intel_pipe_update_end__traceiter_intel_pipe_update_end__tracepoint_intel_frontbuffer_invalidate__SCT__tp_func_intel_frontbuffer_invalidate__traceiter_intel_frontbuffer_invalidate__tracepoint_intel_frontbuffer_flush__SCT__tp_func_intel_frontbuffer_flush__traceiter_intel_frontbuffer_flush__x86_indirect_thunk_rax__x86_return_thunk__probestub_intel_pipe_enable__probestub_intel_pipe_crc__probestub_intel_cpu_fifo_underrun__probestub_intel_memory_cxsr__probestub_vlv_fifo_size__probestub_intel_plane_async_flip__probestub_intel_pipe_update_end__probestub_intel_frontbuffer_invalidatestrlenthis_cpu_offperf_trace_buf_alloc__drm_to_displaymemcpyintel_crtc_get_vblank_counterintel_get_crtc_scanlineperf_trace_run_bpf_submit__stack_chk_failtrace_raw_output_preptrace_event_printftrace_handle_returnintel_crtc_for_pipe__probestub_intel_frontbuffer_flush__probestub_intel_pch_fifo_underrun__probestub_intel_plane_disable_arm__probestub_intel_pipe_update_vblank_evaded__probestub_g4x_wm__probestub_vlv_wm__probestub_intel_plane_update_noarm__probestub_intel_plane_update_arm__probestub_intel_fbc_activate__probestub_intel_crtc_flip_done__probestub_intel_pipe_disable__probestub_intel_fbc_deactivate__probestub_intel_fbc_nuke__probestub_intel_crtc_vblank_work_start__probestub_intel_crtc_vblank_work_end__probestub_intel_pipe_update_starttrace_event_buffer_reservetrace_event_buffer_commit__trace_trigger_soft_disabledtrace_event_regtrace_event_raw_init__SCK__tp_func_intel_frontbuffer_flush__SCK__tp_func_intel_frontbuffer_invalidate__SCK__tp_func_intel_pipe_update_end__SCK__tp_func_intel_pipe_update_vblank_evaded__SCK__tp_func_intel_pipe_update_start__SCK__tp_func_intel_crtc_vblank_work_end__SCK__tp_func_intel_crtc_vblank_work_start__SCK__tp_func_intel_fbc_nuke__SCK__tp_func_intel_fbc_deactivate__SCK__tp_func_intel_fbc_activate__SCK__tp_func_intel_plane_disable_arm__SCK__tp_func_intel_plane_update_arm__SCK__tp_func_intel_plane_update_noarm__SCK__tp_func_intel_plane_async_flip__SCK__tp_func_vlv_fifo_size__SCK__tp_func_vlv_wm__SCK__tp_func_g4x_wm__SCK__tp_func_intel_memory_cxsr__SCK__tp_func_intel_pch_fifo_underrun__SCK__tp_func_intel_cpu_fifo_underrun__SCK__tp_func_intel_pipe_crc__SCK__tp_func_intel_crtc_flip_done__SCK__tp_func_intel_pipe_disable__SCK__tp_func_intel_pipe_enable44D4D4D+4LD4D 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