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0HXDx,HAT$DIHI>T$DHHDLHHHXh,IHI>1҉HHAiLLH߾DH߁8DH߉߉H߾H[]A\A]A^A_HXDx,~Dm`0,``0`AUATUSHH t []A\A]`1H߽`DpHHXDh,E~ CDd,`HADIHI<$DHHDLHHHXh,HHH;1HHH[]A\A]tNff1drivers/gpu/drm/i915/display/intel_dpll.cdrm_WARN_ON_ONCE(!target_freq)using SSC reference clock of %d kHz %s %s: [drm] PLL state assertion failure (expected %s, current %s) [drm] *ERROR* PLL state assertion failure (expected %s, current %s) Unknown DPLL mode %08x in programmed mode drm_WARN_ON(!intel_crtc_needs_modeset(crtc_state))[CRTC:%d:%s] Couldn't calculate DPLL settings drm_WARN_ON(!crtc_state->hw.enable && crtc_state->shared_dpll)[CRTC:%d:%s] Couldn't get a shared DPLL [drm] *ERROR* DPLL %d failed to lock [drm] *ERROR* PLL %d failed to lock drm_WARN_ON((__intel_de_read(_Generic(dev_priv, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(dev_priv)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(dev_priv)), const struct intel_display *: (dev_priv), struct intel_display *: (dev_priv)), ((const i915_reg_t){ .reg = ((((_Generic(dev_priv, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(dev_priv)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(dev_priv)), const struct intel_display *: (dev_priv), struct intel_display *: (dev_priv))->info.__device_info)->mmio_offset)) + (((int)(sizeof(struct { int:(-!!(!(sizeof(int) == sizeof(*(8 ? ((void *)((long)(1) * 0l)) : (int *)8))))); }))) + (((PIPE_B)) < (1) ? ((0x6014) + ((PIPE_B)) * ((0x6014) - (0x6014))) : ((0x6018) + (((PIPE_B)) - (1)) * ((0x6030) - (0x6018)))))) })) & (1 << 28)) == 0)  " D #     %s %s: [drm] %sonoffaP >I;f?a`=>Ib+a =[ a0W5O~  *na0W5O~  pna0W5O  8na0W5Ov  pna0W5O  Pn  Ng5p Ng5P@  8kg5h * N8g5h pUg5h P ag5h  N\*Fxb N\*FxP@  a0W @`a0W @`!a0W @`!i915.import_ns=PWMGCC: (Debian 12.2.0-14) 12.2.0GNU#5Npe0S|o  8r)L9LI H``Lq3|1W@LLLL L#P]: LPLu`L@LL,'L@,`LBLXLo]p!LLp` P@(07 FVf3Jb!*@OPdP"({$' (*2*G+IXp+Ii+(-Dp./J3%?9jNpA_sBCPE`FFF intel_dpll.cpnv_calc_dpll_paramsi9xx_compute_dpllhsw_crtc_get_shared_dpllhsw_crtc_compute_clockdg2_crtc_compute_clockmtl_crtc_compute_clockintel_pll_is_valid.part.0vlv_PLL_is_optimal.part.0__already_done.0ilk_crtc_get_shared_dpllvlv_calc_dpll_params.constprop.0pnv_crtc_compute_clockpnv_limits_sdvopnv_limits_lvdsvlv_crtc_compute_clockintel_limits_vlvassert_pllg4x_find_best_dpll.constprop.0ilk_crtc_compute_clockilk_limits_dacilk_limits_dual_lvdsilk_limits_dual_lvds_100milk_limits_single_lvdsilk_limits_single_lvds_100mg4x_crtc_compute_clockintel_limits_g4x_hdmiintel_limits_g4x_single_channel_lvdsintel_limits_g4x_dual_channel_lvdsintel_limits_i9xx_sdvointel_limits_g4x_sdvoi9xx_find_best_dpll.constprop.0i9xx_crtc_compute_clockintel_limits_i9xx_lvdsi8xx_crtc_compute_clockintel_limits_i8xx_dacintel_limits_i8xx_dvointel_limits_i8xx_lvdschv_find_best_dpll.constprop.0.isra.0chv_crtc_compute_clockintel_limits_chvintel_limits_bxtmtl_dpll_funcsdg2_dpll_funcshsw_dpll_funcsilk_dpll_funcschv_dpll_funcsvlv_dpll_funcsg4x_dpll_funcspnv_dpll_funcsi8xx_dpll_funcsi9xx_dpll_funcs__UNIQUE_ID_import_ns707.LC0__x86_return_thunk__drm_to_display__i915_to_displayintel_panel_use_sscintel_get_crtc_new_encoderintel_reserve_shared_dpllsintel_compute_shared_dpllsintel_crtc_dotclockintel_mpllb_calc_stateintel_cx0pll_calc_stateintel_cx0pll_calc_port_clockdev_driver_string__warn_printkintel_is_dual_link_lvds__drm_dev_dbg__stack_chk_failintel_dmc_wl_getto_intel_uncore__x86_indirect_thunk_raxintel_dmc_wl_put_dev_erri9xx_calc_dpll_params__sw_hweight32chv_calc_dpll_paramsi9xx_dpll_get_hw_statei9xx_crtc_clock_getintel_lvds_port_enabledvlv_crtc_clock_getvlv_pipe_to_channelvlv_pipe_to_phyvlv_iosf_sb_getvlv_dpio_readvlv_iosf_sb_putchv_crtc_clock_getbxt_find_best_dplli9xx_dpll_compute_fpvlv_compute_dpllchv_compute_dpllintel_dpll_crtc_compute_clockintel_dpll_crtc_get_shared_dpllintel_dpll_init_clock_hooki9xx_enable_pllassert_transcoderassert_pps_unlocked__const_udelayvlv_enable_pllvlv_dpio_write__intel_wait_for_registerchv_enable_pllvlv_force_pll_onintel_crtc_for_pipeintel_crtc_state_allocintel_crtc_destroy_statevlv_disable_pllchv_disable_plli9xx_disable_pllvlv_force_pll_offassert_pll_enabledassert_pll_disabled5>??T@A"?A?CDWAbEpDAFGD:(:?HF 0P XI> 9? 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