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^fUSHo8~?HH@t31HcHHPH@Ht11Hex98[]wrpllMissing case (%s == %ld) hw_state->mg_clktop2_hsclkctl%s %s: [drm] bad spll freq %s %s: [drm] %sdrm_WARN_ON(1)[drm] *ERROR* Invalid VCO [CRTC:%d:%s] reserving %s p0p2Incorrect PDiv Incorrect KDiv clockdiv1refclk_khzencoder->portdrm_WARN_ON(clk_div->m1 != 2)Invalid clock for DP: %d [drm] *ERROR* PLL %d locked id[CRTC:%d:%s] allocated %s clock / 2onoffdrm_WARN_ON(!pll->on)drm_WARN_ON(pll->on)enabling %s disabling %s [CRTC:%d:%s] releasing %s &i915->display.dpll.lockdrm_WARN_ON(!dpll_mgr)DPLL 0DPLL 1TBT PLLTC PLL 1TC PLL 2TC PLL 3TC PLL 4DPLL 2DPLL 3DPLL 4TC PLL 5TC PLL 6MG PLL 1MG PLL 2MG PLL 3MG PLL 4PORT PLL APORT PLL BPORT PLL CWRPLL 1WRPLL 2SPLLLCPLL 810LCPLL 1350LCPLL 2700PCH DPLL APCH DPLL Bdrivers/gpu/drm/i915/display/intel_dpll_mgr.c%s %s: [drm] bad port clock sel drm_WARN_ON(((&_Generic(i915, const struct drm_i915_private *: (&((const struct drm_i915_private *)(i915))->display), struct drm_i915_private *: (&((struct drm_i915_private *)(i915))->display), const struct intel_display *: (i915), struct intel_display *: (i915))->info.__runtime_info)->step) == STEP_NONE)drm_WARN_ON(p0 == 0 || p1 == 0 || p2 == 0)drm_WARN_ON((shared_dpll_state->pipe_mask & ((((1UL))) << (crtc->pipe))) != 0)dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, fp0: 0x%x, fp1: 0x%x dpll_hw_state: wrpll: 0x%x spll: 0x%x dpll_hw_state: ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, div0: 0x%x, mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x drm_WARN_ON(!drm_modeset_is_locked(&s->dev->mode_config.connection_mutex))%s %s: [drm] %s: pll in active use but not on in sw tracking [drm] *ERROR* %s: pll in active use but not on in sw tracking %s %s: [drm] %s: pll is on but not used by any active pipe [drm] *ERROR* %s: pll is on but not used by any active pipe %s %s: [drm] %s: pll on state mismatch (expected %i, found %i) [drm] *ERROR* %s: pll on state mismatch (expected %i, found %i) %s %s: [drm] %s: more active pll users than references: 0x%x vs 0x%x [drm] *ERROR* %s: more active pll users than references: 0x%x vs 0x%x %s %s: [drm] %s: pll active mismatch (expected pipe %c in active mask 0x%x) [drm] *ERROR* %s: pll active mismatch (expected pipe %c in active mask 0x%x) %s %s: [drm] %s: pll active mismatch (didn't expect pipe %c in active mask 0x%x) [drm] *ERROR* %s: pll active mismatch (didn't expect pipe %c in active mask 0x%x) %s %s: [drm] %s: pll enabled crtcs mismatch (expected 0x%x in 0x%x) [drm] *ERROR* %s: pll enabled crtcs mismatch (expected 0x%x in 0x%x) %s %s: [drm] %s: pll hw state mismatch [drm] *ERROR* %s: pll hw state mismatch Invalid WRPLL PDIV divider value, fixing it. %s %s: [drm] Unsupported link rate i915->display.dpll.ref_clks.nsscdrm_WARN_ON(clk_div->vco == 0 || clk_div->dot != crtc_state->port_clock)drm_WARN_ON(crtc_state->port_clock / 2 != 135000)[drm] *ERROR* PLL %d not locked [drm] *ERROR* PLL %d Power not enabled drm_WARN_ON(!(val & (1 << 31)))%s %s: [drm] PCH refclk assertion failure, should be active but is disabled [drm] *ERROR* PCH refclk assertion failure, should be active but is disabled [drm] *ERROR* PLL %d Power not disabled [drm] *ERROR* DPLL %d not locked [drm] *ERROR* Power state not reset for PLL:%d drm_WARN_ON(val & ~((u32)(((((1UL))) << (1)) + ((int)(sizeof(struct { int:(-!!((sizeof(int) == sizeof(*(8 ? ((void *)((long)(1) * 0l)) : (int *)8))) && ((1) < 0 || (1) > 31))); }))))))Unexpected flags in TRANS_CMTG_CHICKEN: %08x lane stagger config different for lane 01 (%08x) and 23 (%08x) [drm] *ERROR* Power state not set for PLL:%d drm_WARN_ON_ONCE(i915->display.vbt.override_afc_startup && !(!(_Generic((div0_reg), i915_reg_t: (div0_reg).reg, i915_mcr_reg_t: (div0_reg).reg) == _Generic((((const i915_reg_t){ .reg = (0) })), i915_reg_t: (((const i915_reg_t){ .reg = (0) })).reg, i915_mcr_reg_t: (((const i915_reg_t){ .reg = (0) })).reg))))drm_WARN_ON(dpll_mask & ((((1UL))) << (pll->info->id)))drm_WARN_ON(dpll_mask & ~dpll_mask_all)[CRTC:%d:%s] sharing existing %s (pipe mask 0x%x, active 0x%x) [CRTC:%d:%s] using pre-allocated %s %s %s: [drm] asserting DPLL %s with no DPLL %s %s: [drm] %s assertion failure (expected %s, current %s) [drm] *ERROR* %s assertion failure (expected %s, current %s) drm_WARN_ON(pll == ((void *)0))drm_WARN_ON(!(pll->state.pipe_mask & pipe_mask))drm_WARN_ON(pll->active_mask & pipe_mask)enable %s (active 0x%x, on? %d) for [CRTC:%d:%s] %s %s: [drm] %s not used by [CRTC:%d:%s] disable %s (active 0x%x, on? %d) for [CRTC:%d:%s] drm_WARN_ON((shared_dpll_state->pipe_mask & ((((1UL))) << (crtc->pipe))) == 0)drm_WARN_ON(i >= (sizeof(i915->display.dpll.shared_dplls) / sizeof((i915->display.dpll.shared_dplls)[0]) + ((int)sizeof(struct {_Static_assert(!(__builtin_types_compatible_p(typeof((i915->display.dpll.shared_dplls)), typeof(&(i915->display.dpll.shared_dplls)[0]))), "must be array");}))))drm_WARN_ON(dpll_info[i].id >= 32)drm_WARN_ON(!pll->info->funcs->get_freq)%s hw state readout: pipe_mask 0x%x, on %i %s enabled but not in use, disabling %s %s: [drm] %s: pll active mismatch (didn't expect pipe %c in active mask (0x%x)) [drm] *ERROR* %s: pll active mismatch (didn't expect pipe %c in active mask (0x%x)) %s %s: [drm] %s: pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x)) [drm] *ERROR* %s: pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))  q  . 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