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%s->%s [CRTC:%d:%s] dbuf slices 0x%x -> 0x%x, ddb (%d - %d) -> (%d - %d), active pipes 0x%x -> 0x%x drm_WARN_ON(wm->wm[level].min_ddb_alloc != ((u16)~0U))Requested display configuration exceeds system DDB limitationsdrm_WARN_ON(iter.size != 0 || iter.data_rate != 0)[PLANE:%d:%s] Can't change DDB during async flip [PLANE:%d:%s] Can't change watermarks during async flip [PLANE:%d:%s] ddb (%4d - %4d) -> (%4d - %4d), size %4d -> %4d [PLANE:%d:%s] level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm [PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d [PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d [PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d Restricting QGV points: 0x%x -> 0x%x Relaxing QGV points: 0x%x -> 0x%x [drm] *ERROR* Failed to enable SAGV [drm] Enabling IPC: WM will be proper only after next commit Updating dbuf ratio to %d (mbus joined: %s) [CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x, mbus joined: %s Disabling redundant MBUS joining (active pipes 0x%x) BIOS has misprogrammed the DBUF, disabling all planes drm_WARN_ON(crtc_state->active_planes != 0)[drm] *ERROR* mismatch in DBUF Slices (expected 0x%x, got 0x%x) [drm] *ERROR* [PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u) [drm] *ERROR* [PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u) [drm] *ERROR* [PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u) [drm] *ERROR* [PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u) [drm] *ERROR* [PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u)) drm_WARN_ON(display->sagv.status == I915_SAGV_UNKNOWN)Couldn't read SAGV block time! SAGV supported: %s, original SAGV block time: %u us %s %s: [drm] Excessive SAGV block time %u, ignoring [drm] *ERROR* SKL Mailbox read error = %d ! + * 4  @ @  @ @ @ @ Q    >    ,     5 L                              i915.import_ns=PWMGCC: (Debian 12.2.0-14) 12.2.0GNU,[;@ T`oX04! /P.@ Y@ r  D0 l@``0&pB`#Wm\;` (/W \}\i?`8L@j h*8Io*Ni1M]wO!P200Q LjPR)T:TUtV;`V/.VCJWd W}Xd@Y pYT " 9 V Y1} 0Z    0d d 5 U fq  f @gj   mY  3 0tR k ta Pu   skl_watermark.cintel_crtc_can_enable_sagvskl_wm_latencyintel_dbuf_destroy_stateintel_dbuf_duplicate_statepipe_mbus_dbox_ctl_updateintel_mbus_dbox_updateintel_mbus_joined_pipeintel_sagv_status_openintel_sagv_status_showskl_watermark_ipc_status_openskl_watermark_ipc_status_showsagv_status.0skl_sagv_disableadjust_wm_latency.isra.0skl_ddb_entry_for_slicesskl_compute_transition_wmintel_dbuf_mbus_join_updateskl_compute_dbuf_slices.isra.0adlp_allowed_dbufsdg2_allowed_dbufstgl_allowed_dbufsicl_allowed_dbufsskl_compute_wm_paramsskl_compute_plane_wm_paramsskl_compute_plane_wmskl_compute_wm_levelsskl_build_plane_wm_singleskl_ddb_get_hw_plane_stateskl_pipe_wm_get_hw_stateskl_compute_wmskl_watermark_ipc_status_writeintel_dbuf_funcsintel_dbuf_mdclk_min_tracker_updateskl_wm_get_hw_state_and_sanitizeskl_wm_funcsskl_watermark_ipc_status_fopsintel_sagv_status_fops__UNIQUE_ID_import_ns707.LC2.LC21__x86_return_thunk__i915_to_displaykfreekmemdup_noprofintel_dmc_wl_getto_intel_uncore__x86_indirect_thunk_raxintel_dmc_wl_put__warn_printk__drm_to_displayintel_atomic_get_new_global_obj_stateintel_atomic_get_old_global_obj_stateintel_crtc_for_pipedev_driver_stringsingle_openseq_printf__drm_dev_dbgskl_pcode_request_dev_errmemset__sw_hweight32intel_fb_is_ccs_modifierintel_format_info_is_yuv_semiplanarintel_fb_is_tiled_modifierintel_plane_pixel_rate__stack_chk_failintel_wm_plane_visibleintel_usecs_to_scanlinesintel_atomic_get_global_obj_stateintel_calc_active_pipesintel_atomic_lock_global_statedrm_mode_get_hv_timingintel_atomic_get_crtc_statedrm_format_infointel_atomic_get_bw_stateintel_atomic_get_old_bw_stateintel_cdclk_state_set_joined_mbusdrm_atomic_get_plane_state__drm_debugintel_atomic_serialize_global_stateintel_enabled_dbuf_slices_maskintel_has_sagvintel_sagv_pre_plane_updateintel_atomic_get_new_bw_stateicl_pcode_restrict_qgv_pointsintel_sagv_post_plane_updatesnb_pcode_write_timeoutintel_can_enable_sagvskl_ddb_dbuf_slice_maskskl_plane_relative_data_rateskl_plane_wm_levelskl_plane_trans_wmskl_ddb_allocation_overlapsskl_watermark_ipc_enabledskl_watermark_ipc_updatekstrtobool_from_userintel_runtime_pm_get_dev_infointel_runtime_pm_put_uncheckedskl_watermark_ipc_initintel_atomic_get_dbuf_stateintel_dbuf_initkmalloc_caches__kmalloc_cache_noprofintel_atomic_global_obj_initintel_dbuf_state_set_mdclk_cdclk_ratiointel_dbuf_mdclk_cdclk_ratio_updateintel_cdclk_is_decreasing_laterintel_mdclk_cdclk_ratiointel_plane_disable_noatomicintel_dbuf_mbus_pre_ddb_updateintel_dbuf_mbus_post_ddb_updateintel_crtc_wait_for_next_vblankintel_dbuf_pre_plane_updategen9_dbuf_slices_updateintel_dbuf_post_plane_updateintel_wm_state_verifyintel_display_power_get_if_enabledintel_display_power_put_uncheckedskl_wm_initsnb_pcode_readintel_print_wm_latencyskl_watermark_debugfs_registerdebugfs_create_file_fullskl_watermark_max_latencyintel_program_dpkgc_latencyseq_lseekseq_readsingle_release;0000 0F0e0t003456  700'899J8\:8;N<U X_ g7< 0 7 0  8 3k /y G~> 6 > [> n +> >  3   /)> ?@  ?# @D \ k ? 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