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SW Sequencing must be used. Flash controller busy, cannot get access SW has already locked the resource. Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x) Failed to write receive address at index %d SHRA[%d] might be locked by ME - FWSM=0x%8.8x After fix-ups FlowControl is now = %x Timeout error - flash cycle did not complete. Retrying Byte %2.2X at offset %u Retrying Byte %8.8X at offset %u ERROR: No valid NVM bank present Unable to determine valid NVM bank via EEC - reading flash signature Could not detect valid bank, assuming bank 0 LAN_INIT_DONE not set, increase timeout Auto Read Done did not complete PHY Reset Asserted not set - needs delay ULP_CONFIG_DONE took %d msec. This is a firmware bug ULP_CONFIG_DONE cleared after %d msec Error in ULP disable flow: %d Failed to initialize PHY flow Required LANPHYPC toggle blocked by ME ME blocked access to PHY after reset ERROR: Flash registers not mapped Cannot determine PHY addr. Erroring out CABLE_DISCONNECTED %s set after %dmsec Error initializing identification LED PCI-E Master disable polling has failed. Issuing a global reset to ich8lan Error configuring flow control Workaround applies to ICH8 only. Failed to init PHY flow ret_val=%d Error %d in resume workarounds drivers/net/ethernet/intel/e1000e/ich8lan.cNVM Read Error contention for Phy access NVM read error: %d Flash commit failed. NVM update error: %d EEPROM not present Failed to disable ULP Reset blocked by ME notFailed to force SMBUS: %d Error in ULP enable flow: %d Zeroing the MTA Masking off all interrupts max_frame_size not set. Speed not set. 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