[ { "EventCode": "0x01A0", "EventName": "EAGA_VAL", "BriefDescription": "This event counts valid cycles of EAGA pipeline." }, { "EventCode": "0x01A1", "EventName": "EAGB_VAL", "BriefDescription": "This event counts valid cycles of EAGB pipeline." }, { "EventCode": "0x01A3", "EventName": "PRX_VAL", "BriefDescription": "This event counts valid cycles of PRX pipeline." }, { "EventCode": "0x01A4", "EventName": "EXA_VAL", "BriefDescription": "This event counts valid cycles of EXA pipeline." }, { "EventCode": "0x01A5", "EventName": "EXB_VAL", "BriefDescription": "This event counts valid cycles of EXB pipeline." }, { "EventCode": "0x01A6", "EventName": "EXC_VAL", "BriefDescription": "This event counts valid cycles of EXC pipeline." }, { "EventCode": "0x01A7", "EventName": "EXD_VAL", "BriefDescription": "This event counts valid cycles of EXD pipeline." }, { "EventCode": "0x01A8", "EventName": "FLA_VAL", "BriefDescription": "This event counts valid cycles of FLA pipeline." }, { "EventCode": "0x01A9", "EventName": "FLB_VAL", "BriefDescription": "This event counts valid cycles of FLB pipeline." }, { "EventCode": "0x01AA", "EventName": "STEA_VAL", "BriefDescription": "This event counts valid cycles of STEA pipeline." }, { "EventCode": "0x01AB", "EventName": "STEB_VAL", "BriefDescription": "This event counts valid cycles of STEB pipeline." }, { "EventCode": "0x01AC", "EventName": "STFL_VAL", "BriefDescription": "This event counts valid cycles of STFL pipeline." }, { "EventCode": "0x01AD", "EventName": "STPX_VAL", "BriefDescription": "This event counts valid cycles of STPX pipeline." }, { "EventCode": "0x01B0", "EventName": "FLA_VAL_PRD_CNT", "BriefDescription": "This event counts the number of 1's in the predicate bits of request in FLA pipeline, where it is corrected so that it becomes 32 when all bits are 1." }, { "EventCode": "0x01B1", "EventName": "FLB_VAL_PRD_CNT", "BriefDescription": "This event counts the number of 1's in the predicate bits of request in FLB pipeline, where it is corrected so that it becomes 32 when all bits are 1." }, { "EventCode": "0x01B2", "EventName": "FLA_VAL_FOR_PRD", "BriefDescription": "This event counts valid cycles of FLA pipeline." }, { "EventCode": "0x01B3", "EventName": "FLB_VAL_FOR_PRD", "BriefDescription": "This event counts valid cycles of FLB pipeline." }, { "EventCode": "0x0240", "EventName": "L1_PIPE0_VAL", "BriefDescription": "This event counts valid cycles of L1D cache pipeline#0." }, { "EventCode": "0x0241", "EventName": "L1_PIPE1_VAL", "BriefDescription": "This event counts valid cycles of L1D cache pipeline#1." }, { "EventCode": "0x0242", "EventName": "L1_PIPE2_VAL", "BriefDescription": "This event counts valid cycles of L1D cache pipeline#2." }, { "EventCode": "0x0250", "EventName": "L1_PIPE0_COMP", "BriefDescription": "This event counts completed requests in L1D cache pipeline#0." }, { "EventCode": "0x0251", "EventName": "L1_PIPE1_COMP", "BriefDescription": "This event counts completed requests in L1D cache pipeline#1." }, { "EventCode": "0x025A", "EventName": "L1_PIPE_ABORT_STLD_INTLK", "BriefDescription": "This event counts aborted requests in L1D pipelines that due to store-load interlock." }, { "EventCode": "0x026C", "EventName": "L1I_PIPE_COMP", "BriefDescription": "This event counts completed requests in L1I cache pipeline." }, { "EventCode": "0x026D", "EventName": "L1I_PIPE_VAL", "BriefDescription": "This event counts valid cycles of L1I cache pipeline." }, { "EventCode": "0x0278", "EventName": "L1_PIPE0_VAL_IU_TAG_ADRS_SCE", "BriefDescription": "This event counts requests in L1D cache pipeline#0 that its sce bit of tagged address is 1." }, { "EventCode": "0x0279", "EventName": "L1_PIPE1_VAL_IU_TAG_ADRS_SCE", "BriefDescription": "This event counts requests in L1D cache pipeline#1 that its sce bit of tagged address is 1." }, { "EventCode": "0x02A0", "EventName": "L1_PIPE0_VAL_IU_NOT_SEC0", "BriefDescription": "This event counts requests in L1D cache pipeline#0 that its sector cache ID is not 0." }, { "EventCode": "0x02A1", "EventName": "L1_PIPE1_VAL_IU_NOT_SEC0", "BriefDescription": "This event counts requests in L1D cache pipeline#1 that its sector cache ID is not 0." }, { "EventCode": "0x02B0", "EventName": "L1_PIPE_COMP_GATHER_2FLOW", "BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 2 flows because 2 elements could not be combined." }, { "EventCode": "0x02B1", "EventName": "L1_PIPE_COMP_GATHER_1FLOW", "BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 1 flow because 2 elements could be combined." }, { "EventCode": "0x02B2", "EventName": "L1_PIPE_COMP_GATHER_0FLOW", "BriefDescription": "This event counts the number of times where 2 elements of the gather instructions became 0 flow because both predicate values are 0." }, { "EventCode": "0x02B3", "EventName": "L1_PIPE_COMP_SCATTER_1FLOW", "BriefDescription": "This event counts the number of flows of the scatter instructions." }, { "EventCode": "0x02B8", "EventName": "L1_PIPE0_COMP_PRD_CNT", "BriefDescription": "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#0, where it is corrected so that it becomes 64 when all bits are 1." }, { "EventCode": "0x02B9", "EventName": "L1_PIPE1_COMP_PRD_CNT", "BriefDescription": "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#1, where it is corrected so that it becomes 64 when all bits are 1." }, { "EventCode": "0x0330", "EventName": "L2_PIPE_VAL", "BriefDescription": "This event counts valid cycles of L2 cache pipeline." }, { "EventCode": "0x0350", "EventName": "L2_PIPE_COMP_ALL", "BriefDescription": "This event counts completed requests in L2 cache pipeline." }, { "EventCode": "0x0370", "EventName": "L2_PIPE_COMP_PF_L2MIB_MCH", "BriefDescription": "This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access." }, { "ArchStdEvent": "STALL_FRONTEND_TLB", "BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_MEMBOUND when there is a demand instruction miss in the instruction TLB." }, { "ArchStdEvent": "STALL_BACKEND_TLB", "BriefDescription": "This event counts every cycle counted by STALL_BACKEND_MEMBOUND when there is a demand data miss in the data TLB." }, { "ArchStdEvent": "STALL_BACKEND_ST", "BriefDescription": "This event counts every cycle counted by STALL_BACKEND_MEMBOUND when the backend is stalled waiting for a store." }, { "ArchStdEvent": "STALL_BACKEND_ILOCK", "BriefDescription": "This event counts every cycle counted by STALL_BACKEND when operations are available from the frontend but at least one is not ready to be sent to the backend because of an input dependency." } ]