# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/qcom,sdm670-camss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SDM670 Camera Subsystem (CAMSS)

maintainers:
  - Richard Acayan <mailingradian@gmail.com>

description:
  The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.

properties:
  compatible:
    const: qcom,sdm670-camss

  reg:
    maxItems: 9

  reg-names:
    items:
      - const: csid0
      - const: csid1
      - const: csid2
      - const: csiphy0
      - const: csiphy1
      - const: csiphy2
      - const: vfe0
      - const: vfe1
      - const: vfe_lite

  interrupts:
    maxItems: 9

  interrupt-names:
    items:
      - const: csid0
      - const: csid1
      - const: csid2
      - const: csiphy0
      - const: csiphy1
      - const: csiphy2
      - const: vfe0
      - const: vfe1
      - const: vfe_lite

  clocks:
    maxItems: 22

  clock-names:
    items:
      - const: camnoc_axi
      - const: cpas_ahb
      - const: csi0
      - const: csi1
      - const: csi2
      - const: csiphy0
      - const: csiphy0_timer
      - const: csiphy1
      - const: csiphy1_timer
      - const: csiphy2
      - const: csiphy2_timer
      - const: gcc_camera_ahb
      - const: gcc_camera_axi
      - const: soc_ahb
      - const: vfe0
      - const: vfe0_axi
      - const: vfe0_cphy_rx
      - const: vfe1
      - const: vfe1_axi
      - const: vfe1_cphy_rx
      - const: vfe_lite
      - const: vfe_lite_cphy_rx

  iommus:
    maxItems: 4

  power-domains:
    items:
      - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
      - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
      - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller.

  power-domain-names:
    items:
      - const: ife0
      - const: ife1
      - const: top

  vdda-phy-supply:
    description:
      Phandle to a regulator supply to PHY core block.

  vdda-pll-supply:
    description:
      Phandle to 1.8V regulator supply to PHY refclk pll block.

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    description:
      CSI input ports.

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data from CSIPHY0.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              clock-lanes:
                maxItems: 1

              data-lanes:
                minItems: 1
                maxItems: 4

            required:
              - clock-lanes
              - data-lanes

      port@1:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data from CSIPHY1.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              clock-lanes:
                maxItems: 1

              data-lanes:
                minItems: 1
                maxItems: 4

            required:
              - clock-lanes
              - data-lanes

      port@2:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data from CSIPHY2.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              clock-lanes:
                maxItems: 1

              data-lanes:
                minItems: 1
                maxItems: 4

            required:
              - clock-lanes
              - data-lanes

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - interrupt-names
  - clocks
  - clock-names
  - iommus
  - power-domains
  - power-domain-names
  - vdda-phy-supply
  - vdda-pll-supply

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,camcc-sdm845.h>
    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        isp@acb3000 {
            compatible = "qcom,sdm670-camss";

            reg = <0 0x0acb3000 0 0x1000>,
                  <0 0x0acba000 0 0x1000>,
                  <0 0x0acc8000 0 0x1000>,
                  <0 0x0ac65000 0 0x1000>,
                  <0 0x0ac66000 0 0x1000>,
                  <0 0x0ac67000 0 0x1000>,
                  <0 0x0acaf000 0 0x4000>,
                  <0 0x0acb6000 0 0x4000>,
                  <0 0x0acc4000 0 0x4000>;
            reg-names = "csid0",
                        "csid1",
                        "csid2",
                        "csiphy0",
                        "csiphy1",
                        "csiphy2",
                        "vfe0",
                        "vfe1",
                        "vfe_lite";

            interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>;
            interrupt-names = "csid0",
                              "csid1",
                              "csid2",
                              "csiphy0",
                              "csiphy1",
                              "csiphy2",
                              "vfe0",
                              "vfe1",
                              "vfe_lite";

            clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
                     <&camcc CAM_CC_CPAS_AHB_CLK>,
                     <&camcc CAM_CC_IFE_0_CSID_CLK>,
                     <&camcc CAM_CC_IFE_1_CSID_CLK>,
                     <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
                     <&camcc CAM_CC_CSIPHY0_CLK>,
                     <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
                     <&camcc CAM_CC_CSIPHY1_CLK>,
                     <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
                     <&camcc CAM_CC_CSIPHY2_CLK>,
                     <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
                     <&gcc GCC_CAMERA_AHB_CLK>,
                     <&gcc GCC_CAMERA_AXI_CLK>,
                     <&camcc CAM_CC_SOC_AHB_CLK>,
                     <&camcc CAM_CC_IFE_0_CLK>,
                     <&camcc CAM_CC_IFE_0_AXI_CLK>,
                     <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
                     <&camcc CAM_CC_IFE_1_CLK>,
                     <&camcc CAM_CC_IFE_1_AXI_CLK>,
                     <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
                     <&camcc CAM_CC_IFE_LITE_CLK>,
                     <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>;
            clock-names = "camnoc_axi",
                          "cpas_ahb",
                          "csi0",
                          "csi1",
                          "csi2",
                          "csiphy0",
                          "csiphy0_timer",
                          "csiphy1",
                          "csiphy1_timer",
                          "csiphy2",
                          "csiphy2_timer",
                          "gcc_camera_ahb",
                          "gcc_camera_axi",
                          "soc_ahb",
                          "vfe0",
                          "vfe0_axi",
                          "vfe0_cphy_rx",
                          "vfe1",
                          "vfe1_axi",
                          "vfe1_cphy_rx",
                          "vfe_lite",
                          "vfe_lite_cphy_rx";

            iommus = <&apps_smmu 0x808 0x0>,
                     <&apps_smmu 0x810 0x8>,
                     <&apps_smmu 0xc08 0x0>,
                     <&apps_smmu 0xc10 0x8>;

            power-domains = <&camcc IFE_0_GDSC>,
                            <&camcc IFE_1_GDSC>,
                            <&camcc TITAN_TOP_GDSC>;
            power-domain-names = "ife0",
                                 "ife1",
                                 "top";

            vdda-phy-supply = <&vreg_l1a_1p225>;
            vdda-pll-supply = <&vreg_l8a_1p8>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;

                    csiphy_ep0: endpoint {
                        clock-lanes = <7>;
                        data-lanes = <0 1 2 3>;
                        remote-endpoint = <&front_sensor_ep>;
                    };
                };
            };
        };
    };