# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/qcom,sm8550-iris.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm iris video encode and decode accelerators

maintainers:
  - Vikash Garodia <quic_vgarodia@quicinc.com>
  - Dikshita Agarwal <quic_dikshita@quicinc.com>

description:
  The iris video processing unit is a video encode and decode accelerator
  present on Qualcomm platforms.

allOf:
  - $ref: qcom,venus-common.yaml#

properties:
  compatible:
    const: qcom,sm8550-iris

  power-domains:
    maxItems: 4

  power-domain-names:
    items:
      - const: venus
      - const: vcodec0
      - const: mxc
      - const: mmcx

  clocks:
    maxItems: 3

  clock-names:
    items:
      - const: iface
      - const: core
      - const: vcodec0_core

  interconnects:
    maxItems: 2

  interconnect-names:
    items:
      - const: cpu-cfg
      - const: video-mem

  resets:
    maxItems: 1

  reset-names:
    items:
      - const: bus

  iommus:
    maxItems: 2

  dma-coherent: true

  operating-points-v2: true

  opp-table:
    type: object

required:
  - compatible
  - power-domain-names
  - interconnects
  - interconnect-names
  - resets
  - reset-names
  - iommus
  - dma-coherent

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/clock/qcom,sm8550-gcc.h>
    #include <dt-bindings/clock/qcom,sm8450-videocc.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interconnect/qcom,icc.h>
    #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
    #include <dt-bindings/power/qcom-rpmpd.h>
    #include <dt-bindings/power/qcom,rpmhpd.h>

    video-codec@aa00000 {
        compatible = "qcom,sm8550-iris";
        reg = <0x0aa00000 0xf0000>;
        interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;

        power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
                        <&videocc VIDEO_CC_MVS0_GDSC>,
                        <&rpmhpd RPMHPD_MXC>,
                        <&rpmhpd RPMHPD_MMCX>;
        power-domain-names = "venus", "vcodec0", "mxc", "mmcx";

        clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
                 <&videocc VIDEO_CC_MVS0C_CLK>,
                 <&videocc VIDEO_CC_MVS0_CLK>;
        clock-names = "iface", "core", "vcodec0_core";

        interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
                         &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ALWAYS>,
                        <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS
                         &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
        interconnect-names = "cpu-cfg", "video-mem";

        memory-region = <&video_mem>;

        resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>;
        reset-names = "bus";

        iommus = <&apps_smmu 0x1940 0x0000>,
                 <&apps_smmu 0x1947 0x0000>;
        dma-coherent;

        operating-points-v2 = <&iris_opp_table>;

        iris_opp_table: opp-table {
            compatible = "operating-points-v2";

            opp-240000000 {
                opp-hz = /bits/ 64 <240000000>;
                required-opps = <&rpmhpd_opp_svs>,
                                <&rpmhpd_opp_low_svs>;
            };

            opp-338000000 {
                opp-hz = /bits/ 64 <338000000>;
                required-opps = <&rpmhpd_opp_svs>,
                                <&rpmhpd_opp_svs>;
            };

            opp-366000000 {
                opp-hz = /bits/ 64 <366000000>;
                required-opps = <&rpmhpd_opp_svs_l1>,
                                <&rpmhpd_opp_svs_l1>;
            };

            opp-444000000 {
                opp-hz = /bits/ 64 <444000000>;
                required-opps = <&rpmhpd_opp_turbo>,
                                <&rpmhpd_opp_turbo>;
            };

            opp-533333334 {
                opp-hz = /bits/ 64 <533333334>;
                required-opps = <&rpmhpd_opp_turbo_l1>,
                                <&rpmhpd_opp_turbo_l1>;
            };
        };
    };
...