# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/ti,am65-pci-host.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI AM65 PCI Host

maintainers:
  - Kishon Vijay Abraham I <kishon@ti.com>

allOf:
  - $ref: /schemas/pci/pci-host-bridge.yaml#

properties:
  compatible:
    enum:
      - ti,am654-pcie-rc
      - ti,keystone-pcie

  reg:
    minItems: 4
    maxItems: 6

  reg-names:
    minItems: 4
    items:
      - const: app
      - const: dbics
      - const: config
      - const: atu
      - const: vmap_lp
      - const: vmap_hp

  interrupts:
    maxItems: 1

  power-domains:
    maxItems: 1

  ti,syscon-pcie-id:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: Phandle to the SYSCON entry
          - description: pcie_device_id register offset within SYSCON
    description: Phandle to the SYSCON entry required for getting PCIe device/vendor ID

  ti,syscon-pcie-mode:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: Phandle to the SYSCON entry
          - description: pcie_ctrl register offset within SYSCON
    description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode.

  msi-map: true

  dma-coherent: true

  num-viewport:
    $ref: /schemas/types.yaml#/definitions/uint32

  phys:
    description: per-lane PHYs
    minItems: 1
    maxItems: 2

  phy-names:
    minItems: 1
    maxItems: 2
    items:
      pattern: '^pcie-phy[0-1]$'

  memory-region:
    maxItems: 1
    description: |
      phandle to a restricted DMA pool to be used for all devices behind
      this controller. The regions should be defined according to
      reserved-memory/shared-dma-pool.yaml.
      Note that enforcement via the PVU will only be available to
      ti,am654-pcie-rc devices.

required:
  - compatible
  - reg
  - reg-names
  - max-link-speed
  - ti,syscon-pcie-id
  - ti,syscon-pcie-mode
  - ranges

if:
  properties:
    compatible:
      enum:
        - ti,am654-pcie-rc
then:
  required:
    - dma-coherent
    - power-domains
    - msi-map
    - num-viewport
else:
  properties:
    reg:
      maxItems: 4

    reg-names:
      maxItems: 4

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/phy/phy.h>
    #include <dt-bindings/soc/ti,sci_pm_domain.h>

    pcie0_rc: pcie@5500000 {
        compatible = "ti,am654-pcie-rc";
        reg =  <0x5500000 0x1000>,
               <0x5501000 0x1000>,
               <0x10000000 0x2000>,
               <0x5506000 0x1000>,
               <0x2900000 0x1000>,
               <0x2908000 0x1000>;
        reg-names = "app", "dbics", "config", "atu", "vmap_lp", "vmap_hp";
        power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
        #address-cells = <3>;
        #size-cells = <2>;
        ranges = <0x81000000 0 0          0x10020000 0 0x00010000>,
                 <0x82000000 0 0x10030000 0x10030000 0 0x07FD0000>;
        ti,syscon-pcie-id = <&scm_conf 0x0210>;
        ti,syscon-pcie-mode = <&scm_conf 0x4060>;
        bus-range = <0x0 0xff>;
        num-viewport = <16>;
        max-link-speed = <2>;
        dma-coherent;
        interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
        msi-map = <0x0 &gic_its 0x0 0x10000>;
        device_type = "pci";
        num-lanes = <1>;
        phys = <&serdes0 PHY_TYPE_PCIE 0>;
        phy-names = "pcie-phy0";
    };