// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for NXP LS1088A QDS Board.
 *
 * Copyright 2017 NXP
 *
 * Harninder Rai <harninder.rai@nxp.com>
 *
 */

/dts-v1/;

#include "fsl-ls1088a.dtsi"

/ {
	model = "LS1088A QDS Board";
	compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
};

&dspi {
	bus-num = <0>;
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <1000000>;
	};

	flash@1 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-cpol;
		spi-cpha;
		spi-max-frequency = <3500000>;
		reg = <1>;
	};

	flash@2 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-cpol;
		spi-cpha;
		spi-max-frequency = <3500000>;
		reg = <2>;
	};
};

&i2c0 {
	status = "okay";

	i2c-mux@77 {
		compatible = "nxp,pca9547";
		reg = <0x77>;
		#address-cells = <1>;
		#size-cells = <0>;

		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x2>;

			ina220@40 {
				compatible = "ti,ina220";
				reg = <0x40>;
				shunt-resistor = <1000>;
			};

			ina220@41 {
				compatible = "ti,ina220";
				reg = <0x41>;
				shunt-resistor = <1000>;
			};
		};

		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x3>;

			temp-sensor@4c {
				compatible = "adi,adt7461a";
				reg = <0x4c>;
			};

			rtc@51 {
				compatible = "nxp,pcf2129";
				reg = <0x51>;
				/* IRQ10_B */
				interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
			};

			eeprom@56 {
				compatible = "atmel,24c512";
				reg = <0x56>;
			};

			eeprom@57 {
				compatible = "atmel,24c512";
				reg = <0x57>;
			};
		};
	};
};

&ifc {
	ranges = <0 0 0x5 0x80000000 0x08000000
		  2 0 0x5 0x30000000 0x00010000
		  3 0 0x5 0x20000000 0x00010000>;
	status = "okay";

	flash@0,0 {
		compatible = "cfi-flash";
		reg = <0x0 0x0 0x8000000>;
		bank-width = <2>;
		device-width = <1>;
	};

	nand@2,0 {
		compatible = "fsl,ifc-nand";
		reg = <0x2 0x0 0x10000>;
	};

	fpga: board-control@3,0 {
		compatible = "fsl,ls1088aqds-fpga", "fsl,fpga-qixis";
		reg = <0x3 0x0 0x0000100>;
	};
};

&duart0 {
	status = "okay";
};

&duart1 {
	status = "okay";
};

&esdhc {
	status = "okay";
};

&qspi {
	status = "okay";

	s25fs512s0: flash@0 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <50000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <1>;
		reg = <0>;
	};

	s25fs512s1: flash@1 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <50000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <1>;
		reg = <1>;
	};
};

&sata {
	status = "okay";
};