// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2023 Gateworks Corporation
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/net/ti-dp83867.h>

/ {
	aliases {
		ethernet0 = &eqos;
		rtc0 = &gsc_rtc;
		rtc1 = &snvs_rtc;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x0 0x40000000 0 0x80000000>;
	};

	gpio-keys {
		compatible = "gpio-keys";

		key-user-pb {
			label = "user_pb";
			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
			linux,code = <BTN_0>;
		};

		key-user-pb1x {
			label = "user_pb1x";
			linux,code = <BTN_1>;
			interrupt-parent = <&gsc>;
			interrupts = <0>;
		};

		key-erased {
			label = "key_erased";
			linux,code = <BTN_2>;
			interrupt-parent = <&gsc>;
			interrupts = <1>;
		};

		key-eeprom-wp {
			label = "eeprom_wp";
			linux,code = <BTN_3>;
			interrupt-parent = <&gsc>;
			interrupts = <2>;
		};

		key-tamper {
			label = "tamper";
			linux,code = <BTN_4>;
			interrupt-parent = <&gsc>;
			interrupts = <5>;
		};

		switch-hold {
			label = "switch_hold";
			linux,code = <BTN_5>;
			interrupt-parent = <&gsc>;
			interrupts = <7>;
		};
	};
};

&A53_0 {
	cpu-supply = <&buck3_reg>;
};

&A53_1 {
	cpu-supply = <&buck3_reg>;
};

&A53_2 {
	cpu-supply = <&buck3_reg>;
};

&A53_3 {
	cpu-supply = <&buck3_reg>;
};

&eqos {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_eqos>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	status = "okay";

	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			pinctrl-0 = <&pinctrl_ethphy0>;
			pinctrl-names = "default";
			reg = <0x0>;
			interrupt-parent = <&gpio3>;
			interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
			tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
			rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;

			leds {
				#address-cells = <1>;
				#size-cells = <0>;

				led@1 {
					reg = <1>;
					color = <LED_COLOR_ID_AMBER>;
					function = LED_FUNCTION_LAN;
					default-state = "keep";
				};

				led@2 {
					reg = <2>;
					color = <LED_COLOR_ID_GREEN>;
					function = LED_FUNCTION_LAN;
					default-state = "keep";
				};
			};
		};
	};
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	gsc: gsc@20 {
		compatible = "gw,gsc";
		reg = <0x20>;
		pinctrl-0 = <&pinctrl_gsc>;
		interrupt-parent = <&gpio2>;
		interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
		interrupt-controller;
		#interrupt-cells = <1>;
		#address-cells = <1>;
		#size-cells = <0>;

		adc {
			compatible = "gw,gsc-adc";
			#address-cells = <1>;
			#size-cells = <0>;

			channel@6 {
				gw,mode = <0>;
				reg = <0x06>;
				label = "temp";
			};

			channel@8 {
				gw,mode = <3>;
				reg = <0x08>;
				label = "vdd_bat";
			};

			channel@16 {
				gw,mode = <4>;
				reg = <0x16>;
				label = "fan_tach";
			};

			channel@82 {
				gw,mode = <2>;
				reg = <0x82>;
				label = "vdd_vin";
				gw,voltage-divider-ohms = <22100 1000>;
			};

			channel@84 {
				gw,mode = <2>;
				reg = <0x84>;
				label = "vdd_adc1";
				gw,voltage-divider-ohms = <10000 10000>;
			};

			channel@86 {
				gw,mode = <2>;
				reg = <0x86>;
				label = "vdd_adc2";
				gw,voltage-divider-ohms = <10000 10000>;
			};

			channel@88 {
				gw,mode = <2>;
				reg = <0x88>;
				label = "vdd_1p0";
			};

			channel@8c {
				gw,mode = <2>;
				reg = <0x8c>;
				label = "vdd_1p8";
			};

			channel@8e {
				gw,mode = <2>;
				reg = <0x8e>;
				label = "vdd_2p5";
			};

			channel@90 {
				gw,mode = <2>;
				reg = <0x90>;
				label = "vdd_3p3";
				gw,voltage-divider-ohms = <10000 10000>;
			};

			channel@92 {
				gw,mode = <2>;
				reg = <0x92>;
				label = "vdd_dram";
			};

			channel@98 {
				gw,mode = <2>;
				reg = <0x98>;
				label = "vdd_soc";
			};

			channel@9a {
				gw,mode = <2>;
				reg = <0x9a>;
				label = "vdd_arm";
			};

			channel@a2 {
				gw,mode = <2>;
				reg = <0xa2>;
				label = "vdd_gsc";
				gw,voltage-divider-ohms = <10000 10000>;
			};
		};

		fan-controller@0 {
			compatible = "gw,gsc-fan";
			reg = <0x0a>;
		};
	};

	gpio: gpio@23 {
		compatible = "nxp,pca9555";
		reg = <0x23>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&gsc>;
		interrupts = <4>;
	};

	eeprom@50 {
		compatible = "atmel,24c02";
		reg = <0x50>;
		pagesize = <16>;
	};

	eeprom@51 {
		compatible = "atmel,24c02";
		reg = <0x51>;
		pagesize = <16>;
	};

	eeprom@52 {
		compatible = "atmel,24c02";
		reg = <0x52>;
		pagesize = <16>;
	};

	eeprom@53 {
		compatible = "atmel,24c02";
		reg = <0x53>;
		pagesize = <16>;
	};

	gsc_rtc: rtc@68 {
		compatible = "dallas,ds1672";
		reg = <0x68>;
	};

	pmic@69 {
		compatible = "mps,mp5416";
		reg = <0x69>;

		regulators {
			/* vdd_soc */
			buck1 {
				regulator-name = "buck1";
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <1000000>;
				regulator-always-on;
				regulator-boot-on;
			};

			/* vdd_dram */
			buck2 {
				regulator-name = "buck2";
				regulator-min-microvolt = <1100000>;
				regulator-max-microvolt = <1100000>;
				regulator-always-on;
				regulator-boot-on;
			};

			/* vdd_arm */
			buck3_reg: buck3 {
				regulator-name = "buck3";
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <1000000>;
				regulator-always-on;
				regulator-boot-on;
			};

			/* vdd_1p8 */
			buck4 {
				regulator-name = "buck4";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-boot-on;
			};

			/* OUT2: nvcc_snvs_1p8 */
			ldo1 {
				regulator-name = "ldo1";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-boot-on;
			};

			/* OUT3: vdd_1p0 */
			ldo2 {
				regulator-name = "ldo2";
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <1000000>;
				regulator-always-on;
				regulator-boot-on;
			};

			/* OUT4: vdd_2p5 */
			ldo3 {
				regulator-name = "ldo3";
				regulator-min-microvolt = <2500000>;
				regulator-max-microvolt = <2500000>;
				regulator-always-on;
				regulator-boot-on;
			};

			/* OUT5: vdd_3p3 */
			ldo4 {
				regulator-name = "ldo4";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
				regulator-boot-on;
			};
		};
	};
};

/* off-board header */
&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c2>;
	pinctrl-1 = <&pinctrl_i2c2_gpio>;
	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	eeprom@52 {
		compatible = "atmel,24c32";
		reg = <0x52>;
		pagesize = <32>;
	};
};

/* off-board header */
&i2c3 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c3>;
	pinctrl-1 = <&pinctrl_i2c3_gpio>;
	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";
};

/* off-board header */
&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

/* console */
&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

/* off-board header */
&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";
};

/* off-board */
&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	bus-width = <4>;
	non-removable;
	status = "okay";
	bus-width = <4>;
	non-removable;
	status = "okay";
};

/* eMMC */
&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl_eqos: eqosgrp {
		fsl,pins = <
			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC			0x2
			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO			0x2
			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0		0x90
			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1		0x90
			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2		0x90
			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3		0x90
			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90
			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x90
			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x16
			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x16
			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x16
			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x16
			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x16
			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16
		>;
	};

	pinctrl_ethphy0: ethphy0grp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14	0x140 /* RST# */
			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x150 /* IRQ# */
		>;
	};

	pinctrl_gsc: gscgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x150 /* IRQ# */
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c2
			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c2
		>;
	};

	pinctrl_i2c1_gpio: i2c1gpiogrp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14	0x400001c2
			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15	0x400001c2
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c2
			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c2
		>;
	};

	pinctrl_i2c2_gpio: i2c2gpiogrp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16	0x400001c2
			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17	0x400001c2
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c2
			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c2
		>;
	};

	pinctrl_i2c3_gpio: i2c3gpiogrp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18	0x400001c2
			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19	0x400001c2
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140
			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140
			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x140
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX	0x140
			MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX	0x140
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x190
			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d0
			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d0
			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d0
			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d0
			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d0
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0x166
		>;
	};
};