// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2025 NXP
 */

/dts-v1/;

#include "imx8ulp-evk.dts"

/ {
	model = "NXP i.MX8ULP EVK9";
	compatible = "fsl,imx8ulp-9x9-evk", "fsl,imx8ulp";
};

&btcpu {
	sound-dai = <&sai6>;
};

&iomuxc1 {
	pinctrl_sai6: sai6grp {
		fsl,pins = <
			MX8ULP_PAD_PTE10__I2S6_TX_BCLK  0x43
			MX8ULP_PAD_PTE11__I2S6_TX_FS    0x43
			MX8ULP_PAD_PTE14__I2S6_TXD2     0x43
			MX8ULP_PAD_PTE6__I2S6_RXD0      0x43
		>;
	};
};

&pinctrl_enet {
	fsl,pins = <
		MX8ULP_PAD_PTF9__ENET0_MDC		0x43
		MX8ULP_PAD_PTF8__ENET0_MDIO             0x43
		MX8ULP_PAD_PTF5__ENET0_RXER             0x43
		MX8ULP_PAD_PTF6__ENET0_CRS_DV           0x43
		MX8ULP_PAD_PTF1__ENET0_RXD0             0x43
		MX8ULP_PAD_PTF0__ENET0_RXD1             0x43
		MX8ULP_PAD_PTF4__ENET0_TXEN             0x43
		MX8ULP_PAD_PTF3__ENET0_TXD0             0x43
		MX8ULP_PAD_PTF2__ENET0_TXD1             0x43
		MX8ULP_PAD_PTF7__ENET0_REFCLK           0x43
		MX8ULP_PAD_PTF10__ENET0_1588_CLKIN      0x43
	>;
};

&pinctrl_usb1 {
	fsl,pins = <
		MX8ULP_PAD_PTE16__USB0_ID		0x10003
		MX8ULP_PAD_PTE18__USB0_OC		0x10003
	>;
};

&pinctrl_usb2 {
	fsl,pins = <
		MX8ULP_PAD_PTD23__USB1_ID		0x10003
		MX8ULP_PAD_PTE20__USB1_OC		0x10003
	>;
};

&sai6 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_sai6>;
	pinctrl-1 = <&pinctrl_sai6>;
	assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>, <&cgc2 IMX8ULP_CLK_SAI6_SEL>;
	assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>;
	assigned-clock-rates = <12288000>;
	fsl,dataline = <1 0x01 0x04>;
	status = "okay";
};