// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022,2025 NXP
 */

#include "imx91_93_common.dtsi"

/{
	cm33: remoteproc-cm33 {
		compatible = "fsl,imx93-cm33";
		clocks = <&clk IMX93_CLK_CM33_GATE>;
		status = "disabled";
	};

	thermal-zones {
		cpu-thermal {
			polling-delay-passive = <250>;
			polling-delay = <2000>;

			thermal-sensors = <&tmu 0>;

			trips {
				cpu_alert: cpu-alert {
					temperature = <80000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu_crit: cpu-crit {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert>;
					cooling-device =
						<&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};
	};
};

&aips1 {
	mu1: mailbox@44230000 {
		compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
		reg = <0x44230000 0x10000>;
		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX93_CLK_MU1_B_GATE>;
		#mbox-cells = <2>;
		status = "disabled";
	};

	tmu: tmu@44482000 {
		compatible = "fsl,qoriq-tmu";
		reg = <0x44482000 0x1000>;
		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX93_CLK_TMC_GATE>;
		#thermal-sensor-cells = <1>;
		little-endian;
		fsl,tmu-range = <0x800000da 0x800000e9
				 0x80000102 0x8000012a
				 0x80000166 0x800001a7
				 0x800001b6>;
		fsl,tmu-calibration = <0x00000000 0x0000000e
				       0x00000001 0x00000029
				       0x00000002 0x00000056
				       0x00000003 0x000000a2
				       0x00000004 0x00000116
				       0x00000005 0x00000195
				       0x00000006 0x000001b2>;
	};
};

&aips2 {
	mu2: mailbox@42440000 {
		compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
		reg = <0x42440000 0x10000>;
		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX93_CLK_MU2_B_GATE>;
		#mbox-cells = <2>;
		status = "disabled";
	};
};

&cpus {
	A55_0: cpu@0 {
		device_type = "cpu";
		compatible = "arm,cortex-a55";
		reg = <0x0>;
		enable-method = "psci";
		#cooling-cells = <2>;
		cpu-idle-states = <&cpu_pd_wait>;
		i-cache-size = <32768>;
		i-cache-line-size = <64>;
		i-cache-sets = <128>;
		d-cache-size = <32768>;
		d-cache-line-size = <64>;
		d-cache-sets = <128>;
		next-level-cache = <&l2_cache_l0>;
	};

	A55_1: cpu@100 {
		device_type = "cpu";
		compatible = "arm,cortex-a55";
		reg = <0x100>;
		enable-method = "psci";
		#cooling-cells = <2>;
		cpu-idle-states = <&cpu_pd_wait>;
		i-cache-size = <32768>;
		i-cache-line-size = <64>;
		i-cache-sets = <128>;
		d-cache-size = <32768>;
		d-cache-line-size = <64>;
		d-cache-sets = <128>;
		next-level-cache = <&l2_cache_l1>;
	};

	l2_cache_l0: l2-cache-l0 {
		compatible = "cache";
		cache-size = <65536>;
		cache-line-size = <64>;
		cache-sets = <256>;
		cache-level = <2>;
		cache-unified;
		next-level-cache = <&l3_cache>;
	};

	l2_cache_l1: l2-cache-l1 {
		compatible = "cache";
		cache-size = <65536>;
		cache-line-size = <64>;
		cache-sets = <256>;
		cache-level = <2>;
		cache-unified;
		next-level-cache = <&l3_cache>;
	};

	l3_cache: l3-cache {
		compatible = "cache";
		cache-size = <262144>;
		cache-line-size = <64>;
		cache-sets = <256>;
		cache-level = <3>;
		cache-unified;
	};
};

&src {
	mlmix: power-domain@44461800 {
		compatible = "fsl,imx93-src-slice";
		reg = <0x44461800 0x400>, <0x44464800 0x400>;
		clocks = <&clk IMX93_CLK_ML_APB>,
			 <&clk IMX93_CLK_ML>;
		#power-domain-cells = <0>;
	};
};