// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
 * Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "rockchip,rk3528";

	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
		serial6 = &uart6;
		serial7 = &uart7;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
			};
		};

		cpu0: cpu@0 {
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			device_type = "cpu";
			enable-method = "psci";
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			device_type = "cpu";
			enable-method = "psci";
		};

		cpu2: cpu@2 {
			compatible = "arm,cortex-a53";
			reg = <0x2>;
			device_type = "cpu";
			enable-method = "psci";
		};

		cpu3: cpu@3 {
			compatible = "arm,cortex-a53";
			reg = <0x3>;
			device_type = "cpu";
			enable-method = "psci";
		};
	};

	psci {
		compatible = "arm,psci-1.0", "arm,psci-0.2";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	xin24m: clock-xin24m {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "xin24m";
		#clock-cells = <0>;
	};

	soc {
		compatible = "simple-bus";
		ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>;
		#address-cells = <2>;
		#size-cells = <2>;

		gic: interrupt-controller@fed01000 {
			compatible = "arm,gic-400";
			reg = <0x0 0xfed01000 0 0x1000>,
			      <0x0 0xfed02000 0 0x2000>,
			      <0x0 0xfed04000 0 0x2000>,
			      <0x0 0xfed06000 0 0x2000>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
						 IRQ_TYPE_LEVEL_LOW)>;
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <3>;
		};

		uart0: serial@ff9f0000 {
			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
			reg = <0x0 0xff9f0000 0x0 0x100>;
			clock-frequency = <24000000>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";
		};

		uart1: serial@ff9f8000 {
			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
			reg = <0x0 0xff9f8000 0x0 0x100>;
			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";
		};

		uart2: serial@ffa00000 {
			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
			reg = <0x0 0xffa00000 0x0 0x100>;
			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";
		};

		uart3: serial@ffa08000 {
			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
			reg = <0x0 0xffa08000 0x0 0x100>;
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";
		};

		uart4: serial@ffa10000 {
			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
			reg = <0x0 0xffa10000 0x0 0x100>;
			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";
		};

		uart5: serial@ffa18000 {
			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
			reg = <0x0 0xffa18000 0x0 0x100>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";
		};

		uart6: serial@ffa20000 {
			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
			reg = <0x0 0xffa20000 0x0 0x100>;
			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";
		};

		uart7: serial@ffa28000 {
			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
			reg = <0x0 0xffa28000 0x0 0x100>;
			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";
		};
	};
};