// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
 */

#include <dt-bindings/gpio/gpio.h>

/ {
	chosen {
		stdout-path = "serial2:1500000n8";
	};

	/* Unnamed gated oscillator: 100MHz,3.3V,3225 */
	pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator {
		compatible = "gated-fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
		clock-output-names = "pcie30_refclk";
		vdd-supply = <&vcc3v3_pi6c_05>;
	};

	vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 {
		compatible = "regulator-fixed";
		regulator-name = "vcc3v3_pcie2x1l0";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		startup-delay-us = <5000>;
		vin-supply = <&vcc_3v3_s3>;
	};

	vcc3v3_bkey: regulator-vcc3v3-bkey {
		compatible = "regulator-fixed";
		enable-active-high;
		gpios = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; /* PCIE_4G_PWEN */
		pinctrl-names = "default";
		pinctrl-0 = <&pcie_4g_pwen>;
		regulator-name = "vcc3v3_bkey";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		startup-delay-us = <5000>;
		vin-supply = <&vcc5v0_sys>;
	};

	vcc3v3_pcie30: vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 {
		compatible = "regulator-fixed";
		enable-active-high;
		gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; /* PCIE30x4_PWREN_H */
		pinctrl-names = "default";
		pinctrl-0 = <&pcie30x4_pwren_h>;
		regulator-name = "vcc3v3_pcie30";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		startup-delay-us = <5000>;
		vin-supply = <&vcc5v0_sys>;
	};

	vcc5v0_host: regulator-vcc5v0-host {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&vcc5v0_host_en>;
		regulator-name = "vcc5v0_host";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-boot-on;
		regulator-always-on;
		vin-supply = <&vcc5v0_sys>;
	};
};

&combphy0_ps {
	status = "okay";
};

&combphy1_ps {
	status = "okay";
};

&combphy2_psu {
	status = "okay";
};

&i2c6 {
	status = "okay";

	hym8563: rtc@51 {
		compatible = "haoyu,hym8563";
		reg = <0x51>;
		interrupt-parent = <&gpio0>;
		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
		#clock-cells = <0>;
		clock-output-names = "hym8563";
		pinctrl-names = "default";
		pinctrl-0 = <&hym8563_int>;
		wakeup-source;
	};
};

/* ETH */
&pcie2x1l0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pcie2_0_rst>;
	reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; /* PCIE20_1_PERST_L */
	vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
	status = "okay";
};

&pcie30phy {
	data-lanes = <1 1 2 2>;
	/* separate clock lines from the clock generator to phy and devices */
	rockchip,rx-common-refclk-mode = <0 0 0 0>;
	status = "okay";
};

/* M-Key */
&pcie3x2 {
	/*
	 * The board has a "pcie_refclk" oscillator that needs enabling,
	 * so add it to the list of clocks.
	 */
	clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
		 <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
		 <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>,
		 <&pcie30_port1_refclk>;
	clock-names = "aclk_mst", "aclk_slv",
		      "aclk_dbi", "pclk",
		      "aux", "pipe",
		      "ref";
	num-lanes = <2>;
	pinctrl-names = "default";
	pinctrl-0 = <&pcie30x2_perstn_m1_l>;
	reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; /* PCIE30X2_PERSTn_M1_L */
	vpcie3v3-supply = <&vcc3v3_pcie30>;
	status = "okay";
};

/* B-Key and E-Key */
&pcie3x4 {
	/*
	 * The board has a "pcie_refclk" oscillator that needs enabling,
	 * so add it to the list of clocks.
	 */
	clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
		 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
		 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>,
		 <&pcie30_port0_refclk>;
	clock-names = "aclk_mst", "aclk_slv",
		      "aclk_dbi", "pclk",
		      "aux", "pipe",
		      "ref";
	pinctrl-names = "default";
	pinctrl-0 = <&pcie30x4_perstn_m1_l>;
	reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTn_M1_L */
	vpcie3v3-supply = <&vcc3v3_bkey>;
	status = "okay";
};

&pinctrl {
	pcie2 {
		pcie2_0_rst: pcie2-0-rst {
			rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	pcie3 {
		pcie30x2_perstn_m1_l: pcie30x2-perstn-m1-l {
			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		pcie_4g_pwen: pcie-4g-pwen {
			rockchip,pins = <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
		};

		pcie30x4_perstn_m1_l: pcie30x4-perstn-m1-l {
			rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		pcie30x4_pwren_h: pcie30x4-pwren-h {
			rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>;
		};
	};

	hym8563 {
		hym8563_int: hym8563-int {
			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	usb {
		vcc5v0_host_en: vcc5v0-host-en {
			rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};
};

/* FAN */
&pwm2 {
	pinctrl-0 = <&pwm2m1_pins>;
	pinctrl-names = "default";
	status = "okay";
};

&sata0 {
	status = "okay";
};

&sdmmc {
	bus-width = <4>;
	cap-mmc-highspeed;
	cap-sd-highspeed;
	disable-wp;
	no-sdio;
	no-mmc;
	sd-uhs-sdr104;
	vmmc-supply = <&vcc_3v3_s3>;
	vqmmc-supply = <&vccio_sd_s0>;
	status = "okay";
};

&uart2 {
	pinctrl-0 = <&uart2m0_xfer>;
	status = "okay";
};

/* RS232 */
&uart6 {
	pinctrl-0 = <&uart6m0_xfer>;
	pinctrl-names = "default";
	status = "okay";
};

/* RS485 */
&uart7 {
	pinctrl-0 = <&uart7m2_xfer>;
	pinctrl-names = "default";
	status = "okay";
};

&u2phy2 {
	status = "okay";
};

&u2phy2_host {
	/* connected to USB hub, which is powered by vcc5v0_sys */
	phy-supply = <&vcc5v0_sys>;
	status = "okay";
};

&u2phy3 {
	status = "okay";
};

&u2phy3_host {
	phy-supply = <&vcc5v0_host>;
	status = "okay";
};

&usb_host0_ehci {
	status = "okay";
};

&usb_host0_ohci {
	status = "okay";
};

&usb_host1_ehci {
	status = "okay";
};

&usb_host1_ohci {
	status = "okay";
};

&usb_host2_xhci {
	status = "okay";
};