// SPDX-License-Identifier: GPL-2.0-only OR MIT
/**
 * Device Tree Source for enabling IPC using TI SDK firmware on AM65 SoCs
 *
 * Copyright (C) 2016-2025 Texas Instruments Incorporated - https://www.ti.com/
 */

&reserved_memory {
	mcu_r5fss0_core1_dma_memory_region: memory@a1000000 {
		compatible = "shared-dma-pool";
		reg = <0 0xa1000000 0 0x100000>;
		no-map;
	};

	mcu_r5fss0_core1_memory_region: memory@a1100000 {
		compatible = "shared-dma-pool";
		reg = <0 0xa1100000 0 0xf00000>;
		no-map;
	};

	rtos_ipc_memory_region: memory@a2000000 {
		reg = <0x00 0xa2000000 0x00 0x00100000>;
		alignment = <0x1000>;
		no-map;
	};
};

&mailbox0_cluster0 {
	status = "okay";
	interrupts = <436>;

	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
		ti,mbox-tx = <1 0 0>;
		ti,mbox-rx = <0 0 0>;
	};
};

&mailbox0_cluster1 {
	status = "okay";
	interrupts = <432>;

	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
		ti,mbox-tx = <1 0 0>;
		ti,mbox-rx = <0 0 0>;
	};
};

&mcu_r5fss0 {
	status = "okay";
};

&mcu_r5fss0_core0 {
	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
			<&mcu_r5fss0_core0_memory_region>;
	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
	status = "okay";
};

&mcu_r5fss0_core1 {
	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
			<&mcu_r5fss0_core1_memory_region>;
	mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
	status = "okay";
};