// SPDX-License-Identifier: GPL-2.0-only OR MIT
/**
 * DT Overlay for enabling PCIE1 instance in Endpoint Configuration with the
 * J7 common processor board.
 *
 * J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM
 *
 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
 */

/dts-v1/;
/plugin/;

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>

#include "k3-pinctrl.h"

/*
 * Since Root Complex and Endpoint modes are mutually exclusive
 * disable Root Complex mode.
 */
&pcie1_rc {
	status = "disabled";
};

&cbass_main {
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&gic500>;

	pcie1_ep: pcie-ep@2910000 {
		compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
		reg = <0x00 0x02910000 0x00 0x1000>,
		      <0x00 0x02917000 0x00 0x400>,
		      <0x00 0x0d800000 0x00 0x00800000>,
		      <0x00 0x18000000 0x00 0x08000000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 240 6>;
		clock-names = "fck";
		max-functions = /bits/ 8 <6>;
		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
		dma-coherent;
		phys = <&serdes0_pcie_link>;
		phy-names = "pcie-phy";
		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
	};
};