// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
 * Device Tree Source for J784S4 SoC Family Main Domain peripherals
 *
 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
 */

&cbass_main {
	c71_3: dsp@67800000 {
		compatible = "ti,j721s2-c71-dsp";
		reg = <0x00 0x67800000 0x00 0x00080000>,
		      <0x00 0x67e00000 0x00 0x0000c000>;
		reg-names = "l2sram", "l1dram";
		resets = <&k3_reset 40 1>;
		firmware-name = "j784s4-c71_3-fw";
		ti,sci = <&sms>;
		ti,sci-dev-id = <40>;
		ti,sci-proc-ids = <0x33 0xff>;
		status = "disabled";
	};

	pcie2_rc: pcie@2920000 {
		compatible = "ti,j784s4-pcie-host";
		reg = <0x00 0x02920000 0x00 0x1000>,
		      <0x00 0x02927000 0x00 0x400>,
		      <0x00 0x0e000000 0x00 0x00800000>,
		      <0x44 0x00000000 0x00 0x00001000>;
		ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
			 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
		device_type = "pci";
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 334 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 334 0>;
		clock-names = "fck";
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x0 0xff>;
		vendor-id = <0x104c>;
		device-id = <0xb012>;
		msi-map = <0x0 &gic_its 0x20000 0x10000>;
		dma-coherent;
		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
		ti,syscon-pcie-ctrl = <&pcie2_ctrl 0x0>;
		status = "disabled";
	};

	pcie3_rc: pcie@2930000 {
		compatible = "ti,j784s4-pcie-host";
		reg = <0x00 0x02930000 0x00 0x1000>,
		      <0x00 0x02937000 0x00 0x400>,
		      <0x00 0x0e800000 0x00 0x00800000>,
		      <0x44 0x10000000 0x00 0x00001000>;
		ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
			 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
		device_type = "pci";
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 335 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 335 0>;
		clock-names = "fck";
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x0 0xff>;
		vendor-id = <0x104c>;
		device-id = <0xb012>;
		msi-map = <0x0 &gic_its 0x30000 0x10000>;
		dma-coherent;
		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
		ti,syscon-pcie-ctrl = <&pcie3_ctrl 0x0>;
		status = "disabled";
	};

	serdes_wiz2: wiz@5020000 {
		compatible = "ti,j784s4-wiz-10g";
		ranges = <0x05020000 0x00 0x05020000 0x10000>;
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 406 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 406 2>, <&k3_clks 406 6>, <&serdes_refclk>, <&k3_clks 406 5>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
		assigned-clocks = <&k3_clks 406 6>;
		assigned-clock-parents = <&k3_clks 406 10>;
		num-lanes = <4>;
		#reset-cells = <1>;
		#clock-cells = <1>;
		status = "disabled";

		serdes2: serdes@5020000 {
			compatible = "ti,j721e-serdes-10g";
			reg = <0x05020000 0x010000>;
			reg-names = "torrent_phy";
			resets = <&serdes_wiz2 0>;
			reset-names = "torrent_reset";
			clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
				 <&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>;
			clock-names = "refclk", "phy_en_refclk";
			assigned-clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
					  <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>,
					  <&serdes_wiz2 TI_WIZ_REFCLK_DIG>;
			assigned-clock-parents = <&k3_clks 406 6>,
						 <&k3_clks 406 6>,
						 <&k3_clks 406 6>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;
			status = "disabled";
		};
	};
};

&scm_conf {
	pcie2_ctrl: pcie2-ctrl@4078 {
		compatible = "ti,j784s4-pcie-ctrl", "syscon";
		reg = <0x4078 0x4>;
	};

	pcie3_ctrl: pcie3-ctrl@407c {
		compatible = "ti,j784s4-pcie-ctrl", "syscon";
		reg = <0x407c 0x4>;
	};
};