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0*0I0Z0g0000001141U1n111111core.c__initcall__kmod_core__669_7397_fixup_ht_bug4fixup_ht_bugintel_pmu_event_mapintel_perfmon_event_mapintel_pmu_disable_all__icl_update_topdown_eventintel_pebs_aliases_core2intel_pebs_aliases_snbadl_get_hybrid_cpu_typehsw_limit_periodnhm_limit_periodintel_ht_bugintel_start_schedulingintel_commit_schedulingintel_stop_schedulingexra_is_visiblehybrid_events_is_visiblehybrid_td_is_visibleintel_pmu_v6_addr_offsetdyn_constraintintel_guest_get_msrs__intel_shared_reg_get_constraintsintel_pmu_filterintel_clovertown_quirkintel_nehalem_quirkintel_pmu_updateintel_pmu_set_periodshow_sysctl_tfabranch_counter_width_showbranches_showintel_hybrid_get_attr_cpusset_sysctl_tfaupdate_tfa_schedfreeze_on_smi_storefreeze_on_smi_mutexflip_smm_bitfreeze_on_smi_showeq_showumask2_showfrontend_showldlat_showoffcore_rsp_showin_tx_cp_showin_tx_showcmask_showinv_showany_showpc_showedge_showumask_showevent_showbranch_counter_nr_showhybrid_tsx_is_visiblehybrid_format_is_visibleintel_arch_events_quirkintel_arch_events_mapupdate_saved_topdown_regsintel_pmu_aux_output_matchintel_pmu_swap_task_ctxintel_pmu_sched_taskintel_pmu_read_eventintel_pmu_del_eventintel_pmu_add_eventintel_pmu_cpu_dyingcore_pmu_enable_eventintel_pmu_check_counters_maskintel_pmu_assign_eventintel_check_pebs_isolationisolation_ucodesintel_pebs_aliases_ivbintel_pebs_aliases_sklbdw_limit_periodlbr_is_visibledefault_is_visibledev_attr_allow_tsx_force_abortmem_is_visibleevent_attr_mem_ld_auxevtsel_ext_is_visibleintel_pmu_check_event_constraints.part.0glc_limit_periodintel_snb_check_microcodepebs_ucodesintel_sandybridge_quirkintel_pmu_hw_config.part.0snoop_rsp_showintel_pmu_check_periodintel_pmu_bts_configcore_pmu_hw_configintel_pmu_hw_configintel_pebs_isolation_quirkintel_put_event_constraintscore_guest_get_msrshsw_hw_configadl_hw_configarl_h_hw_configx86_pmu_disable_event__intel_pmu_enable_all.constprop.0__intel_pmu_snapshot_branch_stackintel_pmu_snapshot_arch_branch_stackintel_pmu_enable_allintel_tfa_pmu_enable_allintel_tfa_commit_schedulingintel_pmu_nhm_enable_allnhm_magic.1icl_set_topdown_event_periodhandle_pmi_commoncore_pmu_enable_allintel_pmu_handle_irqwarned.0intel_pmu_disable_eventcheck_msrintel_pmu_cpu_startingintel_pmu_enable_eventintel_get_event_constraintshsw_get_event_constraintscounter2_constraintcmt_get_event_constraintsfixed0_constraintCSWTCH.464fixed0_counter0_1_constrainttnt_get_event_constraintsfixed0_counter0_constraintglp_get_event_constraintsicl_get_event_constraintstfa_get_event_constraintsglc_get_event_constraintsmtl_get_event_constraintscounters_1_7_constraintarl_h_get_event_constraintsadl_get_event_constraintsintel_pmu_cpu_prepareintel_pmu_cpu_deadintel_arch3_formats_attr__quirk.11westmere_hw_cache_event_idsnehalem_hw_cache_extra_regsintel_westmere_event_constraintsintel_westmere_extra_regsempty_attrsnhm_mem_events_attrsnhm_format_attrintel_core_event_constraintsintel_arch_formats_attrsnb_hw_cache_event_ids__quirk.8__quirk.7snb_hw_cache_extra_regsintel_snbep_extra_regsintel_snb_extra_regsintel_snb_event_constraintssnb_mem_events_attrssnb_events_attrsnehalem_hw_cache_event_idsintel_nehalem_event_constraintsintel_nehalem_extra_regs__quirk.9atom_hw_cache_event_idsintel_gen_event_constraintspmu_name_strgroup_format_extra_sklcore2_hw_cache_event_idsintel_core2_event_constraintshsw_hw_cache_event_ids__quirk.5__quirk.4hsw_hw_cache_extra_regshsw_tsx_events_attrshsw_mem_events_attrshsw_events_attrsintel_hsw_event_constraintshsw_format_attrslm_hw_cache_event_idsslm_hw_cache_extra_regsslm_events_attrsslm_format_attrintel_slm_event_constraintsintel_slm_extra_regs__quirk.3intel_bdw_event_constraintsglm_hw_cache_event_idsglm_hw_cache_extra_regsintel_glm_extra_regsglm_events_attrsskl_hw_cache_event_idsskl_hw_cache_extra_regsicl_events_attrsicl_td_events_attrsskl_format_attricl_tsx_events_attrsintel_icl_event_constraintsintel_icl_extra_regs__quirk.2event_attr_td_recovery_bubblesintel_skl_event_constraintsintel_skl_extra_regsglp_hw_cache_event_idstnt_events_attrstnt_hw_cache_extra_regsintel_tnt_extra_regsknl_hw_cache_extra_regsintel_knl_extra_regsintel_glc_extra_regsglc_hw_cache_event_idsglc_hw_cache_extra_regsintel_glc_event_constraintsglc_tsx_events_attrsglc_events_attrsglc_td_events_attrsintel_hybrid_pmu_type_mapmtl_hybrid_extra_attrmtl_hybrid_extra_attr_rtmintel_lnc_event_constraintsintel_lnc_extra_regsintel_grt_event_constraintsintel_grt_extra_regsintel_skt_event_constraintsintel_cmt_extra_regsadl_hybrid_tsx_attrsarl_h_hybrid_mem_attrsarl_h_hybrid_events_attrsgrt_mem_attrshybrid_group_events_tdhybrid_attr_updatehybrid_group_events_memhybrid_group_events_tsxhybrid_group_format_extraintel_v1_event_constraintsadl_hybrid_extra_attradl_hybrid_extra_attr_rtmadl_hybrid_mem_attrsadl_hybrid_events_attrsmtl_hybrid_mem_attrslnl_hybrid_events_attrscmt_events_attrscmt_format_attrintel_rwc_extra_regs__quirk.10__quirk.6intel_ivb_event_constraintsglp_hw_cache_extra_regsevent_attr_td_total_slots_scale_glmintel_v5_gen_event_constraintscounter1_constra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nterruptx86_pmu_stopintel_pmu_lbr_save_brstackintel_bts_disable_localintel_pmu_drain_bts_bufferintel_bts_interruptintel_bts_enable_local__x86_indirect_thunk_rdx__SCT__apic_call_writeperf_event_print_debugintel_pmu_pebs_disablelbr_from_signext_quirk_wrinit_debug_store_on_cpuintel_pmu_lbr_resetcpu_sibling_mapget_this_hybrid_cpu_typeget_this_hybrid_cpu_native_idcheck_hw_existsx86_pmu_show_pmu_capintel_pmu_pebs_enableintel_pmu_save_and_restartx86_get_event_constraintsunconstrainedvlbr_constraintintel_pebs_constraintsbts_constraintintel_cpuc_preparenuma_nodekmalloc_caches__kmalloc_cache_node_noprofintel_cpuc_finishintel_pmu_initx86_schedule_eventsintel_pmu_lbr_reset_64intel_pmu_lbr_read_64intel_pmu_lbr_saveintel_pmu_lbr_restoreintel_pmu_lbr_reset_32intel_pmu_lbr_read_32intel_ds_initintel_pmu_lbr_init_nhmintel_westmere_pebs_event_constraintsintel_pmu_pebs_data_source_nhmp6_pmu_initp4_pmu_initx86_pmu_handle_irqx86_pmu_disable_allintel_pmu_lbr_init_snbintel_snb_pebs_event_constraintsintel_nehalem_pebs_event_constraintsintel_pmu_lbr_init_atomintel_atom_pebs_event_constraintsintel_pmu_lbr_init__SCT__perf_snapshot_branch_stack__SCK__perf_snapshot_branch_stack__static_call_updateintel_pmu_lbr_init_coreintel_core2_pebs_event_constraintsintel_pmu_lbr_init_hswintel_hsw_pebs_event_constraintsintel_pmu_lbr_init_slmintel_slm_pebs_event_constraintsintel_bdw_pebs_event_constraintsintel_pmu_lbr_init_sklintel_glm_pebs_event_constraintsintel_icl_pebs_event_constraintsintel_pmu_pebs_data_source_skl__SCK__intel_pmu_update_topdown_event__SCK__intel_pmu_set_topdown_event_periodintel_skl_pebs_event_constraintsintel_pmu_lbr_init_knlintel_glc_pebs_event_constraints__kmalloc_large_noprofstatic_key_enablearl_h_latency_dataintel_lnc_pebs_event_constraintsintel_grt_pebs_event_constraintsintel_pmu_pebs_data_source_arl_hintel_pmu_pebs_data_source_grtgrt_latency_dataknc_pmu_initintel_pmu_arch_lbr_init__kmalloc_cache_noprofintel_pmu_pebs_data_source_adllnl_latency_dataintel_pmu_pebs_data_source_lnlintel_pmu_pebs_data_source_cmtcmt_latency_dataintel_pmu_pebs_data_source_mtlintel_ivb_pebs_event_constraintsevents_hybrid_sysfs_showdevice_show_stringevents_sysfs_show__SCK__x86_pmu_set_period__SCK__x86_pmu_updateevents_ht_sysfs_show__SCK__apic_call_write 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