ELF>@@54 @tW0 1fAW@AVAUD ATEuPAUASDIc HAEAJBAAƁtt|uEt D9AutD1H[]A\A]A^A_E9te5EADHHH[]A\A]A^A_D9{9te5AADHHtDDHL$L$;H@`S0u9p9t G[1p1HމH[feueHk5}HffeHHet%H HxHHHHHH)H)΁HHe?H)HHet2`<HHH@k5}HǀHAUATUSHHeH%(HD$@1=eD%WHHHt0ƃH$HD$HD$HD$HD$ HD$(HD$0HD$8I߃IAEuLl$ ߃IAEuH|$ 1H=u HcӾH|$ H=~܃oHT$ HH PE u *P=9`HD$@eH+%(*HH[]A\A]HH=C!hP=ttHD$@eH+%(HH`[]A\A]HD$@eH+%(HH[]A\A]DH1HHD$@eH+%(uN뎀=~1HP`U0S<   PP `` wb P`D[]00 t P`p{@1[]@@ < P`pkp: p@uATUS]HH@ =&0pD5 55555P5`A5 5515p1t[]A\2H H HHڹ% H 0HH!1HH y5@ 50A51H޿]DuHwH1G<t1Ht 1 ƃ1fDG<t1S ƃ޿1[fD1H H HHH 01H1ҿ1ff.G<t1U S ƉŁt؉01[]11[]111[]u1U0S  P`pwT[H=tt1[]@W0tff.USeHeH=DeHHHeHHTeH[]eHseHHtHxe uweHseHHtHxe mce5HHAATU@SVIeى¸eA$udHi[]A\eIHseHHt Hxe gdHeA$HseHHt Hxe ]SeA4$H;@@fUS0:t@1t!~HH4uӃ~ HT[]eH^eHHtHxe 0&eHseHHtHxe mce5H$1DUS]޿t[]ff.SH H [fD0I111HfSHu e=tH[eeLI#LH\e[ff.H=uXH=t-@H=uff.@Hut#=uS[H=ut[itfSHu e=tH8[eeLI#LH\e[ff.SHu e=tH[eeLI#LH\e[ff.S0ƁuCPP%ƁW``[%ƁTPH׺HHfVHFr` 1  QP@t P0 ʉP=t#w(f fw uH dGPLGPLGPLGPL1ff.1ff. 1@Ht Ht11f.HUS/Hau'lu!Gl9u1[]HHt!bu{stHHSp)tԸfD1ff.S Åt %H1t 1H H Ћr5t;du0; HHsH H[HHH[ Hff.tp H4ׂCHHHHHHHHH1ff.Hu1H1fDHtJSHHHt%HHu.1[11HH[DHHt.HHHHH11ff. 1@US21HH H HՅu3t+HH [][]H H HՉHff.5tn tdHH tTuIt;H Ht+Huȅuf.AWAVAUATUSHHeH-t'H[]A\A]A^A_> ƃD5L-EE1E1=d~1H H L)L9D=EuHI9yI1HH=wH[]A\A]A^A_H[]A\A]A^A_1H H IWHMD%L-L+-EAH H+ D%ID+%EA$=gDE~ HI ףp= ףLHHIH H?HH)ȉnDEH=JLtH=tu HDžL=d =d~LHH+rHbHvAL$<AD$<?HH==H[]A\A]A^A_5HIi ^EHH $H4ׂCHHHHIiBv1HILHIHMOH $1D LiBvLIIE)HHHLHDD%L5L=D+%E~DHLL)IHL=5H55HHttLLIH?HS㥛 J 2HH)HHHH?HH)HiH)H k)IHHHH)H#HHiMbH&i)HHHbH{sHbH^HNff.<t < u=w@0<w=t=~ Hf.=uWHtd5ttb uHH1H1HfucHtWH=t P=E`f.vt`udH Ht;HHtHHHHuHHHtH1HHHn=uHfH=H=H5HHcH H#H_~HH_H HHп0= RHStHtHtG[HHtH@9sſHuHt [HHH[notscdeadlinenone6Leaving ESR disabled. lapic-deadline6Enabled ExtINT on CPU#%d 6Masked ExtINT on CPU#%d debugverbose7APIC error on CPU%d: %02xc : %sc 6Disabling APIC timer 6... lapic delta = %ld 6... PM-Timer delta = %u 6... PM-Timer result ok 6..... delta %ld 6..... mult: %u 6... verify APIC timer 6... jiffies delta = %lu 6... jiffies result ok 7Synchronizing Arb IDs. 6APIC disabled by BIOS 6APIC: SMP mode deactivated arch/x86/kernel/apic/apic.c6No local APIC present Send CS errorReceive CS errorSend accept errorReceive accept errorRedirectable IPISend illegal vectorReceived illegal vectorIllegal register addressIBM System Summit2lapicLocal APIC4Unknown external NMI delivery mode `%s' ignored 6LVT offset %d assigned for vector 0x%02x 3[Firmware Bug]: cpu %d, try to use APIC%lX (LVT offset %d) for vector 0x%x, but the register is already in use for vector 0x%x on another cpu 3[Firmware Bug]: cpu %d, try to use APIC%lX (LVT offset %d) for vector 0x%x, but the register is already in use for vector 0x%x on this cpu 6ESR value before enabling vector: 0x%08x after: 0x%08x 4APIC: Stale IRR: %256pb ISR: %256pb 4APIC Verbosity level %s not recognised use apic=verbose or apic=debug 6APIC: %s detected, Multi Chassis 4Spurious LAPIC timer interrupt on cpu %d 6Spurious APIC interrupt (vector 0xFF) on CPU#%d, should never happen. 6Spurious interrupt (vector 0x%02x) on CPU#%d. Acked 6Spurious interrupt (vector 0x%02x) on CPU#%d. Not pending! 3Kernel does not support x2APIC, please recompile with CONFIG_X86_X2APIC. 3Disabling APIC, expect reduced performance and functionality. 6lapic timer already calibrated %d 6Using local APIC timer interrupts. Calibrating APIC timer ... 4APIC calibration not consistent with PM-Timer: %ldms instead of 100ms 6APIC delta adjusted to PM-Timer: %lu (%ld) 6TSC delta adjusted to PM-Timer: %lu (%ld) 6..... calibration result: %u 6..... CPU clock speed is %ld.%04ld MHz. 6..... host bus clock speed is %u.%04u MHz. 4APIC frequency too slow, disabling apic timer 4APIC timer disabled due to verification failure 6APIC disabled via kernel command line 6APIC: ACPI MADT or MP tables are not detected 6APIC: Keep in PIC mode(8259) 6APIC: Switch to virtual wire mode setup 6APIC: Switch to virtual wire mode setup with no configuration 6APIC: Switch to symmetric I/O mode setup 6APIC: Switch to symmetric I/O mode setup in no SMP routine 6Not enabling interrupt remapping due to skipped IO-APIC setup 6Mapped APIC to %16lx (%16lx) 3[Firmware Bug]: TSC_DEADLINE disabled due to Errata; please update microcode to version: 0x%x (or later) 6TSC deadline timer available 6APIC: disable apic facility  {HHUSHŐu e=tHH[]eeLI#LH\ef.ATUHSHAĐu e=t&@HDH[]A\eeL@I#LHH\efDUSHŐu e=tHH[]eeLI#LH\ef.USHŐu e=tHH[]eeLI#LH\e#   IBMSummit2apic_extnmiapicnolapic_timernoapictimerlapic_timer_c2_oknolapicdisableapic?:?O VVV V U6UU<"E F=%GN^RRapicpmtimerlapicGCC: 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