ELF>@@@ffffwQ1҃wm4ƒwHt\<t= E1D t1҃ uH례utsH<v;UU@+@A:*UE1tU<u@@++1A:ڭUE1@E1DUU@`A:ڭUE1UU0+1A:pUwD1҃w`4ƒtuw?tS<t4E1Uk&N t1҃ uH뮀utgH<v2E14tI<uE1@ DE1+E1h@fHHHHAUIATUSHw+1w9HE1Ht([D]A\A] t1 uHHHLHAEuA E1[]AEDA\A]@SHHw 1w[ t1 uH[H[UHSw<1҃wJƂHHHH߾H[] t1҃ uHHfDATIUHSHH?HtHNjOt uHLHŅt[]A\AƄ$\H;HtHGu$GG HG u HA$xt ;P8uH$HI$tHPI$|HPI$HPI$@ AƄ$pA$HHH덐UHSw<1҃wJƂHHHH߾H[] t1҃ uHHfDATUHSHHt HHËH@ HD$H;@ HHH߾@ A[]A\DATUHSHHt HHËH@HD$H;@HHH߾@A[]A\DAVAUATUHSHHt HHËE1A$HM$H;HHH߉AE$LAƄ$fC u5[L]A\A]A^ tE1 yLmIeLL[]A\A]A^AUATUHSH Ht HHDeDmHADADeH;DDHHDHmH߉H;1HHH[]A\A]fAUATUHSH Ht HHDeDmHADA DeH;DDHHDHmH߉H;1HHH[]A\A]fAUATA@USHH;@HH@H߉@D8u []A\A]CuA/A ! t2E1 LA4A IA AUATIUSH Ht HHEl$ڃAEl$t@t'HH []A\A]A0El$A$HH}DHHHA$HH}1HHH[]A\A]AEl${f.AUATIUSH Ht HHEl$ڃAEl$t@t'HH []A\A]AEl$A$HH}DHHHA$HH}1HHH[]A\A]AEl${f.AWAVAUIATUSHHL'Mt LIċ-1AHAI]D$DLDI<$DHHDLAADA%8D AD$ L$AxtAxƃEƉ€vy ‹p%` ЉH[]A\A]A^A_ 1 HA|$AD$tAdt AxtAxƃEƉ0At 0‹pAD$ u+%@ ЉH[]A\A]A^A_H% ЉH[]A\A]A^A_T$1L牅pE AI<$޺HHHH%HD LH[]A\A]A^A_A|$lAD$ff.fUHSHHHHH[]ff.UHSHHHHH[]ff.AWAVAUATUSH LH|$Ht$HT$Mt LIHD${E1 ALII?޺HHLAEHIH0I]Ht HHHt$1HAEH߁DAT$H;T$DHHDHEHDH;1DHHDHHHHLHIHtGfAG  Ht$H|$ E1 |HD$LkfAG t)1AG tHD$H|$HH\$HHHHHH|$HHHHH []A\A]A^A_Ll$I?HtHH_PHuHHHHH H []A\A]A^A_fDATIUHSHHHLHHH[]A\f.ATIUHSHHHHHL[]A\fUHSHHH[]fAWAVIAUATUHSHHHt HHIAhDHL$\H$1҉@΀AhDHDH;DHHDHAA@YEAƆmAtAƆ1AƒAEA xCtAtAƆdEI>MMAAAA\E LH|$H|$LE.ALH<$A|HLH[]A\A]A^A_ J HHH$AƆm{HD$HDpA ADH;DHHDH߉D$L$tAƆ1ƒEA`LH|$A`H|$LE@HH;@HHH߾@AxAADAtHHH$QAƆm{EA|HMHHH $fDAVHAUATUHSw'E1w5H t([]A\A]A^ tE1 uLII$Ht HHË`1HLuI$|1HRH3DHtHv1HE$AE$xuAE$@HH;D@HH@H@HH;1Ҿ@HHH߾@ C A$@H߁@A$H;@HHH߾@@HH;1Ҿ@HHH߾@x []A\A]A^Ap1H߅@GAWAVAUATIUHSHHHt HHËCE1TI$EHH$DD$ H;DHHDHAEH3HtHvH1EEHADEH;DDHHDHEHDH;1DHHDH{tPA<fC H[]A\A]A^A_ tE1 LIH$puD$ tH111H1EEHADAEH;DDHHDHEHDH;1DHHDHEEHADEH;DDHHDHEHDH;1DHHDHH1Hߺ11H5HLH[]A\A]A^A_H;HtHH_PHuHHHHH H[]A\A]A^A_ff.@HHQATHUHSw#E1w1Ht$[]A\ tE1 uLII$Ht HHË`1HI$xHKH3HtHvH1A$@H߁A$H;@HHH߾@@HH;1Ҿ@HHH߾@x []A\UHSHHHHHߺ[]G HHHEAWAVAAUAATIUSHHH;DHHDH߉C t Eu@{uEu3C uA,$H[]A\A]A^A_߃{uE}AD|$E1`Lr8AAuH3EEAHtHvH1E11E<$EH߈L$A ADH;DHHDH߉D$L$1Ł`hfAVAUIATUSH/HHt HHŋwWE1weHE1Ht)AHLHA[D]A\A]A^ tE1 uLIff.AWAVAUAATAUHSu1[]A\A]A^A_DHIHrHHtIHt7LH}EL$AHIHtLHzHHHǃHǃHǃXHǃ`HǃhHǃpHǃ@HǃHǃHǃE HǃHǃHǃ Hǃ(Hǃ0Hǃ8HǃHHǃPE tYEt_}HHHHDHHDSHuED$AHtHvH1d}uEtHHHHH(H E NE EuHǃfE HHH8DHH0DǃE R1DfDHǃXHHx*EKHǃHdtLHHdE HǃHǃHǃ Hǃ(Hǃ0HHfE uMtEuHHHHH8DHH0DǃE At_HǃHǃ Hǃ(Hǃ0AH@HǃH1ƃfǃHǃXHHx*yHǃHǃEEHtEuHǃfE vHHqonoffUsing signal levels %08x encoder->hpd_pinMissing case (%s == %ld) signal_levels%s %s: [drm] %s disabling eDP PLL No pipe for DP port %c found DP %c%s %s: [drm] eDP PLL state assertion failure (expected %s, current %s) drivers/gpu/drm/i915/display/g4x_dp.c[drm] *ERROR* eDP PLL state assertion failure (expected %s, current %s) %s %s: [drm] [ENCODER:%d:%s] state assertion failure (expected %s, current %s) [drm] *ERROR* [ENCODER:%d:%s] state assertion failure (expected %s, current %s) intel_dp_training_pattern_symbol(dp_train_pat)drm_WARN_ON(dp_reg & ((u32)(((int)sizeof(struct {_Static_assert(!(__builtin_choose_expr((sizeof(int) == sizeof(*(8 ? ((void *)((long)((31) >= (sizeof(u32) * 8)) * 0l)) : (int *)8))), (31) >= (sizeof(u32) * 8), false)), "const_true((31) >= BITS_PER_TYPE(u32))" " is true");})) + ((((1ULL))) << (31)))))enabling eDP PLL for clock %d drm_WARN_ON((intel_de_read(display, intel_dp->output_reg) & ((u32)(((int)sizeof(struct {_Static_assert(!(__builtin_choose_expr((sizeof(int) == sizeof(*(8 ? ((void *)((long)((31) >= (sizeof(u32) * 8)) * 0l)) : (int *)8))), (31) >= (sizeof(u32) * 8), false)), "const_true((31) >= BITS_PER_TYPE(u32))" " is true");})) + ((((1ULL))) << (31))))) == 0)No VBT child device for DP-%c   2 f | S   Mf:RU:U:ڭU@@@+HH@+@@@+:HU:`U:ژU@@@+UU$+UU@+ xQx  x  x i915.import_ns=PWMGCC: (Debian 12.2.0-14+deb12u1) 12.2.0GNU !08POpf|  @ `     0O6@jE[ `Hd Hm Hv Hj`{{@    5@ nK `t @0P p$"$8T6f .x`j!9`#' 'M()`* ( $;H@Sl7KQbz.FYbt @Zp+E^y  5 T s        4 M (Z (^n    +     , @ ^ r       ) 9 Q g4x_dp.cintel_dp_voltage_max_2intel_dp_voltage_max_3intel_dp_preemph_max_2intel_dp_preemph_max_3vlv_set_signal_levelsCSWTCH.79CSWTCH.78CSWTCH.77CSWTCH.76chv_set_signal_levelsCSWTCH.81CSWTCH.82vlv_enable_dpchv_dp_post_pll_disableg4x_dp_suspend_completeintel_dp_hotplugintel_dp_encoder_destroyg4x_disable_dpg4x_dp_compute_configvlv_dpllg4x_dpllpch_dpllchv_dpllvlv_disable_dpibx_digital_port_connectedilk_digital_port_connectedintel_dp_encoder_resetcpt_set_idle_link_traing4x_set_idle_link_trainassert_edp_pllassert_dp_port.constprop.0g4x_set_signal_levelsg4x_dp_audio_disableg4x_dp_audio_enableg4x_digital_port_connectedCSWTCH.68snb_cpu_edp_set_signal_levelsivb_cpu_edp_set_signal_levelsg4x_set_link_traincpt_set_link_trainintel_dp_preparevlv_dp_pre_pll_enablechv_dp_pre_pll_enableintel_enable_dp.constprop.0chv_pre_enable_dpvlv_pre_enable_dpg4x_enable_dpintel_dp_get_configg4x_pre_enable_dpintel_dp_link_downvlv_post_disable_dpg4x_post_disable_dpchv_post_disable_dpintel_dp_get_hw_stateintel_dp_enc_funcs__UNIQUE_ID_modinfo556.LC3__x86_return_thunkvlv_set_phy_signal_levelchv_set_phy_signal_levelintel_edp_backlight_onchv_phy_post_pll_disableintel_encoder_link_check_flush_workintel_dp_test_phyintel_encoder_hotplugintel_dp_check_link_stateintel_dp_encoder_flush_workdrm_encoder_cleanupkfreeintel_pps_vdd_onintel_edp_backlight_offintel_dp_set_powerintel_pps_off__drm_to_displayintel_dp_compute_configintel_dmc_wl_getto_intel_uncore__x86_indirect_thunk_raxintel_dmc_wl_putintel_dp_invalidate_source_ouiintel_pps_encoder_resetvlv_pps_pipe_reset_dev_errdev_driver_string__warn_printk__drm_dev_dbgintel_audio_codec_disableintel_audio_codec_enableintel_dp_set_link_paramsvlv_phy_pre_pll_enablechv_phy_pre_pll_enableintel_pps_lockintel_dp_program_link_training_patternintel_pps_vdd_on_unlockedintel_pps_on_unlockedintel_pps_vdd_off_unlockedintel_pps_unlockvlv_pps_port_enable_unlockedvlv_wait_port_readyintel_dp_configure_protocol_converterintel_dp_check_frl_trainingintel_dp_pcon_dsc_configureintel_dp_start_link_trainintel_dp_stop_link_trainchv_phy_pre_encoder_enablechv_phy_release_cl2_overridevlv_phy_pre_encoder_enableintel_pch_transcoder_get_m1_n1intel_pch_transcoder_get_m2_n2intel_dotclock_calculateintel_dp_is_edpintel_audio_codec_get_configintel_cpu_transcoder_get_m1_n1intel_cpu_transcoder_get_m2_n2intel_edp_fixup_vbt_bppassert_transcoder__const_udelayintel_wait_for_vblank_if_activemsleepintel_set_cpu_fifo_underrun_reportingintel_set_pch_fifo_underrun_reportingvlv_pps_port_disablechv_data_lane_soft_resetvlv_get_dpllg4x_dp_port_enabledintel_display_power_get_if_enabledintel_display_power_put_uncheckedg4x_dp_initassert_port_validintel_bios_encoder_data_lookupintel_dig_port_allocintel_connector_allocdrm_encoder_initintel_dp_link_checkintel_encoder_link_check_initintel_dp_sync_stateintel_dp_initial_fastset_checkintel_backlight_updateintel_dp_encoder_suspendintel_dp_encoder_shutdownintel_display_power_ddi_lanes_domainintel_hpd_pin_defaultintel_dp_hpd_pulseintel_dp_aux_chintel_dp_init_connectorintel_infoframe_init < <@q <`x < < <`EFGHImKuLMOP%OJ <`Y <  < < KL"MwOQRSTO(Q0RISXTOQRSTU\WOQRSTQ R S] O Q R S T Q R S Q R3 SB Tk r  !p  Y ! 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