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HH H߉{AKDNb HH;Db HHH߾b []A\H?[lH]A\b H;b HHH߾b [i]A\]A>fHHIE1$HH@HHP USPHfvHG(HLJ[]fvHG(HLJ[]Rkdʁxf v/HG(HLJHG(HLJ[]Gu7WtFXwMHǃHC(PHG(HLJ8t6HG(HLJ{xTHǃHC(f vHG(HLJG 0t0HG(HLJHǃHC(f t}HH#WHG(G HLJmH?HtHHoPHuH/HHHH XHG(HLJf t;W tHG(HLJG tHG(HG(t HG(t HG( t HC(t HG({t HG(jG x@tHG(QHC(D ut HG(/uڨt HG(yt HG(Gx@tHG(HG( t HG(t HG(u@H(H?HtHHoPHuH/HHH HC([]ff.fG @G4@GDHcDLGH@USHHHtHHHH{HHtHHH1Ht H49M4t []@D8ED[]@wd@USHHH3DHtHvWI1QHRPHH HE4HHE<EDHHE HHE(E0[]%s %s: [drm] Cannot satisfy minimum cdclk %d with refclk %u drivers/gpu/drm/i915/display/intel_cdclk.c%s %s: [drm] cdclk %d not valid for refclk %u Current CD clock frequency: %d kHz Max CD clock frequency: %d kHz Max pixel clock frequency: %d kHz [drm] *ERROR* Unknown pnv display core clock 0x%04x [drm] *ERROR* Failed to inform PCU about display config (err %d) required cdclk (%d kHz) exceeds max (%d kHz) drm_WARN_ON(cdclk != display->cdclk.hw.bypass)[drm] *ERROR* Bad HPLL VCO (HPLLVCO=0x%02x) [drm] *ERROR* Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x [drm] *ERROR* Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x [drm] *ERROR* Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x drm_WARN_ON(intel_de_read(display, ((const i915_reg_t){ .reg = (0x180000 + 0x650C) })) & (1 << 27))drm_WARN_ON((val & (1 << 30)) == 0)drm_WARN_ON((val & ((1 << ((0) * 6 + 5)) | (1 << ((0) * 6 + 4)) | (1 << ((0) * 6)))) != (1 << ((0) * 6)))cdctl & ((u32)(((int)sizeof(struct {_Static_assert(!(__builtin_choose_expr((sizeof(int) == sizeof(*(8 ? ((void *)((long)((26) > (27)) * 0l)) : (int *)8))), (26) > (27), false)), "const_true((26) > (27))" " is true");})) + (((typeof(u32))((((typeof(u32))1 << (8*sizeof(typeof(u32)) - 1 - (((typeof(u32))(-1)) < ( typeof(u32))1))) - 1) + ((typeof(u32))1 << (8*sizeof(typeof(u32)) - 1 - (((typeof(u32))(-1)) < ( typeof(u32))1))))) << (26) & ((typeof(u32))((((typeof(u32))1 << (8*sizeof(typeof(u32)) - 1 - (((typeof(u32))(-1)) < ( typeof(u32))1))) - 1) + ((typeof(u32))1 << (8*sizeof(typeof(u32)) - 1 - (((typeof(u32))(-1)) < ( typeof(u32))1))))) >> ((sizeof(u32) * 8) - 1 - (27)))))drm_WARN_ON_ONCE(!display->funcs.cdclk->set_cdclk)%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d %s %s: [drm] cdclk state doesn't match! [drm] *ERROR* timeout waiting for FREQ change request ack [drm] *ERROR* timeout waiting for CDCLK PLL unlock [drm] *ERROR* timeout waiting for CDCLK PLL lock [drm] *ERROR* timeout waiting for DE PLL unlock [drm] *ERROR* timeout waiting for DE PLL lock drm_WARN_ON(!new_cdclk_state->base.changed)drm_WARN_ON(cdclk_pll_is_unknown(a->vco))Can change cdclk via crawling and squashing Can change cdclk via squashing Can change cdclk via crawling Can change cdclk cd2x divider with pipe %c active Modeset required for cdclk change New cdclk calculated to be logical %u kHz, actual %u kHz New voltage level calculated to be logical %u, actual %u drm_WARN_ON(vco != 8100000 && vco != 8640000)[drm] *ERROR* Failed to inform PCU about cdclk change (err %d, freq %d) drm_WARN_ON(old_div != new_div)drm_WARN_ON(mid_cdclk_config->cdclk < ({ __auto_type __UNIQUE_ID_x_914 = (old_cdclk_config->cdclk); __auto_type __UNIQUE_ID_y_915 = (new_cdclk_config->cdclk); do { __attribute__((__noreturn__)) extern void __compiletime_assert_916(void) __attribute__((__error__("min""(""old_cdclk_config->cdclk"", ""new_cdclk_config->cdclk"") signedness error"))); if (!(!(!(((((typeof(__UNIQUE_ID_x_914))(-1)) < ( typeof(__UNIQUE_ID_x_914))1) ? (2 + (__builtin_constant_p((long long)(__UNIQUE_ID_x_914) >= 0) && ((long long)(__UNIQUE_ID_x_914) >= 0))) : (1 + 2 * (sizeof(__UNIQUE_ID_x_914) < 4))) & ((((typeof(__UNIQUE_ID_y_915))(-1)) < ( typeof(__UNIQUE_ID_y_915))1) ? (2 + (__builtin_constant_p((long long)(__UNIQUE_ID_y_915) >= 0) && ((long long)(__UNIQUE_ID_y_915) >= 0))) : (1 + 2 * (sizeof(__UNIQUE_ID_y_915) < 4))))))) __compiletime_assert_916(); } while (0); ((__UNIQUE_ID_x_914) < (__UNIQUE_ID_y_915) ? (__UNIQUE_ID_x_914) : (__UNIQUE_ID_y_915)); }))drm_WARN_ON(mid_cdclk_config->cdclk > display->cdclk.max_cdclk_freq)drm_WARN_ON(cdclk_squash_waveform(display, mid_cdclk_config->cdclk) != mid_waveform)[drm] *ERROR* PCode CDCLK freq set failed, (err %d, freq %d) drm_WARN_ON_ONCE(display->platform.skylake && vco == 8640000)[drm] *ERROR* Failed to inform PCU about cdclk change (%d) [drm] *ERROR* Couldn't disable DPLL0 [drm] *ERROR* DPLL0 not locked Sanitizing cdclk programmed by pre-os [drm] *ERROR* timed out waiting for CDclk change %s %s: [drm] trying to change cdclk frequency with cdclk not enabled [drm] *ERROR* failed to inform pcode about cdclk change [drm] *ERROR* Switching to FCLK failed [drm] *ERROR* Switching back to LCPLL failed drm_WARN_ON(((&_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display))->info.__runtime_info)->step) == STEP_NONE)%s %s: [drm] Unknown platform. Assuming i830  *  > r p          C s      < u s   _ s   cdclkMissing case (%s == %ld) %s %s: [drm] %sdrm_WARN_ON(vco != 0)HPLL VCO %u kHz val & (7 << ((0) * 6 + 1))dssmdivider[hw state][sw state]Pre changing CDCLK toPost changing CDCLK toCDCLK changeMax CD clock rate: %d kHz Max dotclock rate: %d kHz Current CDCLKhrawclki915_cdclk_infoS        0 =UaQ>Ia0 =UaQ>I(0 =UaQa2Kl6A0 =UaQ>I0 =UaQa(A  XZ9eF'rS4 ` ! "A # $ "XZ9e @~phS o@"V " "ZS "}"H"@"[J""`Z"9" "x""@"V " "KKK SK2K: KD]]]S](@l].@ ]6 S "KKK K: KD]]]@l].@ ]6  "K K: KD]@l].@ P_6 "K$K(K@KKt K ]] ]4]l@l]\@ ]l D: DKKK KDK: KD ]]]]6@l].@ ]6  " "`5K!jK!K!2K<eK<K<K< KAi915.import_ns=PWMGCC: (Debian 12.2.0-14+deb12u1) 12.2.0GNU&0=PTpk" 0 ,&;0RP_`p `D00 ` 4Rj} 1 p  &U=0Rix`     H<NB*[B`PP^p_l"zzp&* 0pFGKYp\r^  /@hB SfTv x ``  `   ` #` 03 C  S Hc s@     ` @     # 6 H Z` k@ }  I@Nas   , > O _ s        6 I W p           ; U i  1 1+ 2* P2F 2k / 03BP 6r 8)  8   9J  :O0 ? V s :     (0@DV AxPAcES`X "4BWjbd-8dOh ch vi  i@i `i|i j"+:Rintel_cdclk.cfixed_133mhz_get_cdclkfixed_200mhz_get_cdclkfixed_266mhz_get_cdclkfixed_333mhz_get_cdclkfixed_400mhz_get_cdclkfixed_450mhz_get_cdclkbxt_calc_voltage_levelxe3lpd_calc_voltage_levelbxt_calc_cdclkbxt_calc_cdclk_pll_vcointel_cdclk_destroy_stateintel_cdclk_duplicate_statei915_cdclk_info_openi915_cdclk_info_showi85x_get_cdclki915gm_get_cdclki945gm_get_cdclkpnv_get_cdclkvlv_get_cdclkcdclk_squash_waveformicl_calc_voltage_levelicl_voltage_level_max_cdclk.3ehl_calc_voltage_levelehl_voltage_level_max_cdclk.2tgl_calc_voltage_leveltgl_voltage_level_max_cdclk.1rplu_calc_voltage_levelrplu_voltage_level_max_cdclk.0intel_pcode_notify.part.0intel_crtc_compute_min_cdclk.part.0intel_compute_min_cdclkfixed_modeset_calc_cdclkbxt_modeset_calc_cdclkbdw_modeset_calc_cdclkvlv_modeset_calc_cdclkbxt_cdclk_ctl.isra.0skl_modeset_calc_cdclkintel_hpll_vcoblb_vco.8ctg_vco.12elk_vco.11cl_vco.10pnv_vco.9i965gm_get_cdclkdiv_3200.15div_5333.13div_4000.14g33_get_cdclkdiv_4000.6div_5333.4div_3200.7div_4800.5gm45_get_cdclkvlv_program_pfi_creditshsw_get_cdclkbdw_get_cdclkskl_get_cdclkbxt_get_cdclkintel_set_cdclk__already_done.16_bxt_set_cdclkintel_cdclk_funcsskl_set_cdclk__already_done.17vlv_set_cdclkchv_set_cdclkbdw_set_cdclki915_cdclk_info_fopsxe3lpd_cdclk_funcsxe3lpd_cdclk_tablerplu_cdclk_funcsxe2lpd_cdclk_tablemtl_cdclk_tablexe2hpd_cdclk_tableadlp_a_step_cdclk_tabletgl_cdclk_funcsdg2_cdclk_tablerkl_cdclk_tableadlp_cdclk_tableicl_cdclk_tableehl_cdclk_funcsrplu_cdclk_tablebxt_cdclk_funcsglk_cdclk_tableicl_cdclk_funcsbdw_cdclk_funcsbxt_cdclk_tablehsw_cdclk_funcsskl_cdclk_funcschv_cdclk_funcsvlv_cdclk_funcsfixed_400mhz_cdclk_funcsilk_cdclk_funcsgm45_cdclk_funcsi965gm_cdclk_funcsg33_cdclk_funcspnv_cdclk_funcsi945gm_cdclk_funcsi915gm_cdclk_funcsi865g_cdclk_funcsi915g_cdclk_funcsi85x_cdclk_funcsi845g_cdclk_funcsi830_cdclk_funcs__UNIQUE_ID___addressable___SCK__preempt_schedule831.18__UNIQUE_ID___addressable___SCK__preempt_schedule829.19__UNIQUE_ID_modinfo775__UNIQUE_ID___addressable___SCK__might_resched41.20.LC1__x86_return_thunkdev_driver_string__warn_printkkfreekmemdup_noprofsingle_openseq_printf__ref_stack_chk_guardpci_bus_read_config_word__stack_chk_failpci_read_config_word_dev_errvlv_iosf_sb_getvlv_get_hpll_vcovlv_get_cck_clockvlv_iosf_sb_readvlv_iosf_sb_putintel_pcode_request__drm_to_displayhsw_ips_min_cdclkintel_audio_min_cdclkvlv_dsi_min_cdclkintel_vdsc_min_cdclkintel_atomic_get_new_global_obj_stateintel_atomic_lock_global_stateintel_atomic_get_new_bw_stateintel_bw_min_cdclk__drm_dev_dbg__x86_indirect_thunk_rax__sw_hweight32intel_dmc_wl_getto_intel_uncoreintel_dmc_wl_putintel_psr_pauseintel_encoder_can_psrintel_audio_cdclk_change_premutex_lockmutex_unlockintel_psr_resumeintel_audio_cdclk_change_post__intel_wait_for_registerintel_crtc_for_pipeintel_crtc_wait_for_next_vblankintel_cdclk_get_cdclkintel_mdclk_cdclk_ratiointel_cdclk_clock_changedintel_cdclk_dump_configintel_cdclk_is_decreasing_laterintel_atomic_get_old_global_obj_stateintel_set_cdclk_pre_plane_updateintel_set_cdclk_post_plane_updateintel_atomic_get_cdclk_stateintel_atomic_get_global_obj_stateintel_cdclk_atomic_checkintel_plane_calc_min_cdclkintel_bw_calc_min_cdclkintel_cdclk_state_set_joined_mbusintel_cdclk_initkmalloc_caches__kmalloc_cache_noprofintel_atomic_global_obj_initintel_modeset_calc_cdclkintel_calc_active_pipesintel_atomic_serialize_global_stateintel_modeset_all_pipes_lateintel_dbuf_state_set_mdclk_cdclk_ratiointel_atomic_get_crtc_stateintel_cdclk_update_hw_stateto_intel_bw_stateintel_cdclk_crtc_disable_noatomicintel_update_max_cdclkintel_update_cdclkintel_pcode_write_timeoutintel_dbuf_mdclk_cdclk_ratio_updateintel_cdclk_init_hwintel_cdclk_uninit_hwintel_display_power_getvlv_iosf_sb_writektime_get_raw__SCT__might_reschedusleep_range_stateintel_display_power_put_unchecked__preempt_countcpu_numberlocal_clock__SCT__preempt_scheduleintel_read_rawclki9xx_fsb_freqvlv_get_cck_clock_hpllintel_cdclk_debugfs_registerdebugfs_create_file_fullintel_init_cdclk_hooksintel_cdclk_logicalintel_cdclk_actualintel_cdclk_actual_voltage_levelintel_cdclk_min_cdclkintel_cdclk_bw_min_cdclkintel_cdclk_pmdemand_needs_updateintel_cdclk_force_min_cdclkintel_cdclk_read_hwseq_lseekseq_readsingle_release__SCK__preempt_schedule__SCK__might_reschedx yUxg ply{  08 K}[ `}p u}~~Gu~~~)[~l~~2 7Jw x py  y7 p0g p  p pD ] H    7     w    ? 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