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IrDED$ tSIdžHIdžIdžLHHHEI{AG!AAG@LL$ I}@HH@LD$D$tL$ 1I>H7BI.Ht HHEIHzA@HLLAHfPIdž HCIdž(IIdž8Idž0SAIdžXhfPXC<A=DH߉T$ T$ AA1IAHHHHNH|$AMAAW=HH|$AOAHf (C 0Ay{AGAAGIdžHIdžIdžEMAILH#HC EIdžD$ (HDl$ H;HtHHoPHuH/HHHH AGAAGEMAIMIdžHIdžIdžf t'f u { tDBAGAg%LHC 0t=f IdžIdžIdžH6f f AtIdžHIdžIdžIdžLXA[IdžIdžIdžIdžKAA[HH#Su?f tEfC IdžHIdžIdž(HIdžHIdžIdždrm_WARN_ON(!pll)%s %s: [drm] %sMissing case (%s == %ld) drm_WARN_ON(n_entries < 1)crtc_state->pipe_bpppipeenableddisabledport_clock[ENCODER:%d:%s] [CRTC:%d:%s] drm_WARN_ON(ret)disablepll->info->ididclockpin_assignmenttmp & (7 << 12)drm_WARN_ON_ONCE(!trans)drm_WARN_ON(ctl & (1 << 9))drm_WARN_ON(!wakeref)Using signal levels %08x drm_WARN_ON(is_mst)Retry FEC enabling tmpdrm_WARN_ON(!pll_active)valencoder->portTC (TC)non-legacyyeslegacynoportPort %c strap not detected Port %c already claimed VBT says port %c has lspcon DDI %c/PHY %cDDI %s%c/PHY %s%cDDI %c%s/PHY %s%c./include/linux/seq_buf.h%sdrm_WARN_ON(port > PORT_I)drivers/gpu/drm/i915/display/intel_ddi.cconn_state->connector->connector_typedrm_WARN_ON(n_entries > (sizeof(index_to_dp_signal_levels) / sizeof((index_to_dp_signal_levels)[0]) + ((int)sizeof(struct {_Static_assert(!(!(!__builtin_types_compatible_p(typeof((index_to_dp_signal_levels)), typeof(&(index_to_dp_signal_levels)[0])))), "must be array");}))))drm_WARN_ON(master == INVALID_TRANSCODER)drm_WARN_ON(dig_port->aux_wakeref)drm_WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))drm_WARN_ON(dig_port->ddi_io_wakeref)[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs Failed to set FEC_READY to %s in the sink Failed to clear FEC detected flags drm_WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))[drm] *ERROR* [CONNECTOR:%d:%s] Failed to read TMDS config: %d drm_WARN_ON(!dig_port->dp.attached_connector)[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio Failed to %s MSA_TIMING_PAR_IGNORE in the sink [drm] *ERROR* Timeout waiting for DDI BUF %c to get active [drm] *ERROR* Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c drm_WARN_ON((pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))drm_WARN_ON(!intel_tc_port_in_legacy_mode(dig_port))No pipe for [ENCODER:%d:%s] found Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x) Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b %02x) [drm] *ERROR* [ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x) [drm] *ERROR* Timeout waiting for DDI BUF %c to get idle drm_WARN_ON(transcoder_is_dsi(cpu_transcoder))drm_WARN_ON(crtc_state->limited_color_range && crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)Quirk Increase DDI disabled time drm_WARN_ON(ddi_mode == (3 << 24))%s %s: [drm] Unsupported voltage swing/pre-emphasis level: 0x%x drm_WARN_ON_ONCE(level >= n_entries)[drm] *ERROR* Invalid I_boost value %u drm_WARN_ON(((&(display)->info.__runtime_info)->step) == STEP_NONE)drm_WARN_ON(port_mask & ((((1UL))) << (other_encoder->port)))[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it [drm] *ERROR* Timed out waiting for DP idle patterns drm_WARN_ON(dp_tp_ctl & ((u32)(((int)sizeof(struct {_Static_assert(!(__builtin_choose_expr((sizeof(int) == sizeof(*(8 ? ((void *)((long)((31) >= (sizeof(u32) * 8)) * 0l)) : (int *)8))), (31) >= (sizeof(u32) * 8), false)), "const_true((31) >= BITS_PER_TYPE(u32))" " is true");})) + ((((1ULL))) << (31)))))[drm] *ERROR* Timed out waiting for ACT sent [drm] *ERROR* Timeout waiting for FEC live state to get %s Failed waiting for FEC %s to get detected: %d (status 0x%02x) [drm] *ERROR* Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c [drm] *ERROR* Failed to enable FEC after retries drm_WARN_ON(crtc_state->has_pch_encoder)drm_WARN_ON(is_mst && (port == PORT_A || port == PORT_E))drm_WARN_ON(is_mst && port == PORT_A)[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio drm_WARN_ON(port < PORT_A || port > PORT_E)drm_WARN_ON(!(intel_ddi_splitter_pipe_mask(display) & ((((1UL))) << (pipe))))%s %s: [drm] Invalid splitter configuration, dss1=0x%08x drm_WARN_ON(crtc_state->master_transcoder != INVALID_TRANSCODER && crtc_state->sync_mode_slaves_mask)%s %s: [drm] Platform does not support DSI PORT %c / PHY %c reserved by HTI VBT says port %c is not DVI/HDMI/DP compatible, respect it SNPS PHY %c failed to calibrate, proceeding anyway drm_WARN_ON(seq_buf_has_overflowed(s))Forcing DDI_A_4_LANES for port A VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s  M n p  ( X    C  c      " 4   n B     <          S  s {  U B   R O c G  M  x          d  `@   i915.import_ns=PWMGCC: (Debian 12.2.0-14+deb12u1) 12.2.0GNU &0m7|P@Ln"h % DW|3R0%np c   ` , ` ')BP` YP6i |${?{Z0{uP !!"#P$2%H%^&z'm@(p)[* -. /509JP12]2%u4679' <1p>B,=NXdu]ditpo; `w?`x^z.|{|. `@_p (p 9 ARPk=@Pg@, ' `: ,N @(^ u   b      % 6 G ]        7 Q m        . H _ t        0 H Y q        +C[,pbBSctu,/C`@GwGI!J6MLc`M N-POJOk{Q9STUn @VC0Lhs`ttt&vq4Sq.iGco7Vl5Xq~*Ai4F]qpp@_s'?Xl5Ouл1%7JWw )B\$=^n  C V k ~      intel_ddi.cintel_ddi_dp_preemph_maxdp_tp_status_regicl_ddi_tc_port_pll_typeintel_ddi_compute_output_typeintel_ddi_dp_voltage_maxindex_to_dp_signal_levelsintel_ddi_transcoder_func_reg_val_getintel_ddi_tc_encoder_shutdown_completeintel_ddi_tc_encoder_suspend_completeintel_ddi_main_link_aux_domainmain_link_aux_power_domain_getintel_ddi_get_power_domainsintel_ddi_encoder_shutdownintel_ddi_encoder_suspendintel_ddi_initial_fastset_checkintel_ddi_sync_stateintel_dp_sink_set_fec_readyintel_ddi_post_pll_disableintel_ddi_init_dp_buf_regintel_ddi_power_up_lanesintel_ddi_compute_config_lateintel_ddi_encoder_late_registerintel_ddi_hotplugintel_ddi_link_checkintel_ddi_encoder_destroyintel_ddi_encoder_resetintel_ddi_disableintel_ddi_buf_status_reg.isra.0skl_ddi_is_clock_enabledlpt_digital_port_connectedbdw_digital_port_connectedhsw_digital_port_connectedrkl_ddi_is_clock_enableddg1_ddi_is_clock_enabledicl_ddi_combo_is_clock_enabledjsl_ddi_tc_is_clock_enabledadls_ddi_is_clock_enabledintel_ddi_config_transcoder_dp2skl_ddi_disable_clockrkl_ddi_disable_clockdg1_ddi_disable_clockicl_ddi_combo_disable_clockjsl_ddi_tc_disable_clockadls_ddi_disable_clockintel_ddi_buf_enableicl_ddi_tc_disable_clockCSWTCH.340intel_ddi_mso_configureicl_ddi_tc_is_clock_enabledbdw_transcoder_master_readoutskl_ddi_enable_clockmtl_ddi_enable_d2dicl_ddi_tc_enable_clockicl_ddi_combo_enable_clockjsl_ddi_tc_enable_clockrkl_ddi_enable_clockadls_ddi_enable_clockdg1_ddi_enable_clockicl_program_mg_dp_modeintel_ddi_get_encoder_pipes__already_done.8__already_done.2__already_done.1hsw_set_signal_levels__already_done.6icl_mg_phy_set_signal_levels__already_done.4tgl_dkl_phy_set_signal_levels__already_done.3icl_ddi_combo_vswing_program__already_done.5icl_combo_phy_set_signal_levelsintel_ddi_read_func_ctl_dp_mstintel_ddi_read_func_ctl_dp_sstintel_ddi_set_idle_link_trainintel_ddi_set_link_trainintel_ddi_prepare_link_retrainmtl_ddi_prepare_link_retrainintel_ddi_buf_disableintel_ddi_post_disableintel_ddi_enable_fecintel_ddi_pre_enableintel_ddi_enabletrans.0__already_done.7intel_ddi_pre_pll_enableintel_ddi_get_configicl_ddi_tc_get_configdg2_ddi_get_configmtl_ddi_get_configintel_ddi_compute_configskl_ddi_get_configbxt_ddi_get_configicl_ddi_combo_get_configdg1_ddi_get_configrkl_ddi_get_configadls_ddi_get_configintel_ddi_funcs__UNIQUE_ID_modinfo672__UNIQUE_ID___addressable___SCK__might_resched2.9.LC2.LC95__x86_return_thunk__drm_to_displaydev_driver_string__warn_printk__ref_stack_chk_guard__x86_indirect_thunk_rax__stack_chk_failintel_dp_is_uhbrintel_tc_port_cleanupintel_encoder_link_check_flush_workintel_tc_port_suspendintel_psr_needs_aux_io_powerintel_encoder_is_tcintel_aux_power_domainintel_display_power_aux_io_domainintel_display_power_getintel_tc_port_in_tbt_alt_modeintel_dp_encoder_shutdownintel_hdmi_encoder_shutdownintel_dp_encoder_suspend__drm_dev_dbgintel_dp_initial_fastset_checkintel_tc_port_sanitize_modeintel_dp_sync_statedrm_dp_dpcd_writeintel_display_power_put_uncheckedintel_tc_port_put_linkintel_dp_link_symbol_sizeintel_encoder_is_combointel_encoder_to_phyintel_combo_phy_power_up_lanesdrm_mode_matchintel_tc_port_link_resetintel_dp_test_phyintel_encoder_hotplugintel_dp_check_link_state_intel_modeset_lock_begin_intel_modeset_lock_loop_intel_modeset_lock_enddrm_modeset_locktry_wait_for_completiondrm_scdc_readintel_modeset_commit_pipes_dev_errintel_dp_link_checkintel_dp_encoder_flush_workintel_display_power_flush_workdrm_encoder_cleanupkfreeintel_dp_invalidate_source_ouiintel_pps_encoder_resetintel_tc_port_init_modeintel_tc_port_link_cancel_reset_workintel_hdcp_disableintel_hdmi_handle_sink_scramblingintel_panel_unprepareintel_psr_disableintel_alpm_disableintel_edp_backlight_offintel_dp_sink_disable_decompressionhsw_ddi_disable_clockintel_dmc_wl_getto_intel_uncoreintel_dmc_wl_puthsw_ddi_is_clock_enabledmutex_lockmutex_unlock__intel_wait_for_registerusleep_range_stateintel_encoder_to_tchsw_ddi_enable_clockintel_dkl_phy_readintel_tc_port_get_pin_assignmentintel_dkl_phy_writeintel_tc_port_in_legacy_modeintel_display_power_get_if_enabled__sw_hweight32intel_dp_mst_active_streamsintel_ddi_get_hw_statehsw_prepare_dp_ddi_buffersintel_bios_dp_boost_levelintel_wait_ddi_buf_idle__const_udelayintel_ddi_set_dp_msaintel_dp_needs_vsc_sdpintel_ddi_update_pipeintel_hdmi_fastset_infoframesintel_hdcp_update_pipeintel_dp_set_infoframesintel_backlight_updatedrm_connector_update_privacy_screenintel_ddi_enable_transcoder_funcintel_ddi_config_transcoder_funcintel_ddi_disable_transcoder_funcintel_dp_mst_is_slave_transintel_has_quirkmsleepintel_dp_mst_is_master_transintel_ddi_toggle_hdcp_bitsintel_ddi_connector_get_hw_stateintel_ddi_enable_transcoder_clockintel_ddi_disable_transcoder_clockintel_ddi_levelintel_bios_hdmi_level_shiftintel_bios_hdmi_boost_level__x86_indirect_thunk_r11intel_dkl_phy_rmwis_hobl_buf_transicl_ddi_combo_get_pllintel_get_dpll_by_idintel_ddi_enable_clockintel_ddi_disable_clockintel_ddi_sanitize_encoder_pll_mappingdp_tp_ctl_regintel_cpu_transcoder_get_m1_n1intel_hdmi_infoframes_enabledintel_cpu_transcoder_get_m2_n2intel_lspcon_activeintel_dp_has_hdmi_sinkintel_lspcon_infoframes_enabledintel_tc_port_in_dp_alt_modeintel_alpm_port_configureintel_lnl_mac_transmit_lfpsintel_ddi_clear_act_sentintel_ddi_wait_for_act_sentintel_ddi_wait_for_fec_statusktime_get__SCT__might_rescheddrm_dp_dpcd_readintel_dp_dual_mode_set_tmds_outputintel_dp_set_powerintel_pps_vdd_onintel_pps_offintel_crtc_for_pipe_intel_modeset_primary_pipes_intel_modeset_secondary_pipesintel_crtc_vblank_offintel_disable_transcoderintel_vrr_transcoder_disableintel_dsc_disableskl_scaler_disableilk_pfit_disabledrm_dp_dpcd_write_payloaddrm_dp_dpcd_poll_act_handledintel_set_cpu_fifo_underrun_reportingintel_psr_panel_replay_enable_sinkintel_dp_set_link_paramsintel_pps_onintel_dp_configure_protocol_converterintel_dp_check_frl_trainingintel_dp_pcon_dsc_configureintel_dp_start_link_trainis_trans_port_sync_modeintel_dp_128b132b_sdp_crc16intel_dsc_dp_pps_writeintel_dp_lttpr_transparent_mode_enableddrm_dp_lttpr_wake_timeout_setupintel_dp_stop_link_trainintel_dp_sink_enable_decompressionintel_dp_queue_modeset_retry_for_linkintel_vrr_transcoder_enableintel_enable_transcoderintel_crtc_vblank_onintel_hdcp_enableintel_edp_backlight_onintel_panel_prepareintel_ddi_update_active_dpllintel_crtc_joined_pipe_maskintel_dpll_update_activeintel_tc_port_get_linkintel_tc_port_set_fia_lane_countbxt_dpio_phy_set_lane_optim_maskintel_ddi_compute_min_voltage_levelintel_display_power_is_enabledintel_crtc_dotclockintel_hdmi_read_gcp_infoframeintel_read_infoframeintel_psr_get_configintel_read_dp_sdpintel_audio_codec_get_configintel_edp_fixup_vbt_bppbxt_dpio_phy_get_lane_lat_optim_maskintel_dpll_get_hw_stateicl_set_active_port_dpllintel_dpll_get_freqicl_tc_port_to_pll_idintel_mpllb_readout_hw_stateintel_mpllb_calc_port_clockintel_cx0pll_readout_hw_stateintel_mtl_tbt_calc_port_clockintel_cx0pll_calc_port_clockintel_hdmi_compute_has_hdmi_sinkintel_hdmi_compute_configbxt_dpio_phy_calc_lane_lat_optim_maskintel_dp_compute_configintel_ddi_get_clockhsw_ddi_get_configintel_ddi_port_pll_typeintel_ddi_initintel_bios_encoder_portassert_port_validintel_bios_encoder_supports_dsiintel_port_to_phyintel_hti_uses_phyicl_dsi_initintel_bios_encoder_supports_dviintel_bios_encoder_supports_dpintel_bios_encoder_is_lspconintel_phy_is_snpsintel_dig_port_allocintel_port_to_tcseq_buf_printfdrm_encoder_initintel_encoder_link_check_initintel_audio_codec_enableintel_audio_codec_disableintel_display_power_ddi_lanes_domainintel_mtl_pll_enableintel_mtl_pll_disableintel_mtl_port_pll_typeintel_cx0_phy_set_signal_levelsintel_snps_phy_set_signal_levelsbxt_dpio_phy_set_signal_levelsintel_ddi_buf_trans_initintel_bios_encoder_lane_reversalintel_dp_aux_chintel_display_power_ddi_io_domainintel_infoframe_initintel_connector_allocintel_hdmi_init_connectorintel_bios_encoder_supports_hdmiintel_mpllb_enableintel_mpllb_disableintel_bios_encoder_supports_typec_usbintel_tc_port_lockintel_tc_port_unlockintel_tc_port_initintel_tc_port_connectedintel_dp_init_connectorintel_dp_hpd_pulseintel_bios_encoder_supports_tbtintel_hpd_pin_default__SCK__might_reschedAoop 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