ELF>6@@fUHSHH?HtHfP v-HHiu2Hc`B,[]D+BLDL[]D@HcSH?HHtHHHtH@H[xH?HtHH_PHuHHHHH 1[@HHc t/t% tHH 1@ATIUSHHH eHHD$1Ht HHHT$HCLD$H T$~5 wqHcHT$eH+H[]A\H}HtHH_PHuHHHHH 1럐H}HtHH_PHuHHHHH Xff.AVAUATUHSHHL MtLIHEfA$P DpD`Hc|xځEډځEAh@l@tAtA$Pf wnfw tt % Àπ[]A\A]A^$0HtUD A$PD É[]A\A]A^@E=H‰؁ DظtD A$Pf   % Hc|N[HH 7At{At}EtHIcH '@HtD A$P"P`I<$HtHLoPMuL/HLHH A$P w1҃w#H t1҃ uHHHHff.Sw1ۃw/H[ t1ۃ uHH[HH[fATIUSH/HHt HHLHu>fP w&A$h u Ht H[]A\[L]A\dH[]A\@AUATIUSH/HHt HHLHFHxAu#ALtDHHx[]A\A]H}HtHLoPMuL/HLHH AUATUHSL'HMt LIiuowIE1wWLu$IpAhLIp[HL]A\A] tE1 uLI뤐I<$HtHH_PHuHHHHH []A\A]I<$HtHH_PHuHHHHH 4ff.SHv+ u-t.HuH[wt[ u(tH[ff.fAUATUHSL'HMt LIHAt/I4$LK8DCHtHvH1E1M h u[D]A\A]HHu[]A\A]UHSHtwD1wcHHth tHH[]w!w[] t!1 uH뮃 uߋtH또AUAATIUSHHH eHHD$1Ht HHA$u"HD$eH+H[]A\A]HT$ H0HDl$H~_EtHT$HD$HHuHtHvHD$eH+uWHH1[]A\A]HuEIHLDHtHvH1g@AUIATUSHw^1wlLeMt LILHHxHDžxHtLHu%[]A\A] t1 uHH[H]A\A]ff.@AVAUATIUHSL7Mt LIƋv  LL 1ۃHGIA$tDA`t AatfAP AFu|AP fv[]A\A]A^HI{HtE$DDiAli []A\A]A^HtA$=fP=8tr=x=Kul@ L$@L =`=t=\ u60륺=tHHcH 1v=uֺpe`[1E1/fAUATIUSH/HHt HHŋwE1wbHu+[]A\A] tFE1 uHLtHE`[1A$H]A\A]IAWAVAUATIUHSH?HHtHHH7M$$LM8HP DE@`HtHvR1HP^_A$uI1E1ȉ9`uHǃHD!舃[1]A\A]A^A_I$DpHH8HtHfPLHvhzAL$(mE11A;l$(HcHID$0HHHtHRHRHt̀tHD;puPtHH)IT$ HLxAPtOyAOkAh9hXAD9DEA81A9I`H` A`9`A9A9A9A9A9A`HA A;l$(zAt Aff.w1҃w1H1 t1҃ uHH1HH1AWAVAUATIUSHHĀeHHD$xwlE1wzHMHl$8A1D$4HHLtGE1HD$xeH+]HD[]A\A]A^A_ tE1 uLILHL$D$uA$ tLLD$D$EzAA9$ ]EAEG GHL$411HD$Lt$Dl$DD$Ld$H|$4L#Mt LIċF1҃WL8D$3AMt1HT$41HD$4I$HHuMMhL$MtI}(HuML$Ah@lAPtAAuA@sIx(HtH0L $L $QHT$3 LL $L $T$3A:AuA:@ApHLH@ t1҃ HHD$4Lt$Dl$DD$Ld$H;HtHH_PHuHD$HHHH D$I<$IO`AW@HtHAH1+I<$HtHHWPHuHLL$ L$HT$(HT$(HHH LL$ L$9USHH?HtHNjw1҃wwHt'H[] t^1҃ uHHuِH?HtHHoPHuH/HHHH H[]HfAUATUSH/HHt HHŋwJw[E1E1HLuIHHI$L[]A\A] t uLMIILATUSvA u[HHIHƀHHHu[]A\w1۽1E1[L]A\ uLI$LL뙐AWAVAUIATIUHSHHeHHD$1|H}A$h@L#Mt LIHm11HH I4$LM`DE@HtHvHD$eH+yHH1[]A\A]A^A_ 1 XHLE1L}AƆIHLHHHLLLIHt HHA$<t%HT$D$IH~SHD$eH+H[]A\A]A^A_H| tE1 :L.I&H3HtHvHD$eH+u(HIH1[]A\A]A^A_f.f v fv*8F@@@@v } UHSHHt HHËHߍ,aH;HHH[]ff.ATUHSHHt HHËHD$aDH;DHHDH߉[]A\ff.ATUHSHHt HHþ\HDH;\HHH߾\AL$[]A\@ATUHSHHt HHHBH߉H;BHHH߾BAM [H]AA\ATUHSHHt HHËH@ HD$H;@ HHH߾@ A[]A\DATUHSHHt HHËH@HD$H;@HHH߾@A[]A\DATUHSHHt HHËH@DHD$H;@DHHH߾@DA[]A\DAUATUSL/HMt LIHLAĉAAAAAĀBDI}DHHDL [) H]A\A]ff.ATUHSH HeHHD$1Ht HHHABHH HHH$HL$D$ AH;BHHBH߉AHT$eH+u H []A\AUATUHSHHt HHËHD,aDH;DHHDHAAw [1]A\A][H]A\A]fDAUATUSHH L'eHHD$1Mt LIH߽LH HHcHt$HiVUUUH $D$ H )k<ÀBI<$HHLADHT$eH+uH []A\A]ff.AVAAUATIUSHHHt HHA$`Cu fP v_E1EuF H߁ŠH;DHHH[]A\A]A^LAA[]A\A]A^AUATUHSHHt HHL DL\HAH;\HHHH\DHH߾\L[]A\A]ff.AUATUHSHHt HHL HLABHH;BHHHAL$ HH⾀B HH߾BL[]A\A]fAVAUATUSL'HMt LIHM$ LʼnLŀBI<$IHLډL )Ѻ H ILL[]A\A]A^ff.AUATUHSH HeHHD$1Ht HHHL ALHH HHt$H $D$ ABHH;BHHHD⾀BH ¹HBHHD$eH+uH L[]A\A]ATUHSHHt HHDHHB,aH;1HHH[]A\AVAUATUSHH H/eHHD$1Ht HHHL ALH HcH $HHiVUUUHL$D$ H A)kDHHDLD$L$D$L$!9:D%H==UAA}MDT$H\$Lt$u0I7LK8DCHtHvH1D$D$Eu>|$W1҃t|$iDT$MD8oI7T$ALK8DCHtHvR1PQHH}H L[]A\A]A^A_IHLDh,Dh\AD+hLDI?DHHDLAD%p=PA0tHH EHI#G=AdLADI?DHHDL%=I?HK8SHtHAHD$pD$&H []A\A]A^A_EB}v@I7LK8DCHtHvWH1EȸHEXD$A}0AFtYT$0 t#1҃ HT$U HHG~D$fAP =`?EUELfDSHHeHHD$1HT$Ht$D$D$D$u1T$t‰HT$eH+uH[1fAWAVAUATIUHSHHeHHD$1Ht HHLHT$ HD$ DHIH,fP D$D$ CDmE1,I$IcljHH@Dl$AD ,L4H;DHHDmH߃I$DHFt0H;DDHHDHD9|$ XHD$eH+H[]A\A]A^A_{  HD$=uH;HtHH_PHuHHHHH _f AUATUSHPH߉AH;A ADjHǹDHAXEt!H;UAHtH[H]A\A][]A\A]p fAWAVAUIATUSHHH(Ht HHh rLc`AFHc|fA!dDDDDLHHD@DEHHX,B\L+XLH}DHHH[]A\A]A^A_Aa$`HH dDAAtiH}HtHLPMHLHH dDA[]A\A]A^A_AAAH}HtHLgPMt(HLHH @L'L?RDAUIATIUHSHh@t%HHLHHL[L]A\A] tHHHHھLLHHLHh@t됐AWAVAUIATUHSHHHt HHLc`fP Lv{E1tAt AHHLcHDb,FdLAD+bLDH;DDHHDHHLLHAHHh,BlL+hLH;DHHH[]A\A]A^A_fAUATIUSHHH(Ht HHH߾Lc`VHL蛳HAHHX,B\L+XLH}D޹HHH[]A\A]ff.AWAVAUATIUSL7IHtHM4$HfP Mc$`hHHHߋh,BlL+hLH;HHHAAnPPfAEAHHHߋh,BlL+hLH;DHHH߉LHt>A$h@t3H3HtHv1Hd[]A\A]A^A_[]A\A]A^A_EAf *LAEDHHHߋh,BlL+hLH;1HHHG1LI>HtHHoPHuH/HHHH QfDAWIAVAUAATAUSH/Ht HHAHHHHEIcHADEDb,DdLAD+bLDH}DIHLDL!ID DHAH1[]A\A]A^A_H}HtHH_PHuHHHHH []A\A]A^A_AVAUATUHSHHeHHD$1Ht HHLHDD$A$A$HI$XHt$Lat tHcD$HHHߋJ,+jLlLH;HHHAAu>A @A$HHD$eH+H[]A\A]A^AAtAt+At@1Cu)fP wA@1AA @uA @hH;HtHHoPHuH/HHHH 1%AUATIUSHHH(Ht HHD`LAtuPf w`A$f DF$@aHDH}DڹHHD[H]A\A]X[]A\A]DUHSHHHt HHË`t=,@aH߉H;1HHH[][]fAVAULcATIUSHHH/eHHD$1Ht HHD$HLHHT$IHA$h@uzwTE1wbC.4LtkDd$A9$HD$eH+H[]A\A]A^ tE1 uLIHÅyA^ I>HtH1: HH uH?HtHLgPMuL'LHH Dd$E~[12=uH}HtHH_PHuHHHHH 11ۀ=t A\$H}HtHHoPHt:HHHH D9Dd$륉cH/ff.fAWAVIAUATIUSH0HeHHD$(1Ht HHAE1&1LLfP AA/A$h@AH3EAHtHvE1@HAH߁A EH;DHHHHH;1҉HHHD$(eH+H0H[]A\A]A^A_ tE1 MMHD$(eH+YH0[]A\A]A^A_{ IH$Ht HH$AHD$IA$h@AEuBD$$ILLHT$$HH[IcH@HHDPA‰D$DЃ<t[AvUH$H8HtHT$H t!1HT$ IIHD$8Lt$.AH<$ DT$L$H$H8 HHH<$ D$L$DL$DT$tIH<$DT$L$ !ȉ A D EEщT$H$H8T$ HL.H<$ AHD$DT$cL4$ DT$LI>L4$ HHH<$ AD$DH<$DT$  ЁEADDH$H8D HHH<$ Au=H$H8HtHLwPMuL7HLHH ff.AWAVAUATIUHSH0HeHHD$(1Ht HHHAŋD$$O1[A HT$$LHHE,IA,D$MDHH;DHHH<$H<$D߉HDHAFHAƉ$H;4$HHH|$H|$4$ƒH4$HD9t$:$EH$LHPIDHHH@HHL$H;DHHH|$L$H|$DƒH ʹDH$LHIHHH@HHAFAƉD$L$H;t$HHH|$H|$t$HʋL$ ʹt$H<$t^$ tE1 HHD$(eH+6H0[]A\A]A^A_HjD$EDD$LHPDHHH@IHR Љ@ $H;DHHH|$ $H|$DH ʹDHT$LHHHH@IHR ЉAFA@Ɖ$L$H;4$HHH|$L$H|$‹4$H ʹ4$H|$t D$AA$E1HA$ߓAH;A IHLLID H߁9,$uAAE1D$DHA$!ALD$H;DHHH|$H|$D‹$ HDHAHA$!ELH;HHH<$H<$%HD H߁9l$ALALHDuH;IHLLI$H߁DHH;DIHLDLI$DHA9G=H;HtHH_PHt(HHHH HAWAVAUIATUHSHHHeHHD$@1Ht HHHAċD$<1HHT$H}HtHH_PHuHHHHH UHSHH?HtHfP v-HHiu2Hc`B,[]@+BLDL[]@@Hcff.@AVAUIATAUSH/HHt HHDH;`hfP vA ADHfP wHL []A\A]A^HLHAH}DHHDHAAAD@AWAVAUAATIUSHHH/Ht HHA$L;h`E1ɀD艓hfP vD%=NLHt$t$HLHLHAH}DHHDHAAADfP woLtIHL H[]A\A]A^A_M E1 M$HLHAH}DHHDHAAAD7A ADHL >MC9AWAVAUIATUHSH Ht HHL LDLH߉ƉH;IHLLI$HEu fP vvLL|H߉ƉH;AAjHǹHAXEt"H;HtH[H]A\A]A^A_[]A\A]A^A_fAWIAVAUIATAUSH Ht HHILLHAH}DHHDHD<thwZtg<uLLHAH}DڹHHD[H]A\A]A^A_ڀ<D륀렀AWAVAUATIUHSH Ht HHL LLH߉AH;DHHDHAEmA$iALLH߉AH;DDHHDHLLH߉AH;1DHHDHCuPuLM[]A\A]A^A_L?A$EAA&LtaH Ht HHL1Hߺ AADD1ɺHCLu2H;HtHLoPMuL/HLHH RfAWAVAUATIUHSHHHHt HHM$ HLH߉AH;DHHDHAEiQAHLH߉AH;DDHHDHHLH߉AH;1DHHDHLݲID$HLM$ Mt LIA$2E1MGA$<tLHL$ $L$ $Ɖ @EA`tfAPDv A DLL$ I?DHHH<$L$ H<$D%H ʹDLfPAt$v At$LHLAL$HLH[]A\A]A^A_M E1 Mt$AA@B<D@HEAAD} A H;HtHLwPMuL7HLHH $ATIUHSHHt HHLH}H߉ƉH;HHH[]A\ATIUHSHHt HHLH|H߉ƉH;AAjHǹHAXEtH;HtH[H]A\[]A\fDAVAUAATIUSHHH/eHHD$1Ht HHŋE1A$LHE-{HAH}AADjHǹDHAXRMM0Mt LIE1H HT$LDl$ÅD$uQH9' 뭃 E1 A$L1HD$eH+,H[]A\A]A^ZzHAH}1DjHAAHDH_tH}HtHHhI;H}HHuչHT$LD$ÅxpD$IHt0HrP1AIHZPHA1I1YIHt(HpSE1IH1XS1E1IH1^fff.AWIAVAUATUSHL7Ht$Mt LIAL@D$I>HHHH%HLfAP HIHt HHPf AL$fD@ADHH;DHHHDH%߉HDHHH$A E1H9$ADODHH;DHHDH߉uHD$h BIHt HHLl$ALLH߉ƉH;IHLL%I$HLLH߉ƉH;1HHHfAP Ht$HL1[]A\A]A^A_ D$AA@t$LT$H;AHtHHLHLƉI>޺HHHH%HLZt$LD$Dv A >ff.AWAVAUATUHSHH hH<$HL$>Le@Mt LIċE1Y1IHHHL$M(fA$P HHfA$P IpIDžpHtAhLHHtHH L1[]A\A]A^A_ E1 NLBMtLIċhIE1rMLfA$P jHH1HL~1H˖fA$P LLIpIdžpHtAhLHHtHA$Pf fsg@LI<$޺HHHHHLH []A\A]A^A_ t0E1 LMIIMlI$HHc`LDx,D|LAD+xLDI<$DHHH<$H<$D%HDLL.MtLIŋh\HD$@E1D$ AAtlDLIHtHHDD HLsAAHH)H $HHA HxAuHD$HE1HAADLIHtHHDD HLsAHH)H $HHA L`LLfAPvWAAzh> tK1HL$ HHL$H []A\A]A^A_HpHl$\HL$1HHLHfA$P bHC@|HHiL|$11ҾILHHIHHc`LD`,DdLAD+`LDI}DHHH|$H|$DHDLHH1Lv } fAWAVAUATIUHSHHt HHA$u[]A\A]A^A_LHH߉AH;DIHLDL @IDHfPvLHlAH3HtHvH1LHH߉AH;DIHLDL%IDH1LHu{LHH߉AH;DIHLDL @IDHLHXAH;HtH[H]A\A]A^A_ff.AWAVAUATIUHSHH0LoH $Mt LIH\Dp DLh@9HD$LmMtLIAEfAP +1HAPf sLmf EMt LIŋ>HD$AE1hL%D$HHwLHHt HHLu$Ip AhLIpHL!HHHHHHHHHyH&DD$EHLHL=uLHLLHLH{ HHiH|$H0[]A\A]A^A_ t"E1L\$ HHD$Hl$wo1gHH tZ1 H M LL|$M 1 uHHyLmMt LIŋE1I$(HHt HHI$p<A$hLHLI$pHH]I$H $H0HH[]A\A]A^A_ 9E1 YLMHMt LIŋL$AE1h%fAP D$tD$LHHtLHHt HHLu$IpAhLIpHL躥fAP wA} x HHHHHHH@vL$HLHLqHLLT$u fAPvH2HHD$HHHHizH4$HH|$nL|$IU]I 1 sLM HD$HD$LhL%D$ HHrL}Mt LINj1! fAPD$uPD@ tME1LT$ 9HHD$(I$Hl$LILIHl$ tx1 LH@|$t$I}HtHHWPHuHHT$ HT$ HHH HpD@DLI?DHHH|$(H|$(D‹D$ HDLLHHt HHHHHHH^L|$DL$ IELLHLHLVnLHLLHLHHL I}HtHLPMuL?HLHH v ALHLH$HLH0HLmLHLLHLHHHHH|$1ҾHHHL}LHLH$HLH0LLLHLH$HLH0HLlLHLLHLHHHH1ҾLI}HtHHWPHuHHT$ HT$ HHH HLgHLY} AfAE1HLHHuHLI}HtHLwPMuL7HLHH I}HtHHWPHuHHT$ HT$ HHH I}HtHHWPHuHHT$ HT$ HHH 7fAWAVIAUATIUSHH`L.H $eHHD$X1Mt LIŋhHc`@D$<LHHHAHLLd$ArcDLIHtHH HLsA$MN HH)IHxAsLd$DD$I,$EHt HHA$<HD$H$@LAL(A$LD$u(HuMM`EE@HtHvH1fP E} ;M<$Mt LI1HLA$HLD$<LcHT$PHHPLA $Dm\uH|HI#FHHHHHHHHHHHHHHHPfAP4HHHH HHHH"HHH[]A\A]A^A_=0Fǃ|$D%<ƃlHH tƃ]Atƃ@AH}HtHǃh@fP cAAAD$1mV|HC`A $kHcE1HL(Mt LIŋ`LE1AzAaLsJMsDE|$ LDHt/DLz;`uDHDLAAu*I}HtHLgPMuL'HLHH HJƃƃA_I<$HtHLgPMDLHH +E1I>HtHH_PHuHHHHH H[]A\A]A^A_ǃ|ǃ|AGufAP w*1wpHDHHtM tH1 uHDHHxhDHHeUL'SCH닐I<$HtHLgPMuL'HLHH ƃhL}Mt LIǃhHHLAI?DHHDLAAADHc$AWAVAUATUHSL'HMt LIHLANjD4aDI<$DHHDLAD%=wZufH}E1HtIĐI<$HtHLgPMuL'HLHH =t9v(=t0HDH yD%=uоLLeIMt LIMQIEHLLxAAIHLHHDHHHFHxt*HLHH[]A\A]A^A_ALD4aDI<$DHHDLAD%=v#`==t =u1\ lt8=uxDHH 1뵐I<$HtHLoPMt2HLHH lL/@ATLUHLSHLHHH߉[]A\ATLUHSHLtHHH[]A\LHސAVIAUATIUSH/HHt HHL+atA$LHLh@LLHވlAEuCE t%Apu`ut^HH#Eu'H[D]A\A]A^ǃ`gAxfATIUSH/HHt HHMtLLHLHtuH1HHH[]A\H}HtHH_PHuHHHHH []A\H}HtHLgPMt(HLHH LL'@AVAUATIUHSHHt HHËHD,aDH;DHHDHAD%=`w@= =@udHHLHL[H]A\A]A^=t?=u11=tHDH 1맾tվ늾냾yfAVAUATIUHSHHt HHþ\HDH;\HH\HAC v1AsHD!HLHL[H]A\A]A^bfUHSHH?HtHNjw HHHHH[] HHcH 1fUHSHHHHHH[]@AWAVAUIATIUSH/Ht HHLHAÀBH}HHHADHA )D!AFOLLHL[L]A\A]A^A_@AWAVAUIATIUSH(HeHHD$ 1Ht HHLBHHHHT$HH $HL$LHT$D4H;BHHBHAD!DH߉LLHHD$ eH+uH(LL[]A\A]A^A_ff.AWAVIAUATUHSH(HeHHD$ 1Ht HHHHLcD$ H HD$LH0HD$FdMiVUUUL$I A)EkHkT$T$HAuAauHH#G AcELAdLAnDHPAhf HH#CIdžLEA|$AHH@HLA(X1HA(H[]A\A]A^A_IuHtHvH1AƆaHD$HA|$EH3EGAHtHvHDEOAf AAH;AUIHLAXcSuX{1ABD8CIdžHIdžIdž`|HS1|$tS|$HH3HHDIHLDEGAHtHvPH1t$YIdžLIdžIdžIdž]LL L(SYC 0f #IdžIdžIdžIdž`HH#CjH*@LL$I}@HH@LD$D$tL$1I>Hf tC EHHHDIWLHHHEI/I.Ht HHEIH[A@HLLAHfPIdž HCIdž(IIdž8Idž0AIdžXfPwC<A^DHDL$DL$R1HAHH;PHQIHNLRHHDED$AAH;EO=AUAWAI8HHHHIIII`f 5JL8Hxf OC 0AK{AGAzAGqIdžAEAH`HH;HtHHoPHuH/HHHH QC ErIdžpAIdžIdžIdžIdž`LHLH@HHHH_AGAIAG@AEAHIdžIdžIdžIdž`Hf f u { LDHHHHf f A~YIdžIdžIdžIdžIdž`AGAG=IdžIdžIdžIdž`f ;eA~IdžIdžIdžIdžIdž`#HH#SIdž`/DED$A1IdžIdžIdžIdž`IdžIdžIdžIdžIdž`LIdžIdžIdžIdžIdž`?Lf fC 7IdžIdžIdžIdž`drm_WARN_ON(!pll)%s %s: [drm] %sMissing case (%s == %ld) drm_WARN_ON(n_entries < 1)crtc_state->pipe_bpppipeenableddisabledport_clock[ENCODER:%d:%s] [CRTC:%d:%s] drm_WARN_ON(ret)disablepll->info->ididclockpin_assignmenttmp & (7 << 12)drm_WARN_ON_ONCE(!trans)drm_WARN_ON(ctl & (1 << 9))drm_WARN_ON(!wakeref)Using signal levels %08x drm_WARN_ON(is_mst)Retry FEC enabling tmpdrm_WARN_ON(!pll_active)valencoder->portTC (TC)non-legacyyeslegacynoportPort %c strap not detected Port %c already claimed VBT says port %c has lspcon DDI %c/PHY %cDDI %s%c/PHY %s%cDDI %c%s/PHY %s%c&dig_port->hdcp.mutexdrm_WARN_ON(port > PORT_I)drivers/gpu/drm/i915/display/intel_ddi.cconn_state->connector->connector_typedrm_WARN_ON(n_entries > (sizeof(index_to_dp_signal_levels) / sizeof((index_to_dp_signal_levels)[0]) + ((int)sizeof(struct {_Static_assert(!(!(!__builtin_types_compatible_p(typeof((index_to_dp_signal_levels)), typeof(&(index_to_dp_signal_levels)[0])))), "must be array");}))))drm_WARN_ON(master == INVALID_TRANSCODER)drm_WARN_ON(dig_port->aux_wakeref)drm_WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))drm_WARN_ON(dig_port->ddi_io_wakeref)[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs Failed to set FEC_READY to %s in the sink Failed to clear FEC detected flags drm_WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))[drm] *ERROR* [CONNECTOR:%d:%s] Failed to read TMDS config: %d drm_WARN_ON(!dig_port->dp.attached_connector)[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio Failed to %s MSA_TIMING_PAR_IGNORE in the sink [drm] *ERROR* Timeout waiting for DDI BUF %c to get active [drm] *ERROR* Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c drm_WARN_ON((pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))drm_WARN_ON(!intel_tc_port_in_legacy_mode(dig_port))No pipe for [ENCODER:%d:%s] found Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x) Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b %02x) [drm] *ERROR* [ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x) [drm] *ERROR* Timeout waiting for DDI BUF %c to get idle drm_WARN_ON(transcoder_is_dsi(cpu_transcoder))drm_WARN_ON(crtc_state->limited_color_range && crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)Quirk Increase DDI disabled time drm_WARN_ON(ddi_mode == (3 << 24))%s %s: [drm] Unsupported voltage swing/pre-emphasis level: 0x%x drm_WARN_ON_ONCE(level >= n_entries)[drm] *ERROR* Invalid I_boost value %u drm_WARN_ON(((&_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display))->info.__runtime_info)->step) == STEP_NONE)drm_WARN_ON(port_mask & ((((1UL))) << (other_encoder->port)))[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it [drm] *ERROR* Timed out waiting for DP idle patterns drm_WARN_ON(dp_tp_ctl & ((u32)(((int)sizeof(struct {_Static_assert(!(__builtin_choose_expr((sizeof(int) == sizeof(*(8 ? ((void *)((long)((31) >= (sizeof(u32) * 8)) * 0l)) : (int *)8))), (31) >= (sizeof(u32) * 8), false)), "const_true((31) >= BITS_PER_TYPE(u32))" " is true");})) + ((((1ULL))) << (31)))))[drm] *ERROR* Timed out waiting for ACT sent [drm] *ERROR* Timeout waiting for FEC live state to get %s Failed waiting for FEC %s to get detected: %d (status %d) [drm] *ERROR* Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c [drm] *ERROR* Failed to enable FEC after retries drm_WARN_ON(crtc_state->has_pch_encoder)drm_WARN_ON(is_mst && (port == PORT_A || port == PORT_E))drm_WARN_ON(is_mst && port == PORT_A)[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio drm_WARN_ON(port < PORT_A || port > PORT_E)drm_WARN_ON(!(intel_ddi_splitter_pipe_mask(display) & ((((1UL))) << (pipe))))%s %s: [drm] Invalid splitter configuration, dss1=0x%08x drm_WARN_ON(crtc_state->master_transcoder != INVALID_TRANSCODER && crtc_state->sync_mode_slaves_mask)%s %s: [drm] Platform does not support DSI PORT %c / PHY %c reserved by HTI VBT says port %c is not DVI/HDMI/DP compatible, respect it SNPS PHY %c failed to calibrate, proceeding anyway Forcing DDI_A_4_LANES for port A VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s  J l n  ' W    B  `      ! 2   l @     :          Q  q y  S @   T Q e D  J  v          `@   i915.import_ns=PWMGCC: (Debian 12.2.0-14+deb12u1) 12.2.0GNU &0m7|P@Ln"h ( DW|3R0%np c   ` , ` ')BP` YP6i |$={X0{s{P !!"#P$2%H%^&z'm@(p)[* -. /509JP1%b3uP5`7@8P:'<1>B->OYev ^PePjto;!w@x_{.}@|P}.``  ) : BTm``=Pp0g, ) < ,P @(` h     % 8 I [ i        ' ; R t       & B V h        . @ V p        *Fey(>Pc{pbu 2EY,n|-IGw`@H{@JK0M3KbMOOJ: R9UpSv`U0VnVC.@0tVktu0u@wq +?Vvi0&7Zm~ (:M^x*Fb|(Kq0I`,ASp%A_}0'@:0R`ay9KZq+Kay * K ^       !+!C!V!v!!!intel_ddi.cintel_ddi_dp_preemph_maxdp_tp_status_regicl_ddi_tc_port_pll_typeintel_ddi_compute_output_typeintel_ddi_dp_voltage_maxindex_to_dp_signal_levelsintel_ddi_transcoder_func_reg_val_getintel_ddi_tc_encoder_shutdown_completeintel_ddi_tc_encoder_suspend_completeintel_ddi_main_link_aux_domainmain_link_aux_power_domain_getintel_ddi_get_power_domainsintel_ddi_encoder_shutdownintel_ddi_encoder_suspendintel_ddi_initial_fastset_checkintel_ddi_sync_stateintel_dp_sink_set_fec_readyintel_ddi_post_pll_disableintel_ddi_init_dp_buf_regintel_ddi_power_up_lanesintel_ddi_compute_config_lateintel_ddi_encoder_late_registerintel_ddi_hotplugintel_ddi_link_checkintel_ddi_encoder_destroyintel_ddi_encoder_resetintel_ddi_disableintel_ddi_buf_status_reg.isra.0skl_ddi_is_clock_enabledrkl_ddi_is_clock_enabledlpt_digital_port_connectedhsw_digital_port_connectedbdw_digital_port_connecteddg1_ddi_is_clock_enabledicl_ddi_combo_is_clock_enabledjsl_ddi_tc_is_clock_enabledadls_ddi_is_clock_enabledintel_ddi_config_transcoder_dp2skl_ddi_disable_clockrkl_ddi_disable_clockdg1_ddi_disable_clockicl_ddi_combo_disable_clockjsl_ddi_tc_disable_clockadls_ddi_disable_clockintel_ddi_buf_enableicl_ddi_tc_disable_clockCSWTCH.345intel_ddi_mso_configureicl_ddi_tc_is_clock_enabledbdw_transcoder_master_readoutskl_ddi_enable_clockicl_ddi_tc_enable_clockmtl_ddi_enable_d2dicl_ddi_combo_enable_clockjsl_ddi_tc_enable_clockrkl_ddi_enable_clockadls_ddi_enable_clockdg1_ddi_enable_clockicl_program_mg_dp_modeintel_ddi_get_encoder_pipes__already_done.11__already_done.5__already_done.4hsw_set_signal_levels__already_done.9icl_mg_phy_set_signal_levels__already_done.7tgl_dkl_phy_set_signal_levels__already_done.6icl_ddi_combo_vswing_program__already_done.8icl_combo_phy_set_signal_levelsintel_ddi_read_func_ctl_dp_mstintel_ddi_read_func_ctl_dp_sstintel_ddi_set_idle_link_trainintel_ddi_set_link_trainintel_ddi_prepare_link_retrainmtl_ddi_prepare_link_retrainintel_ddi_buf_disableintel_ddi_post_disableintel_ddi_enable_fecintel_ddi_pre_enableintel_ddi_enabletrans.0__already_done.10intel_ddi_pre_pll_enableintel_ddi_get_configicl_ddi_tc_get_configdg2_ddi_get_configmtl_ddi_get_configintel_ddi_compute_configskl_ddi_get_configbxt_ddi_get_configicl_ddi_combo_get_configdg1_ddi_get_configrkl_ddi_get_configadls_ddi_get_configintel_ddi_funcs__key.1__UNIQUE_ID___addressable___SCK__preempt_schedule872.2__UNIQUE_ID___addressable___SCK__preempt_schedule846.3__UNIQUE_ID_modinfo647__UNIQUE_ID___addressable___SCK__might_resched2.12.LC2__x86_return_thunk__drm_to_displaydev_driver_string__warn_printk__ref_stack_chk_guard__x86_indirect_thunk_rax__stack_chk_failintel_dp_is_uhbrintel_tc_port_cleanupintel_encoder_link_check_flush_workintel_tc_port_suspendintel_psr_needs_aux_io_powerintel_encoder_is_tcintel_aux_power_domainintel_display_power_aux_io_domainintel_display_power_getintel_tc_port_in_tbt_alt_modeintel_dp_encoder_shutdownintel_hdmi_encoder_shutdownintel_dp_encoder_suspend__drm_dev_dbgintel_dp_initial_fastset_checkintel_tc_port_sanitize_modeintel_dp_sync_statedrm_dp_dpcd_writeintel_display_power_put_uncheckedintel_tc_port_put_linkintel_dp_link_symbol_sizeintel_encoder_is_combointel_encoder_to_phyintel_combo_phy_power_up_lanesdrm_mode_matchintel_tc_port_link_resetintel_dp_test_phyintel_encoder_hotplugintel_dp_check_link_state_intel_modeset_lock_begin_intel_modeset_lock_loop_intel_modeset_lock_enddrm_modeset_locktry_wait_for_completiondrm_scdc_readintel_modeset_commit_pipes_dev_errintel_dp_link_checkintel_dp_encoder_flush_workintel_display_power_flush_workdrm_encoder_cleanupkfreeintel_dp_invalidate_source_ouiintel_pps_encoder_resetintel_tc_port_init_modeintel_tc_port_link_cancel_reset_workintel_hdcp_disableintel_hdmi_handle_sink_scramblingintel_panel_unprepareintel_psr_disableintel_alpm_disableintel_edp_backlight_offintel_dp_sink_disable_decompressionhsw_ddi_disable_clockintel_dmc_wl_getto_intel_uncoreintel_dmc_wl_puthsw_ddi_is_clock_enabledmutex_lockmutex_unlock__intel_wait_for_registerusleep_range_stateintel_encoder_to_tchsw_ddi_enable_clockktime_get_raw__SCT__might_reschedintel_dkl_phy_readintel_tc_port_get_pin_assignment_maskintel_dkl_phy_writeintel_tc_port_in_legacy_modeintel_display_power_get_if_enabled__sw_hweight32intel_dp_mst_active_streamsintel_ddi_get_hw_statehsw_prepare_dp_ddi_buffersintel_bios_dp_boost_levelintel_wait_ddi_buf_idle__const_udelayintel_ddi_set_dp_msaintel_dp_needs_vsc_sdpintel_ddi_update_pipeintel_hdmi_fastset_infoframesintel_hdcp_update_pipeintel_dp_set_infoframesintel_backlight_updatedrm_connector_update_privacy_screenintel_ddi_enable_transcoder_funcintel_ddi_config_transcoder_funcintel_ddi_disable_transcoder_funcintel_dp_mst_is_slave_transintel_has_quirkmsleepintel_dp_mst_is_master_transintel_ddi_toggle_hdcp_bitsintel_ddi_connector_get_hw_stateintel_ddi_enable_transcoder_clockintel_ddi_disable_transcoder_clockintel_ddi_levelintel_bios_hdmi_level_shiftintel_bios_hdmi_boost_level__x86_indirect_thunk_r11intel_dkl_phy_rmwis_hobl_buf_transicl_ddi_combo_get_pllintel_get_dpll_by_idintel_ddi_enable_clockintel_ddi_disable_clockintel_ddi_sanitize_encoder_pll_mappingdp_tp_ctl_regintel_cpu_transcoder_get_m1_n1intel_hdmi_infoframes_enabledintel_cpu_transcoder_get_m2_n2intel_lspcon_activeintel_dp_has_hdmi_sinkintel_lspcon_infoframes_enabledintel_tc_port_in_dp_alt_modeintel_alpm_port_configureintel_lnl_mac_transmit_lfpsintel_ddi_clear_act_sentintel_ddi_wait_for_act_sentintel_ddi_wait_for_fec_statusktime_getdrm_dp_dpcd_readintel_dp_dual_mode_set_tmds_outputintel_dp_set_powerintel_pps_vdd_onintel_pps_offintel_crtc_for_pipe_intel_modeset_primary_pipes_intel_modeset_secondary_pipesintel_crtc_vblank_offintel_disable_transcoderintel_vrr_transcoder_disableintel_dsc_disableskl_scaler_disableilk_pfit_disabledrm_dp_dpcd_write_payloaddrm_dp_dpcd_poll_act_handledintel_set_cpu_fifo_underrun_reportingintel_psr_panel_replay_enable_sinkintel_dp_set_link_paramsintel_pps_onintel_dp_configure_protocol_converterintel_dp_check_frl_trainingintel_dp_pcon_dsc_configureintel_dp_start_link_trainis_trans_port_sync_modeintel_dp_128b132b_sdp_crc16intel_dsc_dp_pps_writeintel_dp_lttpr_transparent_mode_enableddrm_dp_lttpr_wake_timeout_setupintel_dp_stop_link_trainintel_dp_sink_enable_decompressionintel_dp_queue_modeset_retry_for_linkintel_vrr_transcoder_enableintel_enable_transcoderintel_crtc_vblank_onintel_hdcp_enableintel_edp_backlight_onintel_panel_prepareintel_ddi_update_active_dpllintel_crtc_joined_pipe_maskintel_dpll_update_activeintel_tc_port_get_linkintel_tc_port_set_fia_lane_countbxt_dpio_phy_set_lane_optim_maskintel_ddi_compute_min_voltage_levelintel_display_power_is_enabledintel_crtc_dotclockintel_hdmi_read_gcp_infoframeintel_read_infoframeintel_psr_get_configintel_read_dp_sdpintel_audio_codec_get_configintel_edp_fixup_vbt_bppbxt_dpio_phy_get_lane_lat_optim_maskintel_dpll_get_hw_stateicl_set_active_port_dpllintel_dpll_get_freqicl_tc_port_to_pll_idintel_mpllb_readout_hw_stateintel_mpllb_calc_port_clockintel_cx0pll_readout_hw_stateintel_mtl_tbt_calc_port_clockintel_cx0pll_calc_port_clockintel_hdmi_compute_has_hdmi_sinkintel_hdmi_compute_configbxt_dpio_phy_calc_lane_lat_optim_maskintel_dp_compute_configintel_ddi_get_clockhsw_ddi_get_configintel_ddi_port_pll_typeintel_ddi_initintel_bios_encoder_portassert_port_validintel_bios_encoder_supports_dsiintel_port_to_phyintel_hti_uses_phyicl_dsi_initintel_bios_encoder_supports_dviintel_bios_encoder_supports_dpintel_bios_encoder_is_lspconintel_phy_is_snpskmalloc_caches__kmalloc_cache_noprofintel_port_to_tcdrm_encoder_initintel_encoder_link_check_init__mutex_initintel_audio_codec_enableintel_audio_codec_disableintel_display_power_ddi_lanes_domainintel_mtl_pll_enableintel_cx0_phy_set_signal_levelsintel_mtl_pll_disableintel_mtl_port_pll_typeintel_ddi_buf_trans_initintel_bios_encoder_lane_reversalintel_dp_aux_chintel_display_power_ddi_io_domainintel_infoframe_initintel_connector_allocintel_hdmi_init_connectorintel_bios_encoder_supports_hdmiintel_mpllb_enableintel_snps_phy_set_signal_levelsintel_mpllb_disableintel_bios_encoder_supports_typec_usbintel_tc_port_lockintel_tc_port_unlockintel_tc_port_initbxt_dpio_phy_set_signal_levelsintel_tc_port_connectedintel_dp_init_connectorintel_dp_hpd_pulseintel_bios_encoder_supports_tbtintel_hpd_pin_default__SCK__preempt_schedule__SCK__might_reschedArrs   tp 0w "|turv jhuPsW <a its X twr~x  W "t> lH "Mtoxs p tzzzr|8}rs  tLrss  t. s5 ? G t , r= }] 8l   } ~ u r u  * u7 W q^ yr x~  w r  }z r?}Sf}xC M "Rtr pr rK:\nu} uNYxrRgVs  t  AsM T \ttwrs  X tir}y3;C}ur$Nu_ r2Duu  wrvr#+BvOrv'r2AIbvrrvGrhpvr  v( i rt    v &!u:!rK!!!!v!!u!w "r%"-"D"vR""u"r"#%#;#vH#[#uq#w#r##$v$xi$r$$$$v$v$)%r;%F%S%[%w%v%v%%r%&$&-&F&vv&v&&u&r&)'6'>'Z'vx'v''u'w'r'((vZ(un(r(((()v)v&)3)uN)w)r)))v))))v**rE*M*l*y** *r++A+I+e+v+v+++++v*,rT, je,m,,v, , ",t,s, , ,t8-r---v-v).r4.P.X.o.v|....v.P/Y/o/v{////v/ 0rJ0s0|00v0v01s1 1 !1tn1r1111v 22/272S2vs2v22 2 "2t3 3 "3t;3sB3 L3 T3t3r334v14v<4A4M4m4r4444v4 5 @o5u5r5566$6vP6v]6j6r66v6v66u6s7 7 7t)7uC7w|7r777v78s8 8 8t_8us8r88889v79vD9Q9Y9u9v9v99u9s9 : :t:u4:wo:u:r:=;G;S;m;v;v;;;;v;v;;u.<s5< ?< G<tY<us<w<r<#=-=6=O=v=v====v=v=4>s;> E> M>t>s> > >t?r?6?}B?u????@2@E@e@@@@v@AA1Av@AeAmAAvAAAAvA B B "BtBBsIB SB [BtBrBBBCvCCCCCvD DD @DD E %EtE|EEvEE E "Et FF+Fv8FgF lFFF hFTGGuHu#Hw_HusHrHvII+Iv8ILITInIvyIIuIImImJs J J Jt*JwnJvJJJJ X#KrKKKKv L W'L ",LtnLsuL L LtLsL L MtYMMMMMMrXN`NzNvNNNNvOrfOoOOvOrP'P=PvJPPPPvPPP Q 0QZQQQQvQQsQ Q QtERrWRRRRvRvRR#Ss*S /4S ggg%h@hmIhmihsph zh hthuKiiisi i jt.jwnjujrjjvkLkTkmkvkvkkkkvk0l8lZlvdlullllv#mv-mSmmmmv#nv.nZnnnnvovo%oupomyomoso o otowpupr~F~Z~ve~~x~~r~ #0Ws^ ( h ptrv.;C]vhsvvԀr xxvvˁvxɂsЂ ( ڂ tr4<Wvrރ ` Pudrބr'CYvu߅ y5  :R qu q  Ȇ  ׆ qw q  ( q/  ;rćvv rIQkvvȈ͈ vErfrzvvƉ҉ډvNm  rv̊v֊ervvNrٌvZc|vvx7@[vzvr@NemLYzܐxFOkvvr$19Svqv| sÒΒےvv&3BOWqvvГ ` ,rVrؔrVivƕѕv'2@ H rݖ drvʗJrИv?Qvs  ֙ ʚrs  t.6Rvvvv ' / Bfsm  w tÝ۝  x>Tfq Şݞ  x7hst  { t֟s & .t\sh o wts  turBJXhҡrNn 0 zrvCKgr£vͣvvפv&ur֥C -T{xxΧv2v<GUl}~Ө j 09Pv^{vѩvܩ ,v7v˪ vjsq  { t˫v۫&m3mRsY c kts  twrC}r}T}kyrrѯr  v.԰r ,v:ͱvJ lw!"""Ӳ"#$ $$kr&)rms @ t'Rs_ gts  ts  tݶrv,rǷvշr!s( 2 :t\ f "ktr() *T]tvԹ+  "ts ' /ty,-ɺ.ں/01rk12ʻ34Jrk(y)*sļ μ ּts  t^rzv۽5 ) ".trƾv־5ErXf5{ " t˿5r:CYvf5urS[tv5uwu#r.v5uw|9v O:|;s t  ( "-tDLevuvv <,=S ?@A B @$Cd3DvE   > j@F G  bH  @ ) P4 ? J U `  k  v I J    p 0K L! M, N7 OB QPvQ"rarR}S TMUtV xW@A E 0Q j@YF X Y Z `[     ,= K  V \a ]f^v} P5 & !  _)2Kv\  } ` rU! 8 P}K @|Z {l w |a bE    P$ j@)Fa m P:t @({ "   ^ $ 1cash xr zt 0 P5 & !  Pe o @8 %  E U 0` P$k v p} Yd < % P  P1 * .  `H P5S &^ !i  P1 * .  ` 0 P5 & !! 1 `7< 'G !R ] m `7x ' !   6q{qqq(qq1qqUq:yUy`y{{{H~Vqhq q  q   q q  q qI  q= ,qqq0qAqcquq(q.Pqou]qq"q5qEqUqaqqqqq7 q q!qh"ql#q$4$q$%&')(I)**q*+,,q--q.q.q/q051q2f3q4q56>7q*8q9/:q<n<q >e>q>q.?q@AOEFqHqIqJJqJ LLqpMNO(Q7QqSqUSqTqVVqVVq|WqkZZqaqhq>oqtttvtquvuqvqvvwqwqaxq*zq|*|q}~qe qͅq GqqޓqvLq8qʮq>q`qlq6%ȵqڻqqqAvHq2qi> 0 (08p@HpP X` ` h p xP  P @@`p @ ! !("0#8@$@%H%P&X'`0(h`)p*x,-.//@13@5P708@:<>pBG0H0JJ MMN O(R0`S8PU@ VHVPYX^`@eh@jpox ttt u0wwxz0|@}p PБРЬ Ю(p0P8P@HP X0``h px P " #(l08@HP5Xm`nhppqxv:QRTU (08@H P X ` h pK xL N O ?VWYZ`acd#$ &('0,8,@,H,P,X,`,h,p,x,0%1&1(1)12222233333!3X3Y3[3\3 6(70787@7H7P8X8`!8h"8p9x : :::<K<L<N<O<>Q>R>T>U>i>>>>>BB B(!B0"B8(B@_BH`BPbBXcB`EhEpExEEIJ J"J#JL0L1L3L4LRLLLLLLMMM M(Q0R8R@RHRPSX@S`AShCSpDSxU ? A B X o p r s ߹      3 4 6 7( 0 ڼ8 ۼ@ ݼH ޼P X ` h  p !x  2 3 5 6 w           1 2 4 5 G ~( 0 8  p pnp$(p04p<R@pHLpTXp` dplL ppxW|ppap$p,p,p&1p2p3pY3p7p8p : pL<p R>$p,>0p8B<pD`BHpPETp\ J`ph1LlptLxpMpRpASp=UpXpqXpXp]p*ephp jpopup!w p(u,p48p@DpLPpX\pd3hpp|tp|Špppppplppp?pppp4p ۼpp$3(p04p<@pH2LpTXpDBFB@HPP eef.symtab.strtab.shstrtab.rela.text.data.bss.rela__patchable_function_entries.rodata.str1.1.rodata.str1.8.rela.discard.annotate_insn.rela__bug_table.rela.altinstructions.altinstr_replacement.rela.rodata.rela.discard.addressable.data..once.modinfo.comment.note.GNU-stack.note.gnu.property @@>&6,6681@P S2b2pv^@ q@0! `@&  @p4` @r @4H@5H0( 8!q !`52