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p1LH6!HH;!HH!HAAH߉t$t$DppOH;HtHHoPHuH/HH=HATUS4HHHLJt7HHH8ǃ`uHHH[]A\HLJLLKHLHH;HtHLgPMuL'HH=HLHH[]A\@ATLUHLSHclHhHH HHxbH@uLCuEHHt6HHuIHtHv1HHHH H;hy[L]A\f.UHSHHLJHH߾KHH[]ff.ATUSHHuPHLLHKHu KHLH[]A\H?HtHHoPHuH/HH=HHuATAUHSHHLJHKH{HHxu E4tgHxf v!tHƃi[]A\HH#StVtHƃi[]A\HǃHKHHHdf uwH1Hfx weHHH߾HHH HH[]A\1HATUSiHuZHujHLLHKHu KH*LH[]A\ƃi[]A\H?HtHHoPHt#HH=HH^H/ff.U@SHfx wHH#CtHC=v$[]fC tHC=wܾ HH; HHHH  HH߾ []ff.USfx HwHH#Gt'HHC=vZH[]fG tH/HHuH1H3HHC=w HH; HHHH $HH߾ H[]A1\f.Hfx vuIHHH#GttH<$H<$HfG uHH<$3H<$HHff.fUSfx HwPHH#GufG uf[]H߾HtxtH[]H߾Htxu?tH/Ht;HuH1H8HH[]H[]1AWLAVAUIATILUSHHLI$HHDHHLHA$lE1IcHI$hHHL1HH HHLt7HHsAHHLHHLuAE9$lt[L]A\A]A^A_DUHSHtPLt +[]H}HtHH_PHuHHH=HH[]@UHSHtPLt +[]H}HtHH_PHuHHH=HH[]@UHSHtPLt +X[]H}HtHH_PHuHHH=HH/[]UHSpHtPLt +X[]H}HtHH_PHuHHH=HH5[]UHSHtP Lt +X[]H}HtHH_PHuHHH=HHA[]%s %s: [drm] %s?Missing case (%s == %ld) domainFailed to write to D_COMP Current CDCLKEnabling package C8+ %s %s: [drm] SPLL enabled [drm] *ERROR* SPLL enabled %s %s: [drm] WRPLL1 enabled [drm] *ERROR* WRPLL1 enabled %s %s: [drm] WRPLL2 enabled [drm] *ERROR* WRPLL2 enabled %s %s: [drm] Panel power on [drm] *ERROR* Panel power on %s %s: [drm] PCH GTC enabled %s %s: [drm] IRQs enabled [drm] *ERROR* IRQs enabled drm_WARN_ON(!power_well)Allowed DC state mask %02x enabledisableUpdating dbuf slices to 0x%x Initial PHY_CONTROL=0x%08x Disabling package C8+ enableddisabledRuntime power status: %s Use countPower well/domain%-25s %s %-25s %d %-23s %d DISPLAY_COREPIPE_APIPE_BPIPE_CPIPE_DPIPE_PANEL_FITTER_APIPE_PANEL_FITTER_BPIPE_PANEL_FITTER_CPIPE_PANEL_FITTER_DTRANSCODER_ATRANSCODER_BTRANSCODER_CTRANSCODER_DTRANSCODER_EDPTRANSCODER_DSI_ATRANSCODER_DSI_CTRANSCODER_VDSC_PW2PORT_DDI_LANES_APORT_DDI_LANES_BPORT_DDI_LANES_CPORT_DDI_LANES_DPORT_DDI_LANES_EPORT_DDI_LANES_FPORT_DDI_LANES_TC1PORT_DDI_LANES_TC2PORT_DDI_LANES_TC3PORT_DDI_LANES_TC4PORT_DDI_LANES_TC5PORT_DDI_LANES_TC6PORT_DDI_IO_APORT_DDI_IO_BPORT_DDI_IO_CPORT_DDI_IO_DPORT_DDI_IO_EPORT_DDI_IO_FPORT_DDI_IO_TC1PORT_DDI_IO_TC2PORT_DDI_IO_TC3PORT_DDI_IO_TC4PORT_DDI_IO_TC5PORT_DDI_IO_TC6PORT_DSIPORT_CRTPORT_OTHERVGAAUDIO_MMIOAUDIO_PLAYBACKAUX_IO_AAUX_IO_BAUX_IO_CAUX_IO_DAUX_IO_EAUX_IO_FAUX_AAUX_BAUX_CAUX_DAUX_EAUX_FAUX_USBC1AUX_USBC2AUX_USBC3AUX_USBC4AUX_USBC5AUX_USBC6AUX_TBT1AUX_TBT2AUX_TBT3AUX_TBT4AUX_TBT5AUX_TBT6GMBUSGT_IRQDC_OFFTC_COLD_OFFINITdrivers/gpu/drm/i915/display/intel_display_power.cdrm_WARN_ON(power_domains->async_put_wakeref)drm_WARN_ON(!queue_delayed_work(system_unbound_wq, &power_domains->async_put_work, msecs_to_jiffies(delay_ms)))%s %s: [drm] Use count on domain %s is already zero %s %s: [drm] Async disabling of domain %s is pending %s %s: [drm] ISP not power gated [drm] *ERROR* LCPLL not locked yet [drm] *ERROR* Switching back to LCPLL failed %s %s: [drm] CRTC for pipe %c enabled [drm] *ERROR* CRTC for pipe %c enabled %s %s: [drm] Display power well on [drm] *ERROR* Display power well on %s %s: [drm] CPU PWM1 enabled [drm] *ERROR* CPU PWM1 enabled %s %s: [drm] CPU PWM2 enabled [drm] *ERROR* CPU PWM2 enabled %s %s: [drm] PCH PWM1 enabled [drm] *ERROR* PCH PWM1 enabled %s %s: [drm] Utility pin enabled in PWM mode [drm] *ERROR* Utility pin enabled in PWM mode [drm] *ERROR* PCH GTC enabled [drm] *ERROR* Switching to FCLK failed [drm] *ERROR* LCPLL still locked [drm] *ERROR* D_COMP RCOMP still in progress drm_WARN_ON(power_domains->domain_use_count[domain] != 1)drm_WARN_ON(((__builtin_constant_p(domain) && __builtin_constant_p((uintptr_t)(power_domain_set->mask.bits) != (uintptr_t)((void *)0)) && (uintptr_t)(power_domain_set->mask.bits) != (uintptr_t)((void *)0) && __builtin_constant_p(*(const unsigned long *)(power_domain_set->mask.bits))) ? const_test_bit(domain, power_domain_set->mask.bits) : _test_bit(domain, power_domain_set->mask.bits)))drm_WARN_ON(!bitmap_subset(mask->bits, power_domain_set->mask.bits, POWER_DOMAIN_NUM))Adjusting requested max DC state (%d->%d) [drm] *ERROR* Unexpected value for enable_dc (%d) %s %s: [drm] Invalid set of dbuf slices (0x%x) requested (total dbuf slices 0x%x) %s %s: [drm] DBuf slice %d power %s timeout! drm_WARN_ON(((&(display)->info.__runtime_info)->step) == STEP_NONE)Unknown memory configuration; disabling address buddy logic. toggling display PHY side reset %s %s: [drm] VED not power gated [drm] *ERROR* CDCLK source is not LCPLL [drm] *ERROR* LCPLL is disabled [drm] *ERROR* LCPLL not using non-SSC reference drm_WARN_ON(power_domains->init_wakeref)drm_WARN_ON(power_domains->disable_wakeref)BIOS left unused %s power well enabled, disabling it drm_WARN_ON(!domains || domains->ddi_io == POWER_DOMAIN_INVALID)drm_WARN_ON(!domains || domains->ddi_lanes == POWER_DOMAIN_INVALID)drm_WARN_ON(!domains || domains->aux_io == POWER_DOMAIN_INVALID)drm_WARN_ON(!domains || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID)drm_WARN_ON(!domains || domains->aux_tbt == POWER_DOMAIN_INVALID)   k g              4 ^  {   : F _   u I ( w       8"/5L#L;A 28L/5L#L;A/5L17A/5L88i915.import_ns=PWMGCC: (Debian 12.2.0-14+deb12u1) 12.2.0GNU6@xW  ~ `j 2pa,C`xMxkH| $l`H w ` 3 'w6p(U`)Ak*`HHBq (08.@^HPX`hNp~x>n.^N~ > n   (  0  " ' , 1 H6 < B rH N T hZ ` xf Zl (r x ~         " 2 F ` q         3 > K ` p          / I R m        8`; *<XpT#Cb:  !!P":Mcr0%P%|,F]o37:Yrp;0<B<@=>/?P_@ApB +`CEPjDlElEmFmFm5Fintel_display_power.casync_put_domains_clear_domain__intel_display_power_is_enabledintel_display_power_grab_async_put_refqueue_async_put_domains_work__intel_display_power_put_domainCSWTCH.113release_async_put_domainsintel_display_power_put_async_work__intel_display_power_get_domain.part.0assert_isp_power_gatedisp_ids.0intel_port_domains_for_aux_chd11_port_domainsi9xx_port_domainsd13_port_domainsd12_port_domainsintel_port_domains_for_porthsw_write_dcompintel_pch_reset_handshakehsw_restore_lcpllhsw_enable_pc8bxt_display_core_uninit.part.0icl_display_core_uninit.part.0bxt_display_core_initicl_display_core_initwa_1409767108_buddy_page_maskstgl_buddy_page_masks__UNIQUE_ID_addressable___SCK__WARN_trap_864.3__UNIQUE_ID_addressable___SCK__WARN_trap_863.4__UNIQUE_ID_addressable___SCK__WARN_trap_862.5__UNIQUE_ID_addressable___SCK__WARN_trap_861.6__UNIQUE_ID_addressable___SCK__WARN_trap_860.7__UNIQUE_ID_addressable___SCK__WARN_trap_859.8__UNIQUE_ID_addressable___SCK__WARN_trap_858.9__UNIQUE_ID_addressable___SCK__WARN_trap_857.10__UNIQUE_ID_addressable___SCK__WARN_trap_856.11__UNIQUE_ID_addressable___SCK__WARN_trap_855.12__UNIQUE_ID_addressable___SCK__WARN_trap_854.13__UNIQUE_ID_addressable___SCK__WARN_trap_853.14__UNIQUE_ID_addressable___SCK__WARN_trap_852.15__UNIQUE_ID_addressable___SCK__WARN_trap_851.16__UNIQUE_ID_addressable___SCK__WARN_trap_850.17__UNIQUE_ID_addressable___SCK__WARN_trap_849.18__UNIQUE_ID_addressable___SCK__WARN_trap_848.19__UNIQUE_ID_addressable___SCK__WARN_trap_847.20__UNIQUE_ID_addressable___SCK__WARN_trap_846.21__UNIQUE_ID_addressable___SCK__WARN_trap_845.22__UNIQUE_ID_addressable___SCK__WARN_trap_844.23__UNIQUE_ID_addressable___SCK__WARN_trap_843.24__UNIQUE_ID_addressable___SCK__WARN_trap_842.25__UNIQUE_ID_addressable___SCK__WARN_trap_841.26__UNIQUE_ID_addressable___SCK__WARN_trap_840.27__UNIQUE_ID_addressable___SCK__WARN_trap_839.28__UNIQUE_ID_addressable___SCK__WARN_trap_838.29__UNIQUE_ID_addressable___SCK__WARN_trap_837.30__UNIQUE_ID_addressable___SCK__WARN_trap_836.31__UNIQUE_ID_addressable___SCK__WARN_trap_835.32__UNIQUE_ID_addressable___SCK__WARN_trap_831.33__UNIQUE_ID_addressable___SCK__WARN_trap_830.34__UNIQUE_ID_addressable___SCK__WARN_trap_829.35__UNIQUE_ID_addressable___SCK__WARN_trap_828.36__UNIQUE_ID_addressable___SCK__WARN_trap_827.37__UNIQUE_ID_addressable___SCK__WARN_trap_826.38__UNIQUE_ID_addressable___SCK__WARN_trap_825.39__UNIQUE_ID_addressable___SCK__WARN_trap_824.40__UNIQUE_ID_modinfo_791__UNIQUE_ID_addressable___SCK__might_resched_2.41.LC0.LC1.LC5.LC8.LC7.LC9.LC15.LC21.LC19.LC17.LC23.LC27.LC25.LC37.LC35.LC33.LC31.LC29.LC53.LC51.LC58__x86_return_thunkintel_display_rpm_suspendedintel_power_well_is_always_onintel_power_well_is_enabled_cached__ref_stack_chk_guard__bitmap_or_find_first_bitcancel_delayed_workintel_display_rpm_put_raw__stack_chk_fail__msecs_to_jiffiessystem_unbound_wqqueue_delayed_work_ondev_driver_string__SCT__WARN_trapintel_power_well_putintel_display_rpm_get_noresumeintel_display_rpm_putintel_display_rpm_get_rawmutex_lockmutex_unlockintel_power_well_getpci_dev_presentvlv_iosf_sb_getvlv_iosf_sb_readvlv_iosf_sb_putintel_pcode_write_timeout__drm_dev_dbgintel_dmc_wl_getto_intel_uncore__x86_indirect_thunk_raxintel_dmc_wl_putintel_uncore_forcewake_get__intel_wait_for_register_dev_errintel_uncore_forcewake_putintel_update_cdclkintel_cdclk_dump_configlpt_disable_clkout_dpintel_irqs_enabled__const_udelayktime_get__SCT__might_reschedusleep_range_stateintel_display_power_set_target_dc_statelookup_power_wellintel_power_well_is_enabledintel_power_well_enableintel_power_well_disableintel_display_power_get_current_dc_stateintel_display_power_getintel_display_rpm_getintel_display_power_get_if_enabledintel_display_rpm_get_if_in_use__intel_display_power_put_asyncintel_display_power_flush_workintel_display_power_put_uncheckedintel_display_rpm_put_uncheckedintel_display_power_get_in_setintel_display_power_get_in_set_if_enabledintel_display_power_put_mask_in_set__bitmap_subsetintel_power_domains_initmutex_init_genericdelayed_work_timer_fntimer_init_keyintel_display_power_map_initintel_power_domains_cleanupintel_display_power_map_cleanupgen9_dbuf_slices_updategen9_disable_dc_statesintel_cdclk_uninit_hwintel_pmdemand_program_dbufintel_dmc_disable_programintel_combo_phy_uninitgen9_set_dc_stateintel_cdclk_init_hwintel_enabled_dbuf_slices_maskintel_dmc_load_programintel_combo_phy_initintel_dram_infointel_snps_phy_wait_for_calibrationintel_power_domains_init_hwintel_power_well_sync_hwintel_power_domains_driver_removecancel_delayed_work_syncintel_power_domains_sanitize_stateintel_power_well_nameintel_power_domains_enableintel_power_domains_disableintel_power_domains_suspendintel_dmc_has_payloadintel_power_domains_resumeintel_display_power_suspend_latebxt_enable_dc9intel_display_power_resume_earlygen9_sanitize_dc_statebxt_disable_dc9intel_init_pch_refclkintel_clock_gating_initintel_display_power_suspendintel_display_power_resumegen9_enable_dc5skl_enable_dc6intel_display_power_debugseq_printfintel_power_well_refcountintel_power_well_domainsintel_display_power_ddi_io_domainintel_display_power_ddi_lanes_domainintel_display_power_aux_io_domainintel_display_power_legacy_aux_domainintel_display_power_tbt_aux_domain__SCK__WARN_trap__SCK__might_reschedK`abc2dNcdefgh"i)j=kmlw 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