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T$uFL$$1ب`uBD$A9u9HD$XeH+H`D[]A\A]A^A_L$迎$Ld$1HD$HD$LHH}HH@LLcHƃH}Ht$H|$HtHuHHH=wHpHtHH=wfH H|$HuH|$HAAtPLLtOHAH|$EtAuHLAŅH|HuHtHvIغ1AHNACAWAVAUATUSHHH@+H/IHHIHXH9D$IwE1HtL}MHL1LHHtILHLD$I,$HCHIHXH9tHHt݋n tE1 iL]IUD$D$H[]A\A]A^A_fD`AWAVAUATIUSHH/HHHXH9AA@E1IHAt8ADB)HHHHD!!A @udHI,$HCHHXH9Ht܋d tE1 _LSIKI?HtHfPIw!AGtAHt2HHZHMH[]A\A]A^A_AƇHHH$誌H$@AWAVAUATUSHH/T$HHH94IAHXHE1/IMHAA@4F)HHHHD!!AA!@urt$tXIEHtHfPwAGLHD$蒢HD$AGRA@HI,$HCHHXH9H[]A\A]A^A_ tE1 LIAG:MEMt LIAlsAFeAWA84H)HHHD!H$IEHtHLD$LD$1LLD$HD$5H|$@LD$@ApIxIfPA@ 0xf)drivers/gpu/drm/i915/display/intel_psr.cPSR2/Panel Replay not enabled, Unable to use long enough wake times PSR2/Panel Replay not enabled, too short vblank time %s VSC SDP uncorrectable error [drm] *ERROR* Timed out waiting PSR idle state drm_WARN_ON(transcoder_has_psr2(display, cpu_transcoder) && intel_de_read(display, ((const i915_reg_t){ .reg = ((_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display))->info.__device_info)->trans_offsets[(cpu_transcoder)] - (_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display))->info.__device_info)->trans_offsets[TRANSCODER_A] + ((_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display))->info.__device_info)->mmio_offset) + (0x60900)) })) & ((u32)(((int)sizeof(struct {_Static_assert(!(__builtin_choose_expr((sizeof(int) == sizeof(*(8 ? ((void *)((long)((31) >= (sizeof(u32) * 8)) * 0l)) : (int *)8))), (31) >= (sizeof(u32) * 8), false)), "const_true((31) >= BITS_PER_TYPE(u32))" " is true");})) + ((((1ULL))) << (31)))))drm_WARN_ON(intel_de_read(display, psr_ctl_reg(display, cpu_transcoder)) & ((u32)(((int)sizeof(struct {_Static_assert(!(__builtin_choose_expr((sizeof(int) == sizeof(*(8 ? ((void *)((long)((31) >= (sizeof(u32) * 8)) * 0l)) : (int *)8))), (31) >= (sizeof(u32) * 8), false)), "const_true((31) >= BITS_PER_TYPE(u32))" " is true");})) + ((((1ULL))) << (31)))))drm_WARN_ON(intel_dp->psr.active)drm_WARN_ON(((&_Generic((display), const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)((display))), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)((display))), const struct intel_display *: ((display)), struct intel_display *: ((display)))->info.__runtime_info)->step) == STEP_NONE)drm_WARN_ON(((&_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display))->info.__runtime_info)->step) == STEP_NONE)drm_WARN_ON(!(tmp & ((u32)(((int)sizeof(struct {_Static_assert(!(__builtin_choose_expr((sizeof(int) == sizeof(*(8 ? ((void *)((long)((31) >= (sizeof(u32) * 8)) * 0l)) : (int *)8))), (31) >= (sizeof(u32) * 8), false)), "const_true((31) >= BITS_PER_TYPE(u32))" " is true");})) + ((((1ULL))) << (31)))))), Panel Replay Selective Update = %sSource PSR/PanelReplay ctl: %s [0x%08x] Source PSR/PanelReplay status: %s [0x%08x] Busy frontbuffer bits: 0x%08x Last attempted entry at: %lld drm_WARN_ON(val & ((u32)(((int)sizeof(struct {_Static_assert(!(__builtin_choose_expr((sizeof(int) == sizeof(*(8 ? ((void *)((long)((31) >= (sizeof(u32) * 8)) * 0l)) : (int *)8))), (31) >= (sizeof(u32) * 8), false)), "const_true((31) >= BITS_PER_TYPE(u32))" " is true");})) + ((((1ULL))) << (31)))))drm_WARN_ON(!(val & ((u32)(((int)sizeof(struct {_Static_assert(!(__builtin_choose_expr((sizeof(int) == sizeof(*(8 ? ((void *)((long)((31) >= (sizeof(u32) * 8)) * 0l)) : (int *)8))), (31) >= (sizeof(u32) * 8), false)), "const_true((31) >= BITS_PER_TYPE(u32))" " is true");})) + ((((1ULL))) << (31))))))[drm] *ERROR* Timed out waiting for PSR Idle for re-enable [transcoder %s] PSR entry attempt in 2 vblanks [transcoder %s] PSR exit completed [drm] [transcoder %s] PSR aux error Panel doesn't support AUX-less ALPM, eDP Panel Replay not possible Panel doesn't support early transport, eDP Panel Replay not possible Panel replay %sis supported by panel eDP panel supports PSR version %x PSR support not currently available for this panel Panel lacks power state control, PSR cannot be enabled Unable to get sink synchronization latency, assuming 8 frames Unable to read selective update x granularity Unable to read selective update y granularity PSR sink implementation is not reliable PSR condition failed: Interlaced mode enabled Panel Replay disabled by flag Panel Replay not enabled because it would inhibit pipe CRC calculation Panel Replay is not supported with 128b/132b Panel Replay is not supported with HDCP PSR condition failed: Invalid PSR setup time (0x%02x) PSR condition failed: PSR setup time (%d us) too long PSR condition failed: PSR setup timing not met PSR2 sel fetch not enabled, disabled by parameter PSR2 sel fetch not enabled, async flip enabled Selective update not enabled, selective fetch not valid and no HW tracking available Selective update disabled by flag PSR2 is defeatured for this platform PSR2 not completely functional in this stepping PSR2 not supported in transcoder %s PSR2 cannot be enabled since DSC is enabled PSR2 not enabled, pipe bpp %d > max supported %d PSR2 not enabled, not compatible with HW stepping + VRR PSR2 not enabled, resolution %dx%d > max supported %dx%d Selective update not enabled, SDP indication do not fit in hblank Selective update not enabled because it would inhibit pipe CRC calculation Selective update not enabled, SU granularity not compatible PSR disabled to workaround PSR FSM hang issue drm_WARN_ON(!((intel_dp)->psr.sink_support && (intel_dp)->psr.source_support) && !((intel_dp)->psr.sink_panel_replay_support && (intel_dp)->psr.source_panel_replay_support))[drm] Unbalanced PSR pause/resume! [drm] Selective fetch area calculation failed in pipe %c drm_WARN_ON(crtc_state->psr2_su_area.y1 % 4 || crtc_state->psr2_su_area.y2 % 4)drm_WARN_ON(psr->enabled && !crtc_state->active_planes)drm_WARN_ON(intel_dp->psr.enabled)PSR interruption error set, not enabling PSR [drm] *ERROR* PSR wait timed out, atomic update may fail PSR condition failed: Port not supported [drm] *ERROR* Error reading PSR status or error status PSR sink internal error, disabling PSR PSR RFB storage error, disabling PSR PSR VSC SDP uncorrectable error, disabling PSR PSR Link CRC error, disabling PSR [drm] *ERROR* PSR_ERROR_STATUS unhandled errors %x [drm] *ERROR* Error reading DP_PSR_ESI Sink PSR capability changed, disabling PSR transition to active, capture and displayactive, capture and display on sink device timingstransition to inactive, capture and display, timing re-sync%s %s: [drm] %s%llu PANEL-REPLAYunknownPSRPSR/Panel-Replay Unsupported Sink %s status: 0x%x [%s] Sink %s error status: 0x%x: %s RFB storage error %s Link CRC error yesnodisabled enabledPanel Replay Selective UpdatePanel ReplayPSR2PSR1 (Early Transport)enabledSink support: PSR = %s [0x%02x], Panel Replay = %s PSR mode: %s%s%s PSR sink not reliable: %s PSR2_CTL: 0x%08x Performance counter: %u Last exit at: %lld Frame: PSR2 SU blocks: %d %d PSR2 selective fetch: %s 21Disabling Panel Replay Disabling PSR%s PSR exit events: 0x%x PSR2 watchdog timer expired PSR2 disabled SU dirty FIFO underrun SU CRC FIFO underrun Graphics reset PCH interrupt Memory up Front buffer modification PSR watchdog timer expired PIPE registers updated Register updated HDCP enabled KVMR session enabled VBI enabled LPSP mode exited PSR disabled selective_update not PSR2 %ssupported PSR disabled by flag PSR disabled due to joiner PSR setup entry frames %d PSR2 not supported by phy Enabling Panel Replay Enabling PSR%s Invalid debug mask %llx Setting PSR debug to %llx &intel_dp->psr.locki915_edp_psr_debugi915_edp_psr_statusi915_psr_sink_statusi915_psr_statusABCDEDPDSI ADSI Cinactiveactive, display from RFBreservedsink internal errorIDLESRDONACKSRDENTBUFOFFBUFONAUXACKSRDOFFACKSRDENT_ONCAPTURECAPTURE_FSSLEEPBUFON_FWML_UPSU_STANDBYFAST_SLEEPDEEP_SLEEPBUF_ONTG_ONy  I      D $ ) 8 ;  }            i915.import_ns=PWMGCC: (Debian 12.2.0-14+deb12u1) 12.2.0GNU -E`Wpkj0 "[P|*.@1E@@S`npqu@ k 9  v) < BS@aXo0#~ (,/8`1@F] !/IW->G` !5Gm.202-p8o7U<hxp=yL N,=VOfOwP R  & 6 Q q  S  S pV    7 W bzz 0d f      - w&L  zo` y       9 K b {     }    3 B O e z W k  ` 0   ?VZs/ 3Nintel_psr.cpsr_get_status_and_error_statuspsr_compute_idle_framesalpm_config_validis_dc5_dc6_blockedi915_edp_psr_status_openi915_edp_psr_status_showi915_psr_status_openi915_psr_status_showi915_psr_sink_status_openi915_psr_sink_status_showi915_edp_psr_debug_fops_openi915_edp_psr_debug_seti915_edp_psr_debug_getsink_status.0intel_psr_wait_exit_lockedintel_psr_force_updatepsr2_program_idle_framesintel_psr_apply_underrun_on_idle_wa_lockedtgl_dc3co_disable_workpsr_irq_controlintel_psr_configure_full_frame_updatewm_optimization_waintel_psr_activatemap.5intel_psr_statuslive_status.1live_status.2intel_psr_exitintel_psr_disable_lockedintel_psr_workpsr_dc5_dc6_wa_workCSWTCH.250__print_once.6aux_msg.4__key.3i915_edp_psr_debug_fopsi915_edp_psr_status_fopsi915_psr_sink_status_fopsi915_psr_status_fops__UNIQUE_ID_modinfo553__UNIQUE_ID___addressable___SCK__tp_func_i915_reg_rw548.7__UNIQUE_ID___addressable___SCK__preempt_schedule_notrace29.8.LC2drm_dp_dpcd_read__x86_return_thunk__drm_to_displaydev_driver_string__warn_printkintel_alpm_compute_params__drm_dev_dbgintel_display_power_get_current_dc_statesingle_opensimple_attr_open__ref_stack_chk_guardseq_printfseq_putcseq_write__stack_chk_failintel_dp_is_edpintel_dmc_wl_getto_intel_uncore__intel_wait_for_registerintel_dmc_wl_put_dev_err__x86_indirect_thunk_raxintel_dmc_start_pkgc_exit_at_start_of_undelayed_vblankmutex_lockmutex_unlockintel_display_power_set_target_dc_stateintel_dp_source_supports_tps3intel_display_rpm_getintel_display_rpm_putcancel_delayed_workdrm_dp_dpcd_writeintel_snps_phy_update_psr_power_stateintel_dmc_block_pkgcintel_alpm_disableintel_encoder_can_psrintel_psr_needs_aux_io_powerintel_psr_irq_handlerktime_get_dev_warnqueue_work_onintel_psr_init_dpcdintel_alpm_aux_less_wake_supportedintel_alpm_aux_wake_supportedintel_psr_panel_replay_enable_sinkintel_psr_compute_configdrm_dp_psr_setup_timeintel_usecs_to_scanlinesintel_calc_active_pipesintel_dp_is_uhbrintel_psr_get_configintel_hdmi_infoframe_enableintel_psr_disablecancel_work_synccancel_delayed_work_syncintel_psr_pauseintel_psr_resumeintel_psr_needs_vblank_notificationintel_psr_trigger_frame_change_eventintel_pre_commit_crtc_stateintel_dsb_reg_write__tracepoint_i915_reg_rwcpu_number__cpu_online_mask__preempt_count__SCT__tp_func_i915_reg_rw__SCT__preempt_schedule_notraceintel_psr_min_vblank_delayintel_vrr_possibleintel_psr2_program_trans_man_trk_ctlintel_psr2_sel_fetch_updatedrm_atomic_add_affected_planesdrm_rect_intersect_dev_infodrm_atomic_get_plane_statedrm_atomic_helper_damage_mergedintel_psr2_panic_force_full_updateintel_psr_pre_plane_updateintel_psr_post_plane_update__usecs_to_jiffiesintel_alpm_enable_sinkintel_alpm_configuredrm_mode_vrefresh__x86_indirect_thunk_r11intel_dp_aux_packintel_psr_wait_for_idle_lockedintel_psr_debug_setmutex_lock_interruptibledrm_atomic_state_allocdrm_modeset_acquire_initdrm_connector_list_iter_begindrm_connector_list_iter_nextdrm_atomic_get_connector_statedrm_atomic_get_crtc_statedrm_connector_list_iter_enddrm_atomic_commitdrm_modeset_drop_locksdrm_modeset_acquire_finirefcount_warn_saturatedrm_atomic_state_cleardrm_modeset_backoff__drm_atomic_state_freeintel_psr_invalidateintel_psr_flushmod_delayed_work_onintel_psr_initdelayed_work_timer_fntimer_init_key__mutex_initintel_psr_short_pulseintel_alpm_get_errorintel_psr_enabledintel_psr_link_okintel_psr_lockintel_psr_unlockintel_psr_notify_dc5_dc6system_wqintel_psr_dc5_dc6_wa_initintel_psr_notify_pipe_changeintel_psr_notify_vblank_enable_disableintel_psr_debugfs_registerdebugfs_create_file_fullintel_psr_connector_debugfs_addintel_psr_needs_alpmintel_psr_needs_alpm_aux_lessseq_lseekseq_readsingle_releasegeneric_file_llseeksimple_attr_readsimple_attr_writesimple_attr_release__SCK__tp_func_i915_reg_rw__SCK__preempt_schedule_notraceD3m356 & .758 P95 '95: 0- "]   | @1=6 R -@b +i #t M|>  + # h>?  + #  >) 9 +@ #K S>j z + # >= /@ @LAw5BCDEF* 5CDH5GCPDiHH5T Jv 5 L 5 5] 5 C D H H? 5u 5' 5 C D H C D) == 5 C D H H =FCNDjHA5?CHD_HmF5g5JCSDlHwFCDHFCD4H?FQ55MsC|DHHF#I55GBCDHFCDH2H=FZCcD}HHFCD HF@6G (Q Y7 -  - CD.H=Fh6o  y 76  76   76 `  7:6A K S76  7=5    (>F W a <j>  > P>NJ    # * R3>CDHF    >5+BtC|DHF - 0 > ` >CD6HDFN \>CDHF? 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