ELF>@@@#"HvHff.S11HHHH1H[ff.SHHHH[f.UHSHeHHD$1HT$D$uV|$tOHT$1HD$D$ HT$ Hu7D$ 9D$u-uոHT$eH+uH[]ff.SHHeHHD$1D$t#GsHD$eH+u>H[HT$=D$CstHT$<HD$ff.@AWAVAUAATIUHSH HeHHD$1HT$D$D$IH?HD$ I?HD$HIHIHT$D|$T$LI!H!IH<txL9s&HD$eH+H []A\A]A^A_D$HT$LL|$ID$H}IDHD$EtHLH110HfT$HT$fD$2HHT$D$HI D$HH 9fDATA1UH SHH eHHD$1fT$1HT$fD$HD$HD$"HHT$L$D$HHHH%H9sHD$eH+uUH []A\HHT$HHT$HD$HMH{EtHHHAVAUA1ATI$UHSH(eHHD$ 1fT$1HT$fD$HD$HD$&HHT$D$\$IHIHAftsL9rJL$LLt$HȃHH ""HEHH\$IT$H}HT$Eu{HD$ eH+H([]A\A]A^HT$(HD$D$ ,HHT$ T$D$ 9IH H I H 6HLHjDSH(HHtHHH[fDU1ҾSHHHo8eHHD$1fT$1HT$HfD$2HHT$D$"T$ ЈHD$eH+u H[]ff.@HeHHD$1HT$1fD$D$fHT$eH+u Hf.U1ҹSHHXeHHD$P1Hl$fT$HT$HD$D$D$ HHD$HHHD$(HHL$HHD$HHEHHT$f|$HHHH{<tAHT$$HD$HHHD$PeH+HX[]HHHT$1ҾHf|$I-$H$HHT$1Ҿ$HD$_7HT$(H(H(HHT$ T$(HD$ ff.fAT IHUS1HeHH$1HHHI$؉LHHTujIAhHHXZH$eH+uH[]A\DUH8SHHHHHHHHXH{ H[]HHHH[]HHAVAUATUSHH.=AtsHL=H߽KqHAƃEEHLH[]A\A]A^CtKquHCHx8Hdt$t$9OMH'9tXHOHLHHLHLff.nt=vx1ATIUSHHXeHHD$P1HH[Ht9HE8HtHHtI$0HD$PeH+ufHX[]A\HHHuHHHuHHPHtH|$Hع HHH$HSHǀ HHtPHHfHHHHHǃHHǃH[fUHHSHt,Hh@HHHHHt H1H[]fnttGtt 1Gq:s1H= HtEHPHH@HPHP HP(HP(HP0HP@HP@HPHHPpHPpHPxfff.UHH=8S HHtYHHHCHǀ H`HC1HHǃhHǃpǃǃH[]fDUSHHH8eHHD$1D$Ht5nt/Hl$t9vHHHHHD$eH+u_H[]GqD$tGttD$Hl$HHHH{8ntsff.AVAUATUSHeHHD$1D$~YHc)IHL4AAlHT$LLHډLT$LHI9uHD$eH+uH[]A\A]A^AWAHAVAUMATAUHSHH@eHHD$81HD$HD$H)HD$ HHD$(HD$0IHHuHHEHT$DHAE1҃HD‹T$փE?HUtHHUAǸAtJIAt$HT$HL$HL$D$HL$L$H H AEH I HL MLH!3HHH!I9HH{HDHHT$HL$HD$ H{HHt$(HL$H9L$(H}HHLHHEHHT$8eH+EH@[]A\A]A^A_хHHIǸH}MHE1D$EuW1ɁHIǸH}HrH H!H9HLHHEHU1,HD$ HM LHHEHH)HE։HA"ADEփ>HAIH}fDHAUHHHATHIUSH_8LHEL1LHH`1ID$XHI|$8ID$`H ID$hIt$PIt$XI|$81WIt$`I|$81Fu)@H{tHLHHLI|$HHuŃv[]A\A]ff.AT1ҾUSHHeHHD$1f$D$DEu HD$eH+\H[]A\CnAt$HH,$fktHShAt$HCqShH߾  HT$CqD$tHCHxcH@8HVtAH@t5HHCt$fCt@tPHHHCt$fCt1HT$HfD$D$1ҾHff.fSHHeHHD$1HT$D$D$@tHD$eH+u H[fSHeHHD$1HGD$uRHDKDHDcDAXAt $11HT$ft$f|$ HDl$HfAAHHT$ T$HfD9l$ KI Ј3$HHHT$8eH+#H@[]A\A]A^A_HAAHH8T'HHHT$HD$HHT$H߃fT$H Hs]ASDHHCD1H{DD$HD$ HD$( 1҈HD$0fT$=0D$ E1Ll$ AAl$HT$ H߉HKT%HT$ HIuHT$ 8HD$ 8H8HHT$T$ 8HxT$1 1HHMDHHlvCr8H LD$HHǃ8b8HDHHT$ D$ D$ @t HHS@uHHSBuH1AH1D$HD$ HD$(HD$0fL$L?[D$ E1Ll$ E~HT$ HDDHKT5DHT$ DHIIuHT$ 0HD$ 0H0HHT$T$ 0HxD$tоHE1DB 1HHMDHHEtAvCr0H LD$HHǃ8b0HS@,HHSB.HA0HT$ HD$ D$ L H{HT$Hǃ8HD$pLHD$wLHHL`H{HǃxHT$LHD$vHD$vLHH1jHHH+HHHH1HD$ HD$(HD$0fD$4HT$ HD$ HHLl$ LT$ Hx D$H1MHHtHS@@HHSBBH11HT$HT$HmH)HT$HT$EH-HT$HT$HLH{HT$HǃHD$LHD$LHHLH{HǃHT$LHD$HD$LHHD$ оHOfSHeHHD$11nD$fD$uHD$eH+H1[HT$HuD$ tHT$HuH{HtT$fHu1fuHH1H߾\fSHH1ɺH߾'DAWAVAUAHATAUHSH1Hui==uSPwKftWH[]A\A]A^A_HEEODAH0H1[]A\A]A^A_EtEDAAD$A"DE1HDHuuHT$ >HfT$ 1ҾHfT$ HT$ D$ 1HH@HxH@8HxntPtuH1ɺHLHHLHCH0H|$IIH:HrHAELLHL$HD$0SLLH|$IIRxLHT$HT$HBH HHAHHHH"HBAWH|$H5ff.fAWMAVI1AUIATAUHSHt|Lp@HII9t.IHHIWHqHHHPM?MLHDHxH[]A\A]A^A_H1ATHcUSHHHHeHHD$@1HH4$HD$HHD$HHD$HHD$ HHD$(HHD$0HHD$8H9HHHH)HAAąt5HHHHD$@eH+uNHHD[]A\HHHHuHAff.AWAVIAUEATAUSHHHT$eHHD$@1FID$8<D$*D$1fD$6HHH$HHT$8D$8AljňD$ AKAE^@UH<$HAD$ E3HT$6>HT$6>H߁ D$~EuR D$jNEHT$6>HT$6>H߁DH{ID$<*D$D$E1hI8IHGT$8AAA A A €|$*T$8HD$6DLfA GDEtl$ALDHI|$*HAHHDIAIHH9TAH9C@83H9*LMvMuH4$AEDHHD$D$AD8D8u :T$ H<$@AH>HHT$6T$6>H߁DtT$8H߁l$HT$6>HH<$HD$@eH+RHH[]A\A]A^A_H<$IHEHT$6>HT$6>H߁ D$E9IED8IH;@LD)9 D$AH9MIHpHT$HH9t6HPBtHH߉xH11[]HxHHHH1HH1뤸ff.AUATIHUSLHM$A$IunLImI]H9tHHH9uH1LH1LLL[]A\A]LI|$@H[]A\A]USII9u 8HL9t-HpFtHHth1HSH[]IHHtBHHHH1 H߉H[]1랐HtQUSHHt;HHHHHH[HHE][]ff.AT1USLgHLGH߉L[]A\GPLGPLGPLGPLGPLGPLGPLGPLGPLGPLGPLUnknown bridge window %pR (subtractive decode)PCI bridge to %pR%s config space: 6device released PCI Exclusive%s %pR PCIe unknownconventional PCI%04x:%02x:%02x.%dmarking as untrusted marking as removable BAR 0 %pR: legacy IDE quirk BAR 1 %pR: legacy IDE quirk BAR 2 %pR: legacy IDE quirk BAR 3 %pR: legacy IDE quirk disabling Extended Tags enabling Extended Tags ./include/linux/dma-mapping.hdrivers/pci/probe.c%04x:%02xfailed to add bus: %d domain bus already known pci%04x:%02xPCI host bridge to bus %s 6PCI host bridge to bus %s root bus resource %pR%s can not beisPCI CardBus %04x:%02xPCI Bus %04x:%02xscanning bus fixups for bus %pR extended by %#02x Scanning root bridge failedbusn_res: %pR %s released conventional PCI endpointconventional PCI bridgeCardBus bridgePCIe EndpointPCIe Legacy EndpointPCIe Root PortPCIe Switch Upstream PortPCIe Switch Downstream PortPCIe to PCI/PCI-X bridgePCI/PCI-X to PCIe bridge33 MHz PCI66 MHz PCI66 MHz PCI-X100 MHz PCI-X133 MHz PCI-X66 MHz PCI-X 266100 MHz PCI-X 266133 MHz PCI-X 266Unknown AGP1x AGP2x AGP4x AGP8x AGP66 MHz PCI-X 533100 MHz PCI-X 533133 MHz PCI-X 5332.5 GT/s PCIe5.0 GT/s PCIe8.0 GT/s PCIe16.0 GT/s PCIe32.0 GT/s PCIe64.0 GT/s PCIeprobepci_busPCI busnHHHHLLEE9|C<8r%8rpp9r19ff.HHHFailed attempting to set the MPS Failed attempting to set the MRRS MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d devm_pci_alloc_host_bridge_release[Firmware Bug]: %s: invalid; can't size %s: initial BAR value %#010llx invalid bridge window %pR (subtractive decode) claims to be downstream port but is acting as upstream port, correcting type claims to be upstream port but is acting as downstream port, correcting type [%04x:%04x] type %02x class %#08x %s device has non-compliant BARs; disabling IO/MEM decoding unknown header type %02x, ignoring device ignoring class %#08x (doesn't match header type %02x) 4pci %04x:%02x:%02x.%d: not ready after %dms; giving up 6pci %04x:%02x:%02x.%d: not ready after %dms; waiting 6pci %04x:%02x:%02x.%d: ready after %dms can't set Max Payload Size to %d; if necessary, use "pci=pcie_bus_safe" and report a bug Max Payload Size %d, but upstream %s set to %d; if necessary, use "pci=pcie_bus_safe" and report a bug Upstream bridge's Max Payload Size set to %d (was %d, max %d) Max Payload Size set to %d (was %d, max %d) Relaxed Ordering disabled because the Root Port didn't support it extended config space not accessible busn_res: can not insert %pR under %s%pR (conflicts with %s %pR) (bus address [%#06llx-%#06llx]) (bus address [%#010llx-%#010llx])Unknown NUMA node; performance will be reduced busn_res: %pR end %s updated to %02x scanning [bus %02x-%02x] behind bridge, pass %d Primary bus is hard wired to 0 bridge configuration invalid ([bus %02x-%02x]), reconfiguring bridge has subordinate %02x but max busn %02x devices behind bridge are unusable because %pR cannot be assigned for them bus scan returning with max=%02x No bus number available for hot-added bridge No busn resource found for root bus, will use [bus %02x-ff] PCIe Root Complex Integrated EndpointPCIe Root Complex Event Collector    .    pci_register_host_bridgepci_release_devpci_set_removableset_pcie_untrustedpci_scan_child_bus_extendpci_scan_bridge_extend D 8 ^ TGCC: (Debian 12.2.0-14) 12.2.0GNU (Gz  0@P"`Cpj!Hf 0!@CP``p @  u`&1HUpzh}{:Cp @ }8  ! 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V m @e 08P8`X  1O`- F`7s_8x>98`F8p88 88%@@3 >@IT_j u: d(08@& HV P X ` h& pQ x    H u    A m     08p5w0NP P2$Sz5N@FV`(*1 .X0/~v I <KK1LS@IpJ+  @J       % + A W h }       +:GUo%E^o:5J]0p^p > -:Ibsp% &k'AIPbP(7{(j$0=Kiu "+>Xeq{"0 "0 "1 "5 6H1KXd}=%,AQbq1MdJN6g probe.c__export_symbol_pci_root_buses__export_symbol_no_pci_devices__initcall__kmod_probe__450_110_pcibus_class_init2pcibus_class_init__export_symbol_pci_alloc_host_bridge__export_symbol_devm_pci_alloc_host_bridge__export_symbol_pci_free_host_bridge__export_symbol_pcie_link_speed__export_symbol_pci_speed_string__export_symbol_pcie_update_link_speed__export_symbol_pci_add_new_bus__export_symbol_pci_scan_bridge__export_symbol_pcie_relaxed_ordering_enabled__export_symbol_pci_alloc_dev__export_symbol_pci_bus_read_dev_vendor_id__export_symbol_pci_scan_single_device__export_symbol_pci_scan_slot__export_symbol_pcie_bus_configure_settings__export_symbol_pci_scan_child_bus__export_symbol_pci_create_root_bus__export_symbol_pci_host_probe__export_symbol_pci_scan_root_bus_bridge__export_symbol_pci_scan_root_bus__export_symbol_pci_scan_bus__export_symbol_pci_rescan_bus__export_symbol_pci_lock_rescan_remove__export_symbol_pci_unlock_rescan_remove__export_symbol_pci_hp_add_bridgespeed_strings.8pci_sort_bf_cmppcibus_classrelease_pcibus_devpci_cfg_space_size_extpci_read_irqpci_read_bridge_iopci_read_bridge_mmiopci_read_bridge_mmio_prefpci_release_host_bridge_devpci_read_bridge_windowsearly_dump_pci_devicepci_release_dev__UNIQUE_ID_ddebug501.14pci_rescan_remove_lockpcie_bus_configure_set.part.0pcie_bus_configure_setpci_set_bus_msi_domaindevm_pci_alloc_host_bridge_releasepcie_find_smpsspci_alloc_bus.constprop.0pci_dev_type__UNIQUE_ID_ddebug493.15CSWTCH.252__UNIQUE_ID_ddebug491.16str.3pci_alloc_child_buspcix_bus_speedpci_domain_busn_res_listpci_register_host_bridge__UNIQUE_ID_ddebug464.18pci_scan_bridge_extend__UNIQUE_ID_ddebug483.17pci_scan_child_bus_extend__UNIQUE_ID_ddebug517.12__UNIQUE_ID_ddebug519.11__UNIQUE_ID_ddebug528.9__UNIQUE_ID_ddebug526.10busn_resource__func__.0__func__.2__func__.4__func__.5__func__.6__func__.7__UNIQUE_ID___addressable_pci_hp_add_bridge539__UNIQUE_ID___addressable_pci_unlock_rescan_remove538__UNIQUE_ID___addressable_pci_lock_rescan_remove537__UNIQUE_ID___addressable_pci_rescan_bus536__UNIQUE_ID___addressable_pci_scan_bus535__UNIQUE_ID___addressable_pci_scan_root_bus534__UNIQUE_ID___addressable_pci_scan_root_bus_bridge533__UNIQUE_ID___addressable_pci_host_probe532__UNIQUE_ID___addressable_pci_create_root_bus531__UNIQUE_ID___addressable_pci_scan_child_bus530__UNIQUE_ID___addressable_pcie_bus_configure_settings516__UNIQUE_ID___addressable_pci_scan_slot512__UNIQUE_ID___addressable_pci_scan_single_device511__UNIQUE_ID___addressable_pci_bus_read_dev_vendor_id504__UNIQUE_ID___addressable_pci_alloc_dev503__UNIQUE_ID___addressable_pcie_relaxed_ordering_enabled495__UNIQUE_ID___addressable_pci_scan_bridge485__UNIQUE_ID___addressable_pci_add_new_bus472__UNIQUE_ID___addressable_pcie_update_link_speed458__UNIQUE_ID___addressable_pci_speed_string457__UNIQUE_ID___addressable_pcie_link_speed456__UNIQUE_ID___addressable_pci_free_host_bridge455__UNIQUE_ID___addressable_devm_pci_alloc_host_bridge454__UNIQUE_ID___addressable_pci_alloc_host_bridge453__UNIQUE_ID___addressable_pcibus_class_init451__UNIQUE_ID___addressable_no_pci_devices449__UNIQUE_ID___addressable_pci_root_buses448.LC13.LC47.LC45.LC44__x86_return_thunkput_devicedevice_match_anypci_bus_typebus_find_deviceclass_registerpci_bus_remove_resourceskfree__ref_stack_chk_guardpci_read_config_dword__stack_chk_failpci_read_config_bytepcibios_bus_to_resource_dev_infopci_read_config_word__x86_indirect_thunk_raxpci_free_resource_listpcie_capability_read_wordpci_write_config_wordpci_write_config_dwordprint_hex_dumppci_aer_exitpci_rcec_exitpci_free_cap_save_bufferspcibios_release_devicepci_bus_putbitmap_free__dynamic_dev_dbgmutex_lockmutex_unlockpcie_get_mpspcie_bus_configpcie_set_mpspcie_get_readrqpcie_set_readrq_dev_warn_dev_errpci_host_bridge_acpi_msi_domainirq_find_matching_fwspec__kmalloc_noprofdevice_initialize__devm_add_actionkmalloc_caches__kmalloc_cache_noprofpci_bus_getpci_walk_bus__pci_size_stdbars__pci_read_basepci_resource_namepcibios_resource_to_buspci_read_bridge_basespci_bus_add_resourcepci_bus_resource_nset_pcie_port_typepci_find_capabilitypcie_capability_read_dwordpcie_capability_clear_and_set_word_lockedset_pcie_hotplug_bridgepci_cfg_space_sizepci_setup_devicepci_set_acpi_fwnodepci_dev_assign_slotdev_set_namepci_early_dumppci_find_vsec_capabilitypci_fixup_devicearch_pci_dev_is_removablepcie_get_supported_speedspci_configure_extended_tagspci_find_host_bridgepcie_capability_clear_and_set_word_unlockedpci_bus_generic_read_dev_vendor_idpci_bus_read_config_dword_printkmsleeppci_idt_bus_quirkpcie_report_downtraining__pcie_print_link_statuspci_device_addpci_configure_ltrpci_configure_aspm_l1sspci_acpi_program_hp_paramspcie_failed_link_retrainpci_reassigndev_resource_alignmentpci_ea_initpci_msi_initpci_msix_initpci_allocate_cap_save_bufferspci_pm_initpci_vpd_initpci_configure_aripci_ats_initpci_pri_initpci_pasid_initpci_acs_initpci_aer_initpci_rcec_initpci_rebar_initpci_init_reset_methodspci_bus_semdown_writeup_writepcibios_device_addpci_msi_get_device_domainpc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