// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar
 * and Markus Pargmann, Pengutronix
 */

/dts-v1/;
#include "imx27.dtsi"

/ {
	model = "Phytec pca100";
	compatible = "phytec,imx27-pca100", "fsl,imx27";

	memory@a0000000 {
		device_type = "memory";
		reg = <0xa0000000 0x08000000>; /* 128MB */
	};

	usbotgphy: usbotgphy {
		compatible = "usb-nop-xceiv";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usbotgphy>;
		reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
		#phy-cells = <0>;
	};

	usbh2phy: usbh2phy {
		compatible = "usb-nop-xceiv";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usbh2phy>;
		reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
		#phy-cells = <0>;
	};
};

&cspi1 {
	cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>,
		   <&gpio4 27 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	status = "okay";
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	eeprom@52 {
		compatible = "atmel,24c32";
		pagesize = <32>;
		reg = <0x52>;
	};
};

&iomuxc {
	imx27-phycard-s-som {
		pinctrl_fec1: fec1grp {
			fsl,pins = <
				MX27_PAD_SD3_CMD__FEC_TXD0 0x0
				MX27_PAD_SD3_CLK__FEC_TXD1 0x0
				MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
				MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
				MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
				MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
				MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
				MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
				MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
				MX27_PAD_ATA_DATA7__FEC_MDC 0x0
				MX27_PAD_ATA_DATA8__FEC_CRS 0x0
				MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
				MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
				MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
				MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
				MX27_PAD_ATA_DATA13__FEC_COL 0x0
				MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
				MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
			>;
		};

		pinctrl_i2c2: i2c2grp {
			fsl,pins = <
				MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
				MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
			>;
		};

		pinctrl_nfc: nfcgrp {
			fsl,pins = <
				MX27_PAD_NFRB__NFRB 0x0
				MX27_PAD_NFCLE__NFCLE 0x0
				MX27_PAD_NFWP_B__NFWP_B 0x0
				MX27_PAD_NFCE_B__NFCE_B 0x0
				MX27_PAD_NFALE__NFALE 0x0
				MX27_PAD_NFRE_B__NFRE_B 0x0
				MX27_PAD_NFWE_B__NFWE_B 0x0
			>;
		};

		pinctrl_usbotgphy: usbotgphygrp {
			fsl,pins = <
				MX27_PAD_USBH1_RCV__GPIO2_25		0x1 /* reset gpio */
			>;
		};

		pinctrl_usbotg: usbotggrp {
			fsl,pins = <
				MX27_PAD_USBOTG_CLK__USBOTG_CLK		0x0
				MX27_PAD_USBOTG_DIR__USBOTG_DIR		0x0
				MX27_PAD_USBOTG_NXT__USBOTG_NXT		0x0
				MX27_PAD_USBOTG_STP__USBOTG_STP		0x0
				MX27_PAD_USBOTG_DATA0__USBOTG_DATA0	0x0
				MX27_PAD_USBOTG_DATA1__USBOTG_DATA1	0x0
				MX27_PAD_USBOTG_DATA2__USBOTG_DATA2	0x0
				MX27_PAD_USBOTG_DATA3__USBOTG_DATA3	0x0
				MX27_PAD_USBOTG_DATA4__USBOTG_DATA4	0x0
				MX27_PAD_USBOTG_DATA5__USBOTG_DATA5	0x0
				MX27_PAD_USBOTG_DATA6__USBOTG_DATA6	0x0
				MX27_PAD_USBOTG_DATA7__USBOTG_DATA7	0x0
			>;
		};

		pinctrl_usbh2phy: usbh2phygrp {
			fsl,pins = <
				MX27_PAD_USBH1_SUSP__GPIO2_22		0x0 /* reset gpio */
			>;
		};

		pinctrl_usbh2: usbh2grp {
			fsl,pins = <
				MX27_PAD_USBH2_CLK__USBH2_CLK		0x0
				MX27_PAD_USBH2_DIR__USBH2_DIR		0x0
				MX27_PAD_USBH2_NXT__USBH2_NXT		0x0
				MX27_PAD_USBH2_STP__USBH2_STP		0x0
				MX27_PAD_CSPI2_SCLK__USBH2_DATA0	0x0
				MX27_PAD_CSPI2_MOSI__USBH2_DATA1	0x0
				MX27_PAD_CSPI2_MISO__USBH2_DATA2	0x0
				MX27_PAD_CSPI2_SS1__USBH2_DATA3		0x0
				MX27_PAD_CSPI2_SS2__USBH2_DATA4		0x0
				MX27_PAD_CSPI1_SS2__USBH2_DATA5		0x0
				MX27_PAD_CSPI2_SS0__USBH2_DATA6		0x0
				MX27_PAD_USBH2_DATA7__USBH2_DATA7	0x0
			>;
		};
	};
};

&nfc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_nfc>;
	nand-bus-width = <8>;
	nand-ecc-mode = "hw";
	nand-on-flash-bbt;
	status = "okay";
};

&usbotg {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg>;
	phy_type = "ulpi";
	phys = <&usbotgphy>;
	status = "okay";
};

&usbh2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbh2>;
	phy_type = "ulpi";
	phys = <&usbh2phy>;
	status = "okay";
};
