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Started by upstream project "gerrit-osmo-e1-hardware-build" build number 75 originally caused by: Started by upstream project "gerrit-osmo-e1-hardware" build number 79 originally caused by: Triggered by Gerrit: https://gerrit.osmocom.org/c/osmo-e1-hardware/+/36687 in silent mode. Running as SYSTEM Building remotely on build4-deb12build-ansible (ttcn3 obs ttcn3_with_linux_6.1_or_higher qemu io_uring osmocom-gerrit coverity osmocom-master) in workspace /home/osmocom-build/jenkins/workspace/gerrit-osmo-e1-hardware-build/JOB_TYPE/gateware/a1/default/a3/default/a4/default/label/osmocom-gerrit The recommended git tool is: NONE using credential d5eda5e9-b59d-44ba-88d2-43473cb6e42d > git rev-parse --resolve-git-dir /home/osmocom-build/jenkins/workspace/gerrit-osmo-e1-hardware-build/JOB_TYPE/gateware/a1/default/a3/default/a4/default/label/osmocom-gerrit/.git # timeout=10 Fetching changes from the remote Git repository > git config remote.origin.url ssh://jenkins@gerrit.osmocom.org:29418/osmo-e1-hardware # timeout=10 Fetching upstream changes from ssh://jenkins@gerrit.osmocom.org:29418/osmo-e1-hardware > git --version # timeout=10 > git --version # 'git version 2.39.2' using GIT_SSH to set credentials gerrit.osmocom.org Verifying host key using known hosts file, will automatically accept unseen keys > git fetch --tags --force --progress -- ssh://jenkins@gerrit.osmocom.org:29418/osmo-e1-hardware refs/changes/87/36687/1 # timeout=10 Checking out Revision d633f1b9a02e3059d24211958772646d1f5197b7 (master) > git config core.sparsecheckout # timeout=10 > git checkout -f d633f1b9a02e3059d24211958772646d1f5197b7 # timeout=10 Commit message: "icE1usb fw: Automatically report alarm condition to remote peer" > git rev-parse FETCH_HEAD^{commit} # timeout=10 > git rev-list --no-walk 9d5fa543a72bb6df50f01caff065207e47c3ab90 # timeout=10 > git remote # timeout=10 > git submodule init # timeout=10 > git submodule sync # timeout=10 > git config --get remote.origin.url # timeout=10 > git submodule init # timeout=10 > git config -f .gitmodules --get-regexp ^submodule\.(.+)\.url # timeout=10 > git config --get submodule.gateware/build.url # timeout=10 > git config -f .gitmodules --get submodule.gateware/build.path # timeout=10 > git config --get submodule.gateware/cores/no2e1.url # timeout=10 > git config -f .gitmodules --get submodule.gateware/cores/no2e1.path # timeout=10 > git config --get submodule.gateware/cores/no2ice40.url # timeout=10 > git config -f .gitmodules --get submodule.gateware/cores/no2ice40.path # timeout=10 > git config --get submodule.gateware/cores/no2misc.url # timeout=10 > git config -f .gitmodules --get submodule.gateware/cores/no2misc.path # timeout=10 > git config --get submodule.gateware/cores/no2usb.url # timeout=10 > git config -f .gitmodules --get submodule.gateware/cores/no2usb.path # timeout=10 > git submodule update --init --recursive gateware/build # timeout=10 > git submodule update --init --recursive gateware/cores/no2e1 # timeout=10 > git submodule update --init --recursive gateware/cores/no2ice40 # timeout=10 > git submodule update --init --recursive gateware/cores/no2misc # timeout=10 > git submodule update --init --recursive gateware/cores/no2usb # timeout=10 [osmocom-gerrit] $ /bin/sh -xe /tmp/jenkins7518447689117473919.sh + DOCKER_IMG=osmocom-build/debian-bookworm-build + DOCKER_IMG=registry.osmocom.org/osmocom-build/fpga-build + docker pull registry.osmocom.org/osmocom-build/fpga-build Using default tag: latest latest: Pulling from osmocom-build/fpga-build Digest: sha256:a10bc7e396b0c1300182dc546f283ac50bffe26af36f6b5727b018314ffe6db2 Status: Image is up to date for registry.osmocom.org/osmocom-build/fpga-build:latest registry.osmocom.org/osmocom-build/fpga-build:latest + docker run --rm=true --cap-add SYS_PTRACE -e ASCIIDOC_WARNINGS_CHECK=1 -e HOME=/build -e JOB_NAME=gerrit-osmo-e1-hardware-build/JOB_TYPE=gateware,a1=default,a3=default,a4=default,label=osmocom-gerrit -e MAKE=make -e OSMOPY_DEBUG_TCP_SOCKETS=1 -e OSMO_GSM_MANUALS_DIR=/opt/osmo-gsm-manuals -e PARALLEL_MAKE=-j 12 -e WITH_MANUALS=1 -w /build -i -u build -v /home/osmocom-build/jenkins/workspace/gerrit-osmo-e1-hardware-build/JOB_TYPE/gateware/a1/default/a3/default/a4/default/label/osmocom-gerrit:/build -e JOB_TYPE=gateware registry.osmocom.org/osmocom-build/fpga-build /usr/bin/timeout 30m /build/contrib/jenkins.sh =============== gateware/e1-tracer GATEWARE ============== make: Entering directory '/build/gateware/e1-tracer' make: Leaving directory '/build/gateware/e1-tracer' make: Entering directory '/build/gateware/e1-tracer' /build/gateware/cores/no2usb//utils/microcode.py > /build/gateware/e1-tracer/build-tmp/usb_trans_mc.hex cp -a /build/gateware/cores/no2usb//data/usb_ep_status.hex /build/gateware/e1-tracer/build-tmp/usb_ep_status.hex cp ../common/fw/boot.hex /build/gateware/e1-tracer/build-tmp/boot.hex cd /build/gateware/e1-tracer/build-tmp && \ yosys -s /build/gateware/e1-tracer/build-tmp/e1-tracer.ys \ -l /build/gateware/e1-tracer/build-tmp/e1-tracer.synth.rpt /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9+3568 (open-tool-forge build) (git sha1 859e52af, gcc 9.3.0-10ubuntu2 -Os) -- Executing script file `/build/gateware/e1-tracer/build-tmp/e1-tracer.ys' -- 1. Executing Verilog-2005 frontend: /build/gateware/e1-tracer/rtl/top.v Parsing Verilog input from `/build/gateware/e1-tracer/rtl/top.v' to AST representation. Generating RTLIL representation for module `\top'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_crc4.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_crc4.v' to AST representation. Generating RTLIL representation for module `\e1_crc4'. Successfully finished Verilog frontend. 3. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v' to AST representation. Generating RTLIL representation for module `\e1_rx_clock_recovery'. Successfully finished Verilog frontend. 4. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v' to AST representation. Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:68) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:209) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:214) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:215) is not recognized unless read_verilog is called with -sv! Generating RTLIL representation for module `\e1_rx_deframer'. Successfully finished Verilog frontend. 5. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx_filter.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx_filter.v' to AST representation. Generating RTLIL representation for module `\e1_rx_filter'. Successfully finished Verilog frontend. 6. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx_phy.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx_phy.v' to AST representation. Generating RTLIL representation for module `\e1_rx_phy'. Successfully finished Verilog frontend. 7. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx_liu.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx_liu.v' to AST representation. Generating RTLIL representation for module `\e1_rx_liu'. Successfully finished Verilog frontend. 8. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx.v' to AST representation. Generating RTLIL representation for module `\e1_rx'. Successfully finished Verilog frontend. 9. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_tx_framer.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_tx_framer.v' to AST representation. Generating RTLIL representation for module `\e1_tx_framer'. Successfully finished Verilog frontend. 10. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_tx_phy.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_tx_phy.v' to AST representation. Generating RTLIL representation for module `\e1_tx_phy'. Successfully finished Verilog frontend. 11. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_tx_liu.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_tx_liu.v' to AST representation. Generating RTLIL representation for module `\e1_tx_liu'. Successfully finished Verilog frontend. 12. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_tx.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_tx.v' to AST representation. Generating RTLIL representation for module `\e1_tx'. Successfully finished Verilog frontend. 13. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v' to AST representation. Generating RTLIL representation for module `\e1_buf_if_wb'. Warning: Replacing memory \tx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:165 Warning: Replacing memory \tx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:145 Warning: Replacing memory \rx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:103 Warning: Replacing memory \rx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:102 Successfully finished Verilog frontend. 14. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_wb_rx.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_wb_rx.v' to AST representation. Generating RTLIL representation for module `\e1_wb_rx'. Successfully finished Verilog frontend. 15. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_wb_tx.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_wb_tx.v' to AST representation. Generating RTLIL representation for module `\e1_wb_tx'. Successfully finished Verilog frontend. 16. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_wb.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_wb.v' to AST representation. Generating RTLIL representation for module `\e1_wb'. Successfully finished Verilog frontend. 17. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/hdb3_dec.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/hdb3_dec.v' to AST representation. Generating RTLIL representation for module `\hdb3_dec'. Successfully finished Verilog frontend. 18. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/hdb3_enc.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/hdb3_enc.v' to AST representation. Generating RTLIL representation for module `\hdb3_enc'. Successfully finished Verilog frontend. 19. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_ebr.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_ebr.v' to AST representation. Generating RTLIL representation for module `\ice40_ebr'. Successfully finished Verilog frontend. 20. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_i2c_wb.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_i2c_wb.v' to AST representation. Generating RTLIL representation for module `\ice40_i2c_wb'. Successfully finished Verilog frontend. 21. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v' to AST representation. Generating RTLIL representation for module `\ice40_rgb_wb'. Successfully finished Verilog frontend. 22. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_spi_wb.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_spi_wb.v' to AST representation. Generating RTLIL representation for module `\ice40_spi_wb'. Successfully finished Verilog frontend. 23. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v' to AST representation. Generating RTLIL representation for module `\ice40_spram_gen'. ice40_spram_gen: (32768x32) -> 2x2 array of SPRAM Successfully finished Verilog frontend. 24. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v' to AST representation. Generating RTLIL representation for module `\ice40_spram_wb'. Successfully finished Verilog frontend. 25. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_iserdes.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_iserdes.v' to AST representation. Generating RTLIL representation for module `\ice40_iserdes'. Successfully finished Verilog frontend. 26. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_oserdes.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_oserdes.v' to AST representation. Generating RTLIL representation for module `\ice40_oserdes'. Successfully finished Verilog frontend. 27. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_serdes_crg.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_serdes_crg.v' to AST representation. Generating RTLIL representation for module `\ice40_serdes_crg'. Successfully finished Verilog frontend. 28. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_serdes_dff.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_serdes_dff.v' to AST representation. Generating RTLIL representation for module `\ice40_serdes_dff'. Successfully finished Verilog frontend. 29. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_serdes_sync.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_serdes_sync.v' to AST representation. Generating RTLIL representation for module `\ice40_serdes_sync'. Successfully finished Verilog frontend. 30. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/delay.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/delay.v' to AST representation. Generating RTLIL representation for module `\delay_bit'. Generating RTLIL representation for module `\delay_bus'. Warning: Replacing memory \dl with list of registers. See /build/gateware/cores/no2misc//rtl/delay.v:59 Generating RTLIL representation for module `\delay_toggle'. Successfully finished Verilog frontend. 31. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/fifo_sync_ram.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v' to AST representation. Generating RTLIL representation for module `\fifo_sync_ram'. Successfully finished Verilog frontend. 32. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/fifo_sync_shift.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v' to AST representation. Generating RTLIL representation for module `\fifo_sync_shift'. Successfully finished Verilog frontend. 33. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/glitch_filter.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/glitch_filter.v' to AST representation. Generating RTLIL representation for module `\glitch_filter'. Successfully finished Verilog frontend. 34. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/i2c_master.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/i2c_master.v' to AST representation. Generating RTLIL representation for module `\i2c_master'. Successfully finished Verilog frontend. 35. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/i2c_master_wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/i2c_master_wb.v' to AST representation. Generating RTLIL representation for module `\i2c_master_wb'. Successfully finished Verilog frontend. 36. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/muacm2wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/muacm2wb.v' to AST representation. Generating RTLIL representation for module `\muacm2wb'. Successfully finished Verilog frontend. 37. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/prims.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/prims.v' to AST representation. Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:31) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:75) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:117) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:150) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:186) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:237) is not recognized unless read_verilog is called with -sv! Generating RTLIL representation for module `\lut4_n'. Generating RTLIL representation for module `\lut4_carry_n'. Generating RTLIL representation for module `\dff_n'. Generating RTLIL representation for module `\dffe_n'. Generating RTLIL representation for module `\dffer_n'. Generating RTLIL representation for module `\dffesr_n'. Successfully finished Verilog frontend. 38. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/pdm.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/pdm.v' to AST representation. Warning: Yosys has only limited support for tri-state logic at the moment. (/build/gateware/cores/no2misc//rtl/pdm.v:91) Generating RTLIL representation for module `\pdm'. Generating RTLIL representation for module `\pdm_lfsr'. Successfully finished Verilog frontend. 39. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/pwm.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/pwm.v' to AST representation. Warning: Yosys has only limited support for tri-state logic at the moment. (/build/gateware/cores/no2misc//rtl/pwm.v:69) Generating RTLIL representation for module `\pwm'. Successfully finished Verilog frontend. 40. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/ram_sdp.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/ram_sdp.v' to AST representation. Generating RTLIL representation for module `\ram_sdp'. Successfully finished Verilog frontend. 41. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/stream2wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/stream2wb.v' to AST representation. Generating RTLIL representation for module `\stream2wb'. Successfully finished Verilog frontend. 42. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/uart2wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/uart2wb.v' to AST representation. Generating RTLIL representation for module `\uart2wb'. Successfully finished Verilog frontend. 43. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/uart_rx.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/uart_rx.v' to AST representation. Generating RTLIL representation for module `\uart_rx'. Successfully finished Verilog frontend. 44. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/uart_tx.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/uart_tx.v' to AST representation. Generating RTLIL representation for module `\uart_tx'. Successfully finished Verilog frontend. 45. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/uart_wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/uart_wb.v' to AST representation. Generating RTLIL representation for module `\uart_wb'. Successfully finished Verilog frontend. 46. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/xclk_strobe.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/xclk_strobe.v' to AST representation. Generating RTLIL representation for module `\xclk_strobe'. Successfully finished Verilog frontend. 47. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/xclk_wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/xclk_wb.v' to AST representation. Generating RTLIL representation for module `\xclk_wb'. Successfully finished Verilog frontend. 48. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb.v' to AST representation. Generating RTLIL representation for module `\usb'. Successfully finished Verilog frontend. 49. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_crc.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_crc.v' to AST representation. Generating RTLIL representation for module `\usb_crc'. Successfully finished Verilog frontend. 50. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_ep_buf.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_ep_buf.v' to AST representation. Generating RTLIL representation for module `\usb_ep_buf'. READ_MODE : 3 WRITE_MODE : 3 Successfully finished Verilog frontend. 51. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_ep_status.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_ep_status.v' to AST representation. Generating RTLIL representation for module `\usb_ep_status'. Successfully finished Verilog frontend. 52. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_phy.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_phy.v' to AST representation. Generating RTLIL representation for module `\usb_phy'. Successfully finished Verilog frontend. 53. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_rx_ll.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_rx_ll.v' to AST representation. Generating RTLIL representation for module `\usb_rx_ll'. Successfully finished Verilog frontend. 54. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_rx_pkt.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v' to AST representation. Generating RTLIL representation for module `\usb_rx_pkt'. Successfully finished Verilog frontend. 55. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_trans.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_trans.v' to AST representation. Generating RTLIL representation for module `\usb_trans'. Successfully finished Verilog frontend. 56. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_tx_ll.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_tx_ll.v' to AST representation. Generating RTLIL representation for module `\usb_tx_ll'. Successfully finished Verilog frontend. 57. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_tx_pkt.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v' to AST representation. Generating RTLIL representation for module `\usb_tx_pkt'. Successfully finished Verilog frontend. 58. Executing Verilog-2005 frontend: /build/gateware/e1-tracer/rtl/misc.v Parsing Verilog input from `/build/gateware/e1-tracer/rtl/misc.v' to AST representation. Generating RTLIL representation for module `\misc'. Warning: Replacing memory \tick_e1_sel with list of registers. See /build/gateware/e1-tracer/rtl/misc.v:97 Successfully finished Verilog frontend. 59. Executing Verilog-2005 frontend: /build/gateware/e1-tracer/rtl/sysmgr.v Parsing Verilog input from `/build/gateware/e1-tracer/rtl/sysmgr.v' to AST representation. Generating RTLIL representation for module `\sysmgr'. Successfully finished Verilog frontend. 60. Executing Verilog-2005 frontend: /build/gateware/common/rtl/capcnt.v Parsing Verilog input from `/build/gateware/common/rtl/capcnt.v' to AST representation. Generating RTLIL representation for module `\capcnt'. Successfully finished Verilog frontend. 61. Executing Verilog-2005 frontend: /build/gateware/common/rtl/capcnt_sb_mac16.v Parsing Verilog input from `/build/gateware/common/rtl/capcnt_sb_mac16.v' to AST representation. Generating RTLIL representation for module `\capcnt16_sb_mac16'. Generating RTLIL representation for module `\capcnt32_sb_mac16'. Successfully finished Verilog frontend. 62. Executing Verilog-2005 frontend: /build/gateware/common/rtl/dfu_helper.v Parsing Verilog input from `/build/gateware/common/rtl/dfu_helper.v' to AST representation. Generating RTLIL representation for module `\dfu_helper'. Successfully finished Verilog frontend. 63. Executing Verilog-2005 frontend: /build/gateware/common/rtl/picorv32.v Parsing Verilog input from `/build/gateware/common/rtl/picorv32.v' to AST representation. Generating RTLIL representation for module `\picorv32'. Generating RTLIL representation for module `\picorv32_regs'. Generating RTLIL representation for module `\picorv32_pcpi_mul'. Generating RTLIL representation for module `\picorv32_pcpi_fast_mul'. Generating RTLIL representation for module `\picorv32_pcpi_div'. Generating RTLIL representation for module `\picorv32_axi'. Generating RTLIL representation for module `\picorv32_axi_adapter'. Generating RTLIL representation for module `\picorv32_wb'. Successfully finished Verilog frontend. 64. Executing Verilog-2005 frontend: /build/gateware/common/rtl/picorv32_ice40_regs.v Parsing Verilog input from `/build/gateware/common/rtl/picorv32_ice40_regs.v' to AST representation. Generating RTLIL representation for module `\picorv32_ice40_regs'. Successfully finished Verilog frontend. 65. Executing Verilog-2005 frontend: /build/gateware/common/rtl/soc_base.v Parsing Verilog input from `/build/gateware/common/rtl/soc_base.v' to AST representation. Generating RTLIL representation for module `\soc_base'. Successfully finished Verilog frontend. 66. Executing Verilog-2005 frontend: /build/gateware/common/rtl/soc_bram.v Parsing Verilog input from `/build/gateware/common/rtl/soc_bram.v' to AST representation. Generating RTLIL representation for module `\soc_bram'. Successfully finished Verilog frontend. 67. Executing Verilog-2005 frontend: /build/gateware/common/rtl/soc_iobuf.v Parsing Verilog input from `/build/gateware/common/rtl/soc_iobuf.v' to AST representation. Generating RTLIL representation for module `\soc_iobuf'. Successfully finished Verilog frontend. 68. Executing Verilog-2005 frontend: /build/gateware/common/rtl/soc_picorv32_bridge.v Parsing Verilog input from `/build/gateware/common/rtl/soc_picorv32_bridge.v' to AST representation. Generating RTLIL representation for module `\soc_picorv32_bridge'. Successfully finished Verilog frontend. 69. Executing Verilog-2005 frontend: /build/gateware/common/rtl/soc_spram.v Parsing Verilog input from `/build/gateware/common/rtl/soc_spram.v' to AST representation. Generating RTLIL representation for module `\soc_spram'. Successfully finished Verilog frontend. 70. Executing Verilog-2005 frontend: /build/gateware/common/rtl/wb_arbiter.v Parsing Verilog input from `/build/gateware/common/rtl/wb_arbiter.v' to AST representation. Generating RTLIL representation for module `\wb_arbiter'. Successfully finished Verilog frontend. 71. Executing Verilog-2005 frontend: /build/gateware/common/rtl/wb_dma.v Parsing Verilog input from `/build/gateware/common/rtl/wb_dma.v' to AST representation. Generating RTLIL representation for module `\wb_dma'. Successfully finished Verilog frontend. 72. Executing Verilog-2005 frontend: /build/gateware/common/rtl/wb_epbuf.v Parsing Verilog input from `/build/gateware/common/rtl/wb_epbuf.v' to AST representation. Generating RTLIL representation for module `\wb_epbuf'. Successfully finished Verilog frontend. 73. Executing SYNTH_ICE40 pass. 73.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v' to AST representation. Generating RTLIL representation for module `\SB_IO'. Generating RTLIL representation for module `\SB_GB_IO'. Generating RTLIL representation for module `\SB_GB'. Generating RTLIL representation for module `\SB_LUT4'. Generating RTLIL representation for module `\SB_CARRY'. Generating RTLIL representation for module `\SB_DFF'. Generating RTLIL representation for module `\SB_DFFE'. Generating RTLIL representation for module `\SB_DFFSR'. Generating RTLIL representation for module `\SB_DFFR'. Generating RTLIL representation for module `\SB_DFFSS'. Generating RTLIL representation for module `\SB_DFFS'. Generating RTLIL representation for module `\SB_DFFESR'. Generating RTLIL representation for module `\SB_DFFER'. Generating RTLIL representation for module `\SB_DFFESS'. Generating RTLIL representation for module `\SB_DFFES'. Generating RTLIL representation for module `\SB_DFFN'. Generating RTLIL representation for module `\SB_DFFNE'. Generating RTLIL representation for module `\SB_DFFNSR'. Generating RTLIL representation for module `\SB_DFFNR'. Generating RTLIL representation for module `\SB_DFFNSS'. Generating RTLIL representation for module `\SB_DFFNS'. Generating RTLIL representation for module `\SB_DFFNESR'. Generating RTLIL representation for module `\SB_DFFNER'. Generating RTLIL representation for module `\SB_DFFNESS'. Generating RTLIL representation for module `\SB_DFFNES'. Generating RTLIL representation for module `\SB_RAM40_4K'. Generating RTLIL representation for module `\SB_RAM40_4KNR'. Generating RTLIL representation for module `\SB_RAM40_4KNW'. Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. Generating RTLIL representation for module `\ICESTORM_LC'. Generating RTLIL representation for module `\SB_PLL40_CORE'. Generating RTLIL representation for module `\SB_PLL40_PAD'. Generating RTLIL representation for module `\SB_PLL40_2_PAD'. Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. Generating RTLIL representation for module `\SB_WARMBOOT'. Generating RTLIL representation for module `\SB_SPRAM256KA'. Generating RTLIL representation for module `\SB_HFOSC'. Generating RTLIL representation for module `\SB_LFOSC'. Generating RTLIL representation for module `\SB_RGBA_DRV'. Generating RTLIL representation for module `\SB_LED_DRV_CUR'. Generating RTLIL representation for module `\SB_RGB_DRV'. Generating RTLIL representation for module `\SB_I2C'. Generating RTLIL representation for module `\SB_SPI'. Generating RTLIL representation for module `\SB_LEDDA_IP'. Generating RTLIL representation for module `\SB_FILTER_50NS'. Generating RTLIL representation for module `\SB_IO_I3C'. Generating RTLIL representation for module `\SB_IO_OD'. Generating RTLIL representation for module `\SB_MAC16'. Generating RTLIL representation for module `\ICESTORM_RAM'. Successfully finished Verilog frontend. 73.2. Executing HIERARCHY pass (managing design hierarchy). 73.2.1. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: \ice40_spi_wb Used module: \misc Used module: \capcnt Used module: \capcnt16_sb_mac16 Used module: \dfu_helper Used module: \glitch_filter Used module: \soc_base Used module: \e1_buf_if_wb Used module: \e1_wb Used module: \e1_wb_tx Used module: \e1_tx Used module: \e1_tx_phy Used module: \hdb3_enc Used module: \e1_tx_framer Used module: \e1_crc4 Used module: \fifo_sync_shift Used module: \e1_wb_rx Used module: \e1_rx Used module: \hdb3_dec Used module: \e1_rx_clock_recovery Used module: \e1_rx_filter Used module: \e1_rx_phy Used module: \e1_rx_deframer Used module: \soc_iobuf Used module: \wb_dma Used module: \wb_arbiter Used module: \wb_epbuf Used module: \ice40_spram_wb Used module: \ice40_spram_gen Used module: \xclk_strobe Used module: \xclk_wb Used module: \usb Used module: \usb_ep_status Used module: \usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: \usb_crc Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: \usb_phy Used module: \ice40_rgb_wb Used module: \uart_wb Used module: \fifo_sync_ram Used module: \ram_sdp Used module: \uart_rx Used module: \uart_tx Used module: \soc_spram Used module: \soc_bram Used module: \soc_picorv32_bridge Used module: \picorv32 Used module: \picorv32_ice40_regs Used module: \ice40_ebr Parameter \N_CS = 2 Parameter \WITH_IOB = 1 Parameter \UNIT = 1 73.2.2. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_spi_wb'. Parameter \N_CS = 2 Parameter \WITH_IOB = 1 Parameter \UNIT = 1 Generating RTLIL representation for module `$paramod\ice40_spi_wb\N_CS=2\WITH_IOB=1\UNIT=1'. Parameter \WB_N = 2 Parameter \E1_N = 2 Parameter \E1_UNIT_HAS_RX = 2'11 Parameter \E1_UNIT_HAS_TX = 2'00 Parameter \E1_LIU = 1 73.2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_base'. Parameter \WB_N = 2 Parameter \E1_N = 2 Parameter \E1_UNIT_HAS_RX = 2'11 Parameter \E1_UNIT_HAS_TX = 2'00 Parameter \E1_LIU = 1 Generating RTLIL representation for module `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base'. Parameter \N = 1 Parameter \UNIT_HAS_RX = 1'1 Parameter \UNIT_HAS_TX = 1'1 Parameter \MFW = 7 Parameter \DW = 32 73.2.4. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_buf_if_wb'. Parameter \N = 1 Parameter \UNIT_HAS_RX = 1'1 Parameter \UNIT_HAS_TX = 1'1 Parameter \MFW = 7 Parameter \DW = 32 Generating RTLIL representation for module `$paramod\e1_buf_if_wb\N=1\UNIT_HAS_RX=1'1\UNIT_HAS_TX=1'1\MFW=7\DW=32'. Warning: Replacing memory \tx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:165 Warning: Replacing memory \tx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:145 Warning: Replacing memory \rx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:103 Warning: Replacing memory \rx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:102 Parameter \N = 1 Parameter \UNIT_HAS_RX = 1'1 Parameter \UNIT_HAS_TX = 1'1 Parameter \LIU = 0 Parameter \MFW = 7 73.2.5. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_wb'. Parameter \N = 1 Parameter \UNIT_HAS_RX = 1'1 Parameter \UNIT_HAS_TX = 1'1 Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_wb\N=1\UNIT_HAS_RX=1'1\UNIT_HAS_TX=1'1\LIU=0\MFW=7'. Parameter \DW = 16 Parameter \AW = 12 73.2.6. Executing AST frontend in derive mode using pre-parsed AST for module `\xclk_wb'. Parameter \DW = 16 Parameter \AW = 12 Generating RTLIL representation for module `$paramod\xclk_wb\DW=16\AW=12'. Parameter \EPDW = 32 73.2.7. Executing AST frontend in derive mode using pre-parsed AST for module `\usb'. Parameter \EPDW = 32 Generating RTLIL representation for module `$paramod\usb\EPDW=32'. Parameter \CURRENT_MODE = 24'001100000110001000110001 Parameter \RGB0_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB1_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB2_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 73.2.8. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_rgb_wb'. Parameter \CURRENT_MODE = 24'001100000110001000110001 Parameter \RGB0_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB1_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB2_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Generating RTLIL representation for module `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb'. Parameter \DIV_WIDTH = 12 Parameter \DW = 32 73.2.9. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_wb'. Parameter \DIV_WIDTH = 12 Parameter \DW = 32 Generating RTLIL representation for module `$paramod\uart_wb\DIV_WIDTH=12\DW=32'. Parameter \N_CS = 1 Parameter \WITH_IOB = 0 Parameter \UNIT = 0 73.2.10. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_spi_wb'. Parameter \N_CS = 1 Parameter \WITH_IOB = 0 Parameter \UNIT = 0 Generating RTLIL representation for module `$paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0'. Parameter \AW = 14 73.2.11. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_spram'. Parameter \AW = 14 Generating RTLIL representation for module `$paramod\soc_spram\AW=14'. Parameter \AW = 8 Parameter \INIT_FILE = 64'0110001001101111011011110111010000101110011010000110010101111000 73.2.12. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_bram'. Parameter \AW = 8 Parameter \INIT_FILE = 64'0110001001101111011011110111010000101110011010000110010101111000 Generating RTLIL representation for module `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram'. Parameter \WB_N = 9 Parameter \WB_DW = 32 Parameter \WB_AW = 16 Parameter \WB_AI = 2 Parameter \WB_REG = 4 73.2.13. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_picorv32_bridge'. Parameter \WB_N = 9 Parameter \WB_DW = 32 Parameter \WB_AW = 16 Parameter \WB_AI = 2 Parameter \WB_REG = 4 Generating RTLIL representation for module `$paramod\soc_picorv32_bridge\WB_N=9\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4'. Parameter \ENABLE_COUNTERS = 0 Parameter \BARREL_SHIFTER = 0 Parameter \TWO_CYCLE_COMPARE = 0 Parameter \TWO_CYCLE_ALU = 0 Parameter \COMPRESSED_ISA = 0 Parameter \CATCH_MISALIGN = 0 Parameter \CATCH_ILLINSN = 0 Parameter \ENABLE_MUL = 0 Parameter \ENABLE_DIV = 0 Parameter \ENABLE_IRQ = 0 Parameter \ENABLE_IRQ_QREGS = 0 Parameter \PROGADDR_RESET = 0 Parameter \STACKADDR = 1024 73.2.14. Executing AST frontend in derive mode using pre-parsed AST for module `\picorv32'. Parameter \ENABLE_COUNTERS = 0 Parameter \BARREL_SHIFTER = 0 Parameter \TWO_CYCLE_COMPARE = 0 Parameter \TWO_CYCLE_ALU = 0 Parameter \COMPRESSED_ISA = 0 Parameter \CATCH_MISALIGN = 0 Parameter \CATCH_ILLINSN = 0 Parameter \ENABLE_MUL = 0 Parameter \ENABLE_DIV = 0 Parameter \ENABLE_IRQ = 0 Parameter \ENABLE_IRQ_QREGS = 0 Parameter \PROGADDR_RESET = 0 Parameter \STACKADDR = 1024 Generating RTLIL representation for module `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32'. Parameter \W = 16 73.2.15. Executing AST frontend in derive mode using pre-parsed AST for module `\capcnt'. Parameter \W = 16 Generating RTLIL representation for module `$paramod\capcnt\W=16'. Parameter \W = 16 Found cached RTLIL representation for module `$paramod\capcnt\W=16'. Parameter \TIMER_WIDTH = 26 Parameter \BTN_MODE = 3 Parameter \DFU_MODE = 0 73.2.16. Executing AST frontend in derive mode using pre-parsed AST for module `\dfu_helper'. Parameter \TIMER_WIDTH = 26 Parameter \BTN_MODE = 3 Parameter \DFU_MODE = 0 Generating RTLIL representation for module `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0'. Parameter \W = 32 73.2.17. Executing AST frontend in derive mode using pre-parsed AST for module `\capcnt'. Parameter \W = 32 Generating RTLIL representation for module `$paramod\capcnt\W=32'. Parameter \LIU = 0 Parameter \MFW = 7 73.2.18. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_rx'. Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_rx\LIU=0\MFW=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 73.2.19. Executing AST frontend in derive mode using pre-parsed AST for module `\fifo_sync_shift'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 Generating RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 73.2.20. Executing AST frontend in derive mode using pre-parsed AST for module `\fifo_sync_shift'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 Generating RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7'. Parameter \LIU = 0 Parameter \MFW = 7 73.2.21. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_tx'. Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_tx\LIU=0\MFW=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9'. Parameter \LIU = 0 Parameter \MFW = 7 73.2.22. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_wb_tx'. Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_wb_tx\LIU=0\MFW=7'. Parameter \LIU = 0 Parameter \MFW = 7 73.2.23. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_wb_rx'. Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_wb_rx\LIU=0\MFW=7'. Parameter \ADDR_WIDTH = 14 Parameter \DATA_WIDTH = 32 73.2.24. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_spram_gen'. Parameter \ADDR_WIDTH = 14 Parameter \DATA_WIDTH = 32 Generating RTLIL representation for module `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32'. ice40_spram_gen: (16384x32) -> 1x2 array of SPRAM Parameter \AWIDTH = 8 Parameter \DWIDTH = 16 73.2.25. Executing AST frontend in derive mode using pre-parsed AST for module `\ram_sdp'. Parameter \AWIDTH = 8 Parameter \DWIDTH = 16 Generating RTLIL representation for module `$paramod\ram_sdp\AWIDTH=8\DWIDTH=16'. Parameter \L = 2 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 73.2.26. Executing AST frontend in derive mode using pre-parsed AST for module `\glitch_filter'. Parameter \L = 2 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Generating RTLIL representation for module `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1'. Parameter \DEPTH = 512 Parameter \WIDTH = 8 73.2.27. Executing AST frontend in derive mode using pre-parsed AST for module `\fifo_sync_ram'. Parameter \DEPTH = 512 Parameter \WIDTH = 8 Generating RTLIL representation for module `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8'. Parameter \DIV_WIDTH = 8 Parameter \GLITCH_FILTER = 2 73.2.28. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'. Parameter \DIV_WIDTH = 8 Parameter \GLITCH_FILTER = 2 Generating RTLIL representation for module `$paramod\uart_rx\DIV_WIDTH=8\GLITCH_FILTER=2'. Parameter \DEPTH = 512 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8'. Parameter \DIV_WIDTH = 8 73.2.29. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'. Parameter \DIV_WIDTH = 8 Generating RTLIL representation for module `$paramod\uart_tx\DIV_WIDTH=8'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 16 Parameter \WWIDTH = 8 73.2.30. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_ep_buf'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 16 Parameter \WWIDTH = 8 Generating RTLIL representation for module `$paramod$7d82212fad3e4929db14b64ca83adffce21ba555\usb_ep_buf'. READ_MODE : 2 WRITE_MODE : 3 Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 8 Parameter \WWIDTH = 16 73.2.31. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_ep_buf'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 8 Parameter \WWIDTH = 16 Generating RTLIL representation for module `$paramod$e9a8417cc0e9fc03e370009e77135e9e1e2b5499\usb_ep_buf'. READ_MODE : 3 WRITE_MODE : 2 Parameter \TARGET = 40'0100100101000011010001010011010000110000 73.2.32. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_phy'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Generating RTLIL representation for module `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000'. Parameter \WIDTH = 16 Parameter \POLY = 16'1000000000000101 Parameter \MATCH = 16'1000000000001101 73.2.33. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_crc'. Parameter \WIDTH = 16 Parameter \POLY = 16'1000000000000101 Parameter \MATCH = 16'1000000000001101 Generating RTLIL representation for module `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101'. Parameter \WIDTH = 16 Parameter \POLY = 16'1000000000000101 Parameter \MATCH = 16'1000000000001101 Found cached RTLIL representation for module `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101'. Parameter \WIDTH = 5 Parameter \POLY = 5'00101 Parameter \MATCH = 5'01100 73.2.34. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_crc'. Parameter \WIDTH = 5 Parameter \POLY = 5'00101 Parameter \MATCH = 5'01100 Generating RTLIL representation for module `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100'. Parameter \L = 4 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Parameter \WITH_SAMP_COND = 1'0 73.2.35. Executing AST frontend in derive mode using pre-parsed AST for module `\glitch_filter'. Parameter \L = 4 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Parameter \WITH_SAMP_COND = 1'0 Generating RTLIL representation for module `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0'. Parameter \READ_MODE = 0 Parameter \WRITE_MODE = 0 Parameter \MASK_WORKAROUND = 0 Parameter \NEG_WR_CLK = 0 Parameter \NEG_RD_CLK = 1 73.2.36. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_ebr'. Parameter \READ_MODE = 0 Parameter \WRITE_MODE = 0 Parameter \MASK_WORKAROUND = 0 Parameter \NEG_WR_CLK = 0 Parameter \NEG_RD_CLK = 1 Generating RTLIL representation for module `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr'. Parameter \READ_MODE = 0 Parameter \WRITE_MODE = 0 Parameter \MASK_WORKAROUND = 0 Parameter \NEG_WR_CLK = 0 Parameter \NEG_RD_CLK = 1 Found cached RTLIL representation for module `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr'. Parameter \READ_MODE = 0 Parameter \WRITE_MODE = 0 Parameter \MASK_WORKAROUND = 0 Parameter \NEG_WR_CLK = 0 Parameter \NEG_RD_CLK = 1 Found cached RTLIL representation for module `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr'. Parameter \READ_MODE = 0 Parameter \WRITE_MODE = 0 Parameter \MASK_WORKAROUND = 0 Parameter \NEG_WR_CLK = 0 Parameter \NEG_RD_CLK = 1 Found cached RTLIL representation for module `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr'. Parameter \ADDR_WIDTH = 14 Parameter \DATA_WIDTH = 32 Found cached RTLIL representation for module `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32'. Parameter \A0W = 14 Parameter \A1W = 9 Parameter \DW = 32 73.2.37. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_dma'. Parameter \A0W = 14 Parameter \A1W = 9 Parameter \DW = 32 Generating RTLIL representation for module `$paramod\wb_dma\A0W=14\A1W=9\DW=32'. Parameter \N = 2 Parameter \DW = 32 Parameter \AW = 9 73.2.38. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_arbiter'. Parameter \N = 2 Parameter \DW = 32 Parameter \AW = 9 Generating RTLIL representation for module `$paramod\wb_arbiter\N=2\DW=32\AW=9'. Parameter \AW = 9 Parameter \DW = 32 73.2.39. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_epbuf'. Parameter \AW = 9 Parameter \DW = 32 Generating RTLIL representation for module `$paramod\wb_epbuf\AW=9\DW=32'. Parameter \N = 3 Parameter \DW = 32 Parameter \AW = 14 73.2.40. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_arbiter'. Parameter \N = 3 Parameter \DW = 32 Parameter \AW = 14 Generating RTLIL representation for module `$paramod\wb_arbiter\N=3\DW=32\AW=14'. Parameter \AW = 14 Parameter \DW = 32 Parameter \ZERO_RDATA = 0 73.2.41. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_spram_wb'. Parameter \AW = 14 Parameter \DW = 32 Parameter \ZERO_RDATA = 0 Generating RTLIL representation for module `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0'. 73.2.42. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: $paramod\ice40_spi_wb\N_CS=2\WITH_IOB=1\UNIT=1 Used module: \misc Used module: $paramod\capcnt\W=16 Used module: \capcnt16_sb_mac16 Used module: $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0 Used module: \glitch_filter Used module: $paramod\capcnt\W=32 Used module: \capcnt32_sb_mac16 Used module: $paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base Used module: \e1_buf_if_wb Used module: \e1_wb Used module: $paramod\e1_wb_tx\LIU=0\MFW=7 Used module: \e1_tx Used module: \e1_tx_phy Used module: \hdb3_enc Used module: \e1_tx_framer Used module: \e1_crc4 Used module: \fifo_sync_shift Used module: $paramod\e1_wb_rx\LIU=0\MFW=7 Used module: \e1_rx Used module: \hdb3_dec Used module: \e1_rx_clock_recovery Used module: \e1_rx_filter Used module: \e1_rx_phy Used module: \e1_rx_deframer Used module: \soc_iobuf Used module: $paramod\wb_dma\A0W=14\A1W=9\DW=32 Used module: $paramod\wb_arbiter\N=2\DW=32\AW=9 Used module: $paramod\wb_epbuf\AW=9\DW=32 Used module: $paramod\wb_arbiter\N=3\DW=32\AW=14 Used module: $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0 Used module: \ice40_spram_gen Used module: \xclk_strobe Used module: \xclk_wb Used module: \usb Used module: \usb_ep_status Used module: $paramod$7d82212fad3e4929db14b64ca83adffce21ba555\usb_ep_buf Used module: $paramod$e9a8417cc0e9fc03e370009e77135e9e1e2b5499\usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101 Used module: $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100 Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000 Used module: \ice40_rgb_wb Used module: \uart_wb Used module: $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8 Used module: \ram_sdp Used module: $paramod\uart_rx\DIV_WIDTH=8\GLITCH_FILTER=2 Used module: $paramod\uart_tx\DIV_WIDTH=8 Used module: \ice40_spi_wb Used module: \soc_spram Used module: $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32 Used module: \soc_bram Used module: \soc_picorv32_bridge Used module: \picorv32 Used module: \picorv32_ice40_regs Used module: $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr Parameter \L = 4 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Parameter \WITH_SAMP_COND = 1'0 Found cached RTLIL representation for module `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0'. Parameter \N = 2 Parameter \UNIT_HAS_RX = 2'11 Parameter \UNIT_HAS_TX = 2'00 Parameter \MFW = 7 Parameter \DW = 32 73.2.43. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_buf_if_wb'. Parameter \N = 2 Parameter \UNIT_HAS_RX = 2'11 Parameter \UNIT_HAS_TX = 2'00 Parameter \MFW = 7 Parameter \DW = 32 Generating RTLIL representation for module `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32'. Warning: Replacing memory \tx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:176 Warning: Replacing memory \tx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:175 Warning: Replacing memory \rx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:103 Warning: Replacing memory \rx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:102 Parameter \N = 2 Parameter \UNIT_HAS_RX = 2'11 Parameter \UNIT_HAS_TX = 2'00 Parameter \LIU = 1 Parameter \MFW = 7 73.2.44. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_wb'. Parameter \N = 2 Parameter \UNIT_HAS_RX = 2'11 Parameter \UNIT_HAS_TX = 2'00 Parameter \LIU = 1 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7'. Parameter \DW = 16 Parameter \AW = 12 Found cached RTLIL representation for module `$paramod\xclk_wb\DW=16\AW=12'. Parameter \EPDW = 32 Found cached RTLIL representation for module `$paramod\usb\EPDW=32'. Parameter \CURRENT_MODE = 24'001100000110001000110001 Parameter \RGB0_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB1_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB2_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Found cached RTLIL representation for module `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb'. Parameter \DIV_WIDTH = 12 Parameter \DW = 32 Found cached RTLIL representation for module `$paramod\uart_wb\DIV_WIDTH=12\DW=32'. Parameter \N_CS = 1 Parameter \WITH_IOB = 0 Parameter \UNIT = 0 Found cached RTLIL representation for module `$paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0'. Parameter \AW = 14 Found cached RTLIL representation for module `$paramod\soc_spram\AW=14'. Parameter \AW = 8 Parameter \INIT_FILE = 64'0110001001101111011011110111010000101110011010000110010101111000 Found cached RTLIL representation for module `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram'. Parameter \WB_N = 10 Parameter \WB_DW = 32 Parameter \WB_AW = 16 Parameter \WB_AI = 2 Parameter \WB_REG = 4 73.2.45. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_picorv32_bridge'. Parameter \WB_N = 10 Parameter \WB_DW = 32 Parameter \WB_AW = 16 Parameter \WB_AI = 2 Parameter \WB_REG = 4 Generating RTLIL representation for module `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4'. Parameter \ENABLE_COUNTERS = 0 Parameter \BARREL_SHIFTER = 0 Parameter \TWO_CYCLE_COMPARE = 0 Parameter \TWO_CYCLE_ALU = 0 Parameter \COMPRESSED_ISA = 0 Parameter \CATCH_MISALIGN = 0 Parameter \CATCH_ILLINSN = 0 Parameter \ENABLE_MUL = 0 Parameter \ENABLE_DIV = 0 Parameter \ENABLE_IRQ = 0 Parameter \ENABLE_IRQ_QREGS = 0 Parameter \PROGADDR_RESET = 0 Parameter \STACKADDR = 1024 Found cached RTLIL representation for module `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32'. Parameter \LIU = 0 Parameter \MFW = 7 Found cached RTLIL representation for module `$paramod\e1_tx\LIU=0\MFW=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9'. Parameter \LIU = 0 Parameter \MFW = 7 Found cached RTLIL representation for module `$paramod\e1_rx\LIU=0\MFW=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7'. Parameter \AWIDTH = 9 Parameter \DWIDTH = 8 73.2.46. Executing AST frontend in derive mode using pre-parsed AST for module `\ram_sdp'. Parameter \AWIDTH = 9 Parameter \DWIDTH = 8 Generating RTLIL representation for module `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8'. Parameter \L = 2 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Found cached RTLIL representation for module `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1'. Parameter \ADDR_WIDTH = 14 Parameter \DATA_WIDTH = 32 Found cached RTLIL representation for module `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32'. 73.2.47. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: $paramod\ice40_spi_wb\N_CS=2\WITH_IOB=1\UNIT=1 Used module: \misc Used module: $paramod\capcnt\W=16 Used module: \capcnt16_sb_mac16 Used module: $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0 Used module: $paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0 Used module: $paramod\capcnt\W=32 Used module: \capcnt32_sb_mac16 Used module: $paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base Used module: $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32 Used module: $paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7 Used module: \e1_wb_rx Used module: $paramod\e1_rx\LIU=0\MFW=7 Used module: \hdb3_dec Used module: \e1_rx_clock_recovery Used module: \e1_rx_filter Used module: \e1_rx_phy Used module: \e1_rx_deframer Used module: \e1_crc4 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7 Used module: \soc_iobuf Used module: $paramod\wb_dma\A0W=14\A1W=9\DW=32 Used module: $paramod\wb_arbiter\N=2\DW=32\AW=9 Used module: $paramod\wb_epbuf\AW=9\DW=32 Used module: $paramod\wb_arbiter\N=3\DW=32\AW=14 Used module: $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0 Used module: $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32 Used module: \xclk_strobe Used module: $paramod\xclk_wb\DW=16\AW=12 Used module: $paramod\usb\EPDW=32 Used module: \usb_ep_status Used module: \usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101 Used module: $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100 Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: \usb_phy Used module: $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb Used module: $paramod\uart_wb\DIV_WIDTH=12\DW=32 Used module: \fifo_sync_ram Used module: $paramod\ram_sdp\AWIDTH=8\DWIDTH=16 Used module: \uart_rx Used module: $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1 Used module: \uart_tx Used module: $paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0 Used module: $paramod\soc_spram\AW=14 Used module: \ice40_spram_gen Used module: $paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram Used module: $paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4 Used module: $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32 Used module: \picorv32_ice40_regs Used module: $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 32 Parameter \WWIDTH = 8 73.2.48. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_ep_buf'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 32 Parameter \WWIDTH = 8 Generating RTLIL representation for module `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf'. READ_MODE : 1 WRITE_MODE : 3 Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 8 Parameter \WWIDTH = 32 73.2.49. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_ep_buf'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 8 Parameter \WWIDTH = 32 Generating RTLIL representation for module `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf'. READ_MODE : 3 WRITE_MODE : 1 Parameter \TARGET = 40'0100100101000011010001010011010000110000 Found cached RTLIL representation for module `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000'. Parameter \DEPTH = 512 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8'. Parameter \DIV_WIDTH = 12 Parameter \GLITCH_FILTER = 2 73.2.50. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'. Parameter \DIV_WIDTH = 12 Parameter \GLITCH_FILTER = 2 Generating RTLIL representation for module `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2'. Parameter \DEPTH = 512 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8'. Parameter \DIV_WIDTH = 12 73.2.51. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'. Parameter \DIV_WIDTH = 12 Generating RTLIL representation for module `$paramod\uart_tx\DIV_WIDTH=12'. Parameter \ADDR_WIDTH = 14 Parameter \DATA_WIDTH = 32 Found cached RTLIL representation for module `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32'. Parameter \LIU = 1 Parameter \MFW = 7 73.2.52. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_wb_rx'. Parameter \LIU = 1 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_wb_rx\LIU=1\MFW=7'. Parameter \LIU = 1 Parameter \MFW = 7 Found cached RTLIL representation for module `$paramod\e1_wb_rx\LIU=1\MFW=7'. 73.2.53. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: $paramod\ice40_spi_wb\N_CS=2\WITH_IOB=1\UNIT=1 Used module: \misc Used module: $paramod\capcnt\W=16 Used module: \capcnt16_sb_mac16 Used module: $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0 Used module: $paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0 Used module: $paramod\capcnt\W=32 Used module: \capcnt32_sb_mac16 Used module: $paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base Used module: $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32 Used module: $paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7 Used module: $paramod\e1_wb_rx\LIU=1\MFW=7 Used module: \e1_rx Used module: \hdb3_dec Used module: \e1_rx_clock_recovery Used module: \e1_rx_filter Used module: \e1_rx_phy Used module: \e1_rx_deframer Used module: \e1_crc4 Used module: \fifo_sync_shift Used module: \soc_iobuf Used module: $paramod\wb_dma\A0W=14\A1W=9\DW=32 Used module: $paramod\wb_arbiter\N=2\DW=32\AW=9 Used module: $paramod\wb_epbuf\AW=9\DW=32 Used module: $paramod\wb_arbiter\N=3\DW=32\AW=14 Used module: $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0 Used module: $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32 Used module: \xclk_strobe Used module: $paramod\xclk_wb\DW=16\AW=12 Used module: $paramod\usb\EPDW=32 Used module: \usb_ep_status Used module: $paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf Used module: $paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101 Used module: $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100 Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000 Used module: $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb Used module: $paramod\uart_wb\DIV_WIDTH=12\DW=32 Used module: $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8 Used module: $paramod\ram_sdp\AWIDTH=9\DWIDTH=8 Used module: $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2 Used module: \glitch_filter Used module: $paramod\uart_tx\DIV_WIDTH=12 Used module: $paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0 Used module: $paramod\soc_spram\AW=14 Used module: $paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram Used module: $paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4 Used module: $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32 Used module: \picorv32_ice40_regs Used module: $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr Parameter \L = 2 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Found cached RTLIL representation for module `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1'. Parameter \LIU = 1 Parameter \MFW = 7 73.2.54. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_rx'. Parameter \LIU = 1 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_rx\LIU=1\MFW=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7'. 73.2.55. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: $paramod\ice40_spi_wb\N_CS=2\WITH_IOB=1\UNIT=1 Used module: \misc Used module: $paramod\capcnt\W=16 Used module: \capcnt16_sb_mac16 Used module: $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0 Used module: $paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0 Used module: $paramod\capcnt\W=32 Used module: \capcnt32_sb_mac16 Used module: $paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base Used module: $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32 Used module: $paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7 Used module: $paramod\e1_wb_rx\LIU=1\MFW=7 Used module: $paramod\e1_rx\LIU=1\MFW=7 Used module: \e1_rx_liu Used module: \e1_rx_deframer Used module: \e1_crc4 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7 Used module: \soc_iobuf Used module: $paramod\wb_dma\A0W=14\A1W=9\DW=32 Used module: $paramod\wb_arbiter\N=2\DW=32\AW=9 Used module: $paramod\wb_epbuf\AW=9\DW=32 Used module: $paramod\wb_arbiter\N=3\DW=32\AW=14 Used module: $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0 Used module: $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32 Used module: \xclk_strobe Used module: $paramod\xclk_wb\DW=16\AW=12 Used module: $paramod\usb\EPDW=32 Used module: \usb_ep_status Used module: $paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf Used module: $paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101 Used module: $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100 Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000 Used module: $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb Used module: $paramod\uart_wb\DIV_WIDTH=12\DW=32 Used module: $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8 Used module: $paramod\ram_sdp\AWIDTH=9\DWIDTH=8 Used module: $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2 Used module: $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1 Used module: $paramod\uart_tx\DIV_WIDTH=12 Used module: $paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0 Used module: $paramod\soc_spram\AW=14 Used module: $paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram Used module: $paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4 Used module: $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32 Used module: \picorv32_ice40_regs Used module: $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr 73.2.56. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: $paramod\ice40_spi_wb\N_CS=2\WITH_IOB=1\UNIT=1 Used module: \misc Used module: $paramod\capcnt\W=16 Used module: \capcnt16_sb_mac16 Used module: $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0 Used module: $paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0 Used module: $paramod\capcnt\W=32 Used module: \capcnt32_sb_mac16 Used module: $paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base Used module: $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32 Used module: $paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7 Used module: $paramod\e1_wb_rx\LIU=1\MFW=7 Used module: $paramod\e1_rx\LIU=1\MFW=7 Used module: \e1_rx_liu Used module: \e1_rx_deframer Used module: \e1_crc4 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7 Used module: \soc_iobuf Used module: $paramod\wb_dma\A0W=14\A1W=9\DW=32 Used module: $paramod\wb_arbiter\N=2\DW=32\AW=9 Used module: $paramod\wb_epbuf\AW=9\DW=32 Used module: $paramod\wb_arbiter\N=3\DW=32\AW=14 Used module: $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0 Used module: $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32 Used module: \xclk_strobe Used module: $paramod\xclk_wb\DW=16\AW=12 Used module: $paramod\usb\EPDW=32 Used module: \usb_ep_status Used module: $paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf Used module: $paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101 Used module: $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100 Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000 Used module: $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb Used module: $paramod\uart_wb\DIV_WIDTH=12\DW=32 Used module: $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8 Used module: $paramod\ram_sdp\AWIDTH=9\DWIDTH=8 Used module: $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2 Used module: $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1 Used module: $paramod\uart_tx\DIV_WIDTH=12 Used module: $paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0 Used module: $paramod\soc_spram\AW=14 Used module: $paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram Used module: $paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4 Used module: $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32 Used module: \picorv32_ice40_regs Used module: $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr Removing unused module `$paramod$e9a8417cc0e9fc03e370009e77135e9e1e2b5499\usb_ep_buf'. Removing unused module `$paramod$7d82212fad3e4929db14b64ca83adffce21ba555\usb_ep_buf'. Removing unused module `$paramod\uart_tx\DIV_WIDTH=8'. Removing unused module `$paramod\uart_rx\DIV_WIDTH=8\GLITCH_FILTER=2'. Removing unused module `$paramod\ram_sdp\AWIDTH=8\DWIDTH=16'. Removing unused module `$paramod\e1_wb_rx\LIU=0\MFW=7'. Removing unused module `$paramod\e1_wb_tx\LIU=0\MFW=7'. Removing unused module `$paramod\e1_tx\LIU=0\MFW=7'. Removing unused module `$paramod\e1_rx\LIU=0\MFW=7'. Removing unused module `$paramod\soc_picorv32_bridge\WB_N=9\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4'. Removing unused module `$paramod\e1_wb\N=1\UNIT_HAS_RX=1'1\UNIT_HAS_TX=1'1\LIU=0\MFW=7'. Removing unused module `$paramod\e1_buf_if_wb\N=1\UNIT_HAS_RX=1'1\UNIT_HAS_TX=1'1\MFW=7\DW=32'. Removing unused module `\wb_epbuf'. Removing unused module `\wb_dma'. Removing unused module `\wb_arbiter'. Removing unused module `\soc_spram'. Removing unused module `\soc_picorv32_bridge'. Removing unused module `\soc_bram'. Removing unused module `\soc_base'. Removing unused module `\picorv32_wb'. Removing unused module `\picorv32_axi_adapter'. Removing unused module `\picorv32_axi'. Removing unused module `\picorv32_pcpi_div'. Removing unused module `\picorv32_pcpi_fast_mul'. Removing unused module `\picorv32_pcpi_mul'. Removing unused module `\picorv32_regs'. Removing unused module `\picorv32'. Removing unused module `\dfu_helper'. Removing unused module `\capcnt'. Removing unused module `\usb_phy'. Removing unused module `\usb_ep_buf'. Removing unused module `\usb_crc'. Removing unused module `\usb'. Removing unused module `\xclk_wb'. Removing unused module `\uart_wb'. Removing unused module `\uart_tx'. Removing unused module `\uart_rx'. Removing unused module `\uart2wb'. Removing unused module `\stream2wb'. Removing unused module `\ram_sdp'. Removing unused module `\pwm'. Removing unused module `\pdm_lfsr'. Removing unused module `\pdm'. Removing unused module `\dffesr_n'. Removing unused module `\dffer_n'. Removing unused module `\dffe_n'. Removing unused module `\dff_n'. Removing unused module `\lut4_carry_n'. Removing unused module `\lut4_n'. Removing unused module `\muacm2wb'. Removing unused module `\i2c_master_wb'. Removing unused module `\i2c_master'. Removing unused module `\glitch_filter'. Removing unused module `\fifo_sync_shift'. Removing unused module `\fifo_sync_ram'. Removing unused module `\delay_bus'. Removing unused module `\delay_bit'. Removing unused module `\ice40_serdes_sync'. Removing unused module `\ice40_serdes_dff'. Removing unused module `\ice40_serdes_crg'. Removing unused module `\ice40_oserdes'. Removing unused module `\ice40_iserdes'. Removing unused module `\ice40_spram_wb'. Removing unused module `\ice40_spram_gen'. Removing unused module `\ice40_spi_wb'. Removing unused module `\ice40_rgb_wb'. Removing unused module `\ice40_i2c_wb'. Removing unused module `\ice40_ebr'. Removing unused module `\hdb3_enc'. Removing unused module `\hdb3_dec'. Removing unused module `\e1_wb'. Removing unused module `\e1_wb_tx'. Removing unused module `\e1_wb_rx'. Removing unused module `\e1_buf_if_wb'. Removing unused module `\e1_tx'. Removing unused module `\e1_tx_liu'. Removing unused module `\e1_tx_phy'. Removing unused module `\e1_tx_framer'. Removing unused module `\e1_rx'. Removing unused module `\e1_rx_phy'. Removing unused module `\e1_rx_filter'. Removing unused module `\e1_rx_clock_recovery'. Removed 82 unused modules. 73.3. Executing PROC pass (convert processes to netlists). 73.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5232'. Removing empty process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4484'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5177'. Found and cleaned up 1 empty switch in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4098'. Found and cleaned up 15 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. Found and cleaned up 1 empty switch in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$3900'. Found and cleaned up 6 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:530$3546'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:530$3546'. Found and cleaned up 1 empty switch in `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:0$3352'. Removing empty process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:0$3352'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:471$3221'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:471$3221'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$135'. Cleaned up 26 empty switches. 73.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:909$2917 in module SB_DFFNSR. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$2909 in module SB_DFFES. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:697$2902 in module SB_DFFESS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$2898 in module SB_DFFER. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:566$2891 in module SB_DFFESR. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:497$2888 in module SB_DFFS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:449$2885 in module SB_DFFSS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:380$2882 in module SB_DFFR. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:332$2879 in module SB_DFFSR. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_epbuf.v:51$4862 in module $paramod\wb_epbuf\AW=9\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_arbiter.v:116$4851 in module $paramod\wb_arbiter\N=2\DW=32\AW=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_arbiter.v:80$4841 in module $paramod\wb_arbiter\N=2\DW=32\AW=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_dma.v:190$4809 in module $paramod\wb_dma\A0W=14\A1W=9\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_dma.v:98$4770 in module $paramod\wb_dma\A0W=14\A1W=9\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_dma.v:92$4769 in module $paramod\wb_dma\A0W=14\A1W=9\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_dma.v:86$4765 in module $paramod\wb_dma\A0W=14\A1W=9\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4741 in module $paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4737 in module $paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4733 in module $paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4725 in module $paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0. Removed 2 dead cases from process $proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4686 in module $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4686 in module $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:212$5316 in module $paramod\e1_rx\LIU=1\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:197$5306 in module $paramod\e1_rx\LIU=1\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:248$5296 in module $paramod\e1_wb_rx\LIU=1\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:241$5294 in module $paramod\e1_wb_rx\LIU=1\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$5276 in module $paramod\e1_wb_rx\LIU=1\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$5275 in module $paramod\e1_wb_rx\LIU=1\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$5267 in module $paramod\e1_wb_rx\LIU=1\MFW=7. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5265 in module $paramod\uart_tx\DIV_WIDTH=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:51$5262 in module $paramod\uart_tx\DIV_WIDTH=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:42$5258 in module $paramod\uart_tx\DIV_WIDTH=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:35$5254 in module $paramod\uart_tx\DIV_WIDTH=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:88$5244 in module $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:77$5240 in module $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:70$5236 in module $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4537 in module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4531 in module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4529 in module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:83$4520 in module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:67$4514 in module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4508 in module $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4504 in module $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4500 in module $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4492 in module $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1. Marked 16 switch rules as full_case in process $proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327 in module $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/e1-tracer/rtl/sysmgr.v:81$1598 in module sysmgr. Marked 1 switch rules as full_case in process $proc$/build/gateware/e1-tracer/rtl/misc.v:131$1596 in module misc. Marked 2 switch rules as full_case in process $proc$/build/gateware/e1-tracer/rtl/misc.v:80$1592 in module misc. Marked 1 switch rules as full_case in process $proc$/build/gateware/e1-tracer/rtl/misc.v:70$1587 in module misc. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:159$1546 in module usb_tx_pkt. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:126$1530 in module usb_tx_pkt. Marked 8 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:86$1528 in module usb_tx_pkt. Removed 1 dead cases from process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1525 in module usb_tx_ll. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1525 in module usb_tx_ll. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1503 in module usb_tx_ll. Marked 4 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1497 in module usb_tx_ll. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:236$1493 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:421$1482 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:387$1466 in module usb_trans. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1451 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:345$1448 in module usb_trans. Marked 5 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1443 in module usb_trans. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1432 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:225$1427 in module usb_trans. Removed 1 dead cases from process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1424 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1424 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:175$1415 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:162$1406 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1343 in module usb_rx_pkt. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:244$1340 in module usb_rx_pkt. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:230$1337 in module usb_rx_pkt. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:220$1334 in module usb_rx_pkt. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:188$1324 in module usb_rx_pkt. Marked 18 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:117$1308 in module usb_rx_pkt. Removed 1 dead cases from process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1303 in module usb_rx_ll. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1303 in module usb_rx_ll. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:137$1302 in module usb_rx_ll. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:124$1301 in module usb_rx_ll. Removed 1 dead cases from process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1285 in module usb_rx_ll. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1285 in module usb_rx_ll. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:67$1275 in module usb_rx_ll. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:163$5111 in module $paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4211 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4209 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4200 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4198 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4189 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4187 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4178 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4176 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4165 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4163 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4154 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4152 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4143 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4141 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4132 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4130 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:124$5037 in module $paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:40$1103 in module xclk_strobe. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:34$1102 in module xclk_strobe. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:28$1100 in module xclk_strobe. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/dfu_helper.v:149$4107 in module $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0. Marked 2 switch rules as full_case in process $proc$/build/gateware/common/rtl/dfu_helper.v:120$4098 in module $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/dfu_helper.v:109$4094 in module $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/dfu_helper.v:103$4092 in module $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0. Marked 37 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:1375$3914 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 2 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:1288$3886 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 2 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:1274$3881 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 8 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:1165$3846 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 3 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:840$3586 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 3 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:791$3584 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 2 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:760$3580 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 47 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:684$3579 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 4 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:549$3555 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:414$3517 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Removed 2 dead cases from process $proc$/build/gateware/common/rtl/picorv32.v:385$3514 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 2 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:385$3514 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:374$3509 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:309$3435 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5012 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5006 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$4995 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32. Marked 5 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4962 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:206$4957 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32. Marked 4 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$4955 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:185$3314 in module $paramod\uart_wb\DIV_WIDTH=12\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:177$3304 in module $paramod\uart_wb\DIV_WIDTH=12\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3287 in module $paramod\uart_wb\DIV_WIDTH=12\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:154$3282 in module $paramod\uart_wb\DIV_WIDTH=12\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3275 in module $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:536$3269 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:643$3261 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:636$3257 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:628$3253 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:619$3249 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:514$3235 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3222 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3220 in module $paramod\usb\EPDW=32. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:442$3216 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3198 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:99$3194 in module $paramod\xclk_wb\DW=16\AW=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:73$3187 in module $paramod\xclk_wb\DW=16\AW=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v:50$4926 in module $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_arbiter.v:116$4905 in module $paramod\wb_arbiter\N=3\DW=32\AW=14. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_arbiter.v:80$4893 in module $paramod\wb_arbiter\N=3\DW=32\AW=14. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/soc_base.v:184$3098 in module $paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$2947 in module SB_DFFNES. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1274$2940 in module SB_DFFNESS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$2936 in module SB_DFFNER. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1143$2929 in module SB_DFFNESR. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1074$2926 in module SB_DFFNS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1026$2923 in module SB_DFFNSS. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:406$141 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$135 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$109 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$89 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$67 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:274$55 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:266$51 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:258$47 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$37 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:219$33 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:207$29 in module e1_rx_deframer. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:149$21 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:142$19 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:121$14 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:957$2920 in module SB_DFFNR. Removed a total of 8 dead cases. 73.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 122 redundant assignments. Promoted 277 assignments to connections. 73.3.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2919'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2916'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2914'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2912'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2908'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2901'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2897'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2890'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2887'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2884'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2881'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2878'. Set init value: \Q = 1'0 Found init rule in `\SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2876'. Set init value: \Q = 1'0 Found init rule in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:49$1307'. Set init value: \dec_sym_1 = 2'00 Found init rule in `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2950'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2946'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2939'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2935'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2928'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2925'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2922'. Set init value: \Q = 1'0 73.3.5. Executing PROC_ARST pass (detect async resets in processes). Found async reset \S in `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$2909'. Found async reset \R in `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$2898'. Found async reset \S in `\SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:497$2888'. Found async reset \R in `\SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:380$2882'. Found async reset \rst in `$paramod\wb_epbuf\AW=9\DW=32.$proc$/build/gateware/common/rtl/wb_epbuf.v:51$4862'. Found async reset \rst in `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4851'. Found async reset \rst in `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4841'. Found async reset \rst in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$4809'. Found async reset \rst in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:92$4769'. Found async reset \rst in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:86$4765'. Found async reset \rst in `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4686'. Found async reset \rst in `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:212$5316'. Found async reset \rst in `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:197$5306'. Found async reset \rst in `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:248$5296'. Found async reset \rst in `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:241$5294'. Found async reset \rst in `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$5275'. Found async reset \rst in `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5265'. Found async reset \rst in `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:35$5254'. Found async reset \rst in `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:70$5236'. Found async reset \rst in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4537'. Found async reset \rst in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4531'. Found async reset \rst in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4529'. Found async reset \rst in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:83$4520'. Found async reset \rst in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:67$4514'. Found async reset \pll_lock in `\sysmgr.$proc$/build/gateware/e1-tracer/rtl/sysmgr.v:81$1598'. Found async reset \rst in `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:131$1596'. Found async reset \rst in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:126$1530'. Found async reset \rst in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1525'. Found async reset \ll_start in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1503'. Found async reset \rst in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1497'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:387$1466'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:345$1448'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1443'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1432'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:225$1427'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:175$1415'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:162$1406'. Found async reset \rst in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:188$1324'. Found async reset \rst in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:67$1275'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4211'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4209'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4200'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4198'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4189'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4187'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4178'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4176'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4165'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4163'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4154'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4152'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4143'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4141'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4132'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4130'. Found async reset \rst in `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:40$1103'. Found async reset \rst in `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:34$1102'. Found async reset \rst in `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:28$1100'. Found async reset \rst in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:149$4107'. Found async reset \rst in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4098'. Found async reset \rst in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:109$4094'. Found async reset \rst in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:103$4092'. Found async reset \rst in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5012'. Found async reset \rst in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5006'. Found async reset \rst in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:206$4957'. Found async reset \rst in `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:154$3282'. Found async reset \rst in `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.$proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3275'. Found async reset \rst in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:536$3269'. Found async reset \rst in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:636$3257'. Found async reset \rst in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:514$3235'. Found async reset \rst in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3220'. Found async reset \rst in `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:99$3194'. Found async reset \rst in `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v:50$4926'. Found async reset \rst in `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4905'. Found async reset \rst in `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4893'. Found async reset \rst_sys in `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:184$3098'. Found async reset \S in `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$2947'. Found async reset \R in `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$2936'. Found async reset \S in `\SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1074$2926'. Found async reset \R in `\SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:957$2920'. 73.3.6. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2919'. Creating decoders for process `\SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:909$2917'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2916'. Creating decoders for process `\SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:866$2915'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2914'. Creating decoders for process `\SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:830$2913'. Creating decoders for process `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2912'. Creating decoders for process `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$2909'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2908'. Creating decoders for process `\SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:697$2902'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2901'. Creating decoders for process `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$2898'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2897'. Creating decoders for process `\SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:566$2891'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2890'. Creating decoders for process `\SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:497$2888'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2887'. Creating decoders for process `\SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:449$2885'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2884'. Creating decoders for process `\SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:380$2882'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2881'. Creating decoders for process `\SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:332$2879'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2878'. Creating decoders for process `\SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:289$2877'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2876'. Creating decoders for process `\SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:253$2875'. Creating decoders for process `$paramod\wb_epbuf\AW=9\DW=32.$proc$/build/gateware/common/rtl/wb_epbuf.v:51$4862'. 1/1: $0\ack_i[0:0] Creating decoders for process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4851'. 1/2: $0\busy[0:0] 2/2: $0\sel[1:0] Creating decoders for process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$4844'. 1/2: $0\sel_nxt[1:0] [1] 2/2: $0\sel_nxt[1:0] [0] Creating decoders for process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4841'. 1/4: $0\m_wmsk[3:0] 2/4: $0\m_we[0:0] 3/4: $0\m_wdata[31:0] 4/4: $0\m_addr[8:0] Creating decoders for process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4828'. Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$4809'. 1/3: $0\ctl_ack_i[0:0] 2/3: $0\ctl_do_read[0:0] 3/3: $0\ctl_do_write[0:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:178$4805'. 1/1: $0\dir[0:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:174$4802'. 1/1: $0\len[12:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:157$4792'. 1/1: $0\m1_addr_i[8:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:153$4788'. 1/1: $0\m0_addr_i[13:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:142$4786'. 1/1: $0\data_reg[31:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:98$4770'. 1/1: $0\state_nxt[1:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:92$4769'. 1/1: $0\state[1:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:86$4765'. 1/1: $0\go[0:0] Creating decoders for process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4761'. Creating decoders for process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4757'. Creating decoders for process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4753'. Creating decoders for process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4746'. Creating decoders for process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4741'. 1/2: $0\fall[0:0] 2/2: $0\rise[0:0] Creating decoders for process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4737'. 1/1: $0\state[0:0] Creating decoders for process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4733'. 1/1: $0\cnt[3:0] Creating decoders for process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4725'. 1/2: $2\cnt_move[3:0] 2/2: $1\cnt_move[3:0] Creating decoders for process `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4723'. 1/1: $0\state[4:0] Creating decoders for process `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4710'. 1/1: $0\state[15:0] Creating decoders for process `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4686'. 1/2: $0\dn_state[2:0] 2/2: $0\dp_state[2:0] Creating decoders for process `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:212$5316'. 1/1: $0\bd_crc_e[1:0] Creating decoders for process `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:205$5310'. Creating decoders for process `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:197$5306'. 1/1: $0\mf_valid[0:0] Creating decoders for process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:255$5300'. Creating decoders for process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:248$5296'. 1/1: $0\rx_overflow[0:0] Creating decoders for process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:241$5294'. 1/1: $0\rx_rst[0:0] Creating decoders for process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$5276'. 1/2: $0\bro_rden[0:0] 2/2: $0\bri_wren[0:0] Creating decoders for process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$5275'. 1/2: $0\rx_mode[1:0] 2/2: $0\rx_enabled[0:0] Creating decoders for process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$5267'. 1/2: $0\crx_clear[0:0] 2/2: $0\crx_wren[0:0] Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:67$5266'. Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5265'. 1/1: $0\shift[9:0] Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:51$5262'. 1/1: $0\bit_cnt[4:0] Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:42$5258'. 1/1: $0\div_cnt[12:0] Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:35$5254'. 1/1: $0\active[0:0] Creating decoders for process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:102$5248'. Creating decoders for process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:95$5247'. 1/1: $0\shift[8:0] Creating decoders for process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:88$5244'. 1/1: $0\bit_cnt[4:0] Creating decoders for process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:77$5240'. 1/1: $0\div_cnt[12:0] Creating decoders for process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:70$5236'. 1/1: $0\active[0:0] Creating decoders for process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4537'. 1/1: $0\rd_valid[0:0] Creating decoders for process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4531'. 1/1: $0\ram_rd_addr[8:0] Creating decoders for process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4529'. 1/1: $0\ram_wr_addr[8:0] Creating decoders for process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:83$4520'. 1/1: $0\full[0:0] Creating decoders for process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:67$4514'. 1/1: $0\level[9:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4513'. Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4508'. 1/2: $0\fall[0:0] 2/2: $0\rise[0:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4504'. 1/1: $0\state[0:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4500'. 1/1: $0\cnt[1:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4492'. 1/2: $2\cnt_move[1:0] 2/2: $1\cnt_move[1:0] Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5228'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5224'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5220'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5216'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5212'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5208'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5204'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5200'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5196'. Creating decoders for process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4483'. Creating decoders for process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327'. 1/320: $8\mem_dm_w[7:0] [7] 2/320: $8\mem_dm_w[7:0] [4] 3/320: $8\mem_dm_w[7:0] [2] 4/320: $8\mem_dm_w[7:0] [0] 5/320: $8\mem_dm_w[7:0] [6] 6/320: $8\mem_dm_w[7:0] [1] 7/320: $8\mem_dm_w[7:0] [3] 8/320: $8\mem_dm_w[7:0] [5] 9/320: $8\mem_di_w[31:0] [31] 10/320: $8\mem_di_w[31:0] [24] 11/320: $8\mem_di_w[31:0] [22] 12/320: $8\mem_di_w[31:0] [20] 13/320: $8\mem_di_w[31:0] [18] 14/320: $8\mem_di_w[31:0] [16] 15/320: $8\mem_di_w[31:0] [14] 16/320: $8\mem_di_w[31:0] [12] 17/320: $8\mem_di_w[31:0] [10] 18/320: $8\mem_di_w[31:0] [8] 19/320: $8\mem_di_w[31:0] [6] 20/320: $8\mem_di_w[31:0] [4] 21/320: $8\mem_di_w[31:0] [2] 22/320: $8\mem_di_w[31:0] [0] 23/320: $8\mem_di_w[31:0] [30] 24/320: $8\mem_di_w[31:0] [27] 25/320: $8\mem_di_w[31:0] [23] 26/320: $8\mem_di_w[31:0] [21] 27/320: $8\mem_di_w[31:0] [17] 28/320: $8\mem_di_w[31:0] [13] 29/320: $8\mem_di_w[31:0] [9] 30/320: $8\mem_di_w[31:0] [5] 31/320: $8\mem_di_w[31:0] [1] 32/320: $8\mem_di_w[31:0] [28] 33/320: $8\mem_di_w[31:0] [26] 34/320: $8\mem_di_w[31:0] [15] 35/320: $8\mem_di_w[31:0] [3] 36/320: $8\mem_di_w[31:0] [7] 37/320: $8\mem_di_w[31:0] [25] 38/320: $8\mem_di_w[31:0] [19] 39/320: $8\mem_di_w[31:0] [29] 40/320: $8\mem_di_w[31:0] [11] 41/320: $7\mem_dm_w[7:0] [7] 42/320: $7\mem_dm_w[7:0] [4] 43/320: $7\mem_dm_w[7:0] [2] 44/320: $7\mem_dm_w[7:0] [0] 45/320: $7\mem_dm_w[7:0] [6] 46/320: $7\mem_dm_w[7:0] [1] 47/320: $7\mem_dm_w[7:0] [3] 48/320: $7\mem_dm_w[7:0] [5] 49/320: $7\mem_di_w[31:0] [31] 50/320: $7\mem_di_w[31:0] [24] 51/320: $7\mem_di_w[31:0] [22] 52/320: $7\mem_di_w[31:0] [20] 53/320: $7\mem_di_w[31:0] [18] 54/320: $7\mem_di_w[31:0] [16] 55/320: $7\mem_di_w[31:0] [14] 56/320: $7\mem_di_w[31:0] [12] 57/320: $7\mem_di_w[31:0] [10] 58/320: $7\mem_di_w[31:0] [8] 59/320: $7\mem_di_w[31:0] [6] 60/320: $7\mem_di_w[31:0] [4] 61/320: $7\mem_di_w[31:0] [2] 62/320: $7\mem_di_w[31:0] [0] 63/320: $7\mem_di_w[31:0] [30] 64/320: $7\mem_di_w[31:0] [27] 65/320: $7\mem_di_w[31:0] [23] 66/320: $7\mem_di_w[31:0] [21] 67/320: $7\mem_di_w[31:0] [17] 68/320: $7\mem_di_w[31:0] [13] 69/320: $7\mem_di_w[31:0] [9] 70/320: $7\mem_di_w[31:0] [5] 71/320: $7\mem_di_w[31:0] [1] 72/320: $7\mem_di_w[31:0] [28] 73/320: $7\mem_di_w[31:0] [26] 74/320: $7\mem_di_w[31:0] [15] 75/320: $7\mem_di_w[31:0] [3] 76/320: $7\mem_di_w[31:0] [7] 77/320: $7\mem_di_w[31:0] [25] 78/320: $7\mem_di_w[31:0] [19] 79/320: $7\mem_di_w[31:0] [29] 80/320: $7\mem_di_w[31:0] [11] 81/320: $6\mem_dm_w[7:0] [7] 82/320: $6\mem_dm_w[7:0] [4] 83/320: $6\mem_dm_w[7:0] [2] 84/320: $6\mem_dm_w[7:0] [0] 85/320: $6\mem_dm_w[7:0] [6] 86/320: $6\mem_dm_w[7:0] [1] 87/320: $6\mem_dm_w[7:0] [3] 88/320: $6\mem_dm_w[7:0] [5] 89/320: $6\mem_di_w[31:0] [31] 90/320: $6\mem_di_w[31:0] [24] 91/320: $6\mem_di_w[31:0] [22] 92/320: $6\mem_di_w[31:0] [20] 93/320: $6\mem_di_w[31:0] [18] 94/320: $6\mem_di_w[31:0] [16] 95/320: $6\mem_di_w[31:0] [14] 96/320: $6\mem_di_w[31:0] [12] 97/320: $6\mem_di_w[31:0] [10] 98/320: $6\mem_di_w[31:0] [8] 99/320: $6\mem_di_w[31:0] [6] 100/320: $6\mem_di_w[31:0] [4] 101/320: $6\mem_di_w[31:0] [2] 102/320: $6\mem_di_w[31:0] [0] 103/320: $6\mem_di_w[31:0] [30] 104/320: $6\mem_di_w[31:0] [27] 105/320: $6\mem_di_w[31:0] [23] 106/320: $6\mem_di_w[31:0] [21] 107/320: $6\mem_di_w[31:0] [17] 108/320: $6\mem_di_w[31:0] [13] 109/320: $6\mem_di_w[31:0] [9] 110/320: $6\mem_di_w[31:0] [5] 111/320: $6\mem_di_w[31:0] [1] 112/320: $6\mem_di_w[31:0] [28] 113/320: $6\mem_di_w[31:0] [26] 114/320: $6\mem_di_w[31:0] [15] 115/320: $6\mem_di_w[31:0] [3] 116/320: $6\mem_di_w[31:0] [7] 117/320: $6\mem_di_w[31:0] [25] 118/320: $6\mem_di_w[31:0] [19] 119/320: $6\mem_di_w[31:0] [29] 120/320: $6\mem_di_w[31:0] [11] 121/320: $5\mem_dm_w[7:0] [7] 122/320: $5\mem_dm_w[7:0] [4] 123/320: $5\mem_dm_w[7:0] [2] 124/320: $5\mem_dm_w[7:0] [0] 125/320: $5\mem_dm_w[7:0] [6] 126/320: $5\mem_dm_w[7:0] [1] 127/320: $5\mem_dm_w[7:0] [3] 128/320: $5\mem_dm_w[7:0] [5] 129/320: $5\mem_di_w[31:0] [31] 130/320: $5\mem_di_w[31:0] [24] 131/320: $5\mem_di_w[31:0] [22] 132/320: $5\mem_di_w[31:0] [20] 133/320: $5\mem_di_w[31:0] [18] 134/320: $5\mem_di_w[31:0] [16] 135/320: $5\mem_di_w[31:0] [14] 136/320: $5\mem_di_w[31:0] [12] 137/320: $5\mem_di_w[31:0] [10] 138/320: $5\mem_di_w[31:0] [8] 139/320: $5\mem_di_w[31:0] [6] 140/320: $5\mem_di_w[31:0] [4] 141/320: $5\mem_di_w[31:0] [2] 142/320: $5\mem_di_w[31:0] [0] 143/320: $5\mem_di_w[31:0] [30] 144/320: $5\mem_di_w[31:0] [27] 145/320: $5\mem_di_w[31:0] [23] 146/320: $5\mem_di_w[31:0] [21] 147/320: $5\mem_di_w[31:0] [17] 148/320: $5\mem_di_w[31:0] [13] 149/320: $5\mem_di_w[31:0] [9] 150/320: $5\mem_di_w[31:0] [5] 151/320: $5\mem_di_w[31:0] [1] 152/320: $5\mem_di_w[31:0] [28] 153/320: $5\mem_di_w[31:0] [26] 154/320: $5\mem_di_w[31:0] [15] 155/320: $5\mem_di_w[31:0] [3] 156/320: $5\mem_di_w[31:0] [7] 157/320: $5\mem_di_w[31:0] [25] 158/320: $5\mem_di_w[31:0] [19] 159/320: $5\mem_di_w[31:0] [29] 160/320: $5\mem_di_w[31:0] [11] 161/320: $4\mem_dm_w[7:0] [7] 162/320: $4\mem_dm_w[7:0] [4] 163/320: $4\mem_dm_w[7:0] [2] 164/320: $4\mem_dm_w[7:0] [0] 165/320: $4\mem_dm_w[7:0] [6] 166/320: $4\mem_dm_w[7:0] [1] 167/320: $4\mem_dm_w[7:0] [3] 168/320: $4\mem_dm_w[7:0] [5] 169/320: $4\mem_di_w[31:0] [31] 170/320: $4\mem_di_w[31:0] [24] 171/320: $4\mem_di_w[31:0] [22] 172/320: $4\mem_di_w[31:0] [20] 173/320: $4\mem_di_w[31:0] [18] 174/320: $4\mem_di_w[31:0] [16] 175/320: $4\mem_di_w[31:0] [14] 176/320: $4\mem_di_w[31:0] [12] 177/320: $4\mem_di_w[31:0] [10] 178/320: $4\mem_di_w[31:0] [8] 179/320: $4\mem_di_w[31:0] [6] 180/320: $4\mem_di_w[31:0] [4] 181/320: $4\mem_di_w[31:0] [2] 182/320: $4\mem_di_w[31:0] [0] 183/320: $4\mem_di_w[31:0] [30] 184/320: $4\mem_di_w[31:0] [27] 185/320: $4\mem_di_w[31:0] [23] 186/320: $4\mem_di_w[31:0] [21] 187/320: $4\mem_di_w[31:0] [17] 188/320: $4\mem_di_w[31:0] [13] 189/320: $4\mem_di_w[31:0] [9] 190/320: $4\mem_di_w[31:0] [5] 191/320: $4\mem_di_w[31:0] [1] 192/320: $4\mem_di_w[31:0] [28] 193/320: $4\mem_di_w[31:0] [26] 194/320: $4\mem_di_w[31:0] [15] 195/320: $4\mem_di_w[31:0] [3] 196/320: $4\mem_di_w[31:0] [7] 197/320: $4\mem_di_w[31:0] [25] 198/320: $4\mem_di_w[31:0] [19] 199/320: $4\mem_di_w[31:0] [29] 200/320: $4\mem_di_w[31:0] [11] 201/320: $3\mem_dm_w[7:0] [7] 202/320: $3\mem_dm_w[7:0] [4] 203/320: $3\mem_dm_w[7:0] [2] 204/320: $3\mem_dm_w[7:0] [0] 205/320: $3\mem_dm_w[7:0] [6] 206/320: $3\mem_dm_w[7:0] [1] 207/320: $3\mem_dm_w[7:0] [3] 208/320: $3\mem_dm_w[7:0] [5] 209/320: $3\mem_di_w[31:0] [31] 210/320: $3\mem_di_w[31:0] [24] 211/320: $3\mem_di_w[31:0] [22] 212/320: $3\mem_di_w[31:0] [20] 213/320: $3\mem_di_w[31:0] [18] 214/320: $3\mem_di_w[31:0] [16] 215/320: $3\mem_di_w[31:0] [14] 216/320: $3\mem_di_w[31:0] [12] 217/320: $3\mem_di_w[31:0] [10] 218/320: $3\mem_di_w[31:0] [8] 219/320: $3\mem_di_w[31:0] [6] 220/320: $3\mem_di_w[31:0] [4] 221/320: $3\mem_di_w[31:0] [2] 222/320: $3\mem_di_w[31:0] [0] 223/320: $3\mem_di_w[31:0] [30] 224/320: $3\mem_di_w[31:0] [27] 225/320: $3\mem_di_w[31:0] [23] 226/320: $3\mem_di_w[31:0] [21] 227/320: $3\mem_di_w[31:0] [17] 228/320: $3\mem_di_w[31:0] [13] 229/320: $3\mem_di_w[31:0] [9] 230/320: $3\mem_di_w[31:0] [5] 231/320: $3\mem_di_w[31:0] [1] 232/320: $3\mem_di_w[31:0] [28] 233/320: $3\mem_di_w[31:0] [26] 234/320: $3\mem_di_w[31:0] [15] 235/320: $3\mem_di_w[31:0] [3] 236/320: $3\mem_di_w[31:0] [7] 237/320: $3\mem_di_w[31:0] [25] 238/320: $3\mem_di_w[31:0] [19] 239/320: $3\mem_di_w[31:0] [29] 240/320: $3\mem_di_w[31:0] [11] 241/320: $2\mem_dm_w[7:0] [7] 242/320: $2\mem_dm_w[7:0] [4] 243/320: $2\mem_dm_w[7:0] [2] 244/320: $2\mem_dm_w[7:0] [0] 245/320: $2\mem_dm_w[7:0] [6] 246/320: $2\mem_dm_w[7:0] [1] 247/320: $2\mem_dm_w[7:0] [3] 248/320: $2\mem_dm_w[7:0] [5] 249/320: $2\mem_di_w[31:0] [31] 250/320: $2\mem_di_w[31:0] [24] 251/320: $2\mem_di_w[31:0] [22] 252/320: $2\mem_di_w[31:0] [20] 253/320: $2\mem_di_w[31:0] [18] 254/320: $2\mem_di_w[31:0] [16] 255/320: $2\mem_di_w[31:0] [14] 256/320: $2\mem_di_w[31:0] [12] 257/320: $2\mem_di_w[31:0] [10] 258/320: $2\mem_di_w[31:0] [8] 259/320: $2\mem_di_w[31:0] [6] 260/320: $2\mem_di_w[31:0] [4] 261/320: $2\mem_di_w[31:0] [2] 262/320: $2\mem_di_w[31:0] [0] 263/320: $2\mem_di_w[31:0] [30] 264/320: $2\mem_di_w[31:0] [27] 265/320: $2\mem_di_w[31:0] [23] 266/320: $2\mem_di_w[31:0] [21] 267/320: $2\mem_di_w[31:0] [17] 268/320: $2\mem_di_w[31:0] [13] 269/320: $2\mem_di_w[31:0] [9] 270/320: $2\mem_di_w[31:0] [5] 271/320: $2\mem_di_w[31:0] [1] 272/320: $2\mem_di_w[31:0] [28] 273/320: $2\mem_di_w[31:0] [26] 274/320: $2\mem_di_w[31:0] [15] 275/320: $2\mem_di_w[31:0] [3] 276/320: $2\mem_di_w[31:0] [7] 277/320: $2\mem_di_w[31:0] [25] 278/320: $2\mem_di_w[31:0] [19] 279/320: $2\mem_di_w[31:0] [29] 280/320: $2\mem_di_w[31:0] [11] 281/320: $1\mem_dm_w[7:0] [7] 282/320: $1\mem_dm_w[7:0] [4] 283/320: $1\mem_dm_w[7:0] [2] 284/320: $1\mem_dm_w[7:0] [0] 285/320: $1\mem_dm_w[7:0] [6] 286/320: $1\mem_dm_w[7:0] [1] 287/320: $1\mem_dm_w[7:0] [3] 288/320: $1\mem_dm_w[7:0] [5] 289/320: $1\mem_di_w[31:0] [31] 290/320: $1\mem_di_w[31:0] [24] 291/320: $1\mem_di_w[31:0] [22] 292/320: $1\mem_di_w[31:0] [20] 293/320: $1\mem_di_w[31:0] [18] 294/320: $1\mem_di_w[31:0] [16] 295/320: $1\mem_di_w[31:0] [14] 296/320: $1\mem_di_w[31:0] [12] 297/320: $1\mem_di_w[31:0] [10] 298/320: $1\mem_di_w[31:0] [8] 299/320: $1\mem_di_w[31:0] [6] 300/320: $1\mem_di_w[31:0] [4] 301/320: $1\mem_di_w[31:0] [2] 302/320: $1\mem_di_w[31:0] [0] 303/320: $1\mem_di_w[31:0] [30] 304/320: $1\mem_di_w[31:0] [27] 305/320: $1\mem_di_w[31:0] [23] 306/320: $1\mem_di_w[31:0] [21] 307/320: $1\mem_di_w[31:0] [17] 308/320: $1\mem_di_w[31:0] [13] 309/320: $1\mem_di_w[31:0] [9] 310/320: $1\mem_di_w[31:0] [5] 311/320: $1\mem_di_w[31:0] [1] 312/320: $1\mem_di_w[31:0] [28] 313/320: $1\mem_di_w[31:0] [26] 314/320: $1\mem_di_w[31:0] [15] 315/320: $1\mem_di_w[31:0] [3] 316/320: $1\mem_di_w[31:0] [7] 317/320: $1\mem_di_w[31:0] [25] 318/320: $1\mem_di_w[31:0] [19] 319/320: $1\mem_di_w[31:0] [29] 320/320: $1\mem_di_w[31:0] [11] Creating decoders for process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:73$4326'. 1/1: $0\addr_r[13:0] Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5173'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5169'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5165'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5161'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5157'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5153'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5149'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5145'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5141'. Creating decoders for process `\sysmgr.$proc$/build/gateware/e1-tracer/rtl/sysmgr.v:81$1598'. 1/1: $0\rst_cnt[3:0] Creating decoders for process `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:131$1596'. 1/2: $0\boot_now[0:0] 2/2: $0\boot_sel[1:0] Creating decoders for process `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:95$1593'. 1/2: $0\tick_e1_sel[1][1:0] 2/2: $0\tick_e1_sel[0][1:0] Creating decoders for process `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:80$1592'. 1/1: $0\wb_rdata[31:0] Creating decoders for process `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:70$1587'. 1/2: $0\bus_we_tick_sel[0:0] 2/2: $0\bus_we_boot[0:0] Creating decoders for process `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:64$1582'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:241$1578'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:229$1575'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:202$1569'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:191$1565'. 1/1: $0\len[10:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:182$1559'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:175$1552'. 1/2: $0\shift_last_byte[0:0] 2/2: $0\shift_data_crc[0:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:170$1550'. 1/1: $0\shift_data[7:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:159$1546'. 1/1: $0\shift_load[7:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:152$1543'. 1/1: $0\shift_bit[3:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:136$1531'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:126$1530'. 1/1: $0\state[3:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:86$1528'. 1/8: $8\state_nxt[3:0] 2/8: $7\state_nxt[3:0] 3/8: $6\state_nxt[3:0] 4/8: $5\state_nxt[3:0] 5/8: $4\state_nxt[3:0] 6/8: $3\state_nxt[3:0] 7/8: $2\state_nxt[3:0] 8/8: $1\state_nxt[3:0] Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:134$1527'. Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1525'. 1/1: $0\out_sym[1:0] Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:110$1518'. Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:102$1513'. Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1503'. 1/2: $0\bs_now[0:0] 2/2: $0\bs_cnt[2:0] Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:79$1500'. Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1497'. 1/1: $0\state[2:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:236$1493'. 1/1: $0\pkt_pid[3:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:428$1485'. Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:421$1482'. 1/1: $0\bd_length[10:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:414$1476'. Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:403$1475'. Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:399$1472'. 1/1: $0\txpkt_pid[3:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:387$1466'. 1/1: $0\cel_state_i[0:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:380$1464'. Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1451'. 1/7: $0\bd_state[2:0] 2/7: $0\ep_data_toggle[0:0] 3/7: $0\ep_bd_idx_nxt[0:0] 4/7: $0\ep_bd_idx_cur[0:0] 5/7: $0\ep_bd_ctrl[0:0] 6/7: $0\ep_bd_dual[0:0] 7/7: $0\ep_type[2:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:345$1448'. 1/1: $0\epfw_cap_dl[5:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1443'. 1/1: $0\epfw_state[3:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1439'. 1/4: $0\trans_cel[0:0] 2/4: $0\trans_dir[0:0] 3/4: $0\trans_endp[3:0] 4/4: $0\trans_is_setup[0:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1432'. 1/1: $0\rto_cnt[9:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:225$1427'. 1/1: $0\evt[3:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1424'. 1/1: $0\mc_a_reg[3:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:175$1415'. 1/1: $0\mc_pc_nxt[7:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:162$1406'. 1/1: $0\mc_rst_n[0:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:374$1403'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:353$1394'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:349$1392'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:340$1389'. 1/1: $0\token_data[10:8] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:336$1386'. 1/1: $0\token_data[7:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1369'. 1/5: $0\pid_is_handshake[0:0] 2/5: $0\pid_is_data[0:0] 3/5: $0\pid_is_token[0:0] 4/5: $0\pid_is_sof[0:0] 5/5: $0\pid[3:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:318$1368'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:304$1347'. 1/1: $0\pid_valid[0:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1343'. 1/2: $0\crc16_ok[0:0] 2/2: $0\crc5_ok[0:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:284$1342'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:244$1340'. 1/1: $0\crc_in_first[0:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:230$1337'. 1/1: $0\bit_eop_ok[0:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:220$1334'. 1/1: $0\bit_cnt[3:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:215$1333'. 1/1: $0\data[7:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:198$1325'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:188$1324'. 1/1: $0\state[3:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:117$1308'. 1/18: $18\state_nxt[3:0] 2/18: $17\state_nxt[3:0] 3/18: $16\state_nxt[3:0] 4/18: $15\state_nxt[3:0] 5/18: $14\state_nxt[3:0] 6/18: $13\state_nxt[3:0] 7/18: $12\state_nxt[3:0] 8/18: $11\state_nxt[3:0] 9/18: $10\state_nxt[3:0] 10/18: $9\state_nxt[3:0] 11/18: $8\state_nxt[3:0] 12/18: $7\state_nxt[3:0] 13/18: $6\state_nxt[3:0] 14/18: $5\state_nxt[3:0] 15/18: $4\state_nxt[3:0] 16/18: $3\state_nxt[3:0] 17/18: $2\state_nxt[3:0] 18/18: $1\state_nxt[3:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:49$1307'. Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:181$1305'. 1/1: $0\dec_bs_skip_1[0:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1303'. 1/1: $0\dec_rep_state_1[3:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:137$1302'. 1/1: $0\dec_sync_state_1[3:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:124$1301'. 1/1: $0\dec_eop_state_1[2:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:120$1300'. Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:111$1293'. 1/2: $0\dec_bit_1[0:0] 2/2: $0\dec_sym_1[1:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:97$1286'. Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1285'. 1/1: $0\samp_cnt[2:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:67$1275'. 1/1: $0\samp_active[0:0] Creating decoders for process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5117'. 1/4: $0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5116_EN[7:0]$5120 2/4: $0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5116_DATA[7:0]$5119 3/4: $0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5116_ADDR[8:0]$5118 4/4: $0\rd_data[7:0] Creating decoders for process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:80$1271'. 1/1: $0\s_dout_3[15:0] Creating decoders for process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:76$1269'. 1/1: $0\p_dout_3[15:0] Creating decoders for process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1266'. Creating decoders for process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1258'. Creating decoders for process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:163$5111'. 1/1: $0\wb_rdata_reg[31:0] Creating decoders for process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:160$5109'. Creating decoders for process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:147$5084'. Creating decoders for process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:91$5081'. Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4220'. Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4211'. 1/1: $0\stage[4].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4209'. 1/1: $0\stage[4].l_data[6:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4200'. 1/1: $0\stage[3].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4198'. 1/1: $0\stage[3].l_data[6:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4189'. 1/1: $0\stage[2].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4187'. 1/1: $0\stage[2].l_data[6:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4178'. 1/1: $0\stage[1].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4176'. 1/1: $0\stage[1].l_data[6:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4174'. Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4165'. 1/1: $0\stage[4].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4163'. 1/1: $0\stage[4].l_data[8:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4154'. 1/1: $0\stage[3].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4152'. 1/1: $0\stage[3].l_data[8:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4143'. 1/1: $0\stage[2].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4141'. 1/1: $0\stage[2].l_data[8:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4132'. 1/1: $0\stage[1].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4130'. 1/1: $0\stage[1].l_data[8:0] Creating decoders for process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:0$5042'. Creating decoders for process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:124$5037'. 1/1: $0\wb_rdata[15:0] Creating decoders for process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:116$5032'. Creating decoders for process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:105$5027'. Creating decoders for process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:40$1103'. 1/1: $0\out_stb[0:0] Creating decoders for process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:34$1102'. 1/1: $0\dst[1:0] Creating decoders for process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:28$1100'. 1/1: $0\src[0:0] Creating decoders for process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:149$4107'. 1/1: $0\wb_now[0:0] Creating decoders for process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4098'. 1/3: $0\wb_req[0:0] 2/3: $0\wb_sel[1:0] 3/3: $0\rst_req[0:0] Creating decoders for process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:109$4094'. 1/1: $0\timer[25:0] Creating decoders for process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:103$4092'. 1/1: $0\armed[0:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. 1/82: $0\reg_next_pc[31:0] [31:2] 2/82: $0\reg_next_pc[31:0] [1:0] 3/82: $0\reg_pc[31:0] [1:0] 4/82: $18\next_irq_pending[2:2] 5/82: $17\next_irq_pending[2:2] 6/82: $16\next_irq_pending[2:2] 7/82: $15\next_irq_pending[2:2] 8/82: $14\next_irq_pending[2:2] 9/82: $13\next_irq_pending[2:2] 10/82: $4\next_irq_pending[31:0] [31:2] 11/82: $3\set_mem_do_rdata[0:0] 12/82: $4\next_irq_pending[31:0] [1] 13/82: $3\set_mem_do_wdata[0:0] 14/82: $4\next_irq_pending[31:0] [0] 15/82: $4\set_mem_do_rinst[0:0] 16/82: $3\set_mem_do_rinst[0:0] 17/82: $4\set_mem_do_wdata[0:0] 18/82: $11\next_irq_pending[1:1] 19/82: $10\next_irq_pending[1:1] 20/82: $9\next_irq_pending[1:1] 21/82: $4\set_mem_do_rdata[0:0] 22/82: $7\next_irq_pending[1:1] 23/82: $6\next_irq_pending[1:1] 24/82: $12\next_irq_pending[1:1] 25/82: $5\set_mem_do_rinst[0:0] 26/82: $8\next_irq_pending[1:1] 27/82: $5\next_irq_pending[31:0] 28/82: $3\current_pc[31:0] 29/82: $2\current_pc[31:0] 30/82: $2\set_mem_do_wdata[0:0] 31/82: $2\set_mem_do_rdata[0:0] 32/82: $2\set_mem_do_rinst[0:0] 33/82: $3\next_irq_pending[31:0] 34/82: $1\current_pc[31:0] 35/82: $1\set_mem_do_wdata[0:0] 36/82: $1\set_mem_do_rdata[0:0] 37/82: $1\set_mem_do_rinst[0:0] 38/82: $0\trace_data[35:0] 39/82: $2\next_irq_pending[0:0] 40/82: $1\next_irq_pending[0:0] 41/82: $0\count_instr[63:0] 42/82: $0\count_cycle[63:0] 43/82: $0\trace_valid[0:0] 44/82: $0\do_waitirq[0:0] 45/82: $0\decoder_pseudo_trigger[0:0] 46/82: $0\decoder_trigger[0:0] 47/82: $0\alu_wait_2[0:0] 48/82: $0\alu_wait[0:0] 49/82: $0\reg_out[31:0] 50/82: $0\reg_sh[4:0] 51/82: $0\trap[0:0] 52/82: $0\pcpi_timeout[0:0] 53/82: $0\latched_rd[4:0] 54/82: $0\latched_is_lb[0:0] 55/82: $0\latched_is_lh[0:0] 56/82: $0\latched_is_lu[0:0] 57/82: $0\latched_trace[0:0] 58/82: $0\latched_compr[0:0] 59/82: $0\latched_branch[0:0] 60/82: $0\latched_stalu[0:0] 61/82: $0\latched_store[0:0] 62/82: $0\irq_state[1:0] 63/82: $0\cpu_state[7:0] 64/82: $0\dbg_rs2val_valid[0:0] 65/82: $0\dbg_rs1val_valid[0:0] 66/82: $0\dbg_rs2val[31:0] 67/82: $0\dbg_rs1val[31:0] 68/82: $0\mem_do_wdata[0:0] 69/82: $0\mem_do_rdata[0:0] 70/82: $0\mem_do_rinst[0:0] 71/82: $0\mem_do_prefetch[0:0] 72/82: $0\mem_wordsize[1:0] 73/82: $0\irq_mask[31:0] 74/82: $0\irq_active[0:0] 75/82: $0\irq_delay[0:0] 76/82: $0\reg_op2[31:0] 77/82: $0\reg_op1[31:0] 78/82: $0\reg_pc[31:0] [31:2] 79/82: $19\next_irq_pending[2:2] 80/82: $0\eoi[31:0] 81/82: $0\pcpi_valid[0:0] 82/82: $0\timer[31:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$3900'. Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1288$3886'. 1/4: $2\cpuregs_write[0:0] 2/4: $2\cpuregs_wrdata[31:0] 3/4: $1\cpuregs_wrdata[31:0] 4/4: $1\cpuregs_write[0:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1274$3881'. 1/2: $2\clear_prefetched_high_word[0:0] 2/2: $1\clear_prefetched_high_word[0:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1272$3880'. Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1228$3858'. 1/2: $1\alu_out[31:0] 2/2: $1\alu_out_0[0:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1165$3846'. 1/8: $8\dbg_ascii_state[127:0] 2/8: $7\dbg_ascii_state[127:0] 3/8: $6\dbg_ascii_state[127:0] 4/8: $5\dbg_ascii_state[127:0] 5/8: $4\dbg_ascii_state[127:0] 6/8: $3\dbg_ascii_state[127:0] 7/8: $2\dbg_ascii_state[127:0] 8/8: $1\dbg_ascii_state[127:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. 1/76: $0\decoded_rs1[4:0] [4] 2/76: $0\decoded_imm_uj[31:0] [10] 3/76: $0\decoded_imm_uj[31:0] [7] 4/76: $0\decoded_imm_uj[31:0] [6] 5/76: $0\decoded_imm_uj[31:0] [3:1] 6/76: $0\decoded_imm_uj[31:0] [5] 7/76: $0\decoded_imm_uj[31:0] [9:8] 8/76: $0\decoded_imm_uj[31:0] [31:20] 9/76: $0\decoded_imm_uj[31:0] [4] 10/76: $0\decoded_imm_uj[31:0] [11] 11/76: $0\decoded_imm_uj[31:0] [0] 12/76: $0\decoded_rs1[4:0] [3:0] 13/76: $0\is_lui_auipc_jal_jalr_addi_add_sub[0:0] 14/76: $0\is_alu_reg_reg[0:0] 15/76: $0\is_alu_reg_imm[0:0] 16/76: $0\is_beq_bne_blt_bge_bltu_bgeu[0:0] 17/76: $0\is_sll_srl_sra[0:0] 18/76: $0\is_sb_sh_sw[0:0] 19/76: $0\is_jalr_addi_slti_sltiu_xori_ori_andi[0:0] 20/76: $0\is_slli_srli_srai[0:0] 21/76: $0\is_lb_lh_lw_lbu_lhu[0:0] 22/76: $0\compressed_instr[0:0] 23/76: $0\is_compare[0:0] 24/76: $0\decoded_imm[31:0] 25/76: $0\decoded_rs2[4:0] 26/76: $0\decoded_imm_uj[31:0] [19:12] 27/76: $0\decoded_rd[4:0] 28/76: $0\instr_timer[0:0] 29/76: $0\instr_waitirq[0:0] 30/76: $0\instr_maskirq[0:0] 31/76: $0\instr_retirq[0:0] 32/76: $0\instr_setq[0:0] 33/76: $0\instr_getq[0:0] 34/76: $0\instr_ecall_ebreak[0:0] 35/76: $0\instr_rdinstrh[0:0] 36/76: $0\instr_rdinstr[0:0] 37/76: $0\instr_rdcycleh[0:0] 38/76: $0\instr_rdcycle[0:0] 39/76: $0\instr_and[0:0] 40/76: $0\instr_or[0:0] 41/76: $0\instr_sra[0:0] 42/76: $0\instr_srl[0:0] 43/76: $0\instr_xor[0:0] 44/76: $0\instr_sltu[0:0] 45/76: $0\instr_slt[0:0] 46/76: $0\instr_sll[0:0] 47/76: $0\instr_sub[0:0] 48/76: $0\instr_add[0:0] 49/76: $0\instr_srai[0:0] 50/76: $0\instr_srli[0:0] 51/76: $0\instr_slli[0:0] 52/76: $0\instr_andi[0:0] 53/76: $0\instr_ori[0:0] 54/76: $0\instr_xori[0:0] 55/76: $0\instr_sltiu[0:0] 56/76: $0\instr_slti[0:0] 57/76: $0\instr_addi[0:0] 58/76: $0\instr_sw[0:0] 59/76: $0\instr_sh[0:0] 60/76: $0\instr_sb[0:0] 61/76: $0\instr_lhu[0:0] 62/76: $0\instr_lbu[0:0] 63/76: $0\instr_lw[0:0] 64/76: $0\instr_lh[0:0] 65/76: $0\instr_lb[0:0] 66/76: $0\instr_bgeu[0:0] 67/76: $0\instr_bltu[0:0] 68/76: $0\instr_bge[0:0] 69/76: $0\instr_blt[0:0] 70/76: $0\instr_bne[0:0] 71/76: $0\instr_beq[0:0] 72/76: $0\instr_jalr[0:0] 73/76: $0\instr_jal[0:0] 74/76: $0\instr_auipc[0:0] 75/76: $0\instr_lui[0:0] 76/76: $0\pcpi_insn[31:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3584'. 1/13: $3\dbg_insn_opcode[31:0] 2/13: $2\dbg_insn_rd[4:0] 3/13: $2\dbg_insn_rs2[4:0] 4/13: $2\dbg_insn_rs1[4:0] 5/13: $2\dbg_insn_opcode[31:0] 6/13: $2\dbg_insn_imm[31:0] 7/13: $2\dbg_ascii_instr[63:0] 8/13: $1\dbg_insn_rd[4:0] 9/13: $1\dbg_insn_rs2[4:0] 10/13: $1\dbg_insn_rs1[4:0] 11/13: $1\dbg_insn_imm[31:0] 12/13: $1\dbg_ascii_instr[63:0] 13/13: $1\dbg_insn_opcode[31:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3580'. 1/8: $0\cached_insn_rd[4:0] 2/8: $0\cached_insn_rs2[4:0] 3/8: $0\cached_insn_rs1[4:0] 4/8: $0\cached_insn_opcode[31:0] 5/8: $0\cached_insn_imm[31:0] 6/8: $0\cached_ascii_instr[63:0] 7/8: $0\dbg_valid_insn[0:0] 8/8: $0\dbg_insn_addr[31:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:684$3579'. 1/47: $47\new_ascii_instr[63:0] 2/47: $46\new_ascii_instr[63:0] 3/47: $45\new_ascii_instr[63:0] 4/47: $44\new_ascii_instr[63:0] 5/47: $43\new_ascii_instr[63:0] 6/47: $42\new_ascii_instr[63:0] 7/47: $41\new_ascii_instr[63:0] 8/47: $40\new_ascii_instr[63:0] 9/47: $39\new_ascii_instr[63:0] 10/47: $38\new_ascii_instr[63:0] 11/47: $37\new_ascii_instr[63:0] 12/47: $36\new_ascii_instr[63:0] 13/47: $35\new_ascii_instr[63:0] 14/47: $34\new_ascii_instr[63:0] 15/47: $33\new_ascii_instr[63:0] 16/47: $32\new_ascii_instr[63:0] 17/47: $31\new_ascii_instr[63:0] 18/47: $30\new_ascii_instr[63:0] 19/47: $29\new_ascii_instr[63:0] 20/47: $28\new_ascii_instr[63:0] 21/47: $27\new_ascii_instr[63:0] 22/47: $26\new_ascii_instr[63:0] 23/47: $25\new_ascii_instr[63:0] 24/47: $24\new_ascii_instr[63:0] 25/47: $23\new_ascii_instr[63:0] 26/47: $22\new_ascii_instr[63:0] 27/47: $21\new_ascii_instr[63:0] 28/47: $20\new_ascii_instr[63:0] 29/47: $19\new_ascii_instr[63:0] 30/47: $18\new_ascii_instr[63:0] 31/47: $17\new_ascii_instr[63:0] 32/47: $16\new_ascii_instr[63:0] 33/47: $15\new_ascii_instr[63:0] 34/47: $14\new_ascii_instr[63:0] 35/47: $13\new_ascii_instr[63:0] 36/47: $12\new_ascii_instr[63:0] 37/47: $11\new_ascii_instr[63:0] 38/47: $10\new_ascii_instr[63:0] 39/47: $9\new_ascii_instr[63:0] 40/47: $8\new_ascii_instr[63:0] 41/47: $7\new_ascii_instr[63:0] 42/47: $6\new_ascii_instr[63:0] 43/47: $5\new_ascii_instr[63:0] 44/47: $4\new_ascii_instr[63:0] 45/47: $3\new_ascii_instr[63:0] 46/47: $2\new_ascii_instr[63:0] 47/47: $1\new_ascii_instr[63:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3555'. 1/9: $0\mem_16bit_buffer[15:0] 2/9: $0\prefetched_high_word[0:0] 3/9: $0\mem_la_secondword[0:0] 4/9: $0\mem_state[1:0] 5/9: $0\mem_wstrb[3:0] 6/9: $0\mem_wdata[31:0] 7/9: $0\mem_instr[0:0] 8/9: $0\mem_valid[0:0] 9/9: $0\mem_addr[31:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1218$4079'. Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:414$3517'. 1/9: $0\mem_rdata_q[31:0] [31] 2/9: $0\mem_rdata_q[31:0] [7] 3/9: $0\mem_rdata_q[31:0] [24:20] 4/9: $0\mem_rdata_q[31:0] [19:15] 5/9: $0\mem_rdata_q[31:0] [6:0] 6/9: $0\mem_rdata_q[31:0] [14:12] 7/9: $0\mem_rdata_q[31:0] [11:8] 8/9: $0\mem_rdata_q[31:0] [30:25] 9/9: $0\next_insn_opcode[31:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3514'. 1/5: $3\mem_rdata_word[31:0] 2/5: $2\mem_rdata_word[31:0] 3/5: $1\mem_rdata_word[31:0] 4/5: $1\mem_la_wstrb[3:0] 5/5: $1\mem_la_wdata[31:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:374$3509'. 1/2: $0\last_mem_valid[0:0] 2/2: $0\mem_la_firstword_reg[0:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3435'. 1/2: $1\pcpi_int_rd[31:0] 2/2: $1\pcpi_int_wr[0:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5018'. Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5017'. Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5012'. 1/1: $0\rx_pending[1:1] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5011'. 1/2: $0\rx_addr_reg[1][15:0] 2/2: $0\rx_data_reg[1][7:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5006'. 1/1: $0\rx_pending[0:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5005'. 1/2: $0\rx_addr_reg[0][15:0] 2/2: $0\rx_data_reg[0][7:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$4995'. 1/3: $1\t_done[3:0] 2/3: $1$bitselwrite$data$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:268$4954[3:0]$4999 3/3: $1$bitselwrite$mask$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:268$4953[3:0]$4998 Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4962'. 1/20: $2$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$4948[15:0]$4991 2/20: $2$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$4947[15:0]$4990 3/20: $2$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$4946[15:0]$4988 4/20: $2$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$4945[15:0]$4987 5/20: $2$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$4942[15:0]$4985 6/20: $2$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$4941[15:0]$4984 7/20: $2$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$4940[15:0]$4982 8/20: $2$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$4939[15:0]$4981 9/20: $1\mux.j[31:0] 10/20: $1$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$4948[15:0]$4979 11/20: $1$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$4947[15:0]$4978 12/20: $1$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$4946[15:0]$4977 13/20: $1$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$4945[15:0]$4976 14/20: $1$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$4942[15:0]$4975 15/20: $1$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$4941[15:0]$4974 16/20: $1$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$4940[15:0]$4973 17/20: $1$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$4939[15:0]$4972 18/20: $0\wb_wdata_byte[7:0] 19/20: $0\wb_addr_lsb[1:0] 20/20: $0\wb_addr[13:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:212$4959'. 1/1: $0\t_chan[1:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:206$4957'. 1/1: $0\t_busy[0:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$4955'. 1/4: $4\t_nxt_chan[1:0] 2/4: $3\t_nxt_chan[1:0] 3/4: $2\t_nxt_chan[1:0] 4/4: $1\t_nxt_chan[1:0] Creating decoders for process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3325'. 1/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3321_EN[31:0]$3328 2/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3321_DATA[31:0]$3327 3/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3321_ADDR[7:0]$3326 4/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3322_EN[31:0]$3331 5/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3322_DATA[31:0]$3330 6/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3322_ADDR[7:0]$3329 7/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3323_EN[31:0]$3334 8/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3323_DATA[31:0]$3333 9/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3323_ADDR[7:0]$3332 10/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3324_EN[31:0]$3337 11/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3324_DATA[31:0]$3336 12/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3324_ADDR[7:0]$3335 Creating decoders for process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:193$3316'. 1/1: $0\uart_div[11:0] Creating decoders for process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:185$3314'. 1/1: $0\ub_rdata[31:0] Creating decoders for process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:177$3304'. 1/1: $0\ub_ack[0:0] Creating decoders for process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3287'. 1/4: $0\ub_wr_div[0:0] 2/4: $0\ub_wr_data[0:0] 3/4: $0\ub_rd_ctrl[0:0] 4/4: $0\ub_rd_data[0:0] Creating decoders for process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:154$3282'. 1/1: $0\urf_overflow[0:0] Creating decoders for process `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.$proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3275'. 1/1: $0\led_ctrl[4:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:536$3269'. 1/1: $0\evt_cnt[3:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:656$3264'. Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:653$3262'. Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:643$3261'. 1/1: $0\pad_pu[0:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:636$3257'. 1/1: $0\rst_pending[0:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:628$3253'. 1/1: $0\timeout_reset[19:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:619$3249'. 1/1: $0\timeout_suspend[19:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:514$3235'. 1/1: $0\eps_bus_ack_wait[0:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:510$3232'. Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3222'. 1/3: $0\eps_bus_req[0:0] 2/3: $0\eps_bus_write[0:0] 3/3: $0\eps_bus_read[0:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:697$3273'. Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3220'. 1/4: $0\cr_addr[6:0] 2/4: $0\cr_addr_chk[0:0] 3/4: $0\cr_cel_ena[0:0] 4/4: $0\cr_pu_ena[0:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:442$3216'. 1/2: $2\csr_bus_dout[15:0] 2/2: $1\csr_bus_dout[15:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3198'. 1/7: $0\ir_bus_we[0:0] 2/7: $0\evt_rd_ack[0:0] 3/7: $0\sof_clear[0:0] 4/7: $0\rst_clear[0:0] 5/7: $0\cel_rel[0:0] 6/7: $0\cr_bus_we[0:0] 7/7: $0\csr_bus_req[0:0] Creating decoders for process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:99$3194'. 1/1: $0\m_cyc_i[0:0] Creating decoders for process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:83$3190'. Creating decoders for process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:73$3187'. 1/1: $0\s_rdata[15:0] Creating decoders for process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:68$3186'. 1/1: $0\m_rdata_i[15:0] Creating decoders for process `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v:50$4926'. 1/1: $0\ack_i[0:0] Creating decoders for process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4905'. 1/2: $0\busy[0:0] 2/2: $0\sel[2:0] Creating decoders for process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$4896'. 1/3: $0\sel_nxt[2:0] [2] 2/3: $0\sel_nxt[2:0] [0] 3/3: $0\sel_nxt[2:0] [1] Creating decoders for process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4893'. 1/4: $0\m_wmsk[3:0] 2/4: $0\m_we[0:0] 3/4: $0\m_wdata[31:0] 4/4: $0\m_addr[13:0] Creating decoders for process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4874'. Creating decoders for process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3103'. Creating decoders for process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3101'. Creating decoders for process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3099'. Creating decoders for process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:184$3098'. 1/1: $0\pb_rst_n[0:0] Creating decoders for process `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2950'. Creating decoders for process `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$2947'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2946'. Creating decoders for process `\SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1274$2940'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2939'. Creating decoders for process `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$2936'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2935'. Creating decoders for process `\SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1143$2929'. 1/1: $0\Q[0:0] Creating decoders for process `\e1_rx_liu.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_liu.v:59$177'. Creating decoders for process `\e1_rx_liu.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_liu.v:52$176'. Creating decoders for process `\SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2928'. Creating decoders for process `\SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1074$2926'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2925'. Creating decoders for process `\SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1026$2923'. 1/1: $0\Q[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:406$141'. 1/1: $0\aligned[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$135'. 1/7: $0\out_last[0:0] 2/7: $0\out_first[0:0] 3/7: $0\out_ts_is0[0:0] 4/7: $0\out_ts[4:0] 5/7: $0\out_frame[3:0] 6/7: $0\out_data[7:0] 7/7: $0\out_valid[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:357$127'. Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$109'. 1/4: $0\ec_mfa[1:0] 2/4: $0\ec_crc[1:0] 3/4: $0\ec_nfas[1:0] 4/4: $0\ec_fas[1:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$89'. 1/4: $0\ed_mfa[0:0] 2/4: $0\ep_mfa[0:0] 3/4: $0\ed_crc[0:0] 4/4: $0\ep_crc[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$67'. 1/4: $0\ed_nfas[0:0] 2/4: $0\ep_nfas[0:0] 3/4: $0\ed_fas[0:0] 4/4: $0\ep_fas[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:306$66'. 1/1: $0\crc_smf[3:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:274$55'. 1/3: $0\ts0_msbs_match_crc[0:0] 2/3: $0\ts0_msbs_match_mf[0:0] 3/3: $0\ts0_msbs[15:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:266$51'. 1/1: $0\mfa_timeout[6:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:258$47'. 1/1: $0\fas_pos[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$37'. 1/5: $0\frame_mf_last[0:0] 2/5: $0\frame_mf_first[0:0] 3/5: $0\frame_smf_last[0:0] 4/5: $0\frame_smf_first[0:0] 5/5: $0\frame[3:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:219$33'. 1/3: $0\ts_is_ts31[0:0] 2/3: $0\ts_is_ts0[0:0] 3/3: $0\ts[4:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:207$29'. 1/3: $0\bit_last[0:0] 2/3: $0\bit_first[0:0] 3/3: $0\bit[2:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:149$21'. 1/1: $0\fsm_state_nxt[2:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:142$19'. 1/1: $0\fsm_state[2:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:133$16'. 1/1: $0\data_match_fas[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:128$15'. 1/1: $0\data[7:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:121$14'. 1/1: $0\strobe[0:0] Creating decoders for process `\SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2922'. Creating decoders for process `\SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:957$2920'. 1/1: $0\Q[0:0] Creating decoders for process `\e1_crc4.$proc$/build/gateware/cores/no2e1//rtl/e1_crc4.v:38$10'. 1/1: $0\state[3:0] 73.3.7. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\sel_nxt' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$4844'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\prio.i' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$4844'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\mux_addr' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4828'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\mux_wdata' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4828'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\mux_wmsk' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4828'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\mux.i' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4828'. No latch inferred for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\state_nxt' from process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:98$4770'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:92$4749$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4761'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:92$4752$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4761'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:92$4752$\sig' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4761'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:91$4748$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4757'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:91$4751$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4757'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:91$4751$\sig' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4757'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:81$4747$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4753'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:81$4750$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4753'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:81$4750$\sig' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4753'. No latch inferred for signal `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\cnt_move' from process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4725'. No latch inferred for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\cnt_move' from process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4492'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5186$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5228'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5195$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5228'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5195$\wdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5228'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5185$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5224'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5194$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5224'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5194$\rdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5224'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5184$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5220'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5193$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5220'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5193$\wdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5220'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5183$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5216'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5192$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5216'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5192$\rdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5216'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5182$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5212'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5191$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5212'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5191$\wdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5212'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5181$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5208'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5190$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5208'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5190$\rdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5208'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5180$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5204'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5189$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5204'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5189$\wdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5204'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5179$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5200'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5188$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5200'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5188$\rdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5200'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:220$5178$\ram_wr_shuffle_32' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5196'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:220$5187$\ram_wr_shuffle_32' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5196'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:220$5187$\src' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5196'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_do_m[0]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4483'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di[0]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4483'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di[1]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4483'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm[0]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4483'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm[1]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4483'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\rd_data' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\map.n' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\map.x' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\map.o' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327'. Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [0]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$15269 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [1]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$15384 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [2]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$15547 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [3]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$15758 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [4]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$15969 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [5]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$16180 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [6]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$16391 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [7]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$16602 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [8]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$16813 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [9]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$17024 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [10]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$17235 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [11]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$17446 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [12]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$17657 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [13]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$17868 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [14]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$18079 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [15]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$18290 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [16]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$18501 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [17]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$18712 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [18]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$18923 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [19]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$19134 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [20]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$19345 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [21]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$19556 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [22]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$19767 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [23]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$19978 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [24]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$20189 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [25]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$20400 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [26]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$20611 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [27]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$20822 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [28]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$21033 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [29]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$21244 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [30]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$21455 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [31]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$21666 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [0]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$21733 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [1]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$21800 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [2]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$21867 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [3]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$21934 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [4]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$22001 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [5]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$22068 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [6]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$22135 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [7]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327': $auto$proc_dlatch.cc:430:proc_dlatch$22202 No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5131$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5173'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5140$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5173'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5140$\wdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5173'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5130$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5169'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5139$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5169'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5139$\rdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5169'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5129$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5165'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5138$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5165'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5138$\wdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5165'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5128$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5161'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5137$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5161'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5137$\rdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5161'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5127$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5157'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5136$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5157'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5136$\wdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5157'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5126$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5153'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5135$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5153'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5135$\rdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5153'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5125$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5149'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5134$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5149'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5134$\wdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5149'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5124$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5145'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5133$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5145'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5133$\rdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5145'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:211$5123$\ram_rd_shuffle_32' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5141'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:211$5132$\ram_rd_shuffle_32' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5141'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:211$5132$\src' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5141'. No latch inferred for signal `\usb_tx_pkt.\shift_load' from process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:159$1546'. No latch inferred for signal `\usb_tx_pkt.\state_nxt' from process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:86$1528'. No latch inferred for signal `\usb_rx_pkt.\state_nxt' from process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:117$1308'. No latch inferred for signal `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.\wb_rdata_or' from process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:147$5084'. No latch inferred for signal `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.\wb_or.i' from process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:147$5084'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[0]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4220'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[1]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4220'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[2]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4220'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[3]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4220'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[4]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4220'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[5]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4220'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[0]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4174'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[1]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4174'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[2]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4174'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[3]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4174'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[4]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4174'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[5]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4174'. No latch inferred for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.\bus_rdata_tx[0]' from process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:0$5042'. No latch inferred for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.\bus_rdata_tx[1]' from process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:0$5042'. No latch inferred for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.\bus_rdata' from process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:116$5032'. No latch inferred for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.\rdata_or.j' from process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:116$5032'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cpuregs_rs1' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$3900'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cpuregs_rs2' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$3900'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\decoded_rs' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$3900'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cpuregs_write' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1288$3886'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cpuregs_wrdata' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1288$3886'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\clear_prefetched_high_word' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1274$3881'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_out' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1228$3858'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_out_0' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1228$3858'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_ascii_state' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1165$3846'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_insn_opcode' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3584'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_ascii_instr' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3584'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_insn_imm' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3584'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_insn_rs1' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3584'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_insn_rs2' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3584'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_insn_rd' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3584'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\new_ascii_instr' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:684$3579'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_add_sub' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1218$4079'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_shl' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1218$4079'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_shr' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1218$4079'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_eq' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1218$4079'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_ltu' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1218$4079'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_lts' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1218$4079'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_la_wdata' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3514'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_la_wstrb' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3514'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_rdata_word' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3514'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\pcpi_int_wr' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3435'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\pcpi_int_rd' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3435'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\pcpi_int_wait' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3435'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\pcpi_int_ready' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3435'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\t_done' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$4995'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$bitselwrite$mask$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:268$4953' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$4995'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$bitselwrite$data$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:268$4954' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$4995'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\t_nxt_busy' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$4955'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\t_nxt_chan' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$4955'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\next_sel.j' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$4955'. No latch inferred for signal `$paramod\usb\EPDW=32.\irq' from process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:697$3273'. No latch inferred for signal `$paramod\usb\EPDW=32.\csr_bus_dout' from process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:442$3216'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\sel_nxt' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$4896'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\prio.i' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$4896'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\mux_addr' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4874'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\mux_wdata' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4874'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\mux_wmsk' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4874'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\mux.i' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4874'. No latch inferred for signal `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.\wb_rdata[3] [31:16]' from process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3103'. No latch inferred for signal `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.\wb_rdata[5]' from process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3103'. No latch inferred for signal `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.\wb_rdata[6]' from process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3103'. No latch inferred for signal `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.\wb_rdata[7] [31:16]' from process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3103'. No latch inferred for signal `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$mem2bits$\wb_rdata$/build/gateware/common/rtl/soc_base.v:498$3097' from process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3101'. No latch inferred for signal `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$mem2bits$\wb_rdata$/build/gateware/common/rtl/soc_base.v:401$3096' from process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3099'. No latch inferred for signal `\e1_rx_deframer.\fsm_state_nxt' from process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:149$21'. 73.3.8. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:909$2917'. created $dff cell `$procdff$22203' with negative edge clock. Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:866$2915'. created $dff cell `$procdff$22204' with negative edge clock. Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:830$2913'. created $dff cell `$procdff$22205' with negative edge clock. Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$2909'. created $adff cell `$procdff$22206' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:697$2902'. created $dff cell `$procdff$22207' with positive edge clock. Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$2898'. created $adff cell `$procdff$22208' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:566$2891'. created $dff cell `$procdff$22209' with positive edge clock. Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:497$2888'. created $adff cell `$procdff$22210' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:449$2885'. created $dff cell `$procdff$22211' with positive edge clock. Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:380$2882'. created $adff cell `$procdff$22212' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:332$2879'. created $dff cell `$procdff$22213' with positive edge clock. Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:289$2877'. created $dff cell `$procdff$22214' with positive edge clock. Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:253$2875'. created $dff cell `$procdff$22215' with positive edge clock. Creating register for signal `$paramod\wb_epbuf\AW=9\DW=32.\ack_i' using process `$paramod\wb_epbuf\AW=9\DW=32.$proc$/build/gateware/common/rtl/wb_epbuf.v:51$4862'. created $adff cell `$procdff$22216' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\sel' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4851'. created $adff cell `$procdff$22217' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\busy' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4851'. created $adff cell `$procdff$22218' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\m_addr' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4841'. created $adff cell `$procdff$22219' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\m_wdata' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4841'. created $adff cell `$procdff$22220' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\m_we' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4841'. created $adff cell `$procdff$22221' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\m_wmsk' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4841'. created $adff cell `$procdff$22222' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\ctl_do_write' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$4809'. created $adff cell `$procdff$22223' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\ctl_do_read' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$4809'. created $adff cell `$procdff$22224' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\ctl_ack_i' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$4809'. created $adff cell `$procdff$22225' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\dir' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:178$4805'. created $dff cell `$procdff$22226' with positive edge clock. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\len' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:174$4802'. created $dff cell `$procdff$22227' with positive edge clock. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\m1_addr_i' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:157$4792'. created $dff cell `$procdff$22228' with positive edge clock. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\m0_addr_i' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:153$4788'. created $dff cell `$procdff$22229' with positive edge clock. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\data_reg' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:142$4786'. created $dff cell `$procdff$22230' with positive edge clock. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\state' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:92$4769'. created $adff cell `$procdff$22231' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\go' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:86$4765'. created $adff cell `$procdff$22232' with positive edge clock and positive level reset. Creating register for signal `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\sync' using process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4746'. created $dff cell `$procdff$22233' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\rise' using process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4741'. created $dff cell `$procdff$22234' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\fall' using process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4741'. created $dff cell `$procdff$22235' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\state' using process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4737'. created $dff cell `$procdff$22236' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\cnt' using process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4733'. created $dff cell `$procdff$22237' with positive edge clock. Creating register for signal `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100.\state' using process `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4723'. created $dff cell `$procdff$22238' with positive edge clock. Creating register for signal `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101.\state' using process `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4710'. created $dff cell `$procdff$22239' with positive edge clock. Creating register for signal `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.\dp_state' using process `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4686'. created $adff cell `$procdff$22240' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.\dn_state' using process `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4686'. created $adff cell `$procdff$22241' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_rx\LIU=1\MFW=7.\bd_crc_e' using process `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:212$5316'. created $adff cell `$procdff$22242' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_rx\LIU=1\MFW=7.\bd_done' using process `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:205$5310'. created $dff cell `$procdff$22243' with positive edge clock. Creating register for signal `$paramod\e1_rx\LIU=1\MFW=7.\bd_miss' using process `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:205$5310'. created $dff cell `$procdff$22244' with positive edge clock. Creating register for signal `$paramod\e1_rx\LIU=1\MFW=7.\mf_valid' using process `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:197$5306'. created $adff cell `$procdff$22245' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_rx\LIU=1\MFW=7.\tx_crc_e_auto' using process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:255$5300'. created $dff cell `$procdff$22246' with positive edge clock. Creating register for signal `$paramod\e1_wb_rx\LIU=1\MFW=7.\rx_overflow' using process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:248$5296'. created $adff cell `$procdff$22247' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_rx\LIU=1\MFW=7.\rx_rst' using process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:241$5294'. created $adff cell `$procdff$22248' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_rx\LIU=1\MFW=7.\bri_wren' using process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$5276'. created $dff cell `$procdff$22249' with positive edge clock. Creating register for signal `$paramod\e1_wb_rx\LIU=1\MFW=7.\bro_rden' using process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$5276'. created $dff cell `$procdff$22250' with positive edge clock. Creating register for signal `$paramod\e1_wb_rx\LIU=1\MFW=7.\rx_enabled' using process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$5275'. created $adff cell `$procdff$22251' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_rx\LIU=1\MFW=7.\rx_mode' using process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$5275'. created $adff cell `$procdff$22252' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_rx\LIU=1\MFW=7.\crx_wren' using process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$5267'. created $dff cell `$procdff$22253' with positive edge clock. Creating register for signal `$paramod\e1_wb_rx\LIU=1\MFW=7.\crx_clear' using process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$5267'. created $dff cell `$procdff$22254' with positive edge clock. Creating register for signal `$paramod\uart_tx\DIV_WIDTH=12.\ack' using process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:67$5266'. created $dff cell `$procdff$22255' with positive edge clock. Creating register for signal `$paramod\uart_tx\DIV_WIDTH=12.\shift' using process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5265'. created $adff cell `$procdff$22256' with positive edge clock and positive level reset. Creating register for signal `$paramod\uart_tx\DIV_WIDTH=12.\bit_cnt' using process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:51$5262'. created $dff cell `$procdff$22257' with positive edge clock. Creating register for signal `$paramod\uart_tx\DIV_WIDTH=12.\div_cnt' using process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:42$5258'. created $dff cell `$procdff$22258' with positive edge clock. Creating register for signal `$paramod\uart_tx\DIV_WIDTH=12.\active' using process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:35$5254'. created $adff cell `$procdff$22259' with positive edge clock and positive level reset. Creating register for signal `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.\stb' using process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:102$5248'. created $dff cell `$procdff$22260' with positive edge clock. Creating register for signal `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.\shift' using process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:95$5247'. created $dff cell `$procdff$22261' with positive edge clock. Creating register for signal `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.\bit_cnt' using process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:88$5244'. created $dff cell `$procdff$22262' with positive edge clock. Creating register for signal `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.\div_cnt' using process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:77$5240'. created $dff cell `$procdff$22263' with positive edge clock. Creating register for signal `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.\active' using process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:70$5236'. created $adff cell `$procdff$22264' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.\rd_valid' using process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4537'. created $adff cell `$procdff$22265' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.\ram_rd_addr' using process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4531'. created $adff cell `$procdff$22266' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.\ram_wr_addr' using process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4529'. created $adff cell `$procdff$22267' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.\full' using process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:83$4520'. created $adff cell `$procdff$22268' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.\level' using process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:67$4514'. created $adff cell `$procdff$22269' with positive edge clock and positive level reset. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\sync' using process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4513'. created $dff cell `$procdff$22270' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\rise' using process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4508'. created $dff cell `$procdff$22271' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\fall' using process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4508'. created $dff cell `$procdff$22272' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\state' using process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4504'. created $dff cell `$procdff$22273' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\cnt' using process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4500'. created $dff cell `$procdff$22274' with positive edge clock. Creating register for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\addr_r' using process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:73$4326'. created $dff cell `$procdff$22275' with positive edge clock. Creating register for signal `\sysmgr.\rst_cnt' using process `\sysmgr.$proc$/build/gateware/e1-tracer/rtl/sysmgr.v:81$1598'. created $adff cell `$procdff$22276' with positive edge clock and negative level reset. Creating register for signal `\misc.\boot_sel' using process `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:131$1596'. created $adff cell `$procdff$22277' with positive edge clock and positive level reset. Creating register for signal `\misc.\boot_now' using process `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:131$1596'. created $adff cell `$procdff$22278' with positive edge clock and positive level reset. Creating register for signal `\misc.\tick_e1_sel[0]' using process `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:95$1593'. created $dff cell `$procdff$22279' with positive edge clock. Creating register for signal `\misc.\tick_e1_sel[1]' using process `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:95$1593'. created $dff cell `$procdff$22280' with positive edge clock. Creating register for signal `\misc.\wb_rdata' using process `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:80$1592'. created $dff cell `$procdff$22281' with positive edge clock. Creating register for signal `\misc.\bus_we_boot' using process `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:70$1587'. created $dff cell `$procdff$22282' with positive edge clock. Creating register for signal `\misc.\bus_we_tick_sel' using process `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:70$1587'. created $dff cell `$procdff$22283' with positive edge clock. Creating register for signal `\misc.\wb_ack' using process `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:64$1582'. created $dff cell `$procdff$22284' with positive edge clock. Creating register for signal `\usb_tx_pkt.\pkt_done' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:241$1578'. created $dff cell `$procdff$22285' with positive edge clock. Creating register for signal `\usb_tx_pkt.\pkt_data_ack' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:241$1578'. created $dff cell `$procdff$22286' with positive edge clock. Creating register for signal `\usb_tx_pkt.\ll_start' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:229$1575'. created $dff cell `$procdff$22287' with positive edge clock. Creating register for signal `\usb_tx_pkt.\crc_in_first' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:202$1569'. created $dff cell `$procdff$22288' with positive edge clock. Creating register for signal `\usb_tx_pkt.\len' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:191$1565'. created $dff cell `$procdff$22289' with positive edge clock. Creating register for signal `\usb_tx_pkt.\shift_new_bit' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:182$1559'. created $dff cell `$procdff$22290' with positive edge clock. Creating register for signal `\usb_tx_pkt.\shift_data_crc' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:175$1552'. created $dff cell `$procdff$22291' with positive edge clock. Creating register for signal `\usb_tx_pkt.\shift_last_byte' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:175$1552'. created $dff cell `$procdff$22292' with positive edge clock. Creating register for signal `\usb_tx_pkt.\shift_data' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:170$1550'. created $dff cell `$procdff$22293' with positive edge clock. Creating register for signal `\usb_tx_pkt.\shift_bit' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:152$1543'. created $dff cell `$procdff$22294' with positive edge clock. Creating register for signal `\usb_tx_pkt.\pid_is_handshake' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:136$1531'. created $dff cell `$procdff$22295' with positive edge clock. Creating register for signal `\usb_tx_pkt.\state' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:126$1530'. created $adff cell `$procdff$22296' with positive edge clock and positive level reset. Creating register for signal `\usb_tx_ll.\out_active' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:134$1527'. created $dff cell `$procdff$22297' with positive edge clock. Creating register for signal `\usb_tx_ll.\out_sym' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1525'. created $adff cell `$procdff$22298' with positive edge clock and positive level reset. Creating register for signal `\usb_tx_ll.\ll_ack' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:110$1518'. created $dff cell `$procdff$22299' with positive edge clock. Creating register for signal `\usb_tx_ll.\lvl_prev' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:102$1513'. created $dff cell `$procdff$22300' with positive edge clock. Creating register for signal `\usb_tx_ll.\bs_cnt' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1503'. created $adff cell `$procdff$22301' with positive edge clock and positive level reset. Creating register for signal `\usb_tx_ll.\bs_now' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1503'. created $adff cell `$procdff$22302' with positive edge clock and positive level reset. Creating register for signal `\usb_tx_ll.\br_cnt' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:79$1500'. created $dff cell `$procdff$22303' with positive edge clock. Creating register for signal `\usb_tx_ll.\state' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1497'. created $adff cell `$procdff$22304' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\pkt_pid' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:236$1493'. created $dff cell `$procdff$22305' with positive edge clock. Creating register for signal `\usb_trans.\xfer_length' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:428$1485'. created $dff cell `$procdff$22306' with positive edge clock. Creating register for signal `\usb_trans.\bd_length' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:421$1482'. created $dff cell `$procdff$22307' with positive edge clock. Creating register for signal `\usb_trans.\addr' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:414$1476'. created $dff cell `$procdff$22308' with positive edge clock. Creating register for signal `\usb_trans.\txpkt_start_i' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:403$1475'. created $dff cell `$procdff$22309' with positive edge clock. Creating register for signal `\usb_trans.\txpkt_pid' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:399$1472'. created $dff cell `$procdff$22310' with positive edge clock. Creating register for signal `\usb_trans.\cel_state_i' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:387$1466'. created $adff cell `$procdff$22311' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\epfw_issue_wb' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:380$1464'. created $dff cell `$procdff$22312' with positive edge clock. Creating register for signal `\usb_trans.\ep_type' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1451'. created $dff cell `$procdff$22313' with positive edge clock. Creating register for signal `\usb_trans.\ep_bd_dual' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1451'. created $dff cell `$procdff$22314' with positive edge clock. Creating register for signal `\usb_trans.\ep_bd_ctrl' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1451'. created $dff cell `$procdff$22315' with positive edge clock. Creating register for signal `\usb_trans.\ep_bd_idx_cur' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1451'. created $dff cell `$procdff$22316' with positive edge clock. Creating register for signal `\usb_trans.\ep_bd_idx_nxt' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1451'. created $dff cell `$procdff$22317' with positive edge clock. Creating register for signal `\usb_trans.\ep_data_toggle' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1451'. created $dff cell `$procdff$22318' with positive edge clock. Creating register for signal `\usb_trans.\bd_state' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1451'. created $dff cell `$procdff$22319' with positive edge clock. Creating register for signal `\usb_trans.\epfw_cap_dl' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:345$1448'. created $adff cell `$procdff$22320' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\epfw_state' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1443'. created $adff cell `$procdff$22321' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\trans_is_setup' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1439'. created $dff cell `$procdff$22322' with positive edge clock. Creating register for signal `\usb_trans.\trans_endp' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1439'. created $dff cell `$procdff$22323' with positive edge clock. Creating register for signal `\usb_trans.\trans_dir' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1439'. created $dff cell `$procdff$22324' with positive edge clock. Creating register for signal `\usb_trans.\trans_cel' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1439'. created $dff cell `$procdff$22325' with positive edge clock. Creating register for signal `\usb_trans.\rto_cnt' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1432'. created $adff cell `$procdff$22326' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\evt' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:225$1427'. created $adff cell `$procdff$22327' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\mc_a_reg' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1424'. created $dff cell `$procdff$22328' with positive edge clock. Creating register for signal `\usb_trans.\mc_pc_nxt' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:175$1415'. created $adff cell `$procdff$22329' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\mc_rst_n' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:162$1406'. created $adff cell `$procdff$22330' with positive edge clock and positive level reset. Creating register for signal `\usb_rx_pkt.\pkt_data_stb' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:374$1403'. created $dff cell `$procdff$22331' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pkt_done_ok' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:353$1394'. created $dff cell `$procdff$22332' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pkt_done_err' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:353$1394'. created $dff cell `$procdff$22333' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pkt_start' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:349$1392'. created $dff cell `$procdff$22334' with positive edge clock. Creating register for signal `\usb_rx_pkt.\token_data [10:8]' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:340$1389'. created $dff cell `$procdff$22335' with positive edge clock. Creating register for signal `\usb_rx_pkt.\token_data [7:0]' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:336$1386'. created $dff cell `$procdff$22336' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1369'. created $dff cell `$procdff$22337' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_is_sof' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1369'. created $dff cell `$procdff$22338' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_is_token' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1369'. created $dff cell `$procdff$22339' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_is_data' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1369'. created $dff cell `$procdff$22340' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_is_handshake' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1369'. created $dff cell `$procdff$22341' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_cap_r' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:318$1368'. created $dff cell `$procdff$22342' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_valid' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:304$1347'. created $dff cell `$procdff$22343' with positive edge clock. Creating register for signal `\usb_rx_pkt.\crc5_ok' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1343'. created $dff cell `$procdff$22344' with positive edge clock. Creating register for signal `\usb_rx_pkt.\crc16_ok' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1343'. created $dff cell `$procdff$22345' with positive edge clock. Creating register for signal `\usb_rx_pkt.\crc_cap' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:284$1342'. created $dff cell `$procdff$22346' with positive edge clock. Creating register for signal `\usb_rx_pkt.\crc_in_first' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:244$1340'. created $dff cell `$procdff$22347' with positive edge clock. Creating register for signal `\usb_rx_pkt.\bit_eop_ok' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:230$1337'. created $dff cell `$procdff$22348' with positive edge clock. Creating register for signal `\usb_rx_pkt.\bit_cnt' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:220$1334'. created $dff cell `$procdff$22349' with positive edge clock. Creating register for signal `\usb_rx_pkt.\data' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:215$1333'. created $dff cell `$procdff$22350' with positive edge clock. Creating register for signal `\usb_rx_pkt.\state_prev_idle' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:198$1325'. created $dff cell `$procdff$22351' with positive edge clock. Creating register for signal `\usb_rx_pkt.\state_prev_error' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:198$1325'. created $dff cell `$procdff$22352' with positive edge clock. Creating register for signal `\usb_rx_pkt.\state' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:188$1324'. created $adff cell `$procdff$22353' with positive edge clock and positive level reset. Creating register for signal `\usb_rx_ll.\dec_bs_skip_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:181$1305'. created $dff cell `$procdff$22354' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_rep_state_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1303'. created $dff cell `$procdff$22355' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_sync_state_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:137$1302'. created $dff cell `$procdff$22356' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_eop_state_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:124$1301'. created $dff cell `$procdff$22357' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_valid_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:120$1300'. created $dff cell `$procdff$22358' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_sym_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:111$1293'. created $dff cell `$procdff$22359' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_bit_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:111$1293'. created $dff cell `$procdff$22360' with positive edge clock. Creating register for signal `\usb_rx_ll.\samp_valid_0' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:97$1286'. created $dff cell `$procdff$22361' with positive edge clock. Creating register for signal `\usb_rx_ll.\samp_cnt' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1285'. created $dff cell `$procdff$22362' with positive edge clock. Creating register for signal `\usb_rx_ll.\samp_active' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:67$1275'. created $adff cell `$procdff$22363' with positive edge clock and positive level reset. Creating register for signal `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.\rd_data' using process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5117'. created $dff cell `$procdff$22364' with positive edge clock. Creating register for signal `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5116_ADDR' using process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5117'. created $dff cell `$procdff$22365' with positive edge clock. Creating register for signal `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5116_DATA' using process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5117'. created $dff cell `$procdff$22366' with positive edge clock. Creating register for signal `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5116_EN' using process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5117'. created $dff cell `$procdff$22367' with positive edge clock. Creating register for signal `\usb_ep_status.\s_dout_3' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:80$1271'. created $dff cell `$procdff$22368' with positive edge clock. Creating register for signal `\usb_ep_status.\p_dout_3' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:76$1269'. created $dff cell `$procdff$22369' with positive edge clock. Creating register for signal `\usb_ep_status.\p_read_2' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1266'. created $dff cell `$procdff$22370' with positive edge clock. Creating register for signal `\usb_ep_status.\p_zero_2' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1266'. created $dff cell `$procdff$22371' with positive edge clock. Creating register for signal `\usb_ep_status.\s_read_2' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1266'. created $dff cell `$procdff$22372' with positive edge clock. Creating register for signal `\usb_ep_status.\s_zero_2' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1266'. created $dff cell `$procdff$22373' with positive edge clock. Creating register for signal `\usb_ep_status.\addr_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1258'. created $dff cell `$procdff$22374' with positive edge clock. Creating register for signal `\usb_ep_status.\din_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1258'. created $dff cell `$procdff$22375' with positive edge clock. Creating register for signal `\usb_ep_status.\we_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1258'. created $dff cell `$procdff$22376' with positive edge clock. Creating register for signal `\usb_ep_status.\p_read_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1258'. created $dff cell `$procdff$22377' with positive edge clock. Creating register for signal `\usb_ep_status.\p_zero_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1258'. created $dff cell `$procdff$22378' with positive edge clock. Creating register for signal `\usb_ep_status.\s_read_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1258'. created $dff cell `$procdff$22379' with positive edge clock. Creating register for signal `\usb_ep_status.\s_zero_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1258'. created $dff cell `$procdff$22380' with positive edge clock. Creating register for signal `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.\wb_rdata_reg' using process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:163$5111'. created $dff cell `$procdff$22381' with positive edge clock. Creating register for signal `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.\wb_rdy_reg' using process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:160$5109'. created $dff cell `$procdff$22382' with positive edge clock. Creating register for signal `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.\ram_rdy' using process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:91$5081'. created $dff cell `$procdff$22383' with positive edge clock. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[4].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4211'. created $adff cell `$procdff$22384' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[4].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4209'. created $adff cell `$procdff$22385' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[3].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4200'. created $adff cell `$procdff$22386' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[3].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4198'. created $adff cell `$procdff$22387' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[2].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4189'. created $adff cell `$procdff$22388' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[2].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4187'. created $adff cell `$procdff$22389' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[1].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4178'. created $adff cell `$procdff$22390' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[1].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4176'. created $adff cell `$procdff$22391' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[4].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4165'. created $adff cell `$procdff$22392' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[4].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4163'. created $adff cell `$procdff$22393' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[3].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4154'. created $adff cell `$procdff$22394' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[3].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4152'. created $adff cell `$procdff$22395' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[2].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4143'. created $adff cell `$procdff$22396' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[2].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4141'. created $adff cell `$procdff$22397' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[1].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4132'. created $adff cell `$procdff$22398' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[1].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4130'. created $adff cell `$procdff$22399' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.\wb_rdata' using process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:124$5037'. created $dff cell `$procdff$22400' with positive edge clock. Creating register for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.\wb_ack' using process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:105$5027'. created $dff cell `$procdff$22401' with positive edge clock. Creating register for signal `\xclk_strobe.\out_stb' using process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:40$1103'. created $adff cell `$procdff$22402' with positive edge clock and positive level reset. Creating register for signal `\xclk_strobe.\dst' using process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:34$1102'. created $adff cell `$procdff$22403' with positive edge clock and positive level reset. Creating register for signal `\xclk_strobe.\src' using process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:28$1100'. created $adff cell `$procdff$22404' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.\wb_now' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:149$4107'. created $adff cell `$procdff$22405' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.\rst_req' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4098'. created $adff cell `$procdff$22406' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.\wb_sel' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4098'. created $adff cell `$procdff$22407' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.\wb_req' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4098'. created $adff cell `$procdff$22408' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.\timer' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:109$4094'. created $adff cell `$procdff$22409' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.\armed' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:103$4092'. created $adff cell `$procdff$22410' with positive edge clock and positive level reset. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\timer' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22411' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\trap' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22412' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\pcpi_valid' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22413' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\eoi' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22414' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\trace_valid' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22415' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\trace_data' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22416' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\count_cycle' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22417' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\count_instr' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22418' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\reg_pc' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22419' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\reg_next_pc' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22420' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\reg_op1' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22421' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\reg_op2' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22422' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\reg_out' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22423' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\reg_sh' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22424' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\irq_delay' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22425' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\irq_active' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22426' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\irq_mask' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22427' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\irq_pending' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22428' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_wordsize' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22429' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_do_prefetch' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22430' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_do_rinst' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22431' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_do_rdata' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22432' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_do_wdata' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22433' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\decoder_trigger' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22434' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\decoder_trigger_q' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22435' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\decoder_pseudo_trigger' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22436' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\decoder_pseudo_trigger_q' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22437' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_rs1val' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22438' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_rs2val' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22439' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_rs1val_valid' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22440' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_rs2val_valid' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22441' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cpu_state' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22442' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\irq_state' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22443' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\set_mem_do_rinst' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22444' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\set_mem_do_rdata' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22445' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\set_mem_do_wdata' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22446' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\latched_store' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22447' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\latched_stalu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22448' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\latched_branch' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22449' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\latched_compr' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22450' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\latched_trace' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22451' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\latched_is_lu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22452' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\latched_is_lh' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22453' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\latched_is_lb' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22454' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\latched_rd' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22455' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\current_pc' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22456' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\pcpi_timeout' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22457' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\next_irq_pending' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22458' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\do_waitirq' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22459' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_out_q' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22460' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_out_0_q' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22461' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_wait' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22462' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_wait_2' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. created $dff cell `$procdff$22463' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\clear_prefetched_high_word_q' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1272$3880'. created $dff cell `$procdff$22464' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\pcpi_insn' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22465' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_lui' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22466' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_auipc' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22467' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_jal' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22468' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_jalr' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22469' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_beq' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22470' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_bne' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22471' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_blt' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22472' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_bge' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22473' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_bltu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22474' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_bgeu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22475' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_lb' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22476' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_lh' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22477' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_lw' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22478' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_lbu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22479' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_lhu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22480' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_sb' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22481' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_sh' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22482' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_sw' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22483' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_addi' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22484' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_slti' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22485' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_sltiu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22486' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_xori' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22487' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_ori' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22488' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_andi' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22489' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_slli' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22490' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_srli' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22491' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_srai' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22492' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_add' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22493' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_sub' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22494' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_sll' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22495' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_slt' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22496' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_sltu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22497' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_xor' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22498' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_srl' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22499' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_sra' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22500' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_or' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22501' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_and' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22502' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_rdcycle' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22503' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_rdcycleh' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22504' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_rdinstr' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22505' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_rdinstrh' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22506' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_ecall_ebreak' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22507' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_getq' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22508' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_setq' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22509' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_retirq' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22510' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_maskirq' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22511' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_waitirq' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22512' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_timer' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22513' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\decoded_rd' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22514' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\decoded_rs1' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22515' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\decoded_rs2' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22516' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\decoded_imm' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22517' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\decoded_imm_uj' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22518' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\compressed_instr' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22519' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_lui_auipc_jal' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22520' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_lb_lh_lw_lbu_lhu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22521' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_slli_srli_srai' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22522' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_jalr_addi_slti_sltiu_xori_ori_andi' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22523' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_sb_sh_sw' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22524' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_sll_srl_sra' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22525' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_lui_auipc_jal_jalr_addi_add_sub' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22526' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_slti_blt_slt' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22527' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_sltiu_bltu_sltu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22528' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_beq_bne_blt_bge_bltu_bgeu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22529' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_lbu_lhu_lw' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22530' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_alu_reg_imm' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22531' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_alu_reg_reg' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22532' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_compare' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. created $dff cell `$procdff$22533' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_insn_addr' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3580'. created $dff cell `$procdff$22534' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\q_ascii_instr' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3580'. created $dff cell `$procdff$22535' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\q_insn_imm' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3580'. created $dff cell `$procdff$22536' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\q_insn_opcode' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3580'. created $dff cell `$procdff$22537' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\q_insn_rs1' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3580'. created $dff cell `$procdff$22538' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\q_insn_rs2' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3580'. created $dff cell `$procdff$22539' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\q_insn_rd' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3580'. created $dff cell `$procdff$22540' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_next' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3580'. created $dff cell `$procdff$22541' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_valid_insn' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3580'. created $dff cell `$procdff$22542' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cached_ascii_instr' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3580'. created $dff cell `$procdff$22543' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cached_insn_imm' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3580'. created $dff cell `$procdff$22544' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cached_insn_opcode' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3580'. created $dff cell `$procdff$22545' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cached_insn_rs1' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3580'. created $dff cell `$procdff$22546' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cached_insn_rs2' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3580'. created $dff cell `$procdff$22547' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cached_insn_rd' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3580'. created $dff cell `$procdff$22548' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_addr' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3555'. created $dff cell `$procdff$22549' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_valid' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3555'. created $dff cell `$procdff$22550' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_instr' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3555'. created $dff cell `$procdff$22551' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_wdata' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3555'. created $dff cell `$procdff$22552' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_wstrb' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3555'. created $dff cell `$procdff$22553' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_state' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3555'. created $dff cell `$procdff$22554' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_la_secondword' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3555'. created $dff cell `$procdff$22555' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\prefetched_high_word' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3555'. created $dff cell `$procdff$22556' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_16bit_buffer' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3555'. created $dff cell `$procdff$22557' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\next_insn_opcode' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:414$3517'. created $dff cell `$procdff$22558' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_rdata_q' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:414$3517'. created $dff cell `$procdff$22559' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_la_firstword_reg' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:374$3509'. created $dff cell `$procdff$22560' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\last_mem_valid' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:374$3509'. created $dff cell `$procdff$22561' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\tx_pending [1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5018'. created $dff cell `$procdff$22562' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\tx_data_reg[1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5018'. created $dff cell `$procdff$22563' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\tx_addr_reg[1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5018'. created $dff cell `$procdff$22564' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\tx_pending [0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5017'. created $dff cell `$procdff$22565' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\tx_addr_reg[0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5017'. created $dff cell `$procdff$22566' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\tx_data_reg[0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5017'. created $dff cell `$procdff$22567' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\rx_pending [1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5012'. created $adff cell `$procdff$22568' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\rx_data_reg[1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5011'. created $dff cell `$procdff$22569' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\rx_addr_reg[1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5011'. created $dff cell `$procdff$22570' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\rx_pending [0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5006'. created $adff cell `$procdff$22571' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\rx_data_reg[0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5005'. created $dff cell `$procdff$22572' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\rx_addr_reg[0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5005'. created $dff cell `$procdff$22573' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\wb_addr' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4962'. created $dff cell `$procdff$22574' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$4939' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4962'. created $dff cell `$procdff$22575' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$4940' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4962'. created $dff cell `$procdff$22576' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\wb_addr_lsb' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4962'. created $dff cell `$procdff$22577' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\wb_wdata_byte' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4962'. created $dff cell `$procdff$22578' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\mux.j' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4962'. created $dff cell `$procdff$22579' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$4941' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4962'. created $dff cell `$procdff$22580' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$4942' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4962'. created $dff cell `$procdff$22581' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$4945' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4962'. created $dff cell `$procdff$22582' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$4946' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4962'. created $dff cell `$procdff$22583' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$4947' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4962'. created $dff cell `$procdff$22584' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$4948' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4962'. created $dff cell `$procdff$22585' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\t_chan' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:212$4959'. created $dff cell `$procdff$22586' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\t_busy' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:206$4957'. created $adff cell `$procdff$22587' with positive edge clock and positive level reset. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.\rdata' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3325'. created $dff cell `$procdff$22588' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3321_ADDR' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3325'. created $dff cell `$procdff$22589' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3321_DATA' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3325'. created $dff cell `$procdff$22590' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3321_EN' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3325'. created $dff cell `$procdff$22591' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3322_ADDR' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3325'. created $dff cell `$procdff$22592' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3322_DATA' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3325'. created $dff cell `$procdff$22593' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3322_EN' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3325'. created $dff cell `$procdff$22594' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3323_ADDR' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3325'. created $dff cell `$procdff$22595' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3323_DATA' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3325'. created $dff cell `$procdff$22596' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3323_EN' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3325'. created $dff cell `$procdff$22597' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3324_ADDR' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3325'. created $dff cell `$procdff$22598' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3324_DATA' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3325'. created $dff cell `$procdff$22599' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3324_EN' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3325'. created $dff cell `$procdff$22600' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\uart_div' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:193$3316'. created $dff cell `$procdff$22601' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_rdata' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:185$3314'. created $dff cell `$procdff$22602' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_ack' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:177$3304'. created $dff cell `$procdff$22603' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_rd_data' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3287'. created $dff cell `$procdff$22604' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_rd_ctrl' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3287'. created $dff cell `$procdff$22605' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_wr_data' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3287'. created $dff cell `$procdff$22606' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_wr_div' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3287'. created $dff cell `$procdff$22607' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\urf_overflow' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:154$3282'. created $adff cell `$procdff$22608' with positive edge clock and positive level reset. Creating register for signal `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.\led_ctrl' using process `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.$proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3275'. created $adff cell `$procdff$22609' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\evt_cnt' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:536$3269'. created $adff cell `$procdff$22610' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\sof_pending' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:656$3264'. created $dff cell `$procdff$22611' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\sof_ind' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:653$3262'. created $dff cell `$procdff$22612' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\pad_pu' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:643$3261'. created $dff cell `$procdff$22613' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\rst_pending' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:636$3257'. created $adff cell `$procdff$22614' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\timeout_reset' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:628$3253'. created $dff cell `$procdff$22615' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\timeout_suspend' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:619$3249'. created $dff cell `$procdff$22616' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\eps_bus_ack_wait' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:514$3235'. created $adff cell `$procdff$22617' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\eps_bus_req_ok_dly' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:510$3232'. created $dff cell `$procdff$22618' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\eps_bus_read' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3222'. created $dff cell `$procdff$22619' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\eps_bus_write' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3222'. created $dff cell `$procdff$22620' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\eps_bus_req' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3222'. created $dff cell `$procdff$22621' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\cr_pu_ena' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3220'. created $adff cell `$procdff$22622' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\cr_cel_ena' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3220'. created $adff cell `$procdff$22623' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\cr_addr_chk' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3220'. created $adff cell `$procdff$22624' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\cr_addr' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3220'. created $adff cell `$procdff$22625' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\cel_rel' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3198'. created $dff cell `$procdff$22626' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\csr_bus_req' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3198'. created $dff cell `$procdff$22627' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\cr_bus_we' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3198'. created $dff cell `$procdff$22628' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\ir_bus_we' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3198'. created $dff cell `$procdff$22629' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\evt_rd_ack' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3198'. created $dff cell `$procdff$22630' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\rst_clear' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3198'. created $dff cell `$procdff$22631' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\sof_clear' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3198'. created $dff cell `$procdff$22632' with positive edge clock. Creating register for signal `$paramod\xclk_wb\DW=16\AW=12.\m_cyc_i' using process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:99$3194'. created $adff cell `$procdff$22633' with positive edge clock and positive level reset. Creating register for signal `$paramod\xclk_wb\DW=16\AW=12.\s_cyc_d' using process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:83$3190'. created $dff cell `$procdff$22634' with positive edge clock. Creating register for signal `$paramod\xclk_wb\DW=16\AW=12.\s_ack_d' using process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:83$3190'. created $dff cell `$procdff$22635' with positive edge clock. Creating register for signal `$paramod\xclk_wb\DW=16\AW=12.\s_rdata' using process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:73$3187'. created $dff cell `$procdff$22636' with positive edge clock. Creating register for signal `$paramod\xclk_wb\DW=16\AW=12.\m_rdata_i' using process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:68$3186'. created $dff cell `$procdff$22637' with positive edge clock. Creating register for signal `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0.\ack_i' using process `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v:50$4926'. created $adff cell `$procdff$22638' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\sel' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4905'. created $adff cell `$procdff$22639' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\busy' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4905'. created $adff cell `$procdff$22640' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\m_addr' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4893'. created $adff cell `$procdff$22641' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\m_wdata' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4893'. created $adff cell `$procdff$22642' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\m_we' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4893'. created $adff cell `$procdff$22643' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\m_wmsk' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4893'. created $adff cell `$procdff$22644' with positive edge clock and positive level reset. Creating register for signal `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.\pb_rst_n' using process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:184$3098'. created $adff cell `$procdff$22645' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$2947'. created $adff cell `$procdff$22646' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1274$2940'. created $dff cell `$procdff$22647' with negative edge clock. Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$2936'. created $adff cell `$procdff$22648' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1143$2929'. created $dff cell `$procdff$22649' with negative edge clock. Creating register for signal `\e1_rx_liu.\out_data' using process `\e1_rx_liu.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_liu.v:59$177'. created $dff cell `$procdff$22650' with positive edge clock. Creating register for signal `\e1_rx_liu.\out_valid' using process `\e1_rx_liu.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_liu.v:59$177'. created $dff cell `$procdff$22651' with positive edge clock. Creating register for signal `\e1_rx_liu.\rx_data_r' using process `\e1_rx_liu.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_liu.v:52$176'. created $dff cell `$procdff$22652' with positive edge clock. Creating register for signal `\e1_rx_liu.\rx_clk_r' using process `\e1_rx_liu.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_liu.v:52$176'. created $dff cell `$procdff$22653' with positive edge clock. Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1074$2926'. created $adff cell `$procdff$22654' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1026$2923'. created $dff cell `$procdff$22655' with negative edge clock. Creating register for signal `\e1_rx_deframer.\aligned' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:406$141'. created $dff cell `$procdff$22656' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_data' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$135'. created $dff cell `$procdff$22657' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_frame' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$135'. created $dff cell `$procdff$22658' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_ts' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$135'. created $dff cell `$procdff$22659' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_ts_is0' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$135'. created $dff cell `$procdff$22660' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_first' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$135'. created $dff cell `$procdff$22661' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_last' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$135'. created $dff cell `$procdff$22662' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_valid' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$135'. created $dff cell `$procdff$22663' with positive edge clock. Creating register for signal `\e1_rx_deframer.\error' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:357$127'. created $dff cell `$procdff$22664' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ec_fas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$109'. created $dff cell `$procdff$22665' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ec_nfas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$109'. created $dff cell `$procdff$22666' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ec_crc' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$109'. created $dff cell `$procdff$22667' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ec_mfa' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$109'. created $dff cell `$procdff$22668' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ed_crc' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$89'. created $dff cell `$procdff$22669' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ep_crc' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$89'. created $dff cell `$procdff$22670' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ed_mfa' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$89'. created $dff cell `$procdff$22671' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ep_mfa' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$89'. created $dff cell `$procdff$22672' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ed_fas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$67'. created $dff cell `$procdff$22673' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ep_fas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$67'. created $dff cell `$procdff$22674' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ed_nfas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$67'. created $dff cell `$procdff$22675' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ep_nfas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$67'. created $dff cell `$procdff$22676' with positive edge clock. Creating register for signal `\e1_rx_deframer.\crc_smf' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:306$66'. created $dff cell `$procdff$22677' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts0_msbs' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:274$55'. created $dff cell `$procdff$22678' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts0_msbs_match_mf' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:274$55'. created $dff cell `$procdff$22679' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts0_msbs_match_crc' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:274$55'. created $dff cell `$procdff$22680' with positive edge clock. Creating register for signal `\e1_rx_deframer.\mfa_timeout' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:266$51'. created $dff cell `$procdff$22681' with positive edge clock. Creating register for signal `\e1_rx_deframer.\fas_pos' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:258$47'. created $dff cell `$procdff$22682' with positive edge clock. Creating register for signal `\e1_rx_deframer.\frame' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$37'. created $dff cell `$procdff$22683' with positive edge clock. Creating register for signal `\e1_rx_deframer.\frame_smf_first' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$37'. created $dff cell `$procdff$22684' with positive edge clock. Creating register for signal `\e1_rx_deframer.\frame_smf_last' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$37'. created $dff cell `$procdff$22685' with positive edge clock. Creating register for signal `\e1_rx_deframer.\frame_mf_first' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$37'. created $dff cell `$procdff$22686' with positive edge clock. Creating register for signal `\e1_rx_deframer.\frame_mf_last' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$37'. created $dff cell `$procdff$22687' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:219$33'. created $dff cell `$procdff$22688' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts_is_ts0' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:219$33'. created $dff cell `$procdff$22689' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts_is_ts31' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:219$33'. created $dff cell `$procdff$22690' with positive edge clock. Creating register for signal `\e1_rx_deframer.\bit' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:207$29'. created $dff cell `$procdff$22691' with positive edge clock. Creating register for signal `\e1_rx_deframer.\bit_first' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:207$29'. created $dff cell `$procdff$22692' with positive edge clock. Creating register for signal `\e1_rx_deframer.\bit_last' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:207$29'. created $dff cell `$procdff$22693' with positive edge clock. Creating register for signal `\e1_rx_deframer.\fsm_state' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:142$19'. created $dff cell `$procdff$22694' with positive edge clock. Creating register for signal `\e1_rx_deframer.\data_match_fas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:133$16'. created $dff cell `$procdff$22695' with positive edge clock. Creating register for signal `\e1_rx_deframer.\data' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:128$15'. created $dff cell `$procdff$22696' with positive edge clock. Creating register for signal `\e1_rx_deframer.\strobe' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:121$14'. created $dff cell `$procdff$22697' with positive edge clock. Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:957$2920'. created $adff cell `$procdff$22698' with negative edge clock and positive level reset. Creating register for signal `\e1_crc4.\state' using process `\e1_crc4.$proc$/build/gateware/cores/no2e1//rtl/e1_crc4.v:38$10'. created $dff cell `$procdff$22699' with positive edge clock. 73.3.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2919'. Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:909$2917'. Removing empty process `SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:909$2917'. Removing empty process `SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2916'. Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:866$2915'. Removing empty process `SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:866$2915'. Removing empty process `SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2914'. Removing empty process `SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:830$2913'. Removing empty process `SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2912'. Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$2909'. Removing empty process `SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$2909'. Removing empty process `SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2908'. Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:697$2902'. Removing empty process `SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:697$2902'. Removing empty process `SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2901'. Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$2898'. Removing empty process `SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$2898'. Removing empty process `SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2897'. Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:566$2891'. Removing empty process `SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:566$2891'. Removing empty process `SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2890'. Removing empty process `SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:497$2888'. Removing empty process `SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2887'. Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:449$2885'. Removing empty process `SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:449$2885'. Removing empty process `SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2884'. Removing empty process `SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:380$2882'. Removing empty process `SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2881'. Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:332$2879'. Removing empty process `SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:332$2879'. Removing empty process `SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2878'. Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:289$2877'. Removing empty process `SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:289$2877'. Removing empty process `SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2876'. Removing empty process `SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:253$2875'. Removing empty process `$paramod\wb_epbuf\AW=9\DW=32.$proc$/build/gateware/common/rtl/wb_epbuf.v:51$4862'. Found and cleaned up 1 empty switch in `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4851'. Removing empty process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4851'. Found and cleaned up 2 empty switches in `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$4844'. Removing empty process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$4844'. Found and cleaned up 1 empty switch in `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4841'. Removing empty process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4841'. Removing empty process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4828'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$4809'. Found and cleaned up 1 empty switch in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:178$4805'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:178$4805'. Found and cleaned up 1 empty switch in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:174$4802'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:174$4802'. Found and cleaned up 1 empty switch in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:157$4792'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:157$4792'. Found and cleaned up 1 empty switch in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:153$4788'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:153$4788'. Found and cleaned up 1 empty switch in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:142$4786'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:142$4786'. Found and cleaned up 4 empty switches in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:98$4770'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:98$4770'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:92$4769'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:86$4765'. Removing empty process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4761'. Removing empty process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4757'. Removing empty process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4753'. Removing empty process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4746'. Found and cleaned up 1 empty switch in `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4741'. Removing empty process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4741'. Found and cleaned up 3 empty switches in `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4737'. Removing empty process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4737'. Found and cleaned up 1 empty switch in `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4733'. Removing empty process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4733'. Found and cleaned up 2 empty switches in `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4725'. Removing empty process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4725'. Found and cleaned up 1 empty switch in `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4723'. Removing empty process `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4723'. Found and cleaned up 1 empty switch in `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4710'. Removing empty process `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4710'. Found and cleaned up 2 empty switches in `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4686'. Removing empty process `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4686'. Removing empty process `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:212$5316'. Removing empty process `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:205$5310'. Removing empty process `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:197$5306'. Removing empty process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:255$5300'. Removing empty process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:248$5296'. Removing empty process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:241$5294'. Found and cleaned up 1 empty switch in `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$5276'. Removing empty process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$5276'. Found and cleaned up 1 empty switch in `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$5275'. Removing empty process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$5275'. Found and cleaned up 1 empty switch in `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$5267'. Removing empty process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$5267'. Removing empty process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:67$5266'. Found and cleaned up 2 empty switches in `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5265'. Removing empty process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5265'. Found and cleaned up 2 empty switches in `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:51$5262'. Removing empty process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:51$5262'. Found and cleaned up 1 empty switch in `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:42$5258'. Removing empty process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:42$5258'. Removing empty process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:35$5254'. Removing empty process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:102$5248'. Found and cleaned up 1 empty switch in `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:95$5247'. Removing empty process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:95$5247'. Found and cleaned up 2 empty switches in `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:88$5244'. Removing empty process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:88$5244'. Found and cleaned up 2 empty switches in `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:77$5240'. Removing empty process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:77$5240'. Removing empty process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:70$5236'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4537'. Removing empty process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4537'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4531'. Removing empty process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4531'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4529'. Removing empty process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4529'. Removing empty process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:83$4520'. Removing empty process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:67$4514'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4513'. Found and cleaned up 1 empty switch in `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4508'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4508'. Found and cleaned up 3 empty switches in `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4504'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4504'. Found and cleaned up 1 empty switch in `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4500'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4500'. Found and cleaned up 2 empty switches in `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4492'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4492'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5228'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5224'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5220'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5216'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5212'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5208'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5204'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5200'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5196'. Removing empty process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4483'. Found and cleaned up 16 empty switches in `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327'. Removing empty process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4327'. Found and cleaned up 1 empty switch in `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:73$4326'. Removing empty process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:73$4326'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5173'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5169'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5165'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5161'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5157'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5153'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5149'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5145'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5141'. Found and cleaned up 1 empty switch in `\sysmgr.$proc$/build/gateware/e1-tracer/rtl/sysmgr.v:81$1598'. Removing empty process `sysmgr.$proc$/build/gateware/e1-tracer/rtl/sysmgr.v:81$1598'. Found and cleaned up 1 empty switch in `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:131$1596'. Removing empty process `misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:131$1596'. Found and cleaned up 1 empty switch in `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:95$1593'. Removing empty process `misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:95$1593'. Found and cleaned up 2 empty switches in `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:80$1592'. Removing empty process `misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:80$1592'. Found and cleaned up 1 empty switch in `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:70$1587'. Removing empty process `misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:70$1587'. Removing empty process `misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:64$1582'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:241$1578'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:229$1575'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:202$1569'. Found and cleaned up 1 empty switch in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:191$1565'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:191$1565'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:182$1559'. Found and cleaned up 1 empty switch in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:175$1552'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:175$1552'. Found and cleaned up 1 empty switch in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:170$1550'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:170$1550'. Found and cleaned up 1 empty switch in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:159$1546'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:159$1546'. Found and cleaned up 1 empty switch in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:152$1543'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:152$1543'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:136$1531'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:126$1530'. Found and cleaned up 8 empty switches in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:86$1528'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:86$1528'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:134$1527'. Found and cleaned up 2 empty switches in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1525'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1525'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:110$1518'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:102$1513'. Found and cleaned up 1 empty switch in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1503'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1503'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:79$1500'. Found and cleaned up 4 empty switches in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1497'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1497'. Found and cleaned up 2 empty switches in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:236$1493'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:236$1493'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:428$1485'. Found and cleaned up 1 empty switch in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:421$1482'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:421$1482'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:414$1476'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:403$1475'. Found and cleaned up 1 empty switch in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:399$1472'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:399$1472'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:387$1466'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:380$1464'. Found and cleaned up 2 empty switches in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1451'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1451'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:345$1448'. Found and cleaned up 4 empty switches in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1443'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1443'. Found and cleaned up 1 empty switch in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1439'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1439'. Found and cleaned up 1 empty switch in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1432'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1432'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:225$1427'. Found and cleaned up 2 empty switches in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1424'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1424'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:175$1415'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:162$1406'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:374$1403'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:353$1394'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:349$1392'. Found and cleaned up 1 empty switch in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:340$1389'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:340$1389'. Found and cleaned up 1 empty switch in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:336$1386'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:336$1386'. Found and cleaned up 1 empty switch in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1369'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1369'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:318$1368'. Found and cleaned up 1 empty switch in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:304$1347'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:304$1347'. Found and cleaned up 2 empty switches in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1343'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1343'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:284$1342'. Found and cleaned up 2 empty switches in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:244$1340'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:244$1340'. Found and cleaned up 2 empty switches in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:230$1337'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:230$1337'. Found and cleaned up 2 empty switches in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:220$1334'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:220$1334'. Found and cleaned up 1 empty switch in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:215$1333'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:215$1333'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:198$1325'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:188$1324'. Found and cleaned up 18 empty switches in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:117$1308'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:117$1308'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:49$1307'. Found and cleaned up 1 empty switch in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:181$1305'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:181$1305'. Found and cleaned up 3 empty switches in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1303'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1303'. Found and cleaned up 3 empty switches in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:137$1302'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:137$1302'. Found and cleaned up 2 empty switches in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:124$1301'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:124$1301'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:120$1300'. Found and cleaned up 1 empty switch in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:111$1293'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:111$1293'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:97$1286'. Found and cleaned up 2 empty switches in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1285'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1285'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:67$1275'. Found and cleaned up 2 empty switches in `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5117'. Removing empty process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5117'. Found and cleaned up 1 empty switch in `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:80$1271'. Removing empty process `usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:80$1271'. Found and cleaned up 1 empty switch in `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:76$1269'. Removing empty process `usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:76$1269'. Removing empty process `usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1266'. Removing empty process `usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1258'. Found and cleaned up 1 empty switch in `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:163$5111'. Removing empty process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:163$5111'. Removing empty process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:160$5109'. Removing empty process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:147$5084'. Removing empty process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:91$5081'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4220'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4211'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4211'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4209'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4209'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4200'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4200'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4198'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4198'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4189'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4189'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4187'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4187'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4178'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4178'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4176'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4176'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4174'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4165'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4165'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4163'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4163'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4154'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4154'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4152'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4152'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4143'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4143'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4141'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4141'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4132'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4132'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4130'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4130'. Removing empty process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:0$5042'. Found and cleaned up 1 empty switch in `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:124$5037'. Removing empty process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:124$5037'. Removing empty process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:116$5032'. Removing empty process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:105$5027'. Removing empty process `xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:40$1103'. Removing empty process `xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:34$1102'. Removing empty process `xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:28$1100'. Removing empty process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:149$4107'. Found and cleaned up 2 empty switches in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4098'. Removing empty process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4098'. Removing empty process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:109$4094'. Removing empty process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:103$4092'. Found and cleaned up 55 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3914'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$3900'. Found and cleaned up 2 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1288$3886'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1288$3886'. Found and cleaned up 2 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1274$3881'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1274$3881'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1272$3880'. Found and cleaned up 2 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1228$3858'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1228$3858'. Found and cleaned up 8 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1165$3846'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1165$3846'. Found and cleaned up 22 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3586'. Found and cleaned up 3 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3584'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3584'. Found and cleaned up 5 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3580'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3580'. Found and cleaned up 47 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:684$3579'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:684$3579'. Found and cleaned up 16 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3555'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3555'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1218$4079'. Found and cleaned up 19 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:414$3517'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:414$3517'. Found and cleaned up 3 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3514'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3514'. Found and cleaned up 2 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:374$3509'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:374$3509'. Found and cleaned up 1 empty switch in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3435'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3435'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5018'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5017'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5012'. Found and cleaned up 1 empty switch in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5011'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5011'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5006'. Found and cleaned up 1 empty switch in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5005'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5005'. Found and cleaned up 1 empty switch in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$4995'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$4995'. Found and cleaned up 5 empty switches in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4962'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4962'. Found and cleaned up 1 empty switch in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:212$4959'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:212$4959'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:206$4957'. Found and cleaned up 4 empty switches in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$4955'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$4955'. Found and cleaned up 4 empty switches in `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3325'. Removing empty process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3325'. Found and cleaned up 1 empty switch in `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:193$3316'. Removing empty process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:193$3316'. Found and cleaned up 1 empty switch in `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:185$3314'. Removing empty process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:185$3314'. Found and cleaned up 1 empty switch in `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:177$3304'. Removing empty process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:177$3304'. Found and cleaned up 1 empty switch in `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3287'. Removing empty process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3287'. Removing empty process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:154$3282'. Found and cleaned up 1 empty switch in `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.$proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3275'. Removing empty process `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.$proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3275'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:536$3269'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:656$3264'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:653$3262'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:643$3261'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:643$3261'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:636$3257'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:628$3253'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:628$3253'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:619$3249'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:619$3249'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:514$3235'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:510$3232'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3222'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3222'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:697$3273'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3220'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3220'. Found and cleaned up 2 empty switches in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:442$3216'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:442$3216'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3198'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3198'. Removing empty process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:99$3194'. Removing empty process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:83$3190'. Found and cleaned up 1 empty switch in `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:73$3187'. Removing empty process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:73$3187'. Found and cleaned up 1 empty switch in `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:68$3186'. Removing empty process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:68$3186'. Removing empty process `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v:50$4926'. Found and cleaned up 1 empty switch in `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4905'. Removing empty process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4905'. Found and cleaned up 3 empty switches in `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$4896'. Removing empty process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$4896'. Found and cleaned up 1 empty switch in `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4893'. Removing empty process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4893'. Removing empty process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4874'. Removing empty process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3103'. Removing empty process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3101'. Removing empty process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3099'. Removing empty process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:184$3098'. Removing empty process `SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2950'. Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$2947'. Removing empty process `SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$2947'. Removing empty process `SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2946'. Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1274$2940'. Removing empty process `SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1274$2940'. Removing empty process `SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2939'. Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$2936'. Removing empty process `SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$2936'. Removing empty process `SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2935'. Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1143$2929'. Removing empty process `SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1143$2929'. Removing empty process `e1_rx_liu.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_liu.v:59$177'. Removing empty process `e1_rx_liu.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_liu.v:52$176'. Removing empty process `SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2928'. Removing empty process `SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1074$2926'. Removing empty process `SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2925'. Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1026$2923'. Removing empty process `SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1026$2923'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:406$141'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:406$141'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$135'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$135'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:357$127'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$109'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$109'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$89'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$89'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$67'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$67'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:306$66'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:306$66'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:274$55'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:274$55'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:266$51'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:266$51'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:258$47'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:258$47'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$37'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$37'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:219$33'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:219$33'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:207$29'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:207$29'. Found and cleaned up 10 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:149$21'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:149$21'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:142$19'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:142$19'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:133$16'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:133$16'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:128$15'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:128$15'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:121$14'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:121$14'. Removing empty process `SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2922'. Removing empty process `SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:957$2920'. Found and cleaned up 1 empty switch in `\e1_crc4.$proc$/build/gateware/cores/no2e1//rtl/e1_crc4.v:38$10'. Removing empty process `e1_crc4.$proc$/build/gateware/cores/no2e1//rtl/e1_crc4.v:38$10'. Cleaned up 446 empty switches. 73.4. Executing FLATTEN pass (flatten design). Deleting now unused module $paramod\wb_epbuf\AW=9\DW=32. Deleting now unused module $paramod\wb_arbiter\N=2\DW=32\AW=9. Deleting now unused module $paramod\wb_dma\A0W=14\A1W=9\DW=32. Deleting now unused module $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr. Deleting now unused module $paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0. Deleting now unused module soc_iobuf. Deleting now unused module $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100. Deleting now unused module $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101. Deleting now unused module picorv32_ice40_regs. Deleting now unused module $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000. Deleting now unused module $paramod\e1_rx\LIU=1\MFW=7. Deleting now unused module $paramod\e1_wb_rx\LIU=1\MFW=7. Deleting now unused module $paramod\uart_tx\DIV_WIDTH=12. Deleting now unused module $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2. Deleting now unused module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Deleting now unused module $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1. Deleting now unused module $paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf. Deleting now unused module $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32. Deleting now unused module capcnt32_sb_mac16. Deleting now unused module capcnt16_sb_mac16. Deleting now unused module $paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf. Deleting now unused module sysmgr. Deleting now unused module misc. Deleting now unused module usb_tx_pkt. Deleting now unused module usb_tx_ll. Deleting now unused module usb_trans. Deleting now unused module usb_rx_pkt. Deleting now unused module usb_rx_ll. Deleting now unused module $paramod\ram_sdp\AWIDTH=9\DWIDTH=8. Deleting now unused module usb_ep_status. Deleting now unused module $paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4. Deleting now unused module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Deleting now unused module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Deleting now unused module $paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7. Deleting now unused module xclk_strobe. Deleting now unused module $paramod\capcnt\W=32. Deleting now unused module $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0. Deleting now unused module $paramod\capcnt\W=16. Deleting now unused module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Deleting now unused module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32. Deleting now unused module $paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram. Deleting now unused module $paramod\soc_spram\AW=14. Deleting now unused module $paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0. Deleting now unused module $paramod\uart_wb\DIV_WIDTH=12\DW=32. Deleting now unused module $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb. Deleting now unused module $paramod\usb\EPDW=32. Deleting now unused module $paramod\xclk_wb\DW=16\AW=12. Deleting now unused module $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0. Deleting now unused module $paramod\wb_arbiter\N=3\DW=32\AW=14. Deleting now unused module $paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base. Deleting now unused module $paramod\ice40_spi_wb\N_CS=2\WITH_IOB=1\UNIT=1. Deleting now unused module e1_rx_liu. Deleting now unused module e1_rx_deframer. Deleting now unused module e1_crc4. <suppressed ~64 debug messages> 73.5. Executing TRIBUF pass. 73.6. Executing DEMINOUT pass (demote inout ports to input or output). Demoting inout port top.flash_cs_n to output. Demoting inout port top.liu_cs_n to output. 73.7. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~10757 debug messages> 73.8. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 986 unused cells and 14167 unused wires. <suppressed ~1109 debug messages> 73.9. Executing CHECK pass (checking for obvious problems). checking module top.. found and reported 0 problems. 73.10. Executing OPT pass (performing simple optimizations). 73.10.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.10.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~1413 debug messages> Removed a total of 471 cells. 73.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port B of cell $flatten\misc_I.\dfu_I.$procmux$11979: \misc_I.dfu_I.wb_req -> 1'1 Replacing known input bits on port B of cell $flatten\sys_mgr_I.$procmux$11408: \sys_mgr_I.rst_cnt -> { 1'1 \sys_mgr_I.rst_cnt [2:0] } Analyzing evaluation results. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12103. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12109. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12112. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12124. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12131. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12134. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12147. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12159. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12162. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12171. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12174. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12182. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12184. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12187. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12248. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12250. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12253. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12335. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12340. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12343. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12382. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12385. dead port 1/3 on $pmux $flatten\soc_I.\cpu_I.$procmux$12396. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12428. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12441. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12454. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12493. dead port 1/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12690. dead port 2/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12690. dead port 3/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12690. dead port 4/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12690. dead port 5/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12690. dead port 6/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12690. dead port 1/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$12696. dead port 2/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$12696. dead port 3/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$12696. dead port 4/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$12696. dead port 5/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$12696. dead port 4/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$12729. dead port 5/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$12729. dead port 6/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$12729. dead port 7/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$12729. dead port 8/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$12729. dead port 10/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$12729. dead port 11/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$12729. dead port 1/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12934. dead port 2/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12934. dead port 3/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12934. dead port 4/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12934. dead port 5/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12934. dead port 6/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12934. dead port 3/4 on $pmux $flatten\soc_I.\cpu_I.$procmux$12998. dead port 4/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13017. dead port 5/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13017. dead port 6/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13017. dead port 7/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13017. dead port 8/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13017. dead port 10/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13017. dead port 11/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13017. dead port 3/4 on $pmux $flatten\soc_I.\cpu_I.$procmux$13199. dead port 4/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13215. dead port 5/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13215. dead port 6/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13215. dead port 7/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13215. dead port 8/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13215. dead port 10/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13215. dead port 11/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13215. dead port 4/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13377. dead port 5/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13377. dead port 6/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13377. dead port 7/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13377. dead port 8/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13377. dead port 10/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13377. dead port 11/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13377. dead port 1/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13428. dead port 2/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13428. dead port 3/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13428. dead port 4/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13428. dead port 5/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13428. dead port 7/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13428. dead port 8/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13428. dead port 1/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$13525. dead port 2/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$13525. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$13530. dead port 1/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$13534. dead port 2/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$13534. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$13539. dead port 1/8 on $pmux $flatten\soc_I.\cpu_I.$procmux$13554. dead port 2/8 on $pmux $flatten\soc_I.\cpu_I.$procmux$13554. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$14685. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$14692. dead port 1/2 on $mux $flatten\soc_I.\e1_buf_I.$procmux$14863. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10004. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10004. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10004. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10004. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10004. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10019. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10019. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10019. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10019. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10019. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10036. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10036. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10036. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10036. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10036. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10055. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10055. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10055. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10055. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10076. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10076. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10076. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10076. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10099. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10099. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10099. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10099. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10099. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10124. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10124. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10124. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10124. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10124. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10151. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10151. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10151. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10151. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10151. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10180. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10180. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10180. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10180. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10180. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10211. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10211. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10211. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10211. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10211. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10244. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10244. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10244. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10244. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10244. dead port 1/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10279. dead port 2/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10279. dead port 3/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10279. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10319. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10319. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10319. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10319. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10319. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10329. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10329. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10329. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10329. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10329. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10343. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10343. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10343. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10343. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10343. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10359. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10359. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10359. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10359. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10359. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10379. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10379. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10379. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10379. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10403. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10403. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10403. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10403. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10403. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10431. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10431. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10431. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10431. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10431. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10463. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10463. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10463. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10463. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10463. dead port 1/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10499. dead port 2/3 on $pmux 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port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10539. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10539. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10573. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10573. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10573. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10573. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10603. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10603. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10603. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10603. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10603. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10615. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10615. dead port 3/5 on $pmux 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on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10667. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10667. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10667. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10725. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10725. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10725. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10725. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10725. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10738. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10738. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10738. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10738. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10738. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10753. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10753. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10753. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10753. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10753. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10770. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10770. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10770. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10770. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10770. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10789. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10789. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10789. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10789. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10789. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10810. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10810. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10810. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10810. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10810. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10833. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10833. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10833. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10833. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10833. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10858. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10858. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10858. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10858. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10858. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10885. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10885. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10885. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10885. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10885. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10914. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10914. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10914. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10914. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10914. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10945. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10945. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10945. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10945. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10945. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10978. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10978. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10978. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10978. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10978. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11013. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11013. dead port 4/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11013. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11053. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11053. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11053. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11053. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11053. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11063. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11063. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11063. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11063. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11063. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11077. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11077. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11077. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11077. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11077. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11093. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11093. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11093. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11093. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11093. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11113. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11113. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11113. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11113. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11113. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11137. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11137. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11137. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11137. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11137. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11165. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11165. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11165. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11165. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11165. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11197. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11197. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11197. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11197. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11197. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11233. dead port 3/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11233. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11240. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11240. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11240. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11240. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11240. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11251. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11251. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11251. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11251. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11251. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11273. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11273. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11273. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11273. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11273. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11307. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11307. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11307. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11307. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11337. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11337. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11337. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11337. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11337. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11349. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11349. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11349. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11349. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11349. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11367. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11367. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11367. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11367. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11367. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11375. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11375. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11375. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11375. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11375. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11401. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11401. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11401. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11401. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11401. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5587. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5587. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5587. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5587. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5600. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5600. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5600. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5600. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5615. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5615. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5615. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5615. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5632. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5632. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5632. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5632. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5651. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5651. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5651. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5651. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5672. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5672. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5672. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5672. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5695. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5695. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5695. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5695. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5720. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5720. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5720. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5720. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5747. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5747. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5747. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5747. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5776. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5776. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5776. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5776. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5807. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5807. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5807. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5807. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5840. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5840. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5840. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5840. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5875. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5875. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5875. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5915. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5915. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5915. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5915. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5925. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5925. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5925. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5925. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5939. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5939. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5939. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5939. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5955. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5955. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5955. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5955. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5975. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5975. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5975. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5975. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5999. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5999. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5999. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5999. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6027. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6027. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6027. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6027. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6059. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6059. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6059. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6059. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6095. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6095. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6102. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6102. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6102. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6102. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6113. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6113. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6113. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6113. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6135. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6135. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6135. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6135. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6169. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6169. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6169. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6169. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6199. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6199. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6199. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6199. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6211. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6211. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6211. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6211. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6229. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6229. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6229. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6229. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6237. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6237. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6237. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6237. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6263. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6263. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6263. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6263. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6321. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6321. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6321. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6321. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6321. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6334. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6334. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6334. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6334. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6349. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6349. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6349. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6349. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6366. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6366. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6366. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6366. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6385. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6385. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6385. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6385. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6406. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6406. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6406. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6406. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6429. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6429. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6429. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6429. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6454. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6454. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6454. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6454. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6481. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6481. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6481. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6481. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6510. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6510. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6510. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6510. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6541. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6541. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6541. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6541. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6574. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6574. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6574. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6574. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6609. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6609. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6609. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6649. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6649. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6649. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6649. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6649. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6659. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6659. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6659. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6659. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6673. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6673. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6673. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6673. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6689. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6689. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6689. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6689. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6709. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6709. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6709. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6709. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6733. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6733. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6733. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6733. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6761. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6761. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6761. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6761. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6793. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6793. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6793. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6793. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6829. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6829. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6836. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6836. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6836. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6836. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6836. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6847. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6847. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6847. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6847. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6869. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6869. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6869. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6869. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6903. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6903. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6903. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6903. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6933. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6933. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6933. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6933. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6945. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6945. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6945. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6945. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6963. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6963. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6963. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6963. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6971. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6971. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6971. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6971. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6971. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6997. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6997. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6997. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6997. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7055. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7055. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7055. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7055. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7055. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7068. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7068. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7068. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7068. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7083. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7083. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7083. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7083. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7100. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7100. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7100. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7100. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7119. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7119. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7119. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7119. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7140. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7140. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7140. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7140. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7163. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7163. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7163. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7163. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7163. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7188. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7188. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7188. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7188. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7188. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7215. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7215. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7215. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7215. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7244. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7244. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7244. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7244. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7275. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7275. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7275. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7275. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7308. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7308. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7308. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7308. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7343. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7343. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7343. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7383. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7383. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7383. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7383. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7383. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7393. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7393. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7393. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7393. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7407. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7407. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7407. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7407. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7423. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7423. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7423. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7423. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7443. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7443. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7443. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7443. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7467. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7467. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7467. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7467. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7467. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7495. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7495. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7495. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7495. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7527. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7527. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7527. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7527. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7563. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7563. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7570. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7570. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7570. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7570. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7570. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7581. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7581. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7581. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7581. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7603. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7603. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7603. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7603. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7603. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7637. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7637. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7637. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7637. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7667. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7667. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7667. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7667. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7679. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7679. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7679. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7679. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7697. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7697. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7697. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7697. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7705. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7705. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7705. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7705. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7705. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7731. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7731. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7731. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7731. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7789. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7789. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7789. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7789. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7789. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7802. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7802. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7802. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7802. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7802. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7817. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7817. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7817. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7817. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7834. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7834. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7834. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7834. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7853. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7853. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7853. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7853. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7874. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7874. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7874. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7874. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7897. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7897. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7897. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7897. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7897. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7922. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7922. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7922. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7922. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7922. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7949. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7949. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7949. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7949. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7978. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7978. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7978. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7978. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8009. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8009. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8009. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8009. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8042. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8042. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8042. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8042. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8077. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8077. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8077. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8117. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8117. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8117. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8117. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8117. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8127. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8127. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8127. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8127. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8127. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8141. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8141. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8141. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8141. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8157. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8157. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8157. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8157. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8177. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8177. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8177. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8177. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8201. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8201. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8201. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8201. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8201. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8229. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8229. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8229. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8229. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8261. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8261. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8261. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8261. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8297. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8297. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8304. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8304. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8304. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8304. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8304. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8315. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8315. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8315. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8315. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8315. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8337. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8337. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8337. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8337. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8337. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8371. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8371. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8371. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8371. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8401. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8401. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8401. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8401. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8413. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8413. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8413. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8413. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8413. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8431. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8431. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8431. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8431. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8439. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8439. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8439. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8439. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8439. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8465. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8465. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8465. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8465. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8523. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8523. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8523. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8523. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8523. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8536. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8536. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8536. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8536. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8536. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8551. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8551. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8551. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8551. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8568. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8568. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8568. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8568. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8587. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8587. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8587. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8587. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8608. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8608. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8608. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8608. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8631. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8631. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8631. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8631. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8631. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8656. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8656. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8656. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8656. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8656. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8683. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8683. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8683. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8683. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8683. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8712. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8712. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8712. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8712. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8712. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8743. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8743. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8743. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8743. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8776. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8776. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8776. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8776. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8811. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8811. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8811. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8851. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8851. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8851. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8851. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8851. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8861. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8861. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8861. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8861. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8861. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8875. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8875. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8875. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8875. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8891. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8891. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8891. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8891. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8911. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8911. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8911. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8911. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8935. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8935. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8935. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8935. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8935. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8963. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8963. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8963. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8963. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8963. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8995. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8995. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8995. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8995. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9031. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9031. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9038. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9038. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9038. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9038. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9038. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9049. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9049. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9049. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9049. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9049. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9071. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9071. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9071. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9071. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9071. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9105. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9105. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9105. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9105. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9135. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9135. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9135. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9135. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9147. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9147. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9147. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9147. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9147. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9165. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9165. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9165. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9165. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9173. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9173. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9173. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9173. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9173. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9199. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9199. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9199. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9199. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9199. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9257. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9257. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9257. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9257. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9257. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9270. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9270. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9270. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9270. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9270. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9285. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9285. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9285. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9285. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9285. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9302. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9302. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9302. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9302. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9302. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9321. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9321. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9321. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9321. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9342. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9342. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9342. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9342. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9365. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9365. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9365. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9365. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9365. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9390. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9390. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9390. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9390. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9390. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9417. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9417. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9417. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9417. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9417. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9446. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9446. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9446. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9446. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9446. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9477. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9477. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9477. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9477. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9510. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9510. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9510. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9510. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9545. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9545. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9545. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9585. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9585. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9585. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9585. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9585. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9595. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9595. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9595. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9595. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9595. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9609. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9609. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9609. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9609. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9609. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9625. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9625. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9625. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9625. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9625. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9645. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9645. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9645. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9645. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9669. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9669. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9669. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9669. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9669. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9697. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9697. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9697. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9697. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9697. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9729. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9729. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9729. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9729. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9765. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9765. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9772. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9772. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9772. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9772. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9772. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9783. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9783. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9783. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9783. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9783. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9805. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9805. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9805. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9805. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9805. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9839. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9839. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9839. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9839. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9869. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9869. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9869. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9869. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9881. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9881. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9881. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9881. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9881. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9899. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9899. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9899. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9899. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9907. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9907. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9907. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9907. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9907. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9933. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9933. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9933. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9933. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9933. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9991. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9991. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9991. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9991. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9991. dead port 1/2 on $mux $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procmux$5529. dead port 1/2 on $mux $flatten\misc_I.\dfu_I.\btn_flt_I.$procmux$5416. dead port 2/2 on $mux $flatten\soc_I.\usb_I.$procmux$14948. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11661. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11663. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11665. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11672. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11674. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11680. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11688. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11690. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11697. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11706. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11708. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11716. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11726. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11728. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11737. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11747. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11760. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11763. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11766. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11768. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11770. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11783. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11786. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11788. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11790. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11803. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11805. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11807. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11819. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11821. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11832. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11844. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11857. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11452. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11459. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11467. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11478. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11480. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11482. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11492. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11494. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11503. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11514. Removed 2298 multiplexer ports. <suppressed ~531 debug messages> 73.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $flatten\soc_I.\e1_buf_I.$reduce_or$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:195$4956: { \soc_I.cpu_I.do_waitirq \soc_I.e1_buf_I.rx_pending } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12119: { } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12137: $auto$opt_reduce.cc:134:opt_mux$22703 New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12418: { $flatten\soc_I.\cpu_I.$procmux$12132_CMP $auto$opt_reduce.cc:134:opt_mux$22705 } Consolidated identical input bits for $mux cell $flatten\soc_I.\bram_I.$procmux$14870: Old ports: A=0, B=255, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3321_EN[31:0]$3328 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3321_EN[31:0]$3328 [0] New connections: $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3321_EN[31:0]$3328 [31:1] = { 24'000000000000000000000000 $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3321_EN[31:0]$3328 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3321_EN[31:0]$3328 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3321_EN[31:0]$3328 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3321_EN[31:0]$3328 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3321_EN[31:0]$3328 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3321_EN[31:0]$3328 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3321_EN[31:0]$3328 [0] } Consolidated identical input bits for $mux cell $flatten\soc_I.\bram_I.$procmux$14876: Old ports: A=0, B=65280, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3322_EN[31:0]$3331 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3322_EN[31:0]$3331 [8] New connections: { $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3322_EN[31:0]$3331 [31:9] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3322_EN[31:0]$3331 [7:0] } = { 16'0000000000000000 $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3322_EN[31:0]$3331 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3322_EN[31:0]$3331 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3322_EN[31:0]$3331 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3322_EN[31:0]$3331 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3322_EN[31:0]$3331 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3322_EN[31:0]$3331 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3322_EN[31:0]$3331 [8] 8'00000000 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12431: { $auto$opt_reduce.cc:134:opt_mux$22707 $flatten\soc_I.\cpu_I.$procmux$12110_CMP } Consolidated identical input bits for $mux cell $flatten\soc_I.\bram_I.$procmux$14882: Old ports: A=0, B=16711680, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3323_EN[31:0]$3334 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3323_EN[31:0]$3334 [16] New connections: { $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3323_EN[31:0]$3334 [31:17] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3323_EN[31:0]$3334 [15:0] } = { 8'00000000 $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3323_EN[31:0]$3334 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3323_EN[31:0]$3334 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3323_EN[31:0]$3334 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3323_EN[31:0]$3334 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3323_EN[31:0]$3334 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3323_EN[31:0]$3334 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3323_EN[31:0]$3334 [16] 16'0000000000000000 } Consolidated identical input bits for $mux cell $flatten\soc_I.\bram_I.$procmux$14888: Old ports: A=0, B=32'11111111000000000000000000000000, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3324_EN[31:0]$3337 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3324_EN[31:0]$3337 [24] New connections: { $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3324_EN[31:0]$3337 [31:25] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3324_EN[31:0]$3337 [23:0] } = { $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3324_EN[31:0]$3337 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3324_EN[31:0]$3337 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3324_EN[31:0]$3337 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3324_EN[31:0]$3337 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3324_EN[31:0]$3337 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3324_EN[31:0]$3337 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3324_EN[31:0]$3337 [24] 24'000000000000000000000000 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12444: { $flatten\soc_I.\cpu_I.$procmux$12141_CMP $auto$opt_reduce.cc:134:opt_mux$22709 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12670: { $flatten\soc_I.\cpu_I.$procmux$12141_CMP $flatten\soc_I.\cpu_I.$procmux$12140_CMP $flatten\soc_I.\cpu_I.$procmux$12110_CMP } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12729: { \soc_I.cpu_I.is_slli_srli_srai $auto$opt_reduce.cc:134:opt_mux$22711 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12771: { $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3887_Y $flatten\soc_I.\cpu_I.$procmux$12141_CMP } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12868: { $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3887_Y $flatten\soc_I.\cpu_I.$procmux$12141_CMP } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12911: { $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3887_Y $flatten\soc_I.\cpu_I.$procmux$12141_CMP $auto$opt_reduce.cc:134:opt_mux$22713 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13017: { \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu \soc_I.cpu_I.is_slli_srli_srai $auto$opt_reduce.cc:134:opt_mux$22715 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13189: { $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3887_Y $flatten\soc_I.\cpu_I.$procmux$12121_CMP $flatten\soc_I.\cpu_I.$procmux$12120_CMP $flatten\soc_I.\cpu_I.$procmux$12140_CMP } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13215: { \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu \soc_I.cpu_I.is_slli_srli_srai $auto$opt_reduce.cc:134:opt_mux$22717 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13377: { $auto$opt_reduce.cc:134:opt_mux$22721 $auto$opt_reduce.cc:134:opt_mux$22719 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13525: $auto$opt_reduce.cc:134:opt_mux$22723 New ctrl vector for $mux cell $flatten\soc_I.\cpu_I.$procmux$12100: { } Consolidated identical input bits for $mux cell $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$procmux$11926: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5116_EN[7:0]$5120 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5116_EN[7:0]$5120 [0] New connections: $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5116_EN[7:0]$5120 [7:1] = { $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5116_EN[7:0]$5120 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5116_EN[7:0]$5120 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5116_EN[7:0]$5120 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5116_EN[7:0]$5120 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5116_EN[7:0]$5120 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5116_EN[7:0]$5120 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5116_EN[7:0]$5120 [0] } Consolidated identical input bits for $mux cell $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$procmux$11926: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5116_EN[7:0]$5120 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5116_EN[7:0]$5120 [0] New connections: $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5116_EN[7:0]$5120 [7:1] = { $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5116_EN[7:0]$5120 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5116_EN[7:0]$5120 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5116_EN[7:0]$5120 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5116_EN[7:0]$5120 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5116_EN[7:0]$5120 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5116_EN[7:0]$5120 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5116_EN[7:0]$5120 [0] } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.$procmux$14944: { $flatten\soc_I.\iobuf_I.\dma_I.$eq$/build/gateware/common/rtl/wb_dma.v:183$4807_Y $flatten\soc_I.\iobuf_I.\dma_I.$eq$/build/gateware/common/rtl/wb_dma.v:164$4798_Y } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.\phy_I.$procmux$5425: { $auto$opt_reduce.cc:134:opt_mux$22731 $auto$opt_reduce.cc:134:opt_mux$22729 $flatten\soc_I.\usb_I.\phy_I.$procmux$5434_CMP $flatten\soc_I.\usb_I.\phy_I.$procmux$5433_CMP $auto$opt_reduce.cc:134:opt_mux$22727 $auto$opt_reduce.cc:134:opt_mux$22725 } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.\phy_I.$procmux$5442: { $auto$opt_reduce.cc:134:opt_mux$22739 $auto$opt_reduce.cc:134:opt_mux$22737 $flatten\soc_I.\usb_I.\phy_I.$procmux$5451_CMP $flatten\soc_I.\usb_I.\phy_I.$procmux$5450_CMP $auto$opt_reduce.cc:134:opt_mux$22735 $auto$opt_reduce.cc:134:opt_mux$22733 } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11871: { $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11879_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11878_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11877_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11876_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11875_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11874_CMP $auto$opt_reduce.cc:134:opt_mux$22741 } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11903: { $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11907_CMP $auto$opt_reduce.cc:134:opt_mux$22743 $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11904_CMP } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11914: { $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11921_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11920_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11919_CMP $auto$opt_reduce.cc:134:opt_mux$22745 $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11917_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11916_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11915_CMP } Optimizing cells in module \top. Performed a total of 29 changes. 73.10.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~39 debug messages> Removed a total of 13 cells. 73.10.6. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $flatten\soc_I.\cpu_I.$procdff$22459 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\cpu_I.$procdff$22420 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\cpu_I.$procdff$22420 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\cpu_I.$procdff$22419 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\cpu_I.$procdff$22419 ($dff) from module top. Setting constant 1-bit at position 0 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 1 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 2 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 3 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 4 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 5 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 6 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 7 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 8 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 9 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 10 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 11 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 12 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 13 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 14 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 15 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 16 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 17 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 18 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 19 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 20 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 21 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 22 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 23 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 24 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 25 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 26 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 27 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 28 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 29 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 30 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 31 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 32 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 33 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 34 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 35 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 36 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 37 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 38 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 39 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 40 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 41 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 42 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 43 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 44 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 45 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 46 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 47 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 48 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 49 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 50 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 51 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 52 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 53 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 54 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 55 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 56 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 57 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 58 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 59 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 60 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 61 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 62 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 1-bit at position 63 on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$22378 ($dff) from module top. Setting constant 1-bit at position 0 on $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procdff$22270 ($dff) from module top. Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21934 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21867 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21800 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21733 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21666 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21455 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21244 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21033 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20822 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20611 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20400 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20189 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19978 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19767 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19556 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19345 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19134 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18923 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18712 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18501 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18290 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18079 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17868 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17657 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17446 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17235 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17024 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16813 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16602 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16391 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16180 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$15969 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$15758 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$15547 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$15384 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$15269 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22001 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21934 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21867 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21800 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21733 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21666 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21455 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21244 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21033 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20822 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20611 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20400 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20189 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19978 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19767 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19556 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19345 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19134 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18923 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18712 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18501 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18290 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18079 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17868 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17657 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17446 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17235 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17024 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16813 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16602 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16391 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16180 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$15969 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$15758 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$15547 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$15384 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$15269 ($dlatch) from module top (changing to combinatorial circuit). Setting constant 0-bit at position 0 on $flatten\soc_I.\e1_buf_I.$procdff$22564 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\e1_buf_I.$procdff$22564 ($dff) from module top. Setting constant 0-bit at position 2 on $flatten\soc_I.\e1_buf_I.$procdff$22564 ($dff) from module top. Setting constant 0-bit at position 3 on $flatten\soc_I.\e1_buf_I.$procdff$22564 ($dff) from module top. Setting constant 0-bit at position 4 on $flatten\soc_I.\e1_buf_I.$procdff$22564 ($dff) from module top. Setting constant 0-bit at position 5 on $flatten\soc_I.\e1_buf_I.$procdff$22564 ($dff) from module top. Setting constant 0-bit at position 6 on $flatten\soc_I.\e1_buf_I.$procdff$22564 ($dff) from module top. Setting constant 0-bit at position 7 on $flatten\soc_I.\e1_buf_I.$procdff$22564 ($dff) from module top. Setting constant 0-bit at position 8 on $flatten\soc_I.\e1_buf_I.$procdff$22564 ($dff) from module top. Setting constant 0-bit at position 9 on $flatten\soc_I.\e1_buf_I.$procdff$22564 ($dff) from module top. Setting constant 0-bit at position 10 on $flatten\soc_I.\e1_buf_I.$procdff$22564 ($dff) from module top. Setting constant 0-bit at position 11 on $flatten\soc_I.\e1_buf_I.$procdff$22564 ($dff) from module top. Setting constant 0-bit at position 12 on $flatten\soc_I.\e1_buf_I.$procdff$22564 ($dff) from module top. Setting constant 0-bit at position 13 on $flatten\soc_I.\e1_buf_I.$procdff$22564 ($dff) from module top. Setting constant 0-bit at position 14 on $flatten\soc_I.\e1_buf_I.$procdff$22564 ($dff) from module top. Setting constant 0-bit at position 15 on $flatten\soc_I.\e1_buf_I.$procdff$22564 ($dff) from module top. 73.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 29 unused cells and 636 unused wires. <suppressed ~83 debug messages> 73.10.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~4 debug messages> 73.10.9. Rerunning OPT passes. (Maybe there is more to do..) 73.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~461 debug messages> 73.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $flatten\soc_I.\e1_buf_I.$reduce_or$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:195$4956: \soc_I.e1_buf_I.rx_pending New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12541: $auto$opt_reduce.cc:134:opt_mux$22747 New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12558: { $flatten\soc_I.\cpu_I.$procmux$12141_CMP $auto$opt_reduce.cc:134:opt_mux$22749 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12976: { $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3887_Y $flatten\soc_I.\cpu_I.$procmux$12121_CMP $flatten\soc_I.\cpu_I.$procmux$12120_CMP $flatten\soc_I.\cpu_I.$procmux$12141_CMP $flatten\soc_I.\cpu_I.$procmux$12140_CMP $auto$opt_reduce.cc:134:opt_mux$22751 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$14439: { $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:364$3484_Y $auto$opt_reduce.cc:134:opt_mux$22753 } Optimizing cells in module \top. Performed a total of 5 changes. 73.10.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 73.10.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$22371 ($dff) from module top. Setting constant 1-bit at position 0 on $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procdff$22270 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$22600 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$22600 ($dff) from module top. Setting constant 0-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$22600 ($dff) from module top. Setting constant 0-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$22600 ($dff) from module top. Setting constant 0-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$22600 ($dff) from module top. Setting constant 0-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$22600 ($dff) from module top. Setting constant 0-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$22600 ($dff) from module top. Setting constant 0-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$22600 ($dff) from module top. Setting constant 0-bit at position 8 on $flatten\soc_I.\bram_I.$procdff$22600 ($dff) from module top. Setting constant 0-bit at position 9 on $flatten\soc_I.\bram_I.$procdff$22600 ($dff) from module top. Setting constant 0-bit at position 10 on $flatten\soc_I.\bram_I.$procdff$22600 ($dff) from module top. Setting constant 0-bit at position 11 on $flatten\soc_I.\bram_I.$procdff$22600 ($dff) from module top. Setting constant 0-bit at position 12 on $flatten\soc_I.\bram_I.$procdff$22600 ($dff) from module top. Setting constant 0-bit at position 13 on $flatten\soc_I.\bram_I.$procdff$22600 ($dff) from module top. Setting constant 0-bit at position 14 on $flatten\soc_I.\bram_I.$procdff$22600 ($dff) from module top. Setting constant 0-bit at position 15 on $flatten\soc_I.\bram_I.$procdff$22600 ($dff) from module top. Setting constant 0-bit at position 16 on $flatten\soc_I.\bram_I.$procdff$22600 ($dff) from module top. Setting constant 0-bit at position 17 on $flatten\soc_I.\bram_I.$procdff$22600 ($dff) from module top. Setting constant 0-bit at position 18 on $flatten\soc_I.\bram_I.$procdff$22600 ($dff) from module top. Setting constant 0-bit at position 19 on $flatten\soc_I.\bram_I.$procdff$22600 ($dff) from module top. Setting constant 0-bit at position 20 on $flatten\soc_I.\bram_I.$procdff$22600 ($dff) from module top. Setting constant 0-bit at position 21 on $flatten\soc_I.\bram_I.$procdff$22600 ($dff) from module top. Setting constant 0-bit at position 22 on $flatten\soc_I.\bram_I.$procdff$22600 ($dff) from module top. Setting constant 0-bit at position 23 on $flatten\soc_I.\bram_I.$procdff$22600 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$22597 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$22597 ($dff) from module top. Setting constant 0-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$22597 ($dff) from module top. Setting constant 0-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$22597 ($dff) from module top. Setting constant 0-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$22597 ($dff) from module top. Setting constant 0-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$22597 ($dff) from module top. Setting constant 0-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$22597 ($dff) from module top. Setting constant 0-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$22597 ($dff) from module top. Setting constant 0-bit at position 8 on $flatten\soc_I.\bram_I.$procdff$22597 ($dff) from module top. Setting constant 0-bit at position 9 on $flatten\soc_I.\bram_I.$procdff$22597 ($dff) from module top. Setting constant 0-bit at position 10 on $flatten\soc_I.\bram_I.$procdff$22597 ($dff) from module top. Setting constant 0-bit at position 11 on $flatten\soc_I.\bram_I.$procdff$22597 ($dff) from module top. Setting constant 0-bit at position 12 on $flatten\soc_I.\bram_I.$procdff$22597 ($dff) from module top. Setting constant 0-bit at position 13 on $flatten\soc_I.\bram_I.$procdff$22597 ($dff) from module top. Setting constant 0-bit at position 14 on $flatten\soc_I.\bram_I.$procdff$22597 ($dff) from module top. Setting constant 0-bit at position 15 on $flatten\soc_I.\bram_I.$procdff$22597 ($dff) from module top. Setting constant 0-bit at position 24 on $flatten\soc_I.\bram_I.$procdff$22597 ($dff) from module top. Setting constant 0-bit at position 25 on $flatten\soc_I.\bram_I.$procdff$22597 ($dff) from module top. Setting constant 0-bit at position 26 on $flatten\soc_I.\bram_I.$procdff$22597 ($dff) from module top. Setting constant 0-bit at position 27 on $flatten\soc_I.\bram_I.$procdff$22597 ($dff) from module top. Setting constant 0-bit at position 28 on $flatten\soc_I.\bram_I.$procdff$22597 ($dff) from module top. Setting constant 0-bit at position 29 on $flatten\soc_I.\bram_I.$procdff$22597 ($dff) from module top. Setting constant 0-bit at position 30 on $flatten\soc_I.\bram_I.$procdff$22597 ($dff) from module top. Setting constant 0-bit at position 31 on $flatten\soc_I.\bram_I.$procdff$22597 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$22594 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$22594 ($dff) from module top. Setting constant 0-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$22594 ($dff) from module top. Setting constant 0-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$22594 ($dff) from module top. Setting constant 0-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$22594 ($dff) from module top. Setting constant 0-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$22594 ($dff) from module top. Setting constant 0-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$22594 ($dff) from module top. Setting constant 0-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$22594 ($dff) from module top. Setting constant 0-bit at position 16 on $flatten\soc_I.\bram_I.$procdff$22594 ($dff) from module top. Setting constant 0-bit at position 17 on $flatten\soc_I.\bram_I.$procdff$22594 ($dff) from module top. Setting constant 0-bit at position 18 on $flatten\soc_I.\bram_I.$procdff$22594 ($dff) from module top. Setting constant 0-bit at position 19 on $flatten\soc_I.\bram_I.$procdff$22594 ($dff) from module top. Setting constant 0-bit at position 20 on $flatten\soc_I.\bram_I.$procdff$22594 ($dff) from module top. Setting constant 0-bit at position 21 on $flatten\soc_I.\bram_I.$procdff$22594 ($dff) from module top. Setting constant 0-bit at position 22 on $flatten\soc_I.\bram_I.$procdff$22594 ($dff) from module top. Setting constant 0-bit at position 23 on $flatten\soc_I.\bram_I.$procdff$22594 ($dff) from module top. Setting constant 0-bit at position 24 on $flatten\soc_I.\bram_I.$procdff$22594 ($dff) from module top. Setting constant 0-bit at position 25 on $flatten\soc_I.\bram_I.$procdff$22594 ($dff) from module top. Setting constant 0-bit at position 26 on $flatten\soc_I.\bram_I.$procdff$22594 ($dff) from module top. Setting constant 0-bit at position 27 on $flatten\soc_I.\bram_I.$procdff$22594 ($dff) from module top. Setting constant 0-bit at position 28 on $flatten\soc_I.\bram_I.$procdff$22594 ($dff) from module top. Setting constant 0-bit at position 29 on $flatten\soc_I.\bram_I.$procdff$22594 ($dff) from module top. Setting constant 0-bit at position 30 on $flatten\soc_I.\bram_I.$procdff$22594 ($dff) from module top. Setting constant 0-bit at position 31 on $flatten\soc_I.\bram_I.$procdff$22594 ($dff) from module top. Setting constant 0-bit at position 8 on $flatten\soc_I.\bram_I.$procdff$22591 ($dff) from module top. Setting constant 0-bit at position 9 on $flatten\soc_I.\bram_I.$procdff$22591 ($dff) from module top. Setting constant 0-bit at position 10 on $flatten\soc_I.\bram_I.$procdff$22591 ($dff) from module top. Setting constant 0-bit at position 11 on $flatten\soc_I.\bram_I.$procdff$22591 ($dff) from module top. Setting constant 0-bit at position 12 on $flatten\soc_I.\bram_I.$procdff$22591 ($dff) from module top. Setting constant 0-bit at position 13 on $flatten\soc_I.\bram_I.$procdff$22591 ($dff) from module top. Setting constant 0-bit at position 14 on $flatten\soc_I.\bram_I.$procdff$22591 ($dff) from module top. Setting constant 0-bit at position 15 on $flatten\soc_I.\bram_I.$procdff$22591 ($dff) from module top. Setting constant 0-bit at position 16 on $flatten\soc_I.\bram_I.$procdff$22591 ($dff) from module top. Setting constant 0-bit at position 17 on $flatten\soc_I.\bram_I.$procdff$22591 ($dff) from module top. Setting constant 0-bit at position 18 on $flatten\soc_I.\bram_I.$procdff$22591 ($dff) from module top. Setting constant 0-bit at position 19 on $flatten\soc_I.\bram_I.$procdff$22591 ($dff) from module top. Setting constant 0-bit at position 20 on $flatten\soc_I.\bram_I.$procdff$22591 ($dff) from module top. Setting constant 0-bit at position 21 on $flatten\soc_I.\bram_I.$procdff$22591 ($dff) from module top. Setting constant 0-bit at position 22 on $flatten\soc_I.\bram_I.$procdff$22591 ($dff) from module top. Setting constant 0-bit at position 23 on $flatten\soc_I.\bram_I.$procdff$22591 ($dff) from module top. Setting constant 0-bit at position 24 on $flatten\soc_I.\bram_I.$procdff$22591 ($dff) from module top. Setting constant 0-bit at position 25 on $flatten\soc_I.\bram_I.$procdff$22591 ($dff) from module top. Setting constant 0-bit at position 26 on $flatten\soc_I.\bram_I.$procdff$22591 ($dff) from module top. Setting constant 0-bit at position 27 on $flatten\soc_I.\bram_I.$procdff$22591 ($dff) from module top. Setting constant 0-bit at position 28 on $flatten\soc_I.\bram_I.$procdff$22591 ($dff) from module top. Setting constant 0-bit at position 29 on $flatten\soc_I.\bram_I.$procdff$22591 ($dff) from module top. Setting constant 0-bit at position 30 on $flatten\soc_I.\bram_I.$procdff$22591 ($dff) from module top. Setting constant 0-bit at position 31 on $flatten\soc_I.\bram_I.$procdff$22591 ($dff) from module top. 73.10.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 6 unused wires. <suppressed ~1 debug messages> 73.10.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~6 debug messages> 73.10.16. Rerunning OPT passes. (Maybe there is more to do..) 73.10.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~461 debug messages> 73.10.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 73.10.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.10.20. Executing OPT_DFF pass (perform DFF optimizations). 73.10.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 7 unused wires. <suppressed ~3 debug messages> 73.10.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.10.23. Rerunning OPT passes. (Maybe there is more to do..) 73.10.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~461 debug messages> 73.10.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 73.10.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.10.27. Executing OPT_DFF pass (perform DFF optimizations). 73.10.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 73.10.29. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.10.30. Finished OPT passes. (There is nothing left to do.) 73.11. Executing FSM pass (extract and optimize FSM). 73.11.1. Executing FSM_DETECT pass (finding FSMs in design). Found FSM state register top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.fsm_state. Found FSM state register top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.fsm_state. Not marking top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5116_EN as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5116_EN as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register top.soc_I.cpu_I.cpu_state. Not marking top.soc_I.cpu_I.mem_state as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register top.soc_I.cpu_I.mem_wordsize. Not marking top.soc_I.e1_buf_I.t_chan as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.iobuf_I.dma_I.state as FSM state register: Users of register don't seem to benefit from recoding. Circuit seems to be self-resetting. Not marking top.soc_I.iobuf_I.epbam_arb_I.sel as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.iobuf_I.spram_arb_I.sel as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.phy_I.dn_state as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.phy_I.dp_state as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.rx_ll_I.dec_eop_state_1 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.rx_ll_I.dec_rep_state_1 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.rx_ll_I.dec_sync_state_1 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.rx_ll_I.samp_cnt as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register top.soc_I.usb_I.rx_pkt_I.state. Not marking top.soc_I.usb_I.trans_I.epfw_state as FSM state register: Users of register don't seem to benefit from recoding. Circuit seems to be self-resetting. Not marking top.soc_I.usb_I.tx_ll_I.out_sym as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.tx_ll_I.state as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register top.soc_I.usb_I.tx_pkt_I.state. 73.11.2. Executing FSM_EXTRACT pass (extracting FSM from design). Extracting FSM `$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.fsm_state' from module `\top'. found $dff cell for state register: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22694 root of input selection tree: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] found reset state: 3'000 (guessed from mux tree) found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$or$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:143$20_Y found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.crc_I.in_valid found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procmux$15171_CMP found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$45_Y found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$44_Y found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.align_frame found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:166$22_Y found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.mfa_timeout [6] found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:191$28_Y found state code: 3'100 found state code: 3'000 found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf found state code: 3'011 found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.fas_pos found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.data [6] found state code: 3'001 found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.data_match_fas found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.ctrl_mode_mf found state code: 3'010 found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procmux$15171_CMP found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:389$137_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$69_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$68_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$45_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$44_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.align_frame ctrl inputs: { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.data [6] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.data_match_fas $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.fas_pos $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.mfa_timeout [6] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$or$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:143$20_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:166$22_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:191$28_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.crc_I.in_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.ctrl_mode_mf } ctrl outputs: { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.align_frame $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$44_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$45_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$68_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$69_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:389$137_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procmux$15171_CMP } transition: 3'000 10'-----0--0- -> 3'000 10'1000001100 transition: 3'000 10'-0---0--1- -> 3'000 10'1000001100 transition: 3'000 10'-1---0--1- -> 3'001 10'1001001100 transition: 3'000 10'-----1---- -> 3'000 10'1000001100 transition: 3'100 10'-----0--0- -> 3'100 10'0100001010 transition: 3'100 10'-----0--1- -> 3'100 10'0100001010 transition: 3'100 10'-----1---- -> 3'000 10'0000001010 transition: 3'010 10'-----0--0- -> 3'010 10'0010010100 transition: 3'010 10'-----00-1- -> 3'010 10'0010010100 transition: 3'010 10'---0001-1- -> 3'010 10'0010010100 transition: 3'010 10'---0101-1- -> 3'011 10'0011010100 transition: 3'010 10'---1-01-1- -> 3'000 10'0000010100 transition: 3'010 10'-----1---- -> 3'000 10'0000010100 transition: 3'001 10'-----0--0- -> 3'001 10'0001101100 transition: 3'001 10'-----00-1- -> 3'001 10'0001101100 transition: 3'001 10'0-0--01-1- -> 3'000 10'0000101100 transition: 3'001 10'1-0--01-1- -> 3'001 10'0001101100 transition: 3'001 10'-01--01-1- -> 3'000 10'0000101100 transition: 3'001 10'-11--01-10 -> 3'100 10'0100101100 transition: 3'001 10'-11--01-11 -> 3'010 10'0010101100 transition: 3'001 10'-----1---- -> 3'000 10'0000101100 transition: 3'011 10'-----0--0- -> 3'011 10'0011001101 transition: 3'011 10'-----00-1- -> 3'011 10'0011001101 transition: 3'011 10'---0-0101- -> 3'011 10'0011001101 transition: 3'011 10'---0-0111- -> 3'100 10'0100001101 transition: 3'011 10'---1-01-1- -> 3'000 10'0000001101 transition: 3'011 10'-----1---- -> 3'000 10'0000001101 Extracting FSM `$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.fsm_state' from module `\top'. found $dff cell for state register: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22694 root of input selection tree: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] found reset state: 3'000 (guessed from mux tree) found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$or$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:143$20_Y found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.crc_I.in_valid found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procmux$15171_CMP found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$45_Y found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$44_Y found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.align_frame found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:166$22_Y found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.mfa_timeout [6] found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:191$28_Y found state code: 3'100 found state code: 3'000 found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf found state code: 3'011 found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.fas_pos found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.data [6] found state code: 3'001 found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.data_match_fas found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.ctrl_mode_mf found state code: 3'010 found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procmux$15171_CMP found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:389$137_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$69_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$68_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$45_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$44_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.align_frame ctrl inputs: { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.data [6] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.data_match_fas $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.fas_pos $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.mfa_timeout [6] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$or$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:143$20_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:166$22_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:191$28_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.crc_I.in_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.ctrl_mode_mf } ctrl outputs: { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.align_frame $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$44_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$45_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$68_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$69_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:389$137_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procmux$15171_CMP } transition: 3'000 10'-----0--0- -> 3'000 10'1000001100 transition: 3'000 10'-0---0--1- -> 3'000 10'1000001100 transition: 3'000 10'-1---0--1- -> 3'001 10'1001001100 transition: 3'000 10'-----1---- -> 3'000 10'1000001100 transition: 3'100 10'-----0--0- -> 3'100 10'0100001010 transition: 3'100 10'-----0--1- -> 3'100 10'0100001010 transition: 3'100 10'-----1---- -> 3'000 10'0000001010 transition: 3'010 10'-----0--0- -> 3'010 10'0010010100 transition: 3'010 10'-----00-1- -> 3'010 10'0010010100 transition: 3'010 10'---0001-1- -> 3'010 10'0010010100 transition: 3'010 10'---0101-1- -> 3'011 10'0011010100 transition: 3'010 10'---1-01-1- -> 3'000 10'0000010100 transition: 3'010 10'-----1---- -> 3'000 10'0000010100 transition: 3'001 10'-----0--0- -> 3'001 10'0001101100 transition: 3'001 10'-----00-1- -> 3'001 10'0001101100 transition: 3'001 10'0-0--01-1- -> 3'000 10'0000101100 transition: 3'001 10'1-0--01-1- -> 3'001 10'0001101100 transition: 3'001 10'-01--01-1- -> 3'000 10'0000101100 transition: 3'001 10'-11--01-10 -> 3'100 10'0100101100 transition: 3'001 10'-11--01-11 -> 3'010 10'0010101100 transition: 3'001 10'-----1---- -> 3'000 10'0000101100 transition: 3'011 10'-----0--0- -> 3'011 10'0011001101 transition: 3'011 10'-----00-1- -> 3'011 10'0011001101 transition: 3'011 10'---0-0101- -> 3'011 10'0011001101 transition: 3'011 10'---0-0111- -> 3'100 10'0100001101 transition: 3'011 10'---1-01-1- -> 3'000 10'0000001101 transition: 3'011 10'-----1---- -> 3'000 10'0000001101 Extracting FSM `\soc_I.cpu_I.cpu_state' from module `\top'. found $dff cell for state register: $flatten\soc_I.\cpu_I.$procdff$22442 root of input selection tree: $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] found reset state: 8'10000000 (guessed from mux tree) found ctrl input: $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1917$4075_Y found ctrl input: \soc_I.pb_rst_n found state code: 8'01000000 found ctrl input: $auto$opt_reduce.cc:134:opt_mux$22747 found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12140_CMP found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12141_CMP found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12120_CMP found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12121_CMP found ctrl input: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3887_Y found ctrl input: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4034_Y found ctrl input: $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1851$4038_Y found ctrl input: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1810$4016_Y found ctrl input: \soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu found ctrl input: \soc_I.cpu_I.mem_done found ctrl input: \soc_I.cpu_I.is_sll_srl_sra found ctrl input: \soc_I.cpu_I.is_sb_sh_sw found state code: 8'00001000 found state code: 8'00000100 found state code: 8'00000010 found ctrl input: $auto$opt_reduce.cc:134:opt_mux$22715 found ctrl input: \soc_I.cpu_I.is_slli_srli_srai found ctrl input: \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu found state code: 8'00000001 found ctrl input: \soc_I.cpu_I.decoder_trigger found ctrl input: \soc_I.cpu_I.instr_jal found state code: 8'00100000 found state code: 8'10000000 found ctrl output: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3887_Y found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12110_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12120_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12121_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12132_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12140_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12141_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12145_CMP ctrl inputs: { $auto$opt_reduce.cc:134:opt_mux$22747 $auto$opt_reduce.cc:134:opt_mux$22715 \soc_I.pb_rst_n $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1917$4075_Y $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1851$4038_Y $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4034_Y $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1810$4016_Y \soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu \soc_I.cpu_I.is_sll_srl_sra \soc_I.cpu_I.is_sb_sh_sw \soc_I.cpu_I.is_slli_srli_srai \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu \soc_I.cpu_I.decoder_trigger \soc_I.cpu_I.instr_jal \soc_I.cpu_I.mem_done } ctrl outputs: { $flatten\soc_I.\cpu_I.$procmux$12145_CMP $flatten\soc_I.\cpu_I.$procmux$12141_CMP $flatten\soc_I.\cpu_I.$procmux$12140_CMP $flatten\soc_I.\cpu_I.$procmux$12132_CMP $flatten\soc_I.\cpu_I.$procmux$12121_CMP $flatten\soc_I.\cpu_I.$procmux$12120_CMP $flatten\soc_I.\cpu_I.$procmux$12110_CMP $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3887_Y } transition: 8'10000000 15'--00----------- -> 8'01000000 16'1000000010000000 transition: 8'10000000 15'--10----------- -> 8'10000000 16'1000000100000000 transition: 8'10000000 15'---1----------- -> 8'10000000 16'1000000100000000 transition: 8'01000000 15'--00----------- -> 8'01000000 16'0000000010000001 transition: 8'01000000 15'--10--------0-- -> 8'01000000 16'0000000010000001 transition: 8'01000000 15'--10--------10- -> 8'00100000 16'0000000001000001 transition: 8'01000000 15'--10--------11- -> 8'01000000 16'0000000010000001 transition: 8'01000000 15'---1----------- -> 8'10000000 16'0000000100000001 transition: 8'00100000 15'--00----------- -> 8'01000000 16'0000100010000000 transition: 8'00100000 15'-010----0000--- -> 8'00001000 16'0000100000010000 transition: 8'00100000 15'-010-----100--- -> 8'00000010 16'0000100000000100 transition: 8'00100000 15'-010----1-00--- -> 8'00000100 16'0000100000001000 transition: 8'00100000 15'--10-------1--- -> 8'00000001 16'0000100000000010 transition: 8'00100000 15'--10------1---- -> 8'00000100 16'0000100000001000 transition: 8'00100000 15'-110----------- -> 8'00001000 16'0000100000010000 transition: 8'00100000 15'---1----------- -> 8'10000000 16'0000100100000000 transition: 8'00001000 15'--00----------- -> 8'01000000 16'0100000010000000 transition: 8'00001000 15'--10---0------- -> 8'01000000 16'0100000010000000 transition: 8'00001000 15'--10---1------0 -> 8'00001000 16'0100000000010000 transition: 8'00001000 15'--10---1------1 -> 8'01000000 16'0100000010000000 transition: 8'00001000 15'---1----------- -> 8'10000000 16'0100000100000000 transition: 8'00000100 15'--00----------- -> 8'01000000 16'0010000010000000 transition: 8'00000100 15'--10--0-------- -> 8'00000100 16'0010000000001000 transition: 8'00000100 15'--10--1-------- -> 8'01000000 16'0010000010000000 transition: 8'00000100 15'---1----------- -> 8'10000000 16'0010000100000000 transition: 8'00000010 15'--00----------- -> 8'01000000 16'0001000010000000 transition: 8'00000010 15'--10-0--------- -> 8'00000010 16'0001000000000100 transition: 8'00000010 15'--1001--------- -> 8'00000010 16'0001000000000100 transition: 8'00000010 15'--1011--------- -> 8'01000000 16'0001000010000000 transition: 8'00000010 15'---1----------- -> 8'10000000 16'0001000100000000 transition: 8'00000001 15'--00----------- -> 8'01000000 16'0000001010000000 transition: 8'00000001 15'--10-0--------- -> 8'00000001 16'0000001000000010 transition: 8'00000001 15'--1001--------- -> 8'00000001 16'0000001000000010 transition: 8'00000001 15'--1011--------- -> 8'01000000 16'0000001010000000 transition: 8'00000001 15'---1----------- -> 8'10000000 16'0000001100000000 Extracting FSM `\soc_I.cpu_I.mem_wordsize' from module `\top'. found $dff cell for state register: $flatten\soc_I.\cpu_I.$procdff$22429 root of input selection tree: $flatten\soc_I.\cpu_I.$0\mem_wordsize[1:0] found ctrl input: \soc_I.pb_rst_n found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12110_CMP found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12132_CMP found ctrl input: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3887_Y found ctrl input: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4034_Y found ctrl input: \soc_I.cpu_I.mem_do_rdata found ctrl input: \soc_I.cpu_I.instr_lw found ctrl input: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1866$4043_Y found ctrl input: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1865$4042_Y found state code: 2'00 found state code: 2'01 found state code: 2'10 found ctrl input: \soc_I.cpu_I.mem_do_wdata found ctrl input: \soc_I.cpu_I.instr_sw found ctrl input: \soc_I.cpu_I.instr_sh found ctrl input: \soc_I.cpu_I.instr_sb found ctrl output: $flatten\soc_I.\cpu_I.$procmux$14686_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$14693_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$14698_CMP ctrl inputs: { \soc_I.pb_rst_n $flatten\soc_I.\cpu_I.$procmux$12132_CMP $flatten\soc_I.\cpu_I.$procmux$12110_CMP $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1866$4043_Y $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1865$4042_Y $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4034_Y $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3887_Y \soc_I.cpu_I.instr_sw \soc_I.cpu_I.instr_sh \soc_I.cpu_I.instr_sb \soc_I.cpu_I.instr_lw \soc_I.cpu_I.mem_do_wdata \soc_I.cpu_I.mem_do_rdata } ctrl outputs: { $flatten\soc_I.\cpu_I.$procmux$14698_CMP $flatten\soc_I.\cpu_I.$procmux$14693_CMP $flatten\soc_I.\cpu_I.$procmux$14686_CMP $flatten\soc_I.\cpu_I.$0\mem_wordsize[1:0] } transition: 2'00 13'0------------ -> 2'00 5'10000 transition: 2'00 13'100---0------ -> 2'00 5'10000 transition: 2'00 13'1-----1------ -> 2'00 5'10000 transition: 2'00 13'11---0------- -> 2'00 5'10000 transition: 2'00 13'11---1-000-0- -> INVALID_STATE(2'xx) 5'100xx <ignored invalid transition!> transition: 2'00 13'11---1---1-0- -> 2'10 5'10010 transition: 2'00 13'11---1--1--0- -> 2'01 5'10001 transition: 2'00 13'11---1-1---0- -> 2'00 5'10000 transition: 2'00 13'11---1-----1- -> 2'00 5'10000 transition: 2'00 13'1-1--0------- -> 2'00 5'10000 transition: 2'00 13'1-1001----0-0 -> INVALID_STATE(2'xx) 5'100xx <ignored invalid transition!> transition: 2'00 13'1-1-11------0 -> 2'10 5'10010 transition: 2'00 13'1-11-1------0 -> 2'01 5'10001 transition: 2'00 13'1-1--1----1-0 -> 2'00 5'10000 transition: 2'00 13'1-1--1------1 -> 2'00 5'10000 transition: 2'10 13'0------------ -> 2'10 5'00110 transition: 2'10 13'100---0------ -> 2'10 5'00110 transition: 2'10 13'1-----1------ -> 2'00 5'00100 transition: 2'10 13'11---0------- -> 2'10 5'00110 transition: 2'10 13'11---1-000-0- -> INVALID_STATE(2'xx) 5'001xx <ignored invalid transition!> transition: 2'10 13'11---1---1-0- -> 2'10 5'00110 transition: 2'10 13'11---1--1--0- -> 2'01 5'00101 transition: 2'10 13'11---1-1---0- -> 2'00 5'00100 transition: 2'10 13'11---1-----1- -> 2'10 5'00110 transition: 2'10 13'1-1--0------- -> 2'10 5'00110 transition: 2'10 13'1-1001----0-0 -> INVALID_STATE(2'xx) 5'001xx <ignored invalid transition!> transition: 2'10 13'1-1-11------0 -> 2'10 5'00110 transition: 2'10 13'1-11-1------0 -> 2'01 5'00101 transition: 2'10 13'1-1--1----1-0 -> 2'00 5'00100 transition: 2'10 13'1-1--1------1 -> 2'10 5'00110 transition: 2'01 13'0------------ -> 2'01 5'01001 transition: 2'01 13'100---0------ -> 2'01 5'01001 transition: 2'01 13'1-----1------ -> 2'00 5'01000 transition: 2'01 13'11---0------- -> 2'01 5'01001 transition: 2'01 13'11---1-000-0- -> INVALID_STATE(2'xx) 5'010xx <ignored invalid transition!> transition: 2'01 13'11---1---1-0- -> 2'10 5'01010 transition: 2'01 13'11---1--1--0- -> 2'01 5'01001 transition: 2'01 13'11---1-1---0- -> 2'00 5'01000 transition: 2'01 13'11---1-----1- -> 2'01 5'01001 transition: 2'01 13'1-1--0------- -> 2'01 5'01001 transition: 2'01 13'1-1001----0-0 -> INVALID_STATE(2'xx) 5'010xx <ignored invalid transition!> transition: 2'01 13'1-1-11------0 -> 2'10 5'01010 transition: 2'01 13'1-11-1------0 -> 2'01 5'01001 transition: 2'01 13'1-1--1----1-0 -> 2'00 5'01000 transition: 2'01 13'1-1--1------1 -> 2'01 5'01001 Extracting FSM `\soc_I.usb_I.rx_pkt_I.state' from module `\top'. found $adff cell for state register: $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22353 root of input selection tree: \soc_I.usb_I.rx_pkt_I.state_nxt found reset state: 4'0000 (from async reset) found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:375$1404_Y found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11691_CMP found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:341$1390_Y found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:337$1387_Y found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_error[0:0] found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11771_CMP found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:245$1341_Y found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_idle[0:0] found ctrl input: \soc_I.usb_I.rx_ll_I.dec_valid_1 found ctrl input: \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [2] found ctrl input: \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [3] found state code: 4'0011 found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:180$1322_Y found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:158$1316_Y found ctrl input: \soc_I.usb_I.rx_pkt_I.llu_byte_stb found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:173$1320_Y found state code: 4'0110 found state code: 4'0101 found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:153$1315_Y found ctrl input: \soc_I.usb_I.rx_pkt_I.pid_valid found ctrl input: \soc_I.usb_I.rx_pkt_I.pid_is_sof found ctrl input: \soc_I.usb_I.rx_pkt_I.pid_is_token found ctrl input: \soc_I.usb_I.rx_pkt_I.pid_is_data found ctrl input: \soc_I.usb_I.rx_pkt_I.pid_is_handshake found state code: 4'0111 found state code: 4'0100 found state code: 4'0010 found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:126$1311_Y found state code: 4'0001 found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11771_CMP found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11691_CMP found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:375$1404_Y found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:341$1390_Y found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:337$1387_Y found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:245$1341_Y found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_error[0:0] found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_idle[0:0] ctrl inputs: { \soc_I.usb_I.rx_pkt_I.llu_byte_stb \soc_I.usb_I.rx_pkt_I.pid_valid \soc_I.usb_I.rx_pkt_I.pid_is_sof \soc_I.usb_I.rx_pkt_I.pid_is_token \soc_I.usb_I.rx_pkt_I.pid_is_data \soc_I.usb_I.rx_pkt_I.pid_is_handshake $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:126$1311_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:153$1315_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:158$1316_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:173$1320_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:180$1322_Y \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [2] \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [3] \soc_I.usb_I.rx_ll_I.dec_valid_1 } ctrl outputs: { \soc_I.usb_I.rx_pkt_I.state_nxt $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_idle[0:0] $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_error[0:0] $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:245$1341_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:337$1387_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:341$1390_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:375$1404_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11691_CMP $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11771_CMP } transition: 4'0000 14'------0------- -> 4'0000 12'000010000000 transition: 4'0000 14'------1------- -> 4'0001 12'000110000000 transition: 4'0100 14'0-------0----- -> 4'0100 12'010000010000 transition: 4'0100 14'1-------0----- -> 4'0101 12'010100010000 transition: 4'0100 14'--------1----- -> 4'0011 12'001100010000 transition: 4'0010 14'-0------------ -> 4'0011 12'001100000001 transition: 4'0010 14'-10000-------- -> 4'0011 12'001100000001 transition: 4'0010 14'-10001-------- -> 4'0110 12'011000000001 transition: 4'0010 14'-1001--------- -> 4'0111 12'011100000001 transition: 4'0010 14'-101---------- -> 4'0100 12'010000000001 transition: 4'0010 14'-11----------- -> 4'0100 12'010000000001 transition: 4'0110 14'0-------0----- -> 4'0110 12'011000000010 transition: 4'0110 14'1-------0----- -> 4'0011 12'001100000010 transition: 4'0110 14'--------10---- -> 4'0011 12'001100000010 transition: 4'0110 14'--------11---- -> 4'0000 12'000000000010 transition: 4'0001 14'0------------- -> 4'0001 12'000100100000 transition: 4'0001 14'1------------- -> 4'0010 12'001000100000 transition: 4'0101 14'0-------0----- -> 4'0101 12'010100001000 transition: 4'0101 14'1-------0----- -> 4'0110 12'011000001000 transition: 4'0101 14'--------1----- -> 4'0011 12'001100001000 transition: 4'0011 14'-------0------ -> 4'0011 12'001101000000 transition: 4'0011 14'-------1------ -> 4'0000 12'000001000000 transition: 4'0111 14'-------------0 -> 4'0111 12'011100000100 transition: 4'0111 14'-----------001 -> 4'0111 12'011100000100 transition: 4'0111 14'-----------011 -> 4'0011 12'001100000100 transition: 4'0111 14'----------01-1 -> 4'0011 12'001100000100 transition: 4'0111 14'----------11-1 -> 4'0000 12'000000000100 Extracting FSM `\soc_I.usb_I.tx_pkt_I.state' from module `\top'. found $adff cell for state register: $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$22296 root of input selection tree: \soc_I.usb_I.tx_pkt_I.state_nxt found reset state: 4'0000 (from async reset) found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1555_Y found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11442_CMP found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:177$1554_Y found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1556_Y found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$0\ll_start[0:0] found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:203$1572_Y found ctrl input: \soc_I.usb_I.tx_pkt_I.next found state code: 4'0101 found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:112$1529_Y found state code: 4'0100 found ctrl input: \soc_I.usb_I.tx_pkt_I.pid_is_handshake found ctrl input: \soc_I.usb_I.tx_pkt_I.len [10] found state code: 4'0011 found state code: 4'0010 found ctrl input: \soc_I.usb_I.trans_I.txpkt_start_i found state code: 4'0001 found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11442_CMP found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:203$1572_Y found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1556_Y found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1555_Y found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:177$1554_Y found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$0\ll_start[0:0] ctrl inputs: { \soc_I.usb_I.trans_I.txpkt_start_i \soc_I.usb_I.tx_pkt_I.pid_is_handshake \soc_I.usb_I.tx_pkt_I.next \soc_I.usb_I.tx_pkt_I.len [10] $flatten\soc_I.\usb_I.\tx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:112$1529_Y } ctrl outputs: { \soc_I.usb_I.tx_pkt_I.state_nxt $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:177$1554_Y $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1555_Y $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1556_Y $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:203$1572_Y $flatten\soc_I.\usb_I.\tx_pkt_I.$0\ll_start[0:0] $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11442_CMP } transition: 4'0000 5'0---- -> 4'0000 10'0000000100 transition: 4'0000 5'1---- -> 4'0001 10'0001000100 transition: 4'0100 5'--0-- -> 4'0100 10'0100000001 transition: 4'0100 5'--1-- -> 4'0101 10'0101000001 transition: 4'0010 5'--0-- -> 4'0010 10'0010001000 transition: 4'0010 5'-010- -> 4'0011 10'0011001000 transition: 4'0010 5'-011- -> 4'0100 10'0100001000 transition: 4'0010 5'-11-- -> 4'0000 10'0000001000 transition: 4'0001 5'----- -> 4'0010 10'0010000010 transition: 4'0101 5'--0-- -> 4'0101 10'0101010000 transition: 4'0101 5'--1-- -> 4'0000 10'0000010000 transition: 4'0011 5'----0 -> 4'0011 10'0011100000 transition: 4'0011 5'----1 -> 4'0100 10'0100100000 73.11.3. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\soc_I.usb_I.tx_pkt_I.state$22797' from module `\top'. Optimizing FSM `$fsm$\soc_I.usb_I.rx_pkt_I.state$22787' from module `\top'. Optimizing FSM `$fsm$\soc_I.cpu_I.mem_wordsize$22782' from module `\top'. Optimizing FSM `$fsm$\soc_I.cpu_I.cpu_state$22772' from module `\top'. Removing unused input signal $auto$opt_reduce.cc:134:opt_mux$22747. Optimizing FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.fsm_state$22763' from module `\top'. Merging pattern 10'-----0--0- and 10'-----0--1- from group (1 1 10'0100001010). Merging pattern 10'-----0--1- and 10'-----0--0- from group (1 1 10'0100001010). Optimizing FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.fsm_state$22754' from module `\top'. Merging pattern 10'-----0--0- and 10'-----0--1- from group (1 1 10'0100001010). Merging pattern 10'-----0--1- and 10'-----0--0- from group (1 1 10'0100001010). 73.11.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 123 unused cells and 123 unused wires. <suppressed ~124 debug messages> 73.11.5. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.fsm_state$22754' from module `\top'. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procmux$15171_CMP. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] [0]. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] [1]. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] [2]. Optimizing FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.fsm_state$22763' from module `\top'. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procmux$15171_CMP. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] [0]. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] [1]. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] [2]. Optimizing FSM `$fsm$\soc_I.cpu_I.cpu_state$22772' from module `\top'. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [0]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [1]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [2]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [3]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [4]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [5]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [6]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [7]. Optimizing FSM `$fsm$\soc_I.cpu_I.mem_wordsize$22782' from module `\top'. Removing unused output signal $flatten\soc_I.\cpu_I.$0\mem_wordsize[1:0] [0]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\mem_wordsize[1:0] [1]. Optimizing FSM `$fsm$\soc_I.usb_I.rx_pkt_I.state$22787' from module `\top'. Removing unused output signal $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11771_CMP. Removing unused output signal $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11691_CMP. Removing unused output signal \soc_I.usb_I.rx_pkt_I.state_nxt [0]. Removing unused output signal \soc_I.usb_I.rx_pkt_I.state_nxt [1]. Removing unused output signal \soc_I.usb_I.rx_pkt_I.state_nxt [2]. Removing unused output signal \soc_I.usb_I.rx_pkt_I.state_nxt [3]. Optimizing FSM `$fsm$\soc_I.usb_I.tx_pkt_I.state$22797' from module `\top'. Removing unused output signal \soc_I.usb_I.tx_pkt_I.state_nxt [0]. Removing unused output signal \soc_I.usb_I.tx_pkt_I.state_nxt [1]. Removing unused output signal \soc_I.usb_I.tx_pkt_I.state_nxt [2]. Removing unused output signal \soc_I.usb_I.tx_pkt_I.state_nxt [3]. 73.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). Recoding FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.fsm_state$22754' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 000 -> ----1 100 -> ---1- 010 -> --1-- 001 -> -1--- 011 -> 1---- Recoding FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.fsm_state$22763' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 000 -> ----1 100 -> ---1- 010 -> --1-- 001 -> -1--- 011 -> 1---- Recoding FSM `$fsm$\soc_I.cpu_I.cpu_state$22772' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 10000000 -> ------1 01000000 -> -----1- 00100000 -> ----1-- 00001000 -> ---1--- 00000100 -> --1---- 00000010 -> -1----- 00000001 -> 1------ Recoding FSM `$fsm$\soc_I.cpu_I.mem_wordsize$22782' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 00 -> --1 10 -> -1- 01 -> 1-- Recoding FSM `$fsm$\soc_I.usb_I.rx_pkt_I.state$22787' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 0000 -> -------1 0100 -> ------1- 0010 -> -----1-- 0110 -> ----1--- 0001 -> ---1---- 0101 -> --1----- 0011 -> -1------ 0111 -> 1------- Recoding FSM `$fsm$\soc_I.usb_I.tx_pkt_I.state$22797' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 0000 -> -----1 0100 -> ----1- 0010 -> ---1-- 0001 -> --1--- 0101 -> -1---- 0011 -> 1----- 73.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells). FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.fsm_state$22754' from module `top': ------------------------------------- Information on FSM $fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.fsm_state$22754 ($flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.fsm_state): Number of input signals: 10 Number of output signals: 6 Number of state bits: 5 Input signals: 0: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.ctrl_mode_mf 1: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.crc_I.in_valid 2: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:191$28_Y 3: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:166$22_Y 4: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$or$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:143$20_Y 5: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf 6: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.mfa_timeout [6] 7: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.fas_pos 8: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.data_match_fas 9: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.data [6] Output signals: 0: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:389$137_Y 1: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$69_Y 2: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$68_Y 3: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$45_Y 4: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$44_Y 5: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.align_frame State encoding: 0: 5'----1 <RESET STATE> 1: 5'---1- 2: 5'--1-- 3: 5'-1--- 4: 5'1---- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 10'-----0--0- -> 0 6'100110 1: 0 10'-0---0--1- -> 0 6'100110 2: 0 10'-----1---- -> 0 6'100110 3: 0 10'-1---0--1- -> 3 6'100110 4: 1 10'-----1---- -> 0 6'000101 5: 1 10'-----0---- -> 1 6'000101 6: 2 10'---1-01-1- -> 0 6'001010 7: 2 10'-----1---- -> 0 6'001010 8: 2 10'-----0--0- -> 2 6'001010 9: 2 10'-----00-1- -> 2 6'001010 10: 2 10'---0001-1- -> 2 6'001010 11: 2 10'---0101-1- -> 4 6'001010 12: 3 10'0-0--01-1- -> 0 6'010110 13: 3 10'-01--01-1- -> 0 6'010110 14: 3 10'-----1---- -> 0 6'010110 15: 3 10'-11--01-10 -> 1 6'010110 16: 3 10'-11--01-11 -> 2 6'010110 17: 3 10'-----0--0- -> 3 6'010110 18: 3 10'-----00-1- -> 3 6'010110 19: 3 10'1-0--01-1- -> 3 6'010110 20: 4 10'---1-01-1- -> 0 6'000110 21: 4 10'-----1---- -> 0 6'000110 22: 4 10'---0-0111- -> 1 6'000110 23: 4 10'-----0--0- -> 4 6'000110 24: 4 10'---0-0101- -> 4 6'000110 25: 4 10'-----00-1- -> 4 6'000110 ------------------------------------- FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.fsm_state$22763' from module `top': ------------------------------------- Information on FSM $fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.fsm_state$22763 ($flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.fsm_state): Number of input signals: 10 Number of output signals: 6 Number of state bits: 5 Input signals: 0: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.ctrl_mode_mf 1: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.crc_I.in_valid 2: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:191$28_Y 3: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:166$22_Y 4: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$or$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:143$20_Y 5: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf 6: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.mfa_timeout [6] 7: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.fas_pos 8: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.data_match_fas 9: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.data [6] Output signals: 0: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:389$137_Y 1: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$69_Y 2: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$68_Y 3: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$45_Y 4: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$44_Y 5: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.align_frame State encoding: 0: 5'----1 <RESET STATE> 1: 5'---1- 2: 5'--1-- 3: 5'-1--- 4: 5'1---- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 10'-----0--0- -> 0 6'100110 1: 0 10'-0---0--1- -> 0 6'100110 2: 0 10'-----1---- -> 0 6'100110 3: 0 10'-1---0--1- -> 3 6'100110 4: 1 10'-----1---- -> 0 6'000101 5: 1 10'-----0---- -> 1 6'000101 6: 2 10'---1-01-1- -> 0 6'001010 7: 2 10'-----1---- -> 0 6'001010 8: 2 10'-----0--0- -> 2 6'001010 9: 2 10'-----00-1- -> 2 6'001010 10: 2 10'---0001-1- -> 2 6'001010 11: 2 10'---0101-1- -> 4 6'001010 12: 3 10'0-0--01-1- -> 0 6'010110 13: 3 10'-01--01-1- -> 0 6'010110 14: 3 10'-----1---- -> 0 6'010110 15: 3 10'-11--01-10 -> 1 6'010110 16: 3 10'-11--01-11 -> 2 6'010110 17: 3 10'-----0--0- -> 3 6'010110 18: 3 10'-----00-1- -> 3 6'010110 19: 3 10'1-0--01-1- -> 3 6'010110 20: 4 10'---1-01-1- -> 0 6'000110 21: 4 10'-----1---- -> 0 6'000110 22: 4 10'---0-0111- -> 1 6'000110 23: 4 10'-----0--0- -> 4 6'000110 24: 4 10'---0-0101- -> 4 6'000110 25: 4 10'-----00-1- -> 4 6'000110 ------------------------------------- FSM `$fsm$\soc_I.cpu_I.cpu_state$22772' from module `top': ------------------------------------- Information on FSM $fsm$\soc_I.cpu_I.cpu_state$22772 (\soc_I.cpu_I.cpu_state): Number of input signals: 14 Number of output signals: 8 Number of state bits: 7 Input signals: 0: \soc_I.cpu_I.mem_done 1: \soc_I.cpu_I.instr_jal 2: \soc_I.cpu_I.decoder_trigger 3: \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu 4: \soc_I.cpu_I.is_slli_srli_srai 5: \soc_I.cpu_I.is_sb_sh_sw 6: \soc_I.cpu_I.is_sll_srl_sra 7: \soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu 8: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1810$4016_Y 9: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4034_Y 10: $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1851$4038_Y 11: $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1917$4075_Y 12: \soc_I.pb_rst_n 13: $auto$opt_reduce.cc:134:opt_mux$22715 Output signals: 0: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3887_Y 1: $flatten\soc_I.\cpu_I.$procmux$12110_CMP 2: $flatten\soc_I.\cpu_I.$procmux$12120_CMP 3: $flatten\soc_I.\cpu_I.$procmux$12121_CMP 4: $flatten\soc_I.\cpu_I.$procmux$12132_CMP 5: $flatten\soc_I.\cpu_I.$procmux$12140_CMP 6: $flatten\soc_I.\cpu_I.$procmux$12141_CMP 7: $flatten\soc_I.\cpu_I.$procmux$12145_CMP State encoding: 0: 7'------1 <RESET STATE> 1: 7'-----1- 2: 7'----1-- 3: 7'---1--- 4: 7'--1---- 5: 7'-1----- 6: 7'1------ Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 14'-10----------- -> 0 8'10000000 1: 0 14'--1----------- -> 0 8'10000000 2: 0 14'-00----------- -> 1 8'10000000 3: 1 14'--1----------- -> 0 8'00000001 4: 1 14'-10--------11- -> 1 8'00000001 5: 1 14'-10--------0-- -> 1 8'00000001 6: 1 14'-00----------- -> 1 8'00000001 7: 1 14'-10--------10- -> 2 8'00000001 8: 2 14'--1----------- -> 0 8'00001000 9: 2 14'-00----------- -> 1 8'00001000 10: 2 14'010----0000--- -> 3 8'00001000 11: 2 14'110----------- -> 3 8'00001000 12: 2 14'010----1-00--- -> 4 8'00001000 13: 2 14'-10------1---- -> 4 8'00001000 14: 2 14'010-----100--- -> 5 8'00001000 15: 2 14'-10-------1--- -> 6 8'00001000 16: 3 14'--1----------- -> 0 8'01000000 17: 3 14'-10---1------1 -> 1 8'01000000 18: 3 14'-10---0------- -> 1 8'01000000 19: 3 14'-00----------- -> 1 8'01000000 20: 3 14'-10---1------0 -> 3 8'01000000 21: 4 14'--1----------- -> 0 8'00100000 22: 4 14'-10--1-------- -> 1 8'00100000 23: 4 14'-00----------- -> 1 8'00100000 24: 4 14'-10--0-------- -> 4 8'00100000 25: 5 14'--1----------- -> 0 8'00010000 26: 5 14'-1011--------- -> 1 8'00010000 27: 5 14'-00----------- -> 1 8'00010000 28: 5 14'-10-0--------- -> 5 8'00010000 29: 5 14'-1001--------- -> 5 8'00010000 30: 6 14'--1----------- -> 0 8'00000010 31: 6 14'-1011--------- -> 1 8'00000010 32: 6 14'-00----------- -> 1 8'00000010 33: 6 14'-10-0--------- -> 6 8'00000010 34: 6 14'-1001--------- -> 6 8'00000010 ------------------------------------- FSM `$fsm$\soc_I.cpu_I.mem_wordsize$22782' from module `top': ------------------------------------- Information on FSM $fsm$\soc_I.cpu_I.mem_wordsize$22782 (\soc_I.cpu_I.mem_wordsize): Number of input signals: 13 Number of output signals: 3 Number of state bits: 3 Input signals: 0: \soc_I.cpu_I.mem_do_rdata 1: \soc_I.cpu_I.mem_do_wdata 2: \soc_I.cpu_I.instr_lw 3: \soc_I.cpu_I.instr_sb 4: \soc_I.cpu_I.instr_sh 5: \soc_I.cpu_I.instr_sw 6: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3887_Y 7: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4034_Y 8: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1865$4042_Y 9: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1866$4043_Y 10: $flatten\soc_I.\cpu_I.$procmux$12110_CMP 11: $flatten\soc_I.\cpu_I.$procmux$12132_CMP 12: \soc_I.pb_rst_n Output signals: 0: $flatten\soc_I.\cpu_I.$procmux$14686_CMP 1: $flatten\soc_I.\cpu_I.$procmux$14693_CMP 2: $flatten\soc_I.\cpu_I.$procmux$14698_CMP State encoding: 0: 3'--1 1: 3'-1- 2: 3'1-- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 13'1-1--1----1-0 -> 0 3'100 1: 0 13'1-1--1------1 -> 0 3'100 2: 0 13'11---1-1---0- -> 0 3'100 3: 0 13'11---1-----1- -> 0 3'100 4: 0 13'100---0------ -> 0 3'100 5: 0 13'1-----1------ -> 0 3'100 6: 0 13'1-1--0------- -> 0 3'100 7: 0 13'11---0------- -> 0 3'100 8: 0 13'0------------ -> 0 3'100 9: 0 13'1-1-11------0 -> 1 3'100 10: 0 13'11---1---1-0- -> 1 3'100 11: 0 13'1-11-1------0 -> 2 3'100 12: 0 13'11---1--1--0- -> 2 3'100 13: 1 13'1-1--1----1-0 -> 0 3'001 14: 1 13'11---1-1---0- -> 0 3'001 15: 1 13'1-----1------ -> 0 3'001 16: 1 13'1-1-11------0 -> 1 3'001 17: 1 13'1-1--1------1 -> 1 3'001 18: 1 13'11---1---1-0- -> 1 3'001 19: 1 13'11---1-----1- -> 1 3'001 20: 1 13'100---0------ -> 1 3'001 21: 1 13'1-1--0------- -> 1 3'001 22: 1 13'11---0------- -> 1 3'001 23: 1 13'0------------ -> 1 3'001 24: 1 13'1-11-1------0 -> 2 3'001 25: 1 13'11---1--1--0- -> 2 3'001 26: 2 13'1-1--1----1-0 -> 0 3'010 27: 2 13'11---1-1---0- -> 0 3'010 28: 2 13'1-----1------ -> 0 3'010 29: 2 13'1-1-11------0 -> 1 3'010 30: 2 13'11---1---1-0- -> 1 3'010 31: 2 13'1-11-1------0 -> 2 3'010 32: 2 13'1-1--1------1 -> 2 3'010 33: 2 13'11---1--1--0- -> 2 3'010 34: 2 13'11---1-----1- -> 2 3'010 35: 2 13'100---0------ -> 2 3'010 36: 2 13'1-1--0------- -> 2 3'010 37: 2 13'11---0------- -> 2 3'010 38: 2 13'0------------ -> 2 3'010 ------------------------------------- FSM `$fsm$\soc_I.usb_I.rx_pkt_I.state$22787' from module `top': ------------------------------------- Information on FSM $fsm$\soc_I.usb_I.rx_pkt_I.state$22787 (\soc_I.usb_I.rx_pkt_I.state): Number of input signals: 14 Number of output signals: 6 Number of state bits: 8 Input signals: 0: \soc_I.usb_I.rx_ll_I.dec_valid_1 1: \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [3] 2: \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [2] 3: $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:180$1322_Y 4: $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:173$1320_Y 5: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:158$1316_Y 6: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:153$1315_Y 7: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:126$1311_Y 8: \soc_I.usb_I.rx_pkt_I.pid_is_handshake 9: \soc_I.usb_I.rx_pkt_I.pid_is_data 10: \soc_I.usb_I.rx_pkt_I.pid_is_token 11: \soc_I.usb_I.rx_pkt_I.pid_is_sof 12: \soc_I.usb_I.rx_pkt_I.pid_valid 13: \soc_I.usb_I.rx_pkt_I.llu_byte_stb Output signals: 0: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:375$1404_Y 1: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:341$1390_Y 2: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:337$1387_Y 3: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:245$1341_Y 4: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_error[0:0] 5: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_idle[0:0] State encoding: 0: 8'-------1 <RESET STATE> 1: 8'------1- 2: 8'-----1-- 3: 8'----1--- 4: 8'---1---- 5: 8'--1----- 6: 8'-1------ 7: 8'1------- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 14'------0------- -> 0 6'100000 1: 0 14'------1------- -> 4 6'100000 2: 1 14'0-------0----- -> 1 6'000100 3: 1 14'1-------0----- -> 5 6'000100 4: 1 14'--------1----- -> 6 6'000100 5: 2 14'-101---------- -> 1 6'000000 6: 2 14'-11----------- -> 1 6'000000 7: 2 14'-10001-------- -> 3 6'000000 8: 2 14'-10000-------- -> 6 6'000000 9: 2 14'-0------------ -> 6 6'000000 10: 2 14'-1001--------- -> 7 6'000000 11: 3 14'--------11---- -> 0 6'000000 12: 3 14'0-------0----- -> 3 6'000000 13: 3 14'--------10---- -> 6 6'000000 14: 3 14'1-------0----- -> 6 6'000000 15: 4 14'1------------- -> 2 6'001000 16: 4 14'0------------- -> 4 6'001000 17: 5 14'1-------0----- -> 3 6'000010 18: 5 14'0-------0----- -> 5 6'000010 19: 5 14'--------1----- -> 6 6'000010 20: 6 14'-------1------ -> 0 6'010000 21: 6 14'-------0------ -> 6 6'010000 22: 7 14'----------11-1 -> 0 6'000001 23: 7 14'-----------011 -> 6 6'000001 24: 7 14'----------01-1 -> 6 6'000001 25: 7 14'-------------0 -> 7 6'000001 26: 7 14'-----------001 -> 7 6'000001 ------------------------------------- FSM `$fsm$\soc_I.usb_I.tx_pkt_I.state$22797' from module `top': ------------------------------------- Information on FSM $fsm$\soc_I.usb_I.tx_pkt_I.state$22797 (\soc_I.usb_I.tx_pkt_I.state): Number of input signals: 5 Number of output signals: 6 Number of state bits: 6 Input signals: 0: $flatten\soc_I.\usb_I.\tx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:112$1529_Y 1: \soc_I.usb_I.tx_pkt_I.len [10] 2: \soc_I.usb_I.tx_pkt_I.next 3: \soc_I.usb_I.tx_pkt_I.pid_is_handshake 4: \soc_I.usb_I.trans_I.txpkt_start_i Output signals: 0: $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11442_CMP 1: $flatten\soc_I.\usb_I.\tx_pkt_I.$0\ll_start[0:0] 2: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:203$1572_Y 3: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1556_Y 4: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1555_Y 5: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:177$1554_Y State encoding: 0: 6'-----1 <RESET STATE> 1: 6'----1- 2: 6'---1-- 3: 6'--1--- 4: 6'-1---- 5: 6'1----- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 5'0---- -> 0 6'000100 1: 0 5'1---- -> 3 6'000100 2: 1 5'--0-- -> 1 6'000001 3: 1 5'--1-- -> 4 6'000001 4: 2 5'-11-- -> 0 6'001000 5: 2 5'-011- -> 1 6'001000 6: 2 5'--0-- -> 2 6'001000 7: 2 5'-010- -> 5 6'001000 8: 3 5'----- -> 2 6'000010 9: 4 5'--1-- -> 0 6'010000 10: 4 5'--0-- -> 4 6'010000 11: 5 5'----1 -> 1 6'100000 12: 5 5'----0 -> 5 6'100000 ------------------------------------- 73.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic). Mapping FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.fsm_state$22754' from module `\top'. Mapping FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.fsm_state$22763' from module `\top'. Mapping FSM `$fsm$\soc_I.cpu_I.cpu_state$22772' from module `\top'. Mapping FSM `$fsm$\soc_I.cpu_I.mem_wordsize$22782' from module `\top'. Mapping FSM `$fsm$\soc_I.usb_I.rx_pkt_I.state$22787' from module `\top'. Mapping FSM `$fsm$\soc_I.usb_I.tx_pkt_I.state$22797' from module `\top'. 73.12. Executing OPT pass (performing simple optimizations). 73.12.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~38 debug messages> 73.12.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~96 debug messages> Removed a total of 32 cells. 73.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 2/4 on $pmux $flatten\soc_I.\cpu_I.$procmux$12725. dead port 2/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$13189. dead port 1/3 on $pmux $flatten\soc_I.\cpu_I.$procmux$13374. Removed 3 multiplexer ports. <suppressed ~454 debug messages> 73.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$22708: { \soc_I.cpu_I.cpu_state [6:4] \soc_I.cpu_I.cpu_state [2:0] } New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$22706: \soc_I.cpu_I.cpu_state [5:0] New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$22704: { \soc_I.cpu_I.cpu_state [6] \soc_I.cpu_I.cpu_state [4:0] } Optimizing cells in module \top. Performed a total of 3 changes. 73.12.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.12.6. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $flatten\sys_mgr_I.$procdff$22276 ($adff) from module top (D = $flatten\sys_mgr_I.$add$/build/gateware/e1-tracer/rtl/sysmgr.v:85$1601_Y [2:0], Q = \sys_mgr_I.rst_cnt [2:0]). Adding EN signal on $flatten\soc_I.\wb_48m_xclk_I.$procdff$22637 ($dff) from module top (D = \soc_I.wb_48m_xclk_I.m_rdata, Q = \soc_I.wb_48m_xclk_I.m_rdata_i). Adding SRST signal on $flatten\soc_I.\wb_48m_xclk_I.$procdff$22636 ($dff) from module top (D = \soc_I.wb_48m_xclk_I.m_rdata_i, Q = \soc_I.wb_48m_xclk_I.s_rdata, rval = 16'0000000000000000). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.\crc_16_I.$procdff$22239 ($dff) from module top (D = \soc_I.usb_I.tx_pkt_I.crc_16_I.state_nxt, Q = \soc_I.usb_I.tx_pkt_I.crc_16_I.state). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$22294 ($dff) from module top (D = $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1545_Y [3:0], Q = \soc_I.usb_I.tx_pkt_I.shift_bit). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$22293 ($dff) from module top (D = $flatten\soc_I.\usb_I.\tx_pkt_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:172$1551_Y, Q = \soc_I.usb_I.tx_pkt_I.shift_data). Adding SRST signal on $auto$opt_dff.cc:764:run$23363 ($dffe) from module top (D = \soc_I.usb_I.tx_pkt_I.shift_load [7], Q = \soc_I.usb_I.tx_pkt_I.shift_data [7], rval = 1'0). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$22292 ($dff) from module top (D = $flatten\soc_I.\usb_I.\tx_pkt_I.$or$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1558_Y, Q = \soc_I.usb_I.tx_pkt_I.shift_last_byte). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$22291 ($dff) from module top (D = \soc_I.usb_I.tx_pkt_I.state [5], Q = \soc_I.usb_I.tx_pkt_I.shift_data_crc). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$22289 ($dff) from module top (D = $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1568_Y [10:0], Q = \soc_I.usb_I.tx_pkt_I.len). Adding EN signal on $flatten\soc_I.\usb_I.\tx_ll_I.$procdff$22304 ($adff) from module top (D = $flatten\soc_I.\usb_I.\tx_ll_I.$0\state[2:0], Q = \soc_I.usb_I.tx_ll_I.state). Adding EN signal on $flatten\soc_I.\usb_I.\tx_ll_I.$procdff$22302 ($adff) from module top (D = $flatten\soc_I.\usb_I.\tx_ll_I.$and$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:95$1510_Y, Q = \soc_I.usb_I.tx_ll_I.bs_now). Adding EN signal on $flatten\soc_I.\usb_I.\tx_ll_I.$procdff$22301 ($adff) from module top (D = $flatten\soc_I.\usb_I.\tx_ll_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1508_Y [2:0], Q = \soc_I.usb_I.tx_ll_I.bs_cnt). Adding SRST signal on $flatten\soc_I.\usb_I.\tx_ll_I.$procdff$22300 ($dff) from module top (D = $flatten\soc_I.\usb_I.\tx_ll_I.$xor$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:103$1516_Y, Q = \soc_I.usb_I.tx_ll_I.lvl_prev, rval = 1'1). Adding EN signal on $flatten\soc_I.\usb_I.\tx_ll_I.$procdff$22298 ($adff) from module top (D = $flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11524_Y, Q = \soc_I.usb_I.tx_ll_I.out_sym). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22328 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$procmux$11605_Y, Q = \soc_I.usb_I.trans_I.mc_a_reg). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22325 ($dff) from module top (D = \soc_I.usb_I.trans_I.cel_state_i, Q = \soc_I.usb_I.trans_I.trans_cel). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22324 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:286$1442_Y, Q = \soc_I.usb_I.trans_I.trans_dir). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22323 ($dff) from module top (D = \soc_I.usb_I.rx_pkt_I.token_data [10:7], Q = \soc_I.usb_I.trans_I.trans_endp). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22322 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:284$1441_Y, Q = \soc_I.usb_I.trans_I.trans_is_setup). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22319 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$0\bd_state[2:0], Q = \soc_I.usb_I.trans_I.bd_state). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22316 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_trans.v:363$1453_Y, Q = \soc_I.usb_I.trans_I.ep_bd_idx_cur). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22315 ($dff) from module top (D = \soc_I.usb_I.ep_status_I.p_dout_3 [5], Q = \soc_I.usb_I.trans_I.ep_bd_ctrl). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22314 ($dff) from module top (D = \soc_I.usb_I.ep_status_I.p_dout_3 [4], Q = \soc_I.usb_I.trans_I.ep_bd_dual). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22313 ($dff) from module top (D = \soc_I.usb_I.ep_status_I.p_dout_3 [2:0], Q = \soc_I.usb_I.trans_I.ep_type). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22310 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$xor$/build/gateware/cores/no2usb//rtl/usb_trans.v:401$1474_Y, Q = \soc_I.usb_I.trans_I.txpkt_pid). Adding SRST signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22307 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_trans.v:425$1484_Y, Q = \soc_I.usb_I.trans_I.bd_length, rval = 11'00000000000). Adding SRST signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22306 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:429$1486_Y, Q = \soc_I.usb_I.trans_I.xfer_length, rval = 10'0000000000). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22305 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$procmux$11549_Y, Q = \soc_I.usb_I.trans_I.pkt_pid). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.\crc_5_I.$procdff$22238 ($dff) from module top (D = \soc_I.usb_I.rx_pkt_I.crc_5_I.state_nxt, Q = \soc_I.usb_I.rx_pkt_I.crc_5_I.state). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.\crc_16_I.$procdff$22239 ($dff) from module top (D = \soc_I.usb_I.rx_pkt_I.crc_16_I.state_nxt, Q = \soc_I.usb_I.rx_pkt_I.crc_16_I.state). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22350 ($dff) from module top (D = { \soc_I.usb_I.rx_ll_I.dec_bit_1 \soc_I.usb_I.rx_pkt_I.data [7:1] }, Q = \soc_I.usb_I.rx_pkt_I.data). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22349 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11648_Y, Q = \soc_I.usb_I.rx_pkt_I.bit_cnt, rval = 4'0110). Adding EN signal on $auto$opt_dff.cc:702:run$23398 ($sdff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1336_Y [3:0], Q = \soc_I.usb_I.rx_pkt_I.bit_cnt). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22348 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11643_Y, Q = \soc_I.usb_I.rx_pkt_I.bit_eop_ok, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23400 ($sdff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:234$1339_Y, Q = \soc_I.usb_I.rx_pkt_I.bit_eop_ok). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22347 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11638_Y, Q = \soc_I.usb_I.rx_pkt_I.crc_in_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23402 ($sdff) from module top (D = 1'0, Q = \soc_I.usb_I.rx_pkt_I.crc_in_first). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22345 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11628_Y, Q = \soc_I.usb_I.rx_pkt_I.crc16_ok, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23404 ($sdff) from module top (D = \soc_I.usb_I.rx_pkt_I.crc16_match, Q = \soc_I.usb_I.rx_pkt_I.crc16_ok). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22344 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11633_Y, Q = \soc_I.usb_I.rx_pkt_I.crc5_ok, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23406 ($sdff) from module top (D = \soc_I.usb_I.rx_pkt_I.crc5_match, Q = \soc_I.usb_I.rx_pkt_I.crc5_ok). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22343 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:306$1367_Y, Q = \soc_I.usb_I.rx_pkt_I.pid_valid). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22341 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_or$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:329$1385_Y, Q = \soc_I.usb_I.rx_pkt_I.pid_is_handshake). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22340 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_or$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:328$1380_Y, Q = \soc_I.usb_I.rx_pkt_I.pid_is_data). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22339 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_or$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:327$1377_Y, Q = \soc_I.usb_I.rx_pkt_I.pid_is_token). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22338 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:307$1350_Y, Q = \soc_I.usb_I.rx_pkt_I.pid_is_sof). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22337 ($dff) from module top (D = \soc_I.usb_I.rx_pkt_I.data [4:1], Q = \soc_I.usb_I.rx_pkt_I.pid). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22336 ($dff) from module top (D = { \soc_I.usb_I.rx_ll_I.dec_bit_1 \soc_I.usb_I.rx_pkt_I.data [7:1] }, Q = \soc_I.usb_I.rx_pkt_I.token_data [7:0]). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22335 ($dff) from module top (D = \soc_I.usb_I.rx_pkt_I.data [3:1], Q = \soc_I.usb_I.rx_pkt_I.token_data [10:8]). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$22362 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11914_Y, Q = \soc_I.usb_I.rx_ll_I.samp_cnt, rval = 3'101). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$22360 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:115$1299_Y, Q = \soc_I.usb_I.rx_ll_I.dec_bit_1). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$22359 ($dff) from module top (D = { \soc_I.usb_I.phy_I.dp_state [1] \soc_I.usb_I.phy_I.dn_state [1] }, Q = \soc_I.usb_I.rx_ll_I.dec_sym_1). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$22357 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11903_Y, Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$22356 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11898_Y, Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1). Adding SRST signal on $auto$opt_dff.cc:764:run$23420 ($dffe) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11888_Y, Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1, rval = 4'0000). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$22355 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11881_Y, Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1). Adding SRST signal on $auto$opt_dff.cc:764:run$23422 ($dffe) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11871_Y, Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1, rval = 4'0000). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$22354 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:183$1306_Y, Q = \soc_I.usb_I.rx_ll_I.dec_bs_skip_1). Adding EN signal on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$22369 ($dff) from module top (D = \soc_I.usb_I.ep_status_I.dout_2, Q = \soc_I.usb_I.ep_status_I.p_dout_3). Adding EN signal on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$22368 ($dff) from module top (D = $flatten\soc_I.\usb_I.\ep_status_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:82$1272_Y, Q = \soc_I.usb_I.ep_status_I.s_dout_3). Adding SRST signal on $auto$opt_dff.cc:764:run$23426 ($dffe) from module top (D = \soc_I.usb_I.ep_status_I.dout_2, Q = \soc_I.usb_I.ep_status_I.s_dout_3, rval = 16'0000000000000000). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22632 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:413$3209_Y, Q = \soc_I.usb_I.sof_clear, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22631 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:412$3206_Y, Q = \soc_I.usb_I.rst_clear, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22630 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:414$3212_Y, Q = \soc_I.usb_I.evt_rd_ack, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22628 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:410$3200_Y, Q = \soc_I.usb_I.cr_bus_we, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22626 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:411$3203_Y, Q = \soc_I.usb_I.cel_rel, rval = 1'0). Adding EN signal on $flatten\soc_I.\usb_I.$procdff$22625 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [6:0], Q = \soc_I.usb_I.cr_addr). Adding EN signal on $flatten\soc_I.\usb_I.$procdff$22624 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [7], Q = \soc_I.usb_I.cr_addr_chk). Adding EN signal on $flatten\soc_I.\usb_I.$procdff$22623 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [12], Q = \soc_I.usb_I.cr_cel_ena). Adding EN signal on $flatten\soc_I.\usb_I.$procdff$22622 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [15], Q = \soc_I.usb_I.cr_pu_ena). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22621 ($dff) from module top (D = \soc_I.cpu_I.mem_addr [13], Q = \soc_I.usb_I.eps_bus_req, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22620 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:498$3225_Y, Q = \soc_I.usb_I.eps_bus_write, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22619 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:497$3224_Y, Q = \soc_I.usb_I.eps_bus_read, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22616 ($dff) from module top (D = $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:623$3251_Y, Q = \soc_I.usb_I.timeout_suspend, rval = 20'11011100110110000000). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22615 ($dff) from module top (D = $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:632$3255_Y, Q = \soc_I.usb_I.timeout_reset, rval = 20'10001010110100000000). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22613 ($dff) from module top (D = \soc_I.usb_I.cr_pu_ena, Q = \soc_I.usb_I.pad_pu, rval = 1'0). Adding EN signal on $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$procdff$22364 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5121_DATA, Q = \soc_I.uart_I.uart_tx_fifo_I.ram_I.rd_data). Adding EN signal on $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$procdff$22267 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4530_Y [8:0], Q = \soc_I.uart_I.uart_tx_fifo_I.ram_wr_addr). Adding EN signal on $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$procdff$22266 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4532_Y [8:0], Q = \soc_I.uart_I.uart_tx_fifo_I.ram_rd_addr). Adding EN signal on $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$procdff$22265 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$not$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:114$4535_Y, Q = \soc_I.uart_I.uart_tx_fifo_I.rd_valid). Adding SRST signal on $flatten\soc_I.\uart_I.\uart_tx_I.$procdff$22258 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5261_Y [12], Q = \soc_I.uart_I.uart_tx_I.div_cnt [12], rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.\uart_tx_I.$procdff$22257 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_I.$procmux$5480_Y, Q = \soc_I.uart_I.uart_tx_I.bit_cnt, rval = 5'01000). Adding EN signal on $auto$opt_dff.cc:702:run$23448 ($sdff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5264_Y [4:0], Q = \soc_I.uart_I.uart_tx_I.bit_cnt). Adding EN signal on $flatten\soc_I.\uart_I.\uart_tx_I.$procdff$22256 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_I.$0\shift[9:0], Q = \soc_I.uart_I.uart_tx_I.shift). Adding EN signal on $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$procdff$22364 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5121_DATA, Q = \soc_I.uart_I.uart_rx_fifo_I.ram_I.rd_data). Adding EN signal on $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$procdff$22267 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4530_Y [8:0], Q = \soc_I.uart_I.uart_rx_fifo_I.ram_wr_addr). Adding EN signal on $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$procdff$22266 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4532_Y [8:0], Q = \soc_I.uart_I.uart_rx_fifo_I.ram_rd_addr). Adding EN signal on $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$procdff$22265 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$not$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:114$4535_Y, Q = \soc_I.uart_I.uart_rx_fifo_I.rd_valid). Adding SRST signal on $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procdff$22274 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4501_Y, Q = \soc_I.uart_I.uart_rx_I.gf_I.cnt, rval = 2'11). Adding SRST signal on $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procdff$22273 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procmux$5517_Y, Q = \soc_I.uart_I.uart_rx_I.gf_I.state, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23458 ($sdff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procmux$5517_Y, Q = \soc_I.uart_I.uart_rx_I.gf_I.state). Adding SRST signal on $flatten\soc_I.\uart_I.\uart_rx_I.$procdff$22262 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_I.$procmux$5490_Y, Q = \soc_I.uart_I.uart_rx_I.bit_cnt, rval = 5'01000). Adding EN signal on $auto$opt_dff.cc:702:run$23462 ($sdff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5246_Y [4:0], Q = \soc_I.uart_I.uart_rx_I.bit_cnt). Adding EN signal on $flatten\soc_I.\uart_I.\uart_rx_I.$procdff$22261 ($dff) from module top (D = { \soc_I.uart_I.uart_rx_I.gf_I.state \soc_I.uart_I.uart_rx_I.shift [8:1] }, Q = \soc_I.uart_I.uart_rx_I.shift). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$22607 ($dff) from module top (D = $flatten\soc_I.\uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:174$3303_Y, Q = \soc_I.uart_I.ub_wr_div, rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$22606 ($dff) from module top (D = $flatten\soc_I.\uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:173$3300_Y, Q = \soc_I.uart_I.ub_wr_data, rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$22605 ($dff) from module top (D = $flatten\soc_I.\uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:172$3295_Y, Q = \soc_I.uart_I.ub_rd_ctrl, rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$22604 ($dff) from module top (D = $flatten\soc_I.\uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:171$3291_Y, Q = \soc_I.uart_I.ub_rd_data, rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$22603 ($dff) from module top (D = $flatten\soc_I.\uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:181$3310_Y, Q = \soc_I.uart_I.ub_ack, rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$22602 ($dff) from module top (D = { $flatten\soc_I.\uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3315_Y [31] $flatten\soc_I.\uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3315_Y [27:12] $flatten\soc_I.\uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3315_Y [7:0] }, Q = { \soc_I.uart_I.ub_rdata [31] \soc_I.uart_I.ub_rdata [27:12] \soc_I.uart_I.ub_rdata [7:0] }, rval = 25'0000000000000000000000000). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$22602 ($dff) from module top (D = { \soc_I.uart_I.urf_overflow \soc_I.uart_I.uart_tx_fifo_I.rd_empty \soc_I.uart_I.uart_tx_fifo_I.full \soc_I.uart_I.uart_div [11:8] }, Q = { \soc_I.uart_I.ub_rdata [30:28] \soc_I.uart_I.ub_rdata [11:8] }, rval = 7'0000000). Adding EN signal on $flatten\soc_I.\uart_I.$procdff$22601 ($dff) from module top (D = \soc_I.cpu_I.mem_wdata [11:0], Q = \soc_I.uart_I.uart_div). Adding EN signal on $flatten\soc_I.\rgb_I.$procdff$22609 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [4:0], Q = \soc_I.rgb_I.led_ctrl). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$22644 ($adff) from module top (D = \soc_I.iobuf_I.spram_arb_I.mux_wmsk, Q = \soc_I.iobuf_I.spram_arb_I.m_wmsk). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$22643 ($adff) from module top (D = $flatten\soc_I.\iobuf_I.\spram_arb_I.$reduce_or$/build/gateware/common/rtl/wb_arbiter.v:91$4895_Y, Q = \soc_I.iobuf_I.spram_arb_I.m_we). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$22642 ($adff) from module top (D = \soc_I.iobuf_I.spram_arb_I.mux_wdata, Q = \soc_I.iobuf_I.spram_arb_I.m_wdata). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$22641 ($adff) from module top (D = \soc_I.iobuf_I.spram_arb_I.mux_addr, Q = \soc_I.iobuf_I.spram_arb_I.m_addr). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$22640 ($adff) from module top (D = $flatten\soc_I.\iobuf_I.\spram_arb_I.$reduce_or$/build/gateware/common/rtl/wb_arbiter.v:121$4908_Y, Q = \soc_I.iobuf_I.spram_arb_I.busy). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$22639 ($adff) from module top (D = \soc_I.iobuf_I.spram_arb_I.sel_nxt, Q = \soc_I.iobuf_I.spram_arb_I.sel). Adding EN signal on $flatten\soc_I.\iobuf_I.\epbam_arb_I.$procdff$22221 ($adff) from module top (D = $flatten\soc_I.\iobuf_I.\epbam_arb_I.$reduce_or$/build/gateware/common/rtl/wb_arbiter.v:91$4843_Y, Q = \soc_I.iobuf_I.epbam_arb_I.m_we). Adding EN signal on $flatten\soc_I.\iobuf_I.\epbam_arb_I.$procdff$22220 ($adff) from module top (D = \soc_I.iobuf_I.epbam_arb_I.mux_wdata, Q = \soc_I.iobuf_I.epbam_arb_I.m_wdata). Adding EN signal on $flatten\soc_I.\iobuf_I.\epbam_arb_I.$procdff$22219 ($adff) from module top (D = \soc_I.iobuf_I.epbam_arb_I.mux_addr, Q = \soc_I.iobuf_I.epbam_arb_I.m_addr). Adding EN signal on $flatten\soc_I.\iobuf_I.\epbam_arb_I.$procdff$22218 ($adff) from module top (D = $flatten\soc_I.\iobuf_I.\epbam_arb_I.$reduce_or$/build/gateware/common/rtl/wb_arbiter.v:121$4854_Y, Q = \soc_I.iobuf_I.epbam_arb_I.busy). Adding EN signal on $flatten\soc_I.\iobuf_I.\epbam_arb_I.$procdff$22217 ($adff) from module top (D = \soc_I.iobuf_I.epbam_arb_I.sel_nxt, Q = \soc_I.iobuf_I.epbam_arb_I.sel). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$22231 ($adff) from module top (D = \soc_I.iobuf_I.dma_I.state_nxt, Q = \soc_I.iobuf_I.dma_I.state). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$22230 ($dff) from module top (D = $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:144$4787_Y, Q = \soc_I.iobuf_I.dma_I.data_reg). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$22229 ($dff) from module top (D = $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:155$4791_Y [13:0], Q = \soc_I.iobuf_I.dma_I.m0_addr_i). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$22228 ($dff) from module top (D = $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:159$4795_Y [8:0], Q = \soc_I.iobuf_I.dma_I.m1_addr_i). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$22227 ($dff) from module top (D = $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:176$4804_Y [12:0], Q = \soc_I.iobuf_I.dma_I.len). Adding SRST signal on $auto$opt_dff.cc:764:run$23501 ($dffe) from module top (D = $flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$4803_Y [12], Q = \soc_I.iobuf_I.dma_I.len [12], rval = 1'0). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$22226 ($dff) from module top (D = \soc_I.cpu_I.mem_wdata [14], Q = \soc_I.iobuf_I.dma_I.dir). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$22586 ($dff) from module top (D = \soc_I.e1_buf_I.t_nxt_chan, Q = \soc_I.e1_buf_I.t_chan). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$22578 ($dff) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$14823_Y, Q = \soc_I.e1_buf_I.wb_wdata_byte). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$22577 ($dff) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$14838_Y, Q = \soc_I.e1_buf_I.wb_addr_lsb). Adding SRST signal on $auto$opt_dff.cc:764:run$23506 ($dffe) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$14832_Y, Q = \soc_I.e1_buf_I.wb_addr_lsb, rval = 2'00). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$22574 ($dff) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$14853_Y, Q = \soc_I.e1_buf_I.wb_addr). Adding SRST signal on $auto$opt_dff.cc:764:run$23510 ($dffe) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$14847_Y, Q = \soc_I.e1_buf_I.wb_addr, rval = 14'00000000000000). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$22573 ($dff) from module top (D = { \soc_I.e1_buf_I.buf_rx_mf [6:0] \soc_I.e1_buf_I.buf_rx_frame [3:0] \soc_I.e1_buf_I.buf_rx_ts [4:0] }, Q = \soc_I.e1_buf_I.rx_addr_reg[0]). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$22572 ($dff) from module top (D = \soc_I.e1_buf_I.buf_rx_data [7:0], Q = \soc_I.e1_buf_I.rx_data_reg[0]). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$22570 ($dff) from module top (D = { \soc_I.e1_buf_I.buf_rx_mf [13:7] \soc_I.e1_buf_I.buf_rx_frame [7:4] \soc_I.e1_buf_I.buf_rx_ts [9:5] }, Q = \soc_I.e1_buf_I.rx_addr_reg[1]). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$22569 ($dff) from module top (D = \soc_I.e1_buf_I.buf_rx_data [15:8], Q = \soc_I.e1_buf_I.rx_data_reg[1]). Adding SRST signal on $flatten\soc_I.\e1_I.$procdff$22400 ($dff) from module top (D = \soc_I.e1_I.bus_rdata, Q = \soc_I.e1_I.wb_rdata, rval = 16'0000000000000000). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.\crc_I.$procdff$22699 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.\crc_I.$xor$/build/gateware/cores/no2e1//rtl/e1_crc4.v:40$11_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.crc_I.out_crc4). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22697 ($dff) from module top (D = \misc_I.tick_e1 [6], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.crc_I.in_valid, rval = 1'0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22696 ($dff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.data [6:0] \soc_I.e1_I.lb_bit [1] }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.data). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22695 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:135$18_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.data_match_fas). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22693 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procmux$15148_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.bit_last, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23523 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:215$32_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.bit_last). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22692 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procmux$15153_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.bit_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23525 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:214$31_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.bit_first). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22691 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procmux$15158_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.bit, rval = 3'000). Adding EN signal on $auto$opt_dff.cc:702:run$23527 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$30_Y [2:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.bit). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22690 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procmux$15133_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.ts_is_ts31, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23529 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:227$36_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.ts_is_ts31). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22689 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procmux$15138_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.ts_is_ts0, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23531 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.ts_is_ts31, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.ts_is_ts0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22688 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procmux$15143_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.ts, rval = 5'00001). Adding EN signal on $auto$opt_dff.cc:702:run$23533 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$35_Y [4:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.ts). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22687 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procmux$15108_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.frame_mf_last, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23535 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:243$42_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.frame_mf_last). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22686 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procmux$15113_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.frame_mf_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23537 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.frame_mf_last, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.frame_mf_first). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22685 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procmux$15118_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.frame_smf_last, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23539 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:241$41_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.frame_smf_last). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22684 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procmux$15123_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.frame_smf_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23541 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.frame_smf_last, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.frame_smf_first). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22683 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procmux$15128_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.frame, rval = 4'0000). Adding EN signal on $auto$opt_dff.cc:702:run$23543 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$40_Y [3:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.frame). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22682 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$xor$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:262$50_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.fas_pos, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22681 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procmux$15100_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.mfa_timeout, rval = 7'0111111). Adding EN signal on $auto$opt_dff.cc:702:run$23546 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$54_Y [6:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.mfa_timeout). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22680 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procmux$15085_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.ts0_msbs_match_crc, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23548 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:285$60_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.ts0_msbs_match_crc). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22679 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procmux$15090_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23550 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:284$59_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22678 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procmux$15095_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.ts0_msbs, rval = 16'1111111111111111). Adding EN signal on $auto$opt_dff.cc:702:run$23552 ($sdff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.ts0_msbs [14:0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.data [0] }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.ts0_msbs). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22677 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.crc_I.out_crc4, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.crc_smf). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22676 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:325$82_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.ep_nfas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22675 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:326$88_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.ed_nfas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22674 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:323$73_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.ep_fas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22673 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:324$78_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.ed_fas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22672 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:340$103_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.ep_mfa, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22671 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:341$108_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.ed_mfa, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22670 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:338$95_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.ep_crc, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22669 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:339$100_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.ed_crc, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22668 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$125_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.ec_mfa, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22667 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$121_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.ec_crc, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22666 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$117_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.ec_nfas, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22665 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$113_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.ec_fas, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22663 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:389$138_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.out_valid, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22662 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:396$140_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.out_last, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22661 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:395$139_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.out_first, rval = 1'1). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22659 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.ts, Q = \soc_I.e1_buf_I.buf_rx_ts [9:5], rval = 5'00000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22658 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.frame, Q = \soc_I.e1_buf_I.buf_rx_frame [7:4], rval = 4'0000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22657 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.data, Q = \soc_I.e1_buf_I.buf_rx_data [15:8], rval = 8'00000000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$procdff$22656 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:389$137_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.aligned, rval = 1'0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\bd_rx_out_I.$procdff$22399 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\bd_rx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4131_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_out_I.data[1]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\bd_rx_out_I.$procdff$22398 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4136_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_out_I.stage[1].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\bd_rx_out_I.$procdff$22397 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\bd_rx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4142_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_out_I.data[2]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\bd_rx_out_I.$procdff$22396 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4147_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_out_I.stage[2].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\bd_rx_out_I.$procdff$22395 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\bd_rx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4153_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_out_I.data[3]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\bd_rx_out_I.$procdff$22394 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4158_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_out_I.stage[3].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\bd_rx_out_I.$procdff$22393 ($adff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_out_I.data[5] [8:7] \soc_I.e1_buf_I.buf_rx_mf [13:7] }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_out_I.data[4]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\bd_rx_out_I.$procdff$22392 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4169_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_out_I.stage[4].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\bd_rx_in_I.$procdff$22391 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\bd_rx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4177_Y, Q = \soc_I.e1_buf_I.buf_rx_mf [13:7]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\bd_rx_in_I.$procdff$22390 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4182_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_in_I.stage[1].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\bd_rx_in_I.$procdff$22389 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\bd_rx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4188_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_in_I.data[2]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\bd_rx_in_I.$procdff$22388 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4193_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_in_I.stage[2].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\bd_rx_in_I.$procdff$22387 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\bd_rx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4199_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_in_I.data[3]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\bd_rx_in_I.$procdff$22386 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4204_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_in_I.stage[3].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\bd_rx_in_I.$procdff$22385 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [6:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_in_I.data[4]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\bd_rx_in_I.$procdff$22384 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4215_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_in_I.stage[4].l_valid). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.$procdff$22254 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:114$5274_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.crx_clear, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.$procdff$22253 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:113$5271_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.$procmux$5466_CMP, rval = 1'0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.$procdff$22252 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [2:1], Q = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_mode [1] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.ctrl_mode_mf }). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.$procdff$22251 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bus_rd_rx_status [0]). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.$procdff$22250 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:149$5287_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_out_I.rd_ena, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.$procdff$22249 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:148$5281_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_in_I.wr_ena, rval = 1'0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.\crc_I.$procdff$22699 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.\crc_I.$xor$/build/gateware/cores/no2e1//rtl/e1_crc4.v:40$11_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.crc_I.out_crc4). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22697 ($dff) from module top (D = \misc_I.tick_e1 [2], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.crc_I.in_valid, rval = 1'0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22696 ($dff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.data [6:0] \soc_I.e1_I.lb_bit [0] }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.data). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22695 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:135$18_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.data_match_fas). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22693 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procmux$15148_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.bit_last, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23608 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:215$32_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.bit_last). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22692 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procmux$15153_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.bit_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23610 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:214$31_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.bit_first). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22691 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procmux$15158_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.bit, rval = 3'000). Adding EN signal on $auto$opt_dff.cc:702:run$23612 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$30_Y [2:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.bit). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22690 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procmux$15133_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.ts_is_ts31, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23614 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:227$36_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.ts_is_ts31). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22689 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procmux$15138_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.ts_is_ts0, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23616 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.ts_is_ts31, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.ts_is_ts0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22688 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procmux$15143_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.ts, rval = 5'00001). Adding EN signal on $auto$opt_dff.cc:702:run$23618 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$35_Y [4:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.ts). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22687 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procmux$15108_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.frame_mf_last, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23620 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:243$42_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.frame_mf_last). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22686 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procmux$15113_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.frame_mf_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23622 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.frame_mf_last, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.frame_mf_first). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22685 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procmux$15118_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.frame_smf_last, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23624 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:241$41_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.frame_smf_last). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22684 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procmux$15123_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.frame_smf_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23626 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.frame_smf_last, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.frame_smf_first). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22683 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procmux$15128_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.frame, rval = 4'0000). Adding EN signal on $auto$opt_dff.cc:702:run$23628 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$40_Y [3:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.frame). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22682 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$xor$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:262$50_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.fas_pos, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22681 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procmux$15100_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.mfa_timeout, rval = 7'0111111). Adding EN signal on $auto$opt_dff.cc:702:run$23631 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$54_Y [6:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.mfa_timeout). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22680 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procmux$15085_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_crc, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23633 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:285$60_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_crc). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22679 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procmux$15090_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23635 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:284$59_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22678 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procmux$15095_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.ts0_msbs, rval = 16'1111111111111111). Adding EN signal on $auto$opt_dff.cc:702:run$23637 ($sdff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.ts0_msbs [14:0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.data [0] }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.ts0_msbs). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22677 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.crc_I.out_crc4, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.crc_smf). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22676 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:325$82_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.ep_nfas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22675 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:326$88_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.ed_nfas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22674 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:323$73_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.ep_fas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22673 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:324$78_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.ed_fas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22672 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:340$103_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.ep_mfa, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22671 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:341$108_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.ed_mfa, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22670 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:338$95_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.ep_crc, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22669 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:339$100_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.ed_crc, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22668 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$125_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.ec_mfa, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22667 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$121_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.ec_crc, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22666 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$117_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.ec_nfas, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22665 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$113_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.ec_fas, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22663 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:389$138_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.out_valid, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22662 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:396$140_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.out_last, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22661 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:395$139_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.out_first, rval = 1'1). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22659 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.ts, Q = \soc_I.e1_buf_I.buf_rx_ts [4:0], rval = 5'00000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22658 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.frame, Q = \soc_I.e1_buf_I.buf_rx_frame [3:0], rval = 4'0000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22657 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.data, Q = \soc_I.e1_buf_I.buf_rx_data [7:0], rval = 8'00000000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$procdff$22656 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:389$137_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.aligned, rval = 1'0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\bd_rx_out_I.$procdff$22399 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\bd_rx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4131_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_out_I.data[1]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\bd_rx_out_I.$procdff$22398 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4136_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_out_I.stage[1].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\bd_rx_out_I.$procdff$22397 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\bd_rx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4142_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_out_I.data[2]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\bd_rx_out_I.$procdff$22396 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4147_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_out_I.stage[2].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\bd_rx_out_I.$procdff$22395 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\bd_rx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4153_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_out_I.data[3]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\bd_rx_out_I.$procdff$22394 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4158_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_out_I.stage[3].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\bd_rx_out_I.$procdff$22393 ($adff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_out_I.data[5] [8:7] \soc_I.e1_buf_I.buf_rx_mf [6:0] }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_out_I.data[4]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\bd_rx_out_I.$procdff$22392 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4169_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_out_I.stage[4].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\bd_rx_in_I.$procdff$22391 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\bd_rx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4177_Y, Q = \soc_I.e1_buf_I.buf_rx_mf [6:0]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\bd_rx_in_I.$procdff$22390 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4182_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_in_I.stage[1].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\bd_rx_in_I.$procdff$22389 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\bd_rx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4188_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_in_I.data[2]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\bd_rx_in_I.$procdff$22388 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4193_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_in_I.stage[2].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\bd_rx_in_I.$procdff$22387 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\bd_rx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4199_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_in_I.data[3]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\bd_rx_in_I.$procdff$22386 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4204_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_in_I.stage[3].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\bd_rx_in_I.$procdff$22385 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [6:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_in_I.data[4]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\bd_rx_in_I.$procdff$22384 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4215_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_in_I.stage[4].l_valid). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.$procdff$22254 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:114$5274_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.crx_clear, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.$procdff$22253 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:113$5271_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.$procmux$5466_CMP, rval = 1'0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.$procdff$22252 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [2:1], Q = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_mode [1] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.ctrl_mode_mf }). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.$procdff$22251 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bus_rd_rx_status [0]). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.$procdff$22250 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:149$5287_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_out_I.rd_ena, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.$procdff$22249 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:148$5281_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_in_I.wr_ena, rval = 1'0). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22559 ($dff) from module top (D = \soc_I.cpu_I.mem_rdata, Q = \soc_I.cpu_I.mem_rdata_q). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22554 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$0\mem_state[1:0], Q = \soc_I.cpu_I.mem_state). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22553 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14414_Y, Q = \soc_I.cpu_I.mem_wstrb). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22552 ($dff) from module top (D = \soc_I.cpu_I.mem_la_wdata, Q = \soc_I.cpu_I.mem_wdata). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22550 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$0\mem_valid[0:0], Q = \soc_I.cpu_I.mem_valid). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22549 ($dff) from module top (D = \soc_I.cpu_I.mem_la_addr, Q = \soc_I.cpu_I.mem_addr). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22533 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$reduce_or$/build/gateware/common/rtl/picorv32.v:846$3592_Y, Q = \soc_I.cpu_I.is_compare, rval = 1'0). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22532 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:860$3612_Y, Q = \soc_I.cpu_I.is_alu_reg_reg). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22531 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:859$3611_Y, Q = \soc_I.cpu_I.is_alu_reg_imm). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22529 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13795_Y, Q = \soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23734 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:856$3608_Y, Q = \soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22526 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$reduce_or$/build/gateware/common/rtl/picorv32.v:842$3588_Y, Q = \soc_I.cpu_I.is_lui_auipc_jal_jalr_addi_add_sub, rval = 1'0). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22525 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1091$3841_Y, Q = \soc_I.cpu_I.is_sll_srl_sra). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22524 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:858$3610_Y, Q = \soc_I.cpu_I.is_sb_sh_sw). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22523 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1082$3830_Y, Q = \soc_I.cpu_I.is_jalr_addi_slti_sltiu_xori_ori_andi). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22522 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1076$3821_Y, Q = \soc_I.cpu_I.is_slli_srli_srai). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22521 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:857$3609_Y, Q = \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22519 ($dff) from module top (D = 1'0, Q = \soc_I.cpu_I.compressed_instr). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$23742 ($dffe) from module top. Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22518 ($dff) from module top (D = { \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [19:12] \soc_I.cpu_I.mem_rdata_latched [20] \soc_I.cpu_I.mem_rdata_latched [30:21] 1'0 }, Q = \soc_I.cpu_I.decoded_imm_uj). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$23743 ($dffe) from module top. Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22517 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841_Y, Q = \soc_I.cpu_I.decoded_imm). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22516 ($dff) from module top (D = \soc_I.cpu_I.mem_rdata_latched [24:20], Q = \soc_I.cpu_I.decoded_rs2). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22515 ($dff) from module top (D = \soc_I.cpu_I.mem_rdata_latched [19:15], Q = \soc_I.cpu_I.decoded_rs1). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22514 ($dff) from module top (D = \soc_I.cpu_I.mem_rdata_latched [11:7], Q = \soc_I.cpu_I.decoded_rd). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22510 ($dff) from module top (D = 1'0, Q = \soc_I.cpu_I.instr_retirq). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$23748 ($dffe) from module top. Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22507 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1068$3788_Y, Q = \soc_I.cpu_I.instr_ecall_ebreak). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22502 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13951_Y, Q = \soc_I.cpu_I.instr_and, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23750 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1059$3757_Y, Q = \soc_I.cpu_I.instr_and). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22501 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13955_Y, Q = \soc_I.cpu_I.instr_or, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23752 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1058$3753_Y, Q = \soc_I.cpu_I.instr_or). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22500 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13959_Y, Q = \soc_I.cpu_I.instr_sra, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23754 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1057$3749_Y, Q = \soc_I.cpu_I.instr_sra). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22499 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13963_Y, Q = \soc_I.cpu_I.instr_srl, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23756 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1056$3745_Y, Q = \soc_I.cpu_I.instr_srl). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22498 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13967_Y, Q = \soc_I.cpu_I.instr_xor, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23758 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1055$3741_Y, Q = \soc_I.cpu_I.instr_xor). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22497 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13971_Y, Q = \soc_I.cpu_I.instr_sltu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23760 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1054$3737_Y, Q = \soc_I.cpu_I.instr_sltu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22496 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13975_Y, Q = \soc_I.cpu_I.instr_slt, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23762 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1053$3733_Y, Q = \soc_I.cpu_I.instr_slt). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22495 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13979_Y, Q = \soc_I.cpu_I.instr_sll, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23764 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1052$3729_Y, Q = \soc_I.cpu_I.instr_sll). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22494 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13983_Y, Q = \soc_I.cpu_I.instr_sub, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23766 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1051$3725_Y, Q = \soc_I.cpu_I.instr_sub). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22493 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13987_Y, Q = \soc_I.cpu_I.instr_add, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23768 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1050$3721_Y, Q = \soc_I.cpu_I.instr_add). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22492 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1048$3717_Y, Q = \soc_I.cpu_I.instr_srai). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22491 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1047$3713_Y, Q = \soc_I.cpu_I.instr_srli). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22490 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1046$3709_Y, Q = \soc_I.cpu_I.instr_slli). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22489 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13997_Y, Q = \soc_I.cpu_I.instr_andi, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23773 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1044$3705_Y, Q = \soc_I.cpu_I.instr_andi). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22488 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14001_Y, Q = \soc_I.cpu_I.instr_ori, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23775 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1043$3703_Y, Q = \soc_I.cpu_I.instr_ori). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22487 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14005_Y, Q = \soc_I.cpu_I.instr_xori, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23777 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1042$3701_Y, Q = \soc_I.cpu_I.instr_xori). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22486 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14009_Y, Q = \soc_I.cpu_I.instr_sltiu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23779 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1041$3699_Y, Q = \soc_I.cpu_I.instr_sltiu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22485 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14013_Y, Q = \soc_I.cpu_I.instr_slti, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23781 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1040$3697_Y, Q = \soc_I.cpu_I.instr_slti). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22484 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14017_Y, Q = \soc_I.cpu_I.instr_addi, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23783 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1039$3695_Y, Q = \soc_I.cpu_I.instr_addi). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22483 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1037$3693_Y, Q = \soc_I.cpu_I.instr_sw). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22482 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1036$3691_Y, Q = \soc_I.cpu_I.instr_sh). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22481 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1035$3689_Y, Q = \soc_I.cpu_I.instr_sb). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22480 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1033$3687_Y, Q = \soc_I.cpu_I.instr_lhu). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22479 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1032$3685_Y, Q = \soc_I.cpu_I.instr_lbu). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22478 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1031$3683_Y, Q = \soc_I.cpu_I.instr_lw). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22477 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1030$3681_Y, Q = \soc_I.cpu_I.instr_lh). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22476 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1029$3679_Y, Q = \soc_I.cpu_I.instr_lb). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22475 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14037_Y, Q = \soc_I.cpu_I.instr_bgeu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23793 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1027$3677_Y, Q = \soc_I.cpu_I.instr_bgeu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22474 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14041_Y, Q = \soc_I.cpu_I.instr_bltu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23795 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1026$3675_Y, Q = \soc_I.cpu_I.instr_bltu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22473 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14045_Y, Q = \soc_I.cpu_I.instr_bge, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23797 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1025$3673_Y, Q = \soc_I.cpu_I.instr_bge). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22472 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14049_Y, Q = \soc_I.cpu_I.instr_blt, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23799 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1024$3671_Y, Q = \soc_I.cpu_I.instr_blt). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22471 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14053_Y, Q = \soc_I.cpu_I.instr_bne, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23801 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1023$3669_Y, Q = \soc_I.cpu_I.instr_bne). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22470 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14057_Y, Q = \soc_I.cpu_I.instr_beq, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23803 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1022$3667_Y, Q = \soc_I.cpu_I.instr_beq). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22469 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:852$3599_Y, Q = \soc_I.cpu_I.instr_jalr). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22468 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:851$3596_Y, Q = \soc_I.cpu_I.instr_jal). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22467 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:850$3595_Y, Q = \soc_I.cpu_I.instr_auipc). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22466 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:849$3594_Y, Q = \soc_I.cpu_I.instr_lui). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22455 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12771_Y, Q = \soc_I.cpu_I.latched_rd, rval = 5'00010). Adding EN signal on $auto$opt_dff.cc:702:run$23809 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12771_Y, Q = \soc_I.cpu_I.latched_rd). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22454 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12797_Y, Q = \soc_I.cpu_I.latched_is_lb, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23817 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12797_Y, Q = \soc_I.cpu_I.latched_is_lb). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22453 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12810_Y, Q = \soc_I.cpu_I.latched_is_lh, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23827 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12810_Y, Q = \soc_I.cpu_I.latched_is_lh). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22452 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12823_Y, Q = \soc_I.cpu_I.latched_is_lu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23837 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12823_Y, Q = \soc_I.cpu_I.latched_is_lu). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22450 ($dff) from module top (D = \soc_I.cpu_I.compressed_instr, Q = \soc_I.cpu_I.latched_compr). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22449 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12868_Y, Q = \soc_I.cpu_I.latched_branch, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23850 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12868_Y, Q = \soc_I.cpu_I.latched_branch). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22448 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12904_Y, Q = \soc_I.cpu_I.latched_stalu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23854 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12904_Y, Q = \soc_I.cpu_I.latched_stalu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22447 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12911_Y, Q = \soc_I.cpu_I.latched_store, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23862 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12911_Y, Q = \soc_I.cpu_I.latched_store). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22436 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12537_Y, Q = \soc_I.cpu_I.decoder_pseudo_trigger, rval = 1'0). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22433 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13175_Y, Q = \soc_I.cpu_I.mem_do_wdata, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23869 ($sdff) from module top (D = 1'0, Q = \soc_I.cpu_I.mem_do_wdata). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22432 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13179_Y, Q = \soc_I.cpu_I.mem_do_rdata, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23871 ($sdff) from module top (D = 1'0, Q = \soc_I.cpu_I.mem_do_rdata). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22431 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13250_Y, Q = \soc_I.cpu_I.mem_do_rinst, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23873 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13250_Y, Q = \soc_I.cpu_I.mem_do_rinst). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22430 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13275_Y, Q = \soc_I.cpu_I.mem_do_prefetch, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23887 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1552$3970_Y, Q = \soc_I.cpu_I.mem_do_prefetch). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22423 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12670_Y, Q = \soc_I.cpu_I.reg_out, rval = 1024). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22422 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13377_Y, Q = \soc_I.cpu_I.reg_op2). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22421 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13400_Y [31], Q = \soc_I.cpu_I.reg_op1 [31]). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22421 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13400_Y [30:0], Q = \soc_I.cpu_I.reg_op1 [30:0]). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22420 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12012_Y, Q = \soc_I.cpu_I.reg_next_pc [31:2], rval = 30'000000000000000000000000000000). Adding EN signal on $auto$opt_dff.cc:702:run$23931 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12001_Y, Q = \soc_I.cpu_I.reg_next_pc [31:2]). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22419 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13448_Y, Q = \soc_I.cpu_I.reg_pc [31:2], rval = 30'000000000000000000000000000000). Adding EN signal on $auto$opt_dff.cc:702:run$23933 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$3\current_pc[31:0] [31:2], Q = \soc_I.cpu_I.reg_pc [31:2]). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22412 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12753_Y, Q = \soc_I.cpu_I.trap, rval = 1'0). Adding SRST signal on $flatten\soc_I.\bridge_I.$procdff$22381 ($dff) from module top (D = \soc_I.bridge_I.wb_rdata_or, Q = \soc_I.bridge_I.wb_rdata_reg, rval = 0). Adding SRST signal on $flatten\soc_I.\bram_I.$procdff$22596 ($dff) from module top (D = 8'xxxxxxxx, Q = $flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3323_DATA [31:24], rval = 8'00000000). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$23937 ($sdff) from module top. Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$23937 ($sdff) from module top. Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$23937 ($sdff) from module top. Setting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$23937 ($sdff) from module top. Setting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$23937 ($sdff) from module top. Setting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$23937 ($sdff) from module top. Setting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$23937 ($sdff) from module top. Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$23937 ($sdff) from module top. Adding SRST signal on $flatten\soc_I.\bram_I.$procdff$22593 ($dff) from module top (D = 16'xxxxxxxxxxxxxxxx, Q = $flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3322_DATA [31:16], rval = 16'0000000000000000). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$23938 ($sdff) from module top. Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$23938 ($sdff) from module top. Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$23938 ($sdff) from module top. Setting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$23938 ($sdff) from module top. Setting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$23938 ($sdff) from module top. Setting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$23938 ($sdff) from module top. Setting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$23938 ($sdff) from module top. Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$23938 ($sdff) from module top. Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$23938 ($sdff) from module top. Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$23938 ($sdff) from module top. Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$23938 ($sdff) from module top. Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$23938 ($sdff) from module top. Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$23938 ($sdff) from module top. Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$23938 ($sdff) from module top. Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$23938 ($sdff) from module top. Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$23938 ($sdff) from module top. Adding SRST signal on $flatten\soc_I.\bram_I.$procdff$22590 ($dff) from module top (D = 24'xxxxxxxxxxxxxxxxxxxxxxxx, Q = $flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3321_DATA [31:8], rval = 24'000000000000000000000000). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$23939 ($sdff) from module top. Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$23939 ($sdff) from module top. Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$23939 ($sdff) from module top. Setting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$23939 ($sdff) from module top. Setting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$23939 ($sdff) from module top. Setting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$23939 ($sdff) from module top. Setting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$23939 ($sdff) from module top. Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$23939 ($sdff) from module top. Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$23939 ($sdff) from module top. Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$23939 ($sdff) from module top. Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$23939 ($sdff) from module top. Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$23939 ($sdff) from module top. Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$23939 ($sdff) from module top. Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$23939 ($sdff) from module top. Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$23939 ($sdff) from module top. Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$23939 ($sdff) from module top. Setting constant 0-bit at position 16 on $auto$opt_dff.cc:702:run$23939 ($sdff) from module top. Setting constant 0-bit at position 17 on $auto$opt_dff.cc:702:run$23939 ($sdff) from module top. Setting constant 0-bit at position 18 on $auto$opt_dff.cc:702:run$23939 ($sdff) from module top. Setting constant 0-bit at position 19 on $auto$opt_dff.cc:702:run$23939 ($sdff) from module top. Setting constant 0-bit at position 20 on $auto$opt_dff.cc:702:run$23939 ($sdff) from module top. Setting constant 0-bit at position 21 on $auto$opt_dff.cc:702:run$23939 ($sdff) from module top. Setting constant 0-bit at position 22 on $auto$opt_dff.cc:702:run$23939 ($sdff) from module top. Setting constant 0-bit at position 23 on $auto$opt_dff.cc:702:run$23939 ($sdff) from module top. Adding SRST signal on $flatten\misc_I.\dfu_I.\btn_flt_I.$procdff$22236 ($dff) from module top (D = $flatten\misc_I.\dfu_I.\btn_flt_I.$procmux$5401_Y, Q = \misc_I.dfu_I.btn_flt_I.state, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23940 ($sdff) from module top (D = 1'1, Q = \misc_I.dfu_I.btn_flt_I.state). Adding EN signal on $flatten\misc_I.\dfu_I.$procdff$22407 ($adff) from module top (D = $flatten\misc_I.\dfu_I.$procmux$11982_Y, Q = \misc_I.dfu_I.wb_sel). Adding EN signal on $flatten\misc_I.\dfu_I.$procdff$22406 ($adff) from module top (D = $flatten\misc_I.\dfu_I.$procmux$11987_Y, Q = \misc_I.dfu_I.rst_req). Adding SRST signal on $flatten\misc_I.$procdff$22283 ($dff) from module top (D = $flatten\misc_I.$eq$/build/gateware/e1-tracer/rtl/misc.v:76$1591_Y, Q = \misc_I.bus_we_tick_sel, rval = 1'0). Adding SRST signal on $flatten\misc_I.$procdff$22282 ($dff) from module top (D = $flatten\misc_I.$eq$/build/gateware/e1-tracer/rtl/misc.v:75$1590_Y, Q = \misc_I.bus_we_boot, rval = 1'0). Adding SRST signal on $flatten\misc_I.$procdff$22281 ($dff) from module top (D = $flatten\misc_I.$procmux$11419_Y, Q = \misc_I.wb_rdata, rval = 0). Adding EN signal on $flatten\misc_I.$procdff$22280 ($dff) from module top (D = \soc_I.cpu_I.mem_wdata [17:16], Q = \misc_I.tick_e1_sel[1]). Adding EN signal on $flatten\misc_I.$procdff$22279 ($dff) from module top (D = \soc_I.cpu_I.mem_wdata [1:0], Q = \misc_I.tick_e1_sel[0]). Adding EN signal on $flatten\misc_I.$procdff$22278 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [2], Q = \misc_I.boot_now). Adding EN signal on $flatten\misc_I.$procdff$22277 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [1:0], Q = \misc_I.boot_sel). 73.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 433 unused cells and 509 unused wires. <suppressed ~436 debug messages> 73.12.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~19 debug messages> 73.12.9. Rerunning OPT passes. (Maybe there is more to do..) 73.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~164 debug messages> 73.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 73.12.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~69 debug messages> Removed a total of 23 cells. 73.12.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$23849 ($dffe) from module top. 73.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 27 unused wires. <suppressed ~2 debug messages> 73.12.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~1 debug messages> 73.12.16. Rerunning OPT passes. (Maybe there is more to do..) 73.12.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~163 debug messages> 73.12.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 73.12.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.12.20. Executing OPT_DFF pass (perform DFF optimizations). 73.12.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 1 unused wires. <suppressed ~1 debug messages> 73.12.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.12.23. Rerunning OPT passes. (Maybe there is more to do..) 73.12.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~163 debug messages> 73.12.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 73.12.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.12.27. Executing OPT_DFF pass (perform DFF optimizations). 73.12.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 73.12.29. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.12.30. Finished OPT passes. (There is nothing left to do.) 73.13. Executing WREDUCE pass (reducing word size of cells). Removed top 24 address bits (of 32) from memory init port top.$flatten\soc_I.\bram_I.$meminit$\mem$/build/gateware/common/rtl/soc_bram.v:0$3347 (soc_I.bram_I.mem). Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23354 ($eq). Removed top 2 bits (of 4) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$23693 ($ne). Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23323 ($eq). Removed top 2 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22890 ($eq). Removed top 2 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22886 ($eq). Removed top 1 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22894 ($eq). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$23718 ($ne). Removed top 2 bits (of 3) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$23714 ($ne). Removed top 3 bits (of 5) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$23883 ($ne). Removed top 1 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22919 ($eq). Removed top 3 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22915 ($eq). Removed top 1 bits (of 6) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23066 ($eq). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$23490 ($ne). Removed top 2 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22923 ($eq). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$23494 ($ne). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$23492 ($ne). Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23254 ($eq). Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23258 ($eq). Removed top 2 bits (of 4) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$23369 ($ne). Removed top 3 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22860 ($eq). Removed top 2 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23293 ($eq). Removed top 3 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22820 ($eq). Removed top 1 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22824 ($eq). Removed top 1 bits (of 6) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23053 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\e1_buf_I.$eq$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:233$4983 ($eq). Removed top 3 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5001 ($shl). Removed top 3 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_buf_I.$and$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5003 ($and). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\e1_buf_I.$ne$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:253$5020 ($ne). Removed top 2 bits (of 4) from mux cell top.$flatten\soc_I.\e1_buf_I.$procmux$14735 ($mux). Removed cell top.$flatten\soc_I.\e1_buf_I.$procmux$14820 ($mux). Removed top 1 bits (of 2) from mux cell top.$flatten\soc_I.\e1_buf_I.$procmux$14866 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\e1_I.$eq$/build/gateware/cores/no2e1//rtl/e1_wb.v:148$5039 ($eq). Removed top 30 bits (of 32) from mux cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$9 ($mux). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.\crc_I.$xor$/build/gateware/cores/no2e1//rtl/e1_crc4.v:40$11 ($xor). Removed top 1 bits (of 16) from FF cell top.$auto$opt_dff.cc:764:run$23638 ($sdffe). Removed top 1 bits (of 7) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23044 ($eq). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$125 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$121 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$117 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$113 ($add). Removed top 3 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.\crc_I.$and$/build/gateware/cores/no2e1//rtl/e1_crc4.v:35$3 ($and). Removed top 2 bits (of 6) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:284$59 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$54 ($sub). Removed top 25 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$54 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$40 ($add). Removed top 28 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$40 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$35 ($add). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$35 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$30 ($add). Removed top 29 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$30 ($add). Removed top 1 bits (of 2) from FF cell top.$auto$opt_dff.cc:764:run$23685 ($adffe). Removed top 2 bits (of 6) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:135$17 ($eq). Removed top 30 bits (of 32) from mux cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$9 ($mux). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.\crc_I.$xor$/build/gateware/cores/no2e1//rtl/e1_crc4.v:40$11 ($xor). Removed top 1 bits (of 16) from FF cell top.$auto$opt_dff.cc:764:run$23553 ($sdffe). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$125 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$121 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$117 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$113 ($add). Removed top 3 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.\crc_I.$and$/build/gateware/cores/no2e1//rtl/e1_crc4.v:35$3 ($and). Removed top 2 bits (of 6) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:284$59 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$54 ($sub). Removed top 25 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$54 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$40 ($add). Removed top 28 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$40 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$35 ($add). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$35 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$30 ($add). Removed top 29 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$30 ($add). Removed top 1 bits (of 2) from FF cell top.$auto$opt_dff.cc:764:run$23600 ($adffe). Removed top 2 bits (of 6) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:135$17 ($eq). Removed top 16 bits (of 32) from port B of cell top.$flatten\soc_I.\iobuf_I.$or$/build/gateware/common/rtl/soc_iobuf.v:250$2531 ($or). Removed top 1 bits (of 2) from FF cell top.$auto$opt_dff.cc:764:run$23504 ($dffe). Removed cell top.$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5391 ($mux). Removed cell top.$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5388 ($mux). Removed cell top.$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5384 ($mux). Removed top 20 bits (of 32) from mux cell top.$flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:176$4804 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$4803 ($sub). Removed top 19 bits (of 32) from port Y of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$4803 ($sub). Removed top 23 bits (of 32) from mux cell top.$flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:159$4795 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$4793 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$4793 ($add). Removed top 18 bits (of 32) from mux cell top.$flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:155$4791 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$4789 ($add). Removed top 18 bits (of 32) from port Y of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$4789 ($add). Removed top 3 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5457_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5456_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5455_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5454_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5453_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5452_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5451_CMP0 ($eq). Removed top 3 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5440_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5439_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5438_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5437_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5436_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5435_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5434_CMP0 ($eq). Removed cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11543 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11527_CMP0 ($eq). Removed top 29 bits (of 32) from mux cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1508 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1506 ($add). Removed top 29 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1506 ($add). Removed top 30 bits (of 32) from port A of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1502 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1502 ($add). Removed top 29 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1502 ($add). Removed top 16 bits (of 32) from mux cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.\crc_16_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4708 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1568 ($sub). Removed top 21 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1568 ($sub). Removed top 21 bits (of 32) from port A of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1568 ($sub). Removed top 21 bits (of 32) from mux cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1567 ($mux). Removed top 1 bits (of 8) from mux cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:172$1551 ($mux). Removed top 28 bits (of 32) from port A of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1545 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1545 ($sub). Removed top 28 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1545 ($sub). Removed top 1 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22989 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:137$1532 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11921_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11920_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11919_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11906_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11895_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11894_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11893_CMP0 ($eq). Removed top 3 bits (of 4) from mux cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11886 ($mux). Removed top 2 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11878_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11877_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11876_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:98$1287 ($eq). Removed top 16 bits (of 32) from mux cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.\crc_16_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4708 ($mux). Removed top 1 bits (of 16) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.\crc_16_I.$eq$/build/gateware/cores/no2usb//rtl/usb_crc.v:44$4711 ($eq). Removed top 29 bits (of 32) from mux cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.\crc_5_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4721 ($mux). Removed top 2 bits (of 5) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.\crc_5_I.$xor$/build/gateware/cores/no2usb//rtl/usb_crc.v:38$4722 ($xor). Removed top 2 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22985 ($eq). Removed top 2 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22981 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:313$1361 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:311$1357 ($eq). Removed top 3 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:308$1351 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:307$1350 ($eq). Removed top 29 bits (of 32) from port A of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1336 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1336 ($sub). Removed top 28 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1336 ($sub). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$procmux$11608_CMP0 ($eq). Removed top 1 bits (of 4) from mux cell top.$flatten\soc_I.\usb_I.\trans_I.$procmux$11585 ($mux). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$procmux$11583_CMP0 ($eq). Removed cell top.$flatten\soc_I.\usb_I.\trans_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_trans.v:375$1463 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:303$1445 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:207$1423 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:206$1422 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:205$1421 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:204$1420 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:203$1419 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:202$1418 ($eq). Removed top 3 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:201$1417 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:179$1416 ($add). Removed top 24 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:179$1416 ($add). Removed top 2 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22828 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\uart_I.$eq$/build/gateware/cores/no2misc//rtl/uart_wb.v:172$3294 ($eq). Removed top 24 bits (of 32) from mux cell top.$flatten\soc_I.\uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3315 ($mux). Removed top 1 bits (of 5) from FF cell top.$auto$opt_dff.cc:764:run$23477 ($adffe). Removed top 1 bits (of 13) from mux cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$procmux$5486 ($mux). Removed cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$procmux$5475 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5264 ($sub). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5264 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5261 ($sub). Removed top 19 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5261 ($sub). Removed cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$procmux$11928 ($mux). Removed cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$procmux$11930 ($mux). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$procdff$22367 ($dff). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4532 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4532 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4530 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4530 ($add). Removed top 1 bits (of 10) from port B of cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$eq$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:81$4519 ($eq). Removed top 2 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22839 ($eq). Removed cell top.$flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procmux$5514 ($mux). Removed top 1 bits (of 2) from mux cell top.$flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procmux$5532 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5246 ($sub). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5246 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5243 ($sub). Removed top 19 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5243 ($sub). Removed top 21 bits (of 32) from port A of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5242 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5242 ($sub). Removed top 20 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5242 ($sub). Removed cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$procmux$11928 ($mux). Removed cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$procmux$11930 ($mux). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$procdff$22367 ($dff). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4532 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4532 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4530 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4530 ($add). Removed top 1 bits (of 10) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$eq$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:81$4519 ($eq). Removed cell top.$flatten\soc_I.\bram_I.$procmux$14872 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$14874 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$14878 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$14880 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$14884 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$14886 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$14890 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$14892 ($mux). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\bram_I.$procdff$22591 ($dff). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\bram_I.$procdff$22594 ($dff). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\bram_I.$procdff$22597 ($dff). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\bram_I.$procdff$22600 ($dff). Removed top 24 bits (of 32) from port A of cell top.$flatten\soc_I.\bridge_I.$or$/build/gateware/common/rtl/soc_picorv32_bridge.v:152$5086 ($or). Removed top 16 bits (of 32) from port B of cell top.$flatten\soc_I.\bridge_I.$or$/build/gateware/common/rtl/soc_picorv32_bridge.v:152$5088 ($or). Removed top 16 bits (of 32) from port B of cell top.$flatten\soc_I.\bridge_I.$or$/build/gateware/common/rtl/soc_picorv32_bridge.v:152$5092 ($or). Removed top 24 bits (of 32) from port B of cell top.$flatten\soc_I.\bridge_I.$or$/build/gateware/common/rtl/soc_picorv32_bridge.v:152$5094 ($or). Removed top 3 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5098 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5099 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5100 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5101 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5102 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5103 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5104 ($eq). Removed top 3 bits (of 4) from port A of cell top.$flatten\soc_I.\cpu_I.$shl$/build/gateware/common/rtl/picorv32.v:403$3516 ($shl). Removed top 30 bits (of 32) from mux cell top.$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:601$3575 ($mux). Removed top 1 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:849$3594 ($eq). Removed top 2 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:850$3595 ($eq). Removed top 5 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:857$3609 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:858$3610 ($eq). Removed top 2 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:859$3611 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:860$3612 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1023$3668 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1031$3682 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1041$3698 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1048$3716 ($eq). Removed top 29 bits (of 32) from port B of cell top.$flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1296$3889 ($add). Removed top 29 bits (of 32) from port B of cell top.$flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1539$3966 ($add). Removed top 29 bits (of 32) from port B of cell top.$flatten\soc_I.\cpu_I.$ge$/build/gateware/common/rtl/picorv32.v:1814$4017 ($ge). Removed top 29 bits (of 32) from port B of cell top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4025 ($sub). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4025 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4032 ($sub). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4032 ($sub). Removed top 3 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22955 ($eq). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12399 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12402 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12666 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12668 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12673 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12723 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12743 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12766 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12793 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12795 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12806 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12808 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12819 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12821 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12899 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13187 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13248 ($mux). Removed top 2 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22934 ($eq). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13396 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13398 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13404 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13406 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13421 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13542 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14384 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14388 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14394 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\cpu_I.$procmux$14396_CMP0 ($eq). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14397 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14403 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14437 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14447 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14449 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14453 ($mux). Removed top 24 bits (of 32) from mux cell top.$flatten\soc_I.\cpu_I.$procmux$14680 ($pmux). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\cpu_I.$procmux$14683_CMP0 ($eq). Removed top 16 bits (of 32) from mux cell top.$flatten\soc_I.\cpu_I.$procmux$14689 ($pmux). Removed top 11 bits (of 31) from FF cell top.$auto$opt_dff.cc:764:run$23743 ($dffe). Removed top 25 bits (of 26) from port B of cell top.$flatten\misc_I.\dfu_I.$add$/build/gateware/common/rtl/dfu_helper.v:113$4096 ($add). Removed top 1 bits (of 4) from port B of cell top.$flatten\misc_I.$procmux$11421_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\misc_I.$procmux$11420_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\misc_I.$shiftx$/build/gateware/e1-tracer/rtl/misc.v:0$1594 ($shiftx). Removed top 1 bits (of 4) from port B of cell top.$flatten\misc_I.$eq$/build/gateware/e1-tracer/rtl/misc.v:76$1591 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\sys_mgr_I.$add$/build/gateware/e1-tracer/rtl/sysmgr.v:85$1601 ($add). Removed top 28 bits (of 32) from port Y of cell top.$flatten\sys_mgr_I.$add$/build/gateware/e1-tracer/rtl/sysmgr.v:85$1601 ($add). Removed top 1 bits (of 2) from port A of cell top.$flatten\soc_I.\e1_buf_I.$eq$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:233$4983 ($eq). Removed top 1 bits (of 2) from port A of cell top.$flatten\soc_I.\e1_buf_I.$eq$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:241$4986 ($eq). Removed top 1 bits (of 2) from port A of cell top.$flatten\soc_I.\e1_buf_I.$eq$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:241$4989 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5000 ($shl). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5001 ($shl). Removed top 2 bits (of 4) from port Y of cell top.$flatten\soc_I.\e1_buf_I.$or$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5004 ($or). Removed top 2 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_buf_I.$or$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5004 ($or). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\e1_buf_I.$or$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5004 ($or). Removed top 2 bits (of 4) from port Y of cell top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5001 ($shl). Removed top 2 bits (of 4) from port Y of cell top.$flatten\soc_I.\e1_buf_I.$and$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5003 ($and). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\e1_buf_I.$and$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5003 ($and). Removed top 2 bits (of 4) from port Y of cell top.$flatten\soc_I.\e1_buf_I.$not$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5002 ($not). Removed top 2 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_buf_I.$not$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5002 ($not). Removed top 2 bits (of 4) from port Y of cell top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5000 ($shl). Removed top 24 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3321_EN[31:0]$3328. Removed top 16 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3322_DATA[31:0]$3330. Removed top 8 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3323_DATA[31:0]$3333. Removed top 8 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3323_EN[31:0]$3334. Removed top 24 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3321_DATA. Removed top 16 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3322_DATA. Removed top 8 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3323_DATA. Removed top 16 bits (of 32) from wire top.$flatten\soc_I.\cpu_I.$2\mem_rdata_word[31:0]. Removed top 24 bits (of 32) from wire top.$flatten\soc_I.\cpu_I.$3\mem_rdata_word[31:0]. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4025_Y. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4032_Y. Removed top 29 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$30_Y. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$35_Y. Removed top 28 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$40_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$113_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$117_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$121_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$125_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$9_Y. Removed top 3 bits (of 16) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bus_rd_rx_status. Removed top 29 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$30_Y. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$35_Y. Removed top 28 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$40_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$113_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$117_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$121_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$125_Y. Removed top 25 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$54_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$9_Y. Removed top 3 bits (of 16) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bus_rd_rx_status. Removed top 2 bits (of 4) from wire top.$flatten\soc_I.\e1_buf_I.$and$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5003_Y. Removed top 2 bits (of 4) from wire top.$flatten\soc_I.\e1_buf_I.$not$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5002_Y. Removed top 2 bits (of 4) from wire top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5000_Y. Removed top 2 bits (of 4) from wire top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5001_Y. Removed top 18 bits (of 32) from wire top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$4789_Y. Removed top 23 bits (of 32) from wire top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$4793_Y. Removed top 19 bits (of 32) from wire top.$flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$4803_Y. Removed top 23 bits (of 32) from wire top.$flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:159$4795_Y. Removed top 20 bits (of 32) from wire top.$flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:176$4804_Y. Removed top 19 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5242_Y. Removed top 19 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5243_Y. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5246_Y. Removed top 23 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4532_Y. Removed top 1 bits (of 13) from wire top.$flatten\soc_I.\uart_I.\uart_tx_I.$0\div_cnt[12:0]. Removed top 1 bits (of 10) from wire top.$flatten\soc_I.\uart_I.\uart_tx_I.$procmux$5475_Y. Removed top 19 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5261_Y. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5264_Y. Removed top 23 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4532_Y. Removed top 23 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4530_Y. Removed top 3 bits (of 4) from wire top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11886_Y. Removed top 28 bits (of 32) from wire top.$flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1336_Y. Removed top 29 bits (of 32) from wire top.$flatten\soc_I.\usb_I.\rx_pkt_I.\crc_5_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4721_Y. Removed top 1 bits (of 4) from wire top.$flatten\soc_I.\usb_I.\trans_I.$procmux$11585_Y. Removed top 29 bits (of 32) from wire top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1506_Y. Removed top 29 bits (of 32) from wire top.$flatten\soc_I.\usb_I.\tx_ll_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1508_Y. Removed top 28 bits (of 32) from wire top.$flatten\sys_mgr_I.$add$/build/gateware/e1-tracer/rtl/sysmgr.v:85$1601_Y. Removed top 8 bits (of 32) from wire top.wb_rdata[0]. Removed top 24 bits (of 32) from wire top.wb_rdata[1]. Removed top 24 bits (of 64) from wire top.wb_rdata_flat. 73.14. Executing PEEPOPT pass (run peephole optimizers). 73.15. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 121 unused wires. <suppressed ~1 debug messages> 73.16. Executing SHARE pass (SAT-based resource sharing). 73.17. Executing TECHMAP pass (map to technology primitives). 73.17.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/cmp2lut.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 73.17.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~88 debug messages> 73.18. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~5 debug messages> 73.19. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 4 unused wires. <suppressed ~1 debug messages> 73.20. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module top: creating $macc model for $flatten\misc_I.\dfu_I.$add$/build/gateware/common/rtl/dfu_helper.v:113$4096 ($add). creating $macc model for $flatten\misc_I.\dfu_I.\btn_flt_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4734 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1219$4081 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1296$3889 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1539$3966 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1548$3967 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1785$4011 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1848$4036 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1219$4080 ($sub). creating $macc model for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4025 ($sub). creating $macc model for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4032 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$30 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$35 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$40 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$113 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$117 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$121 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$125 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$54 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$30 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$35 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$40 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$113 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$117 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$121 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$125 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$54 ($sub). creating $macc model for $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$4789 ($add). creating $macc model for $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$4793 ($add). creating $macc model for $flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$4803 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5242 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5243 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5246 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4501 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4532 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4515 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4530 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5261 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5264 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4532 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4515 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4530 ($add). creating $macc model for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:540$3270 ($add). creating $macc model for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:623$3251 ($add). creating $macc model for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:632$3255 ($add). creating $macc model for $flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1336 ($sub). creating $macc model for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:179$1416 ($add). creating $macc model for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:415$1477 ($add). creating $macc model for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:429$1486 ($add). creating $macc model for $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:258$1433 ($sub). creating $macc model for $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:425$1483 ($sub). creating $macc model for $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1502 ($add). creating $macc model for $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1506 ($add). creating $macc model for $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1545 ($sub). creating $macc model for $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1568 ($sub). creating $macc model for $flatten\sys_mgr_I.$add$/build/gateware/e1-tracer/rtl/sysmgr.v:85$1601 ($add). creating $alu model for $macc $flatten\sys_mgr_I.$add$/build/gateware/e1-tracer/rtl/sysmgr.v:85$1601. creating $alu model for $macc $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1568. creating $alu model for $macc $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1545. creating $alu model for $macc $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1506. creating $alu model for $macc $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1502. creating $alu model for $macc $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:425$1483. creating $alu model for $macc $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:258$1433. creating $alu model for $macc $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:429$1486. creating $alu model for $macc $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:415$1477. creating $alu model for $macc $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:179$1416. creating $alu model for $macc $flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1336. creating $alu model for $macc $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:632$3255. creating $alu model for $macc $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:623$3251. creating $alu model for $macc $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:540$3270. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4530. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4515. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4532. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5264. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5261. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4530. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4515. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4532. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4501. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5246. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5243. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5242. creating $alu model for $macc $flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$4803. creating $alu model for $macc $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$4793. creating $alu model for $macc $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$4789. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$54. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$125. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$121. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$117. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$113. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$40. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$35. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$30. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$54. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$125. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$121. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$117. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$113. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$40. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$35. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$30. creating $alu model for $macc $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4032. creating $alu model for $macc $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4025. creating $alu model for $macc $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1219$4080. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1848$4036. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1785$4011. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1548$3967. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1539$3966. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1296$3889. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1219$4081. creating $alu model for $macc $flatten\misc_I.\dfu_I.\btn_flt_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4734. creating $alu model for $macc $flatten\misc_I.\dfu_I.$add$/build/gateware/common/rtl/dfu_helper.v:113$4096. creating $alu model for $flatten\soc_I.\cpu_I.$ge$/build/gateware/common/rtl/picorv32.v:1814$4017 ($ge): new $alu creating $alu model for $flatten\soc_I.\cpu_I.$lt$/build/gateware/common/rtl/picorv32.v:1221$4084 ($lt): new $alu creating $alu model for $flatten\soc_I.\cpu_I.$lt$/build/gateware/common/rtl/picorv32.v:1222$4085 ($lt): new $alu creating $alu model for $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1220$4083 ($eq): merged with $flatten\soc_I.\cpu_I.$lt$/build/gateware/common/rtl/picorv32.v:1222$4085. creating $alu cell for $flatten\soc_I.\cpu_I.$ge$/build/gateware/common/rtl/picorv32.v:1814$4017: $auto$alumacc.cc:485:replace_alu$24013 creating $alu cell for $flatten\misc_I.\dfu_I.$add$/build/gateware/common/rtl/dfu_helper.v:113$4096: $auto$alumacc.cc:485:replace_alu$24022 creating $alu cell for $flatten\misc_I.\dfu_I.\btn_flt_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4734: $auto$alumacc.cc:485:replace_alu$24025 creating $alu cell for $flatten\soc_I.\cpu_I.$lt$/build/gateware/common/rtl/picorv32.v:1222$4085, $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1220$4083: $auto$alumacc.cc:485:replace_alu$24028 creating $alu cell for $flatten\soc_I.\cpu_I.$lt$/build/gateware/common/rtl/picorv32.v:1221$4084: $auto$alumacc.cc:485:replace_alu$24039 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1219$4081: $auto$alumacc.cc:485:replace_alu$24052 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1296$3889: $auto$alumacc.cc:485:replace_alu$24055 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1539$3966: $auto$alumacc.cc:485:replace_alu$24058 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1548$3967: $auto$alumacc.cc:485:replace_alu$24061 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1785$4011: $auto$alumacc.cc:485:replace_alu$24064 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1848$4036: $auto$alumacc.cc:485:replace_alu$24067 creating $alu cell for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1219$4080: $auto$alumacc.cc:485:replace_alu$24070 creating $alu cell for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4025: $auto$alumacc.cc:485:replace_alu$24073 creating $alu cell for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4032: $auto$alumacc.cc:485:replace_alu$24076 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$30: $auto$alumacc.cc:485:replace_alu$24079 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$35: $auto$alumacc.cc:485:replace_alu$24082 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$40: $auto$alumacc.cc:485:replace_alu$24085 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$113: $auto$alumacc.cc:485:replace_alu$24088 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$117: $auto$alumacc.cc:485:replace_alu$24091 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$121: $auto$alumacc.cc:485:replace_alu$24094 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$125: $auto$alumacc.cc:485:replace_alu$24097 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$54: $auto$alumacc.cc:485:replace_alu$24100 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$30: $auto$alumacc.cc:485:replace_alu$24103 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$35: $auto$alumacc.cc:485:replace_alu$24106 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$40: $auto$alumacc.cc:485:replace_alu$24109 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$113: $auto$alumacc.cc:485:replace_alu$24112 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$117: $auto$alumacc.cc:485:replace_alu$24115 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$121: $auto$alumacc.cc:485:replace_alu$24118 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$125: $auto$alumacc.cc:485:replace_alu$24121 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$54: $auto$alumacc.cc:485:replace_alu$24124 creating $alu cell for $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$4789: $auto$alumacc.cc:485:replace_alu$24127 creating $alu cell for $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$4793: $auto$alumacc.cc:485:replace_alu$24130 creating $alu cell for $flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$4803: $auto$alumacc.cc:485:replace_alu$24133 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5242: $auto$alumacc.cc:485:replace_alu$24136 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5243: $auto$alumacc.cc:485:replace_alu$24139 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5246: $auto$alumacc.cc:485:replace_alu$24142 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4501: $auto$alumacc.cc:485:replace_alu$24145 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4532: $auto$alumacc.cc:485:replace_alu$24148 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4515: $auto$alumacc.cc:485:replace_alu$24151 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4530: $auto$alumacc.cc:485:replace_alu$24154 creating $alu cell for $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5261: $auto$alumacc.cc:485:replace_alu$24157 creating $alu cell for $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5264: $auto$alumacc.cc:485:replace_alu$24160 creating $alu cell for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4532: $auto$alumacc.cc:485:replace_alu$24163 creating $alu cell for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4515: $auto$alumacc.cc:485:replace_alu$24166 creating $alu cell for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4530: $auto$alumacc.cc:485:replace_alu$24169 creating $alu cell for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:540$3270: $auto$alumacc.cc:485:replace_alu$24172 creating $alu cell for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:623$3251: $auto$alumacc.cc:485:replace_alu$24175 creating $alu cell for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:632$3255: $auto$alumacc.cc:485:replace_alu$24178 creating $alu cell for $flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1336: $auto$alumacc.cc:485:replace_alu$24181 creating $alu cell for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:179$1416: $auto$alumacc.cc:485:replace_alu$24184 creating $alu cell for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:415$1477: $auto$alumacc.cc:485:replace_alu$24187 creating $alu cell for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:429$1486: $auto$alumacc.cc:485:replace_alu$24190 creating $alu cell for $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:258$1433: $auto$alumacc.cc:485:replace_alu$24193 creating $alu cell for $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:425$1483: $auto$alumacc.cc:485:replace_alu$24196 creating $alu cell for $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1502: $auto$alumacc.cc:485:replace_alu$24199 creating $alu cell for $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1506: $auto$alumacc.cc:485:replace_alu$24202 creating $alu cell for $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1545: $auto$alumacc.cc:485:replace_alu$24205 creating $alu cell for $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1568: $auto$alumacc.cc:485:replace_alu$24208 creating $alu cell for $flatten\sys_mgr_I.$add$/build/gateware/e1-tracer/rtl/sysmgr.v:85$1601: $auto$alumacc.cc:485:replace_alu$24211 created 59 $alu and 0 $macc cells. 73.21. Executing OPT pass (performing simple optimizations). 73.21.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~2 debug messages> 73.21.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~12 debug messages> Removed a total of 4 cells. 73.21.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~151 debug messages> 73.21.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13400: { \soc_I.cpu_I.cpu_state [2] \soc_I.cpu_I.cpu_state [4] $auto$opt_reduce.cc:134:opt_mux$24215 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$14386: { $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:364$3484_Y $flatten\soc_I.\cpu_I.$procmux$14396_CMP $auto$opt_reduce.cc:134:opt_mux$24217 } Optimizing cells in module \top. Performed a total of 2 changes. 73.21.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~3 debug messages> Removed a total of 1 cells. 73.21.6. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 1-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$22599 ($dff) from module top. Setting constant 1-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$22599 ($dff) from module top. Setting constant 1-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$22599 ($dff) from module top. Setting constant 1-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$22599 ($dff) from module top. Setting constant 1-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$22599 ($dff) from module top. Setting constant 1-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$22599 ($dff) from module top. Setting constant 1-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$22599 ($dff) from module top. Setting constant 1-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$22599 ($dff) from module top. Setting constant 1-bit at position 8 on $flatten\soc_I.\bram_I.$procdff$22599 ($dff) from module top. Setting constant 1-bit at position 9 on $flatten\soc_I.\bram_I.$procdff$22599 ($dff) from module top. Setting constant 1-bit at position 10 on $flatten\soc_I.\bram_I.$procdff$22599 ($dff) from module top. Setting constant 1-bit at position 11 on $flatten\soc_I.\bram_I.$procdff$22599 ($dff) from module top. Setting constant 1-bit at position 12 on $flatten\soc_I.\bram_I.$procdff$22599 ($dff) from module top. Setting constant 1-bit at position 13 on $flatten\soc_I.\bram_I.$procdff$22599 ($dff) from module top. Setting constant 1-bit at position 14 on $flatten\soc_I.\bram_I.$procdff$22599 ($dff) from module top. Setting constant 1-bit at position 15 on $flatten\soc_I.\bram_I.$procdff$22599 ($dff) from module top. Setting constant 1-bit at position 16 on $flatten\soc_I.\bram_I.$procdff$22599 ($dff) from module top. Setting constant 1-bit at position 17 on $flatten\soc_I.\bram_I.$procdff$22599 ($dff) from module top. Setting constant 1-bit at position 18 on $flatten\soc_I.\bram_I.$procdff$22599 ($dff) from module top. Setting constant 1-bit at position 19 on $flatten\soc_I.\bram_I.$procdff$22599 ($dff) from module top. Setting constant 1-bit at position 20 on $flatten\soc_I.\bram_I.$procdff$22599 ($dff) from module top. Setting constant 1-bit at position 21 on $flatten\soc_I.\bram_I.$procdff$22599 ($dff) from module top. Setting constant 1-bit at position 22 on $flatten\soc_I.\bram_I.$procdff$22599 ($dff) from module top. Setting constant 1-bit at position 23 on $flatten\soc_I.\bram_I.$procdff$22599 ($dff) from module top. Setting constant 1-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$22596 ($dff) from module top. Setting constant 1-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$22596 ($dff) from module top. Setting constant 1-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$22596 ($dff) from module top. Setting constant 1-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$22596 ($dff) from module top. Setting constant 1-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$22596 ($dff) from module top. Setting constant 1-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$22596 ($dff) from module top. Setting constant 1-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$22596 ($dff) from module top. Setting constant 1-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$22596 ($dff) from module top. Setting constant 1-bit at position 8 on $flatten\soc_I.\bram_I.$procdff$22596 ($dff) from module top. Setting constant 1-bit at position 9 on $flatten\soc_I.\bram_I.$procdff$22596 ($dff) from module top. Setting constant 1-bit at position 10 on $flatten\soc_I.\bram_I.$procdff$22596 ($dff) from module top. Setting constant 1-bit at position 11 on $flatten\soc_I.\bram_I.$procdff$22596 ($dff) from module top. Setting constant 1-bit at position 12 on $flatten\soc_I.\bram_I.$procdff$22596 ($dff) from module top. Setting constant 1-bit at position 13 on $flatten\soc_I.\bram_I.$procdff$22596 ($dff) from module top. Setting constant 1-bit at position 14 on $flatten\soc_I.\bram_I.$procdff$22596 ($dff) from module top. Setting constant 1-bit at position 15 on $flatten\soc_I.\bram_I.$procdff$22596 ($dff) from module top. Setting constant 1-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$22593 ($dff) from module top. Setting constant 1-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$22593 ($dff) from module top. Setting constant 1-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$22593 ($dff) from module top. Setting constant 1-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$22593 ($dff) from module top. Setting constant 1-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$22593 ($dff) from module top. Setting constant 1-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$22593 ($dff) from module top. Setting constant 1-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$22593 ($dff) from module top. Setting constant 1-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$22593 ($dff) from module top. Adding SRST signal on $auto$opt_dff.cc:764:run$23721 ($dffe) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14439_Y, Q = \soc_I.cpu_I.mem_valid, rval = 1'0). Adding SRST signal on $auto$opt_dff.cc:764:run$23704 ($dffe) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14386_Y, Q = \soc_I.cpu_I.mem_state, rval = 2'00). Removing never-active SRST on $auto$opt_dff.cc:702:run$23513 ($sdffce) from module top. Removing never-active SRST on $auto$opt_dff.cc:702:run$23509 ($sdffce) from module top. Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$23470 ($sdff) from module top. Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$23470 ($sdff) from module top. Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$23470 ($sdff) from module top. Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$23470 ($sdff) from module top. Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$23470 ($sdff) from module top. Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$23470 ($sdff) from module top. Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$23470 ($sdff) from module top. Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$23470 ($sdff) from module top. Setting constant 0-bit at position 16 on $auto$opt_dff.cc:702:run$23470 ($sdff) from module top. Setting constant 0-bit at position 17 on $auto$opt_dff.cc:702:run$23470 ($sdff) from module top. Setting constant 0-bit at position 18 on $auto$opt_dff.cc:702:run$23470 ($sdff) from module top. Setting constant 0-bit at position 19 on $auto$opt_dff.cc:702:run$23470 ($sdff) from module top. Setting constant 0-bit at position 20 on $auto$opt_dff.cc:702:run$23470 ($sdff) from module top. Setting constant 0-bit at position 21 on $auto$opt_dff.cc:702:run$23470 ($sdff) from module top. Setting constant 0-bit at position 22 on $auto$opt_dff.cc:702:run$23470 ($sdff) from module top. Setting constant 0-bit at position 23 on $auto$opt_dff.cc:702:run$23470 ($sdff) from module top. 73.21.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 13 unused wires. <suppressed ~3 debug messages> 73.21.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.21.9. Rerunning OPT passes. (Maybe there is more to do..) 73.21.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~151 debug messages> 73.21.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 73.21.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.21.13. Executing OPT_DFF pass (perform DFF optimizations). 73.21.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 73.21.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.21.16. Finished OPT passes. (There is nothing left to do.) 73.22. Executing MEMORY pass. 73.22.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 73.22.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). Checking cell `$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3348' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3349' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3350' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3351' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5122' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5122' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\bram_I.$memrd$\mem$/build/gateware/common/rtl/soc_bram.v:32$3338' in module `\top': merged data $dff to cell. Checking cell `$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5121' in module `\top': merged data $dff to cell. Checking cell `$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5121' in module `\top': merged data $dff to cell. 73.22.3. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 18 unused cells and 21 unused wires. <suppressed ~19 debug messages> 73.22.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). Consolidating write ports of memory top.soc_I.bram_I.mem by address: New clock domain: posedge \misc_I.clk Port 0 ($flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3348) has addr \soc_I.cpu_I.mem_addr [9:2]. Active bits: 00000000000000000000000011111111 Port 1 ($flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3349) has addr \soc_I.cpu_I.mem_addr [9:2]. Active bits: 00000000000000001111111100000000 Merging port 0 into this one. Active bits: 00000000000000001111111111111111 Port 2 ($flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3350) has addr \soc_I.cpu_I.mem_addr [9:2]. Active bits: 00000000111111110000000000000000 Merging port 1 into this one. Active bits: 00000000111111111111111111111111 Port 3 ($flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3351) has addr \soc_I.cpu_I.mem_addr [9:2]. Active bits: 11111111000000000000000000000000 Merging port 2 into this one. Active bits: 11111111111111111111111111111111 73.22.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 73.22.6. Executing MEMORY_COLLECT pass (generating $mem cells). Collecting $memrd, $memwr and $meminit for memory `\soc_I.bram_I.mem' in module `\top': $flatten\soc_I.\bram_I.$meminit$\mem$/build/gateware/common/rtl/soc_bram.v:0$3347 ($meminit) $flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3351 ($memwr) $flatten\soc_I.\bram_I.$memrd$\mem$/build/gateware/common/rtl/soc_bram.v:32$3338 ($memrd) Collecting $memrd, $memwr and $meminit for memory `\soc_I.uart_I.uart_rx_fifo_I.ram_I.ram' in module `\top': $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5122 ($memwr) $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5121 ($memrd) Collecting $memrd, $memwr and $meminit for memory `\soc_I.uart_I.uart_tx_fifo_I.ram_I.ram' in module `\top': $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5122 ($memwr) $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5121 ($memrd) 73.23. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 73.24. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). Processing top.soc_I.bram_I.mem: Properties: ports=2 bits=8192 rports=1 wports=1 dbits=32 abits=8 words=256 Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=0 efficiency=100 Storing for later selection. Checking rule #2 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=256 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=768 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 2): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=3072 efficiency=25 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1792 dwaste=0 bwaste=3584 waste=3584 efficiency=12 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=3584 efficiency=12 Storing for later selection. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=256 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=768 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1792 dwaste=0 bwaste=3584 waste=3584 efficiency=12 Rule for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=256 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=768 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1792 dwaste=0 bwaste=3584 waste=3584 efficiency=12 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'max wports 0' not met. Selecting best of 4 rules: Efficiency for rule 4.3: efficiency=12, cells=16, acells=1 Efficiency for rule 4.2: efficiency=25, cells=8, acells=1 Efficiency for rule 4.1: efficiency=50, cells=4, acells=1 Efficiency for rule 1.1: efficiency=100, cells=2, acells=1 Selected rule 1.1 with efficiency 100. Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Creating $__ICE40_RAM4K_M0 cell at grid position <0 0 0>: soc_I.bram_I.mem.0.0.0 Creating $__ICE40_RAM4K_M0 cell at grid position <1 0 0>: soc_I.bram_I.mem.1.0.0 Processing top.soc_I.uart_I.uart_rx_fifo_I.ram_I.ram: Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512 Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #2 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=0 efficiency=100 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 2): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=3072 efficiency=25 Storing for later selection. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'max wports 0' not met. Selecting best of 4 rules: Efficiency for rule 4.3: efficiency=25, cells=4, acells=1 Efficiency for rule 4.2: efficiency=50, cells=2, acells=1 Efficiency for rule 4.1: efficiency=100, cells=1, acells=1 Efficiency for rule 1.1: efficiency=50, cells=2, acells=2 Selected rule 4.1 with efficiency 100. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Creating $__ICE40_RAM4K_M123 cell at grid position <0 0 0>: soc_I.uart_I.uart_rx_fifo_I.ram_I.ram.0.0.0 Processing top.soc_I.uart_I.uart_tx_fifo_I.ram_I.ram: Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512 Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #2 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=0 efficiency=100 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 2): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=3072 efficiency=25 Storing for later selection. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'max wports 0' not met. Selecting best of 4 rules: Efficiency for rule 4.3: efficiency=25, cells=4, acells=1 Efficiency for rule 4.2: efficiency=50, cells=2, acells=1 Efficiency for rule 4.1: efficiency=100, cells=1, acells=1 Efficiency for rule 1.1: efficiency=50, cells=2, acells=2 Selected rule 4.1 with efficiency 100. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Creating $__ICE40_RAM4K_M123 cell at grid position <0 0 0>: soc_I.uart_I.uart_tx_fifo_I.ram_I.ram.0.0.0 73.25. Executing TECHMAP pass (map to technology primitives). 73.25.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/brams_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ICE40_RAM4K'. Generating RTLIL representation for module `\$__ICE40_RAM4K_M0'. Generating RTLIL representation for module `\$__ICE40_RAM4K_M123'. Successfully finished Verilog frontend. 73.25.2. Continuing TECHMAP pass. Using template $paramod\$__ICE40_RAM4K_M123\CFG_ABITS=9\CFG_DBITS=8\CLKPOL2=1\CLKPOL3=1 for cells of type $__ICE40_RAM4K_M123. Using template $paramod$b9e8582c288289ac723b215129f56c6fb55d152a\$__ICE40_RAM4K_M0 for cells of type $__ICE40_RAM4K_M0. Using template $paramod$4db28c01ad2f8fb3d28d8b45acd344e29c76a5e2\$__ICE40_RAM4K_M0 for cells of type $__ICE40_RAM4K_M0. Using template $paramod$66c3fa288a62dc560ce3ddd26d81551ab195105f\$__ICE40_RAM4K for cells of type $__ICE40_RAM4K. Using template $paramod$604ec1e346c2dd44ad2f04f633da753d2abbf02c\$__ICE40_RAM4K for cells of type $__ICE40_RAM4K. Using template $paramod$7577afd8fd444532bbc3532c110d9d682708035f\$__ICE40_RAM4K for cells of type $__ICE40_RAM4K. No more expansions possible. <suppressed ~207 debug messages> 73.26. Executing ICE40_BRAMINIT pass. Processing soc_I.usb_I.trans_I.mc_rom_I : usb_trans_mc.hex 73.27. Executing OPT pass (performing simple optimizations). 73.27.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~232 debug messages> 73.27.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.27.3. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22424 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$0\reg_sh[4:0] [1:0], Q = \soc_I.cpu_I.reg_sh [1:0]). 73.27.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 38 unused cells and 196 unused wires. <suppressed ~50 debug messages> 73.27.5. Rerunning OPT passes. (Removed registers in this run.) 73.27.6. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.27.7. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.27.8. Executing OPT_DFF pass (perform DFF optimizations). 73.27.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 73.27.10. Finished fast OPT passes. 73.28. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). 73.29. Executing OPT pass (performing simple optimizations). 73.29.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.29.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.29.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 1/2 on $mux $flatten\soc_I.\e1_buf_I.$procmux$14829. dead port 1/2 on $mux $flatten\soc_I.\e1_buf_I.$procmux$14844. Removed 2 multiplexer ports. <suppressed ~137 debug messages> 73.29.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $techmap$techmap24241\soc_I.bram_I.mem.0.0.0.$reduce_or$/opt/fpga-toolchain/bin/../share/yosys/ice40/brams_map.v:222$24240: { $auto$wreduce.cc:454:run$23951 [7] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3322_EN[31:0]$3331 [15] } New input vector for $reduce_or cell $techmap$techmap24238\soc_I.bram_I.mem.1.0.0.$reduce_or$/opt/fpga-toolchain/bin/../share/yosys/ice40/brams_map.v:222$24237: { $auto$wreduce.cc:454:run$23954 [23] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3324_EN[31:0]$3337 [31] } Consolidated identical input bits for $mux cell $flatten\misc_I.\dfu_I.\btn_flt_I.$procmux$5413: Old ports: A=4'0000, B=4'1111, Y=$flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] New ports: A=1'0, B=1'1, Y=$flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] New connections: $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [3:1] = { $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] } Consolidated identical input bits for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12662: Old ports: A=\soc_I.cpu_I.mem_rdata_word, B={ \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15:0] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7:0] }, Y=$flatten\soc_I.\cpu_I.$procmux$12662_Y New ports: A=\soc_I.cpu_I.mem_rdata_word [31:8], B={ \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15:7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] }, Y=$flatten\soc_I.\cpu_I.$procmux$12662_Y [31:8] New connections: $flatten\soc_I.\cpu_I.$procmux$12662_Y [7:0] = \soc_I.cpu_I.mem_rdata_word [7:0] Consolidated identical input bits for $pmux cell $flatten\soc_I.\cpu_I.$procmux$14705: Old ports: A=\soc_I.cpu_I.reg_op2, B={ \soc_I.cpu_I.reg_op2 [15:0] \soc_I.cpu_I.reg_op2 [15:0] \soc_I.cpu_I.reg_op2 [7:0] \soc_I.cpu_I.reg_op2 [7:0] \soc_I.cpu_I.reg_op2 [7:0] \soc_I.cpu_I.reg_op2 [7:0] }, Y=\soc_I.cpu_I.mem_la_wdata New ports: A=\soc_I.cpu_I.reg_op2 [31:8], B={ \soc_I.cpu_I.reg_op2 [15:0] \soc_I.cpu_I.reg_op2 [15:0] \soc_I.cpu_I.reg_op2 [7:0] \soc_I.cpu_I.reg_op2 [7:0] }, Y=\soc_I.cpu_I.mem_la_wdata [31:8] New connections: \soc_I.cpu_I.mem_la_wdata [7:0] = \soc_I.cpu_I.reg_op2 [7:0] Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1192$3857: Old ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 2'00 }, B={ \soc_I.cpu_I.reg_out [31:1] 1'0 }, Y=\soc_I.cpu_I.next_pc New ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 1'0 }, B=\soc_I.cpu_I.reg_out [31:1], Y=\soc_I.cpu_I.next_pc [31:1] New connections: \soc_I.cpu_I.next_pc [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$3926: Old ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 2'00 }, B={ $auto$opt_expr.cc:205:group_cell_inputs$24306 1'0 }, Y=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$3926_Y New ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 1'0 }, B=$auto$opt_expr.cc:205:group_cell_inputs$24306, Y=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$3926_Y [31:1] New connections: $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$3926_Y [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1621$3979: Old ports: A={ \soc_I.cpu_I.reg_pc [31:2] 2'00 }, B=0, Y=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1621$3979_Y New ports: A=\soc_I.cpu_I.reg_pc [31:2], B=30'000000000000000000000000000000, Y=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1621$3979_Y [31:2] New connections: $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1621$3979_Y [1:0] = 2'00 Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:366$3500: Old ports: A={ \soc_I.cpu_I.reg_op1 [31:2] 2'00 }, B={ \soc_I.cpu_I.next_pc [31:2] 2'00 }, Y=\soc_I.cpu_I.mem_la_addr New ports: A=\soc_I.cpu_I.reg_op1 [31:2], B=\soc_I.cpu_I.next_pc [31:2], Y=\soc_I.cpu_I.mem_la_addr [31:2] New connections: \soc_I.cpu_I.mem_la_addr [1:0] = 2'00 Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3515: Old ports: A=4'0011, B=4'1100, Y=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3515_Y New ports: A=2'01, B=2'10, Y={ $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3515_Y [2] $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3515_Y [0] } New connections: { $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3515_Y [3] $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3515_Y [1] } = { $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3515_Y [2] $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3515_Y [0] } Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:601$3575: Old ports: A=2'11, B=2'00, Y=$flatten\soc_I.\cpu_I.$procmux$14392_Y New ports: A=1'1, B=1'0, Y=$flatten\soc_I.\cpu_I.$procmux$14392_Y [0] New connections: $flatten\soc_I.\cpu_I.$procmux$14392_Y [1] = $flatten\soc_I.\cpu_I.$procmux$14392_Y [0] Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5289: Old ports: A={ 3'000 $auto$wreduce.cc:454:run$23970 [12] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_out_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_out_I.rd_empty $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_in_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_in_I.rd_empty 6'000000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.aligned $auto$wreduce.cc:454:run$23970 [0] }, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_out_I.stage[1].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_out_I.data[1] [8:7] 6'000000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_out_I.data[1] [6:0] }, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5289_Y New ports: A={ 3'000 $auto$wreduce.cc:454:run$23970 [12] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_out_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_out_I.rd_empty $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_in_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_in_I.rd_empty 5'00000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.aligned $auto$wreduce.cc:454:run$23970 [0] }, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_out_I.stage[1].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_out_I.data[1] [8:7] 5'00000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.bd_rx_out_I.data[1] [6:0] }, Y={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5289_Y [15:8] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5289_Y [6:0] } New connections: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5289_Y [7] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.\rx_I.\deframer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$9: Old ports: A=2'00, B=2'11, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [1:0] New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [0] New connections: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [1] = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [0] Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5289: Old ports: A={ 3'000 $auto$wreduce.cc:454:run$23980 [12] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_out_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_out_I.rd_empty $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_in_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_in_I.rd_empty 6'000000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.aligned $auto$wreduce.cc:454:run$23980 [0] }, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_out_I.stage[1].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_out_I.data[1] [8:7] 6'000000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_out_I.data[1] [6:0] }, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5289_Y New ports: A={ 3'000 $auto$wreduce.cc:454:run$23980 [12] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_out_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_out_I.rd_empty $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_in_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_in_I.rd_empty 5'00000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.aligned $auto$wreduce.cc:454:run$23980 [0] }, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_out_I.stage[1].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_out_I.data[1] [8:7] 5'00000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.bd_rx_out_I.data[1] [6:0] }, Y={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5289_Y [15:8] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5289_Y [6:0] } New connections: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5289_Y [7] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.\rx_I.\deframer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$9: Old ports: A=2'00, B=2'11, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [1:0] New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [0] New connections: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [1] = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [0] Consolidated identical input bits for $mux cell $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:115$4771: Old ports: A=2'10, B=2'00, Y=$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5384_Y New ports: A=1'1, B=1'0, Y=$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5384_Y [1] New connections: $flatten\soc_I.\iobuf_I.\dma_I.$procmux$5384_Y [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:205$4821: Old ports: A=16'0000000000000000, B={ \soc_I.iobuf_I.dma_I.state [1] \soc_I.iobuf_I.dma_I.dir 1'0 \soc_I.iobuf_I.dma_I.len }, Y=\soc_I.iobuf_I.wb_rdata_dma [15:0] New ports: A=15'000000000000000, B={ \soc_I.iobuf_I.dma_I.state [1] \soc_I.iobuf_I.dma_I.dir \soc_I.iobuf_I.dma_I.len }, Y={ \soc_I.iobuf_I.wb_rdata_dma [15:14] \soc_I.iobuf_I.wb_rdata_dma [12:0] } New connections: \soc_I.iobuf_I.wb_rdata_dma [13] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$4889: Old ports: A=0, B={ \soc_I.e1_buf_I.wb_wdata_byte \soc_I.e1_buf_I.wb_wdata_byte \soc_I.e1_buf_I.wb_wdata_byte \soc_I.e1_buf_I.wb_wdata_byte }, Y=$flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$4889_Y New ports: A=8'00000000, B=\soc_I.e1_buf_I.wb_wdata_byte, Y=$flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$4889_Y [7:0] New connections: $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$4889_Y [31:8] = { $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$4889_Y [7:0] $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$4889_Y [7:0] $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$4889_Y [7:0] } Consolidated identical input bits for $mux cell $flatten\soc_I.\uart_I.\uart_tx_I.$procmux$5478: Old ports: A={ 1'1 \soc_I.uart_I.uart_tx_I.shift [9:1] }, B={ 1'1 \soc_I.uart_I.uart_tx_fifo_I.ram_I.rd_data 1'0 }, Y=$flatten\soc_I.\uart_I.\uart_tx_I.$0\shift[9:0] New ports: A=\soc_I.uart_I.uart_tx_I.shift [9:1], B={ \soc_I.uart_I.uart_tx_fifo_I.ram_I.rd_data 1'0 }, Y=$flatten\soc_I.\uart_I.\uart_tx_I.$0\shift[9:0] [8:0] New connections: $flatten\soc_I.\uart_I.\uart_tx_I.$0\shift[9:0] [9] = 1'1 Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\rx_pkt_I.\crc_16_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4708: Old ports: A=16'0000000000000000, B=16'1000000000000101, Y=\soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux New ports: A=1'0, B=1'1, Y=\soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux [0] New connections: \soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux [15:1] = { \soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux [0] 12'000000000000 \soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\rx_pkt_I.\crc_5_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4721: Old ports: A=3'000, B=3'101, Y=\soc_I.usb_I.rx_pkt_I.crc_5_I.state_upd_mux [2:0] New ports: A=1'0, B=1'1, Y=\soc_I.usb_I.rx_pkt_I.crc_5_I.state_upd_mux [0] New connections: \soc_I.usb_I.rx_pkt_I.crc_5_I.state_upd_mux [2:1] = { \soc_I.usb_I.rx_pkt_I.crc_5_I.state_upd_mux [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$procmux$11585: Old ports: A=3'000, B=3'110, Y=$auto$wreduce.cc:454:run$24003 [2:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:454:run$24003 [1] New connections: { $auto$wreduce.cc:454:run$24003 [2] $auto$wreduce.cc:454:run$24003 [0] } = { $auto$wreduce.cc:454:run$24003 [1] 1'0 } Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$procmux$11588: Old ports: A={ 1'0 $auto$wreduce.cc:454:run$24003 [2:0] }, B=4'0100, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11588_Y New ports: A=$auto$wreduce.cc:454:run$24003 [2:0], B=3'100, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11588_Y [2:0] New connections: $flatten\soc_I.\usb_I.\trans_I.$procmux$11588_Y [3] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_trans.v:340$1447: Old ports: A={ 8'00000000 \soc_I.usb_I.trans_I.ep_data_toggle \soc_I.usb_I.trans_I.ep_bd_idx_nxt \soc_I.usb_I.trans_I.ep_bd_ctrl \soc_I.usb_I.trans_I.ep_bd_dual 1'0 \soc_I.usb_I.trans_I.ep_type }, B={ \soc_I.usb_I.trans_I.bd_state \soc_I.usb_I.trans_I.trans_is_setup 2'00 \soc_I.usb_I.trans_I.xfer_length }, Y=\soc_I.usb_I.ep_status_I.p_din_0 New ports: A={ 6'000000 \soc_I.usb_I.trans_I.ep_data_toggle \soc_I.usb_I.trans_I.ep_bd_idx_nxt \soc_I.usb_I.trans_I.ep_bd_ctrl \soc_I.usb_I.trans_I.ep_bd_dual 1'0 \soc_I.usb_I.trans_I.ep_type }, B={ \soc_I.usb_I.trans_I.bd_state \soc_I.usb_I.trans_I.trans_is_setup \soc_I.usb_I.trans_I.xfer_length }, Y={ \soc_I.usb_I.ep_status_I.p_din_0 [15:12] \soc_I.usb_I.ep_status_I.p_din_0 [9:0] } New connections: \soc_I.usb_I.ep_status_I.p_din_0 [11:10] = 2'00 Consolidated identical input bits for $pmux cell $flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11536: Old ports: A=3'000, B=6'110111, Y=$flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11536_Y New ports: A=2'00, B=4'1011, Y=$flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11536_Y [1:0] New connections: $flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11536_Y [2] = $flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11536_Y [1] Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\tx_pkt_I.\crc_16_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4708: Old ports: A=16'0000000000000000, B=16'1000000000000101, Y=\soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux New ports: A=1'0, B=1'1, Y=\soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux [0] New connections: \soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux [15:1] = { \soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux [0] 12'000000000000 \soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux [0] 1'0 } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\misc_I.\dfu_I.\btn_flt_I.$procmux$5419: Old ports: A=$flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0], B=4'0001, Y=\misc_I.dfu_I.btn_flt_I.cnt_move New ports: A={ $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] }, B=2'01, Y=\misc_I.dfu_I.btn_flt_I.cnt_move [1:0] New connections: \misc_I.dfu_I.btn_flt_I.cnt_move [3:2] = { \misc_I.dfu_I.btn_flt_I.cnt_move [1] \misc_I.dfu_I.btn_flt_I.cnt_move [1] } Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$procmux$12396: Old ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 2'00 }, B=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$3926_Y, Y={ $flatten\soc_I.\cpu_I.$3\current_pc[31:0] [31:2] $auto$alumacc.cc:501:replace_alu$24059 [1:0] } New ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 1'0 }, B=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$3926_Y [31:1], Y={ $flatten\soc_I.\cpu_I.$3\current_pc[31:0] [31:2] $auto$alumacc.cc:501:replace_alu$24059 [1] } New connections: $auto$alumacc.cc:501:replace_alu$24059 [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5290: Old ports: A=16'0000000000000000, B=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5289_Y, Y=\soc_I.e1_I.bus_rdata_rx[0] New ports: A=15'000000000000000, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5289_Y [15:8] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5025[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5289_Y [6:0] }, Y={ \soc_I.e1_I.bus_rdata_rx[0] [15:8] \soc_I.e1_I.bus_rdata_rx[0] [6:0] } New connections: \soc_I.e1_I.bus_rdata_rx[0] [7] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5290: Old ports: A=16'0000000000000000, B=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5289_Y, Y=\soc_I.e1_I.bus_rdata_rx[1] New ports: A=15'000000000000000, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5289_Y [15:8] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5026[1].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5289_Y [6:0] }, Y={ \soc_I.e1_I.bus_rdata_rx[1] [15:8] \soc_I.e1_I.bus_rdata_rx[1] [6:0] } New connections: \soc_I.e1_I.bus_rdata_rx[1] [7] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$procmux$11588: Old ports: A=$auto$wreduce.cc:454:run$24003 [2:0], B=3'100, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11588_Y [2:0] New ports: A={ $auto$wreduce.cc:454:run$24003 [1] $auto$wreduce.cc:454:run$24003 [1] }, B=2'10, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11588_Y [2:1] New connections: $flatten\soc_I.\usb_I.\trans_I.$procmux$11588_Y [0] = 1'0 Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$procmux$11591: Old ports: A=$flatten\soc_I.\usb_I.\trans_I.$procmux$11588_Y, B=4'1000, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11591_Y New ports: A={ 1'0 $flatten\soc_I.\usb_I.\trans_I.$procmux$11588_Y [2:1] }, B=3'100, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11591_Y [3:1] New connections: $flatten\soc_I.\usb_I.\trans_I.$procmux$11591_Y [0] = 1'0 Optimizing cells in module \top. Performed a total of 32 changes. 73.29.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.29.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$22375 ($dff) from module top (D = \soc_I.cpu_I.mem_wdata [11:10], Q = \soc_I.usb_I.ep_status_I.din_1 [11:10], rval = 2'00). 73.29.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 2 unused wires. <suppressed ~1 debug messages> 73.29.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~28 debug messages> 73.29.9. Rerunning OPT passes. (Maybe there is more to do..) 73.29.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~138 debug messages> 73.29.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 73.29.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.29.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$23726 ($dffe) from module top. Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$23726 ($dffe) from module top. Setting constant 1-bit at position 9 on $auto$opt_dff.cc:764:run$23452 ($adffe) from module top. 73.29.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 10 unused wires. <suppressed ~1 debug messages> 73.29.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.29.16. Rerunning OPT passes. (Maybe there is more to do..) 73.29.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~138 debug messages> 73.29.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 73.29.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.29.20. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$23518 ($sdff) from module top. 73.29.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 73.29.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~5 debug messages> 73.29.23. Rerunning OPT passes. (Maybe there is more to do..) 73.29.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~138 debug messages> 73.29.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 73.29.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.29.27. Executing OPT_DFF pass (perform DFF optimizations). 73.29.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 2 unused wires. <suppressed ~1 debug messages> 73.29.29. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.29.30. Rerunning OPT passes. (Maybe there is more to do..) 73.29.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~138 debug messages> 73.29.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 73.29.33. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.29.34. Executing OPT_DFF pass (perform DFF optimizations). 73.29.35. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 73.29.36. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.29.37. Finished OPT passes. (There is nothing left to do.) 73.30. Executing ICE40_WRAPCARRY pass (wrap carries). 73.31. Executing TECHMAP pass (map to technology primitives). 73.31.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/techmap.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 73.31.2. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ice40_alu'. Successfully finished Verilog frontend. 73.31.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $xor. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $reduce_bool. Using extmapper simplemap for cells of type $ne. Using extmapper simplemap for cells of type $sdff. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $dffe. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $sdffce. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $sdffe. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $adffe. Using extmapper simplemap for cells of type $adff. Using extmapper simplemap for cells of type $mux. Using template $paramod$constmap:a4d8bd4c83ae7aadb9a39a6a6c198c7f62a08526$paramod$39430ff77e1846062046cba1eb3ce5685e03f0fe\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=7\B_WIDTH=1\Y_WIDTH=7 for cells of type $alu. Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu. Using extmapper simplemap for cells of type $logic_and. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=3\Y_WIDTH=3 for cells of type $alu. Using extmapper simplemap for cells of type $logic_or. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=14\Y_WIDTH=14 for cells of type $alu. Using template $paramod\_90_pmux\WIDTH=2\S_WIDTH=3 for cells of type $pmux. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=11\B_WIDTH=1\Y_WIDTH=12 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=13\B_WIDTH=1\Y_WIDTH=13 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=9\Y_WIDTH=9 for cells of type $alu. Using extmapper simplemap for cells of type $reduce_xor. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=20\Y_WIDTH=20 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=1\Y_WIDTH=4 for cells of type $alu. Using template $paramod\_90_pmux\WIDTH=16\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=5 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=2\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=1\Y_WIDTH=4 for cells of type $alu. Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=4 for cells of type $pmux. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=11\B_WIDTH=1\Y_WIDTH=11 for cells of type $alu. Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=6 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=3 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=8 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=6 for cells of type $pmux. Using extmapper simplemap for cells of type $reduce_xnor. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=8\Y_WIDTH=8 for cells of type $alu. Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=3 for cells of type $pmux. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=9\B_WIDTH=1\Y_WIDTH=9 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=2\Y_WIDTH=3 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=10\Y_WIDTH=10 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=11\Y_WIDTH=11 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=1\Y_WIDTH=5 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=10\B_WIDTH=10\Y_WIDTH=10 for cells of type $alu. Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu. Using template $paramod$constmap:66d421c313e4e958be776b99540ac2de3b59fdbc$paramod$9b74a473ccd678a23e1df4cc12019cbbece20051\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=30\Y_WIDTH=30 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=31\B_WIDTH=31\Y_WIDTH=31 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=30\B_WIDTH=30\Y_WIDTH=30 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=26\Y_WIDTH=26 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=1\Y_WIDTH=3 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=1\B_SIGNED=1\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu. Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=3 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=24\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=5 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=4 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=5 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu. Using template $paramod$constmap:f52804453afb21971b2ae6a008b16eeac8518095$paramod$00673b792be9df78f478ac12e847ffbbf69ec54f\_90_shift_shiftx for cells of type $shiftx. Using template $paramod$constmap:86dc5286c5df415b7afb14b9cb1987cdb8d95694$paramod$46cd3b166c849b74a0d50b3191f97ef695044070\_90_shift_shiftx for cells of type $shiftx. Using extmapper simplemap for cells of type $pos. Using template $paramod\_90_lcu\WIDTH=2 for cells of type $lcu. No more expansions possible. <suppressed ~4329 debug messages> 73.32. Executing OPT pass (performing simple optimizations). 73.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~2759 debug messages> 73.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~3621 debug messages> Removed a total of 1207 cells. 73.32.3. Executing OPT_DFF pass (perform DFF optimizations). 73.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 614 unused cells and 3766 unused wires. <suppressed ~626 debug messages> 73.32.5. Finished fast OPT passes. 73.33. Executing ICE40_OPT pass (performing simple optimizations). 73.33.1. Running ICE40 specific optimizations. Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24013.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24013.BB [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24055.slice[0].carry: CO=\soc_I.cpu_I.reg_pc [2] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24058.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24058.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24073.slice[0].carry: CO=\soc_I.cpu_I.reg_sh [2] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24076.slice[0].carry: CO=\soc_I.cpu_I.reg_sh [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24079.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24079.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24082.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24082.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24085.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24085.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24100.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24100.A [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24103.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24103.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24106.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24106.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24109.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24109.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24124.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24124.A [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24127.slice[0].carry: CO=\soc_I.iobuf_I.dma_I.m0_addr_i [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24130.slice[0].carry: CO=\soc_I.iobuf_I.dma_I.m1_addr_i [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24133.slice[0].carry: CO=\soc_I.iobuf_I.dma_I.len [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24136.slice[0].carry: CO=\soc_I.uart_I.uart_div [1] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24136.slice[11].carry: CO=$auto$alumacc.cc:485:replace_alu$24136.C [11] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24139.slice[0].carry: CO=\soc_I.uart_I.uart_rx_I.div_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24142.slice[0].carry: CO=\soc_I.uart_I.uart_rx_I.bit_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24148.slice[0].carry: CO=\soc_I.uart_I.uart_rx_fifo_I.ram_rd_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24154.slice[0].carry: CO=\soc_I.uart_I.uart_rx_fifo_I.ram_wr_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24157.slice[0].carry: CO=\soc_I.uart_I.uart_tx_I.div_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24160.slice[0].carry: CO=\soc_I.uart_I.uart_tx_I.bit_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24163.slice[0].carry: CO=\soc_I.uart_I.uart_tx_fifo_I.ram_rd_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24169.slice[0].carry: CO=\soc_I.uart_I.uart_tx_fifo_I.ram_wr_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24181.slice[0].carry: CO=\soc_I.usb_I.rx_pkt_I.bit_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24181.slice[3].carry: CO=$auto$alumacc.cc:485:replace_alu$24181.C [3] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24184.slice[0].carry: CO=\soc_I.usb_I.trans_I.mc_pc [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24199.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24199.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24199.slice[2].carry: CO=1'0 Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24202.slice[0].carry: CO=\soc_I.usb_I.tx_ll_I.bs_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24205.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24205.A [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24208.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24208.A [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24211.slice[0].carry: CO=\sys_mgr_I.rst_cnt [0] 73.33.2. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~38 debug messages> 73.33.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.33.4. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$29604 ($_SDFFCE_PP0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11871.B_AND_S [3], Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [3], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$29603 ($_SDFFCE_PP0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11871.Y_B [2], Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [2], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$29602 ($_SDFFCE_PP0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11871.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [1], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$29600 ($_SDFFCE_PN0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11888.B_AND_S [3], Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1 [3], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$29599 ($_SDFFCE_PN0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11888.Y_B [2], Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1 [2], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$29598 ($_SDFFCE_PN0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11888.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1 [1], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$30197 ($_SDFF_PP0_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11914.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.samp_cnt [1], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33822 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841.Y_B [31], Q = \soc_I.cpu_I.decoded_imm [31], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33821 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841.Y_B [30], Q = \soc_I.cpu_I.decoded_imm [30], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33820 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841.Y_B [29], Q = \soc_I.cpu_I.decoded_imm [29], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33819 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841.Y_B [28], Q = \soc_I.cpu_I.decoded_imm [28], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33818 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841.Y_B [27], Q = \soc_I.cpu_I.decoded_imm [27], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33817 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841.Y_B [26], Q = \soc_I.cpu_I.decoded_imm [26], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33816 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841.Y_B [25], Q = \soc_I.cpu_I.decoded_imm [25], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33815 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841.Y_B [24], Q = \soc_I.cpu_I.decoded_imm [24], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33814 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841.Y_B [23], Q = \soc_I.cpu_I.decoded_imm [23], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33813 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841.Y_B [22], Q = \soc_I.cpu_I.decoded_imm [22], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33812 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841.Y_B [21], Q = \soc_I.cpu_I.decoded_imm [21], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33811 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841.Y_B [20], Q = \soc_I.cpu_I.decoded_imm [20], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33810 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841.Y_B [19], Q = \soc_I.cpu_I.decoded_imm [19], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33809 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841.Y_B [18], Q = \soc_I.cpu_I.decoded_imm [18], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33808 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841.Y_B [17], Q = \soc_I.cpu_I.decoded_imm [17], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33807 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841.Y_B [16], Q = \soc_I.cpu_I.decoded_imm [16], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33806 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841.Y_B [15], Q = \soc_I.cpu_I.decoded_imm [15], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33805 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841.Y_B [14], Q = \soc_I.cpu_I.decoded_imm [14], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33804 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841.Y_B [13], Q = \soc_I.cpu_I.decoded_imm [13], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33803 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841.Y_B [12], Q = \soc_I.cpu_I.decoded_imm [12], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33802 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841.Y_B [11], Q = \soc_I.cpu_I.decoded_imm [11], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33801 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841.Y_B [10], Q = \soc_I.cpu_I.decoded_imm [10], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33800 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841.Y_B [9], Q = \soc_I.cpu_I.decoded_imm [9], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33799 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841.Y_B [8], Q = \soc_I.cpu_I.decoded_imm [8], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33798 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841.Y_B [7], Q = \soc_I.cpu_I.decoded_imm [7], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33797 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841.Y_B [6], Q = \soc_I.cpu_I.decoded_imm [6], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33796 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841.Y_B [5], Q = \soc_I.cpu_I.decoded_imm [5], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33795 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841.Y_B [4], Q = \soc_I.cpu_I.decoded_imm [4], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33794 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841.Y_B [3], Q = \soc_I.cpu_I.decoded_imm [3], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33793 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841.Y_B [2], Q = \soc_I.cpu_I.decoded_imm [2], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33792 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13841.Y_B [1], Q = \soc_I.cpu_I.decoded_imm [1], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$29594 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11903.B_AND_S [2], Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [2], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$29593 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11903.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [1], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$29592 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11903.Y_B [0], Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [0], rval = 1'0). 73.33.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 42 unused cells and 11 unused wires. <suppressed ~43 debug messages> 73.33.6. Rerunning OPT passes. (Removed registers in this run.) 73.33.7. Running ICE40 specific optimizations. 73.33.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.33.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~18 debug messages> Removed a total of 6 cells. 73.33.10. Executing OPT_DFF pass (perform DFF optimizations). 73.33.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 6 unused wires. <suppressed ~1 debug messages> 73.33.12. Rerunning OPT passes. (Removed registers in this run.) 73.33.13. Running ICE40 specific optimizations. 73.33.14. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.33.15. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.33.16. Executing OPT_DFF pass (perform DFF optimizations). 73.33.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 73.33.18. Finished OPT passes. (There is nothing left to do.) 73.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 73.35. Executing TECHMAP pass (map to technology primitives). 73.35.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. Successfully finished Verilog frontend. 73.35.2. Continuing TECHMAP pass. Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_. Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template \$_SDFFCE_PP0P_ for cells of type $_SDFFCE_PP0P_. Using template \$_SDFFCE_PP1P_ for cells of type $_SDFFCE_PP1P_. Using template \$_DFF_P_ for cells of type $_DFF_P_. Using template \$_DFF_PP0_ for cells of type $_DFF_PP0_. Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_. Using template \$_DFFE_PP0P_ for cells of type $_DFFE_PP0P_. Using template \$_DFF_PP1_ for cells of type $_DFF_PP1_. Using template \$_DFFE_PP1P_ for cells of type $_DFFE_PP1P_. No more expansions possible. <suppressed ~1818 debug messages> 73.36. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). Mapping top.$auto$alumacc.cc:485:replace_alu$24055.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24058.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24073.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24076.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24079.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24082.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24085.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24100.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24103.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24106.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24109.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24124.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24127.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24130.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24133.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24136.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24136.slice[11].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24139.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24142.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24148.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24154.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24157.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24160.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24163.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24169.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24181.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24181.slice[3].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24184.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24199.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24199.slice[2].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24202.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24205.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24208.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24211.slice[0].carry ($lut). 73.38. Executing ICE40_OPT pass (performing simple optimizations). 73.38.1. Running ICE40 specific optimizations. 73.38.2. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~1028 debug messages> 73.38.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~1320 debug messages> Removed a total of 440 cells. 73.38.4. Executing OPT_DFF pass (perform DFF optimizations). 73.38.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 9891 unused wires. <suppressed ~1 debug messages> 73.38.6. Rerunning OPT passes. (Removed registers in this run.) 73.38.7. Running ICE40 specific optimizations. 73.38.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.38.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.38.10. Executing OPT_DFF pass (perform DFF optimizations). 73.38.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 73.38.12. Finished OPT passes. (There is nothing left to do.) 73.39. Executing TECHMAP pass (map to technology primitives). 73.39.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/latches_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/latches_map.v' to AST representation. Generating RTLIL representation for module `\$_DLATCH_N_'. Generating RTLIL representation for module `\$_DLATCH_P_'. Successfully finished Verilog frontend. 73.39.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~4 debug messages> 73.40. Executing ABC pass (technology mapping using ABC). 73.40.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'.. Extracted 5804 gates and 7924 wires to a netlist network with 2118 inputs and 1578 outputs. 73.40.1.1. Executing ABC. Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1 ABC: ABC command line: "source <abc-temp-dir>/abc.script". ABC: ABC: + read_blif <abc-temp-dir>/input.blif ABC: + read_lut <abc-temp-dir>/lutdefs.txt ABC: + strash ABC: + ifraig ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + strash ABC: + dch -f ABC: + if ABC: + mfs2 ABC: + lutpack -S 1 ABC: + dress ABC: Total number of equiv classes = 1939. ABC: Participating nodes from both networks = 4077. ABC: Participating nodes from the first network = 1949. ( 77.37 % of nodes) ABC: Participating nodes from the second network = 2128. ( 84.48 % of nodes) ABC: Node pairs (any polarity) = 1949. ( 77.37 % of names can be moved) ABC: Node pairs (same polarity) = 1697. ( 67.37 % of names can be moved) ABC: Total runtime = 0.04 sec ABC: + write_blif <abc-temp-dir>/output.blif 73.40.1.2. Re-integrating ABC results. ABC RESULTS: $lut cells: 2518 ABC RESULTS: internal signals: 4228 ABC RESULTS: input signals: 2118 ABC RESULTS: output signals: 1578 Removing temp directory. 73.41. Executing ICE40_WRAPCARRY pass (wrap carries). 73.42. Executing TECHMAP pass (map to technology primitives). 73.42.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. Successfully finished Verilog frontend. 73.42.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~22 debug messages> Removed 112 unused cells and 5241 unused wires. 73.43. Executing OPT_LUT pass (optimize LUTs). Discovering LUTs. Number of LUTs: 3004 1-LUT 119 2-LUT 762 3-LUT 1042 4-LUT 1081 Eliminating LUTs. Number of LUTs: 3004 1-LUT 119 2-LUT 762 3-LUT 1042 4-LUT 1081 Combining LUTs. Number of LUTs: 2850 1-LUT 118 2-LUT 577 3-LUT 961 4-LUT 1194 Eliminated 0 LUTs. Combined 154 LUTs. <suppressed ~16273 debug messages> 73.44. Executing TECHMAP pass (map to technology primitives). 73.44.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v' to AST representation. Generating RTLIL representation for module `\$lut'. Successfully finished Verilog frontend. 73.44.2. Continuing TECHMAP pass. Using template $paramod\$lut\WIDTH=2\LUT=4'0001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000110011001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0110100110010110 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'1000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00001011 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'0100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110101100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=1\LUT=2'01 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100101000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'1011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000011101110111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'0110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010110010100011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111001111110101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011000010111011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100010011110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101001101011100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100110101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000110000001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'1110 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00110101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101110011001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101110111011 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111100000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111110111011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101001111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011101100001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000011100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00001101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101110001010011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000101110111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111001011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00010100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11101111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100011101110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000001001 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111111110 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'0111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000111111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011010100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01010011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100000011 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01001011 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00000111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111011111110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00011111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111110000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00001110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000010001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'1001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100111110110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011101111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100111110100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101011111100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011110011111010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111111111110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011111110011111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101000001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000001000100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000010111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100110011000101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000011111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11101000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000100011110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001111101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100101011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11100111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100111101000100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100001011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111100010001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111010000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000111110001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001010000101000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10101100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000011100001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1001011001101001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010110011001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0110000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00111010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111110000001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000010111011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111010000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100111111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11010100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100000000000010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011110011001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111010111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101001100110011 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11000101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000110000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110110000110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011010111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100000011001110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000110100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011110010101010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001000111110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111000011001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111100011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1001011010010110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011001100110101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000001100000101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110111000001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011101111110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10111100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111110011111010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101001100110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110111011110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101111100001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000001100001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011101000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0010101111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111010100110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1101111111000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011011100110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011101001000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11111110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0010111111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111011001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010110011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001011 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10110010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110111111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111000001110111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111010001000100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011101110110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010110000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100001110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1101000000110011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111110110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011101100110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000001110111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111111110000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11110001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110000011101110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0110000000001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00011000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111011101110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000011111001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010101010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001010000010100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010001111001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010010111110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1001110010011100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100101110110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010001000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110101110111110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010101011000011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100111000001100 for cells of type $lut. No more expansions possible. <suppressed ~5564 debug messages> Removed 0 unused cells and 6060 unused wires. 73.45. Executing AUTONAME pass. Renamed 163058 objects in module top (116 iterations). <suppressed ~7000 debug messages> 73.46. Executing HIERARCHY pass (managing design hierarchy). 73.46.1. Analyzing design hierarchy.. Top module: \top 73.46.2. Analyzing design hierarchy.. Top module: \top Removed 0 unused modules. 73.47. Printing statistics. === top === Number of wires: 3147 Number of wire bits: 16050 Number of public wires: 3147 Number of public wire bits: 16050 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 5270 SB_CARRY 545 SB_DFF 201 SB_DFFE 539 SB_DFFER 295 SB_DFFES 10 SB_DFFESR 192 SB_DFFESS 56 SB_DFFR 143 SB_DFFS 29 SB_DFFSR 303 SB_DFFSS 28 SB_GB 1 SB_GB_IO 1 SB_IO 13 SB_LEDDA_IP 1 SB_LUT4 2883 SB_MAC16 3 SB_PLL40_2F_CORE 1 SB_RAM40_4K 14 SB_RAM40_4KNR 4 SB_RGBA_DRV 1 SB_SPI 2 SB_SPRAM256KA 4 SB_WARMBOOT 1 73.48. Executing CHECK pass (checking for obvious problems). checking module top.. found and reported 0 problems. 73.49. Executing JSON backend. Warnings: 10 unique messages, 16 total End of script. Logfile hash: c2c527453c, CPU: user 11.43s system 0.10s, MEM: 281.60 MB peak Yosys 0.9+3568 (open-tool-forge build) (git sha1 859e52af, gcc 9.3.0-10ubuntu2 -Os) Time spent: 23% 35x opt_expr (2 sec), 18% 31x opt_clean (2 sec), ... nextpnr-ice40 --no-promote-globals --pre-pack data/clocks.py --seed 19 --timing-allow-fail \ --up5k --package sg48 \ -l /build/gateware/e1-tracer/build-tmp/e1-tracer.pnr.rpt \ --json /build/gateware/e1-tracer/build-tmp/e1-tracer.json \ --pcf /build/gateware/e1-tracer/data/top-e1-tracer.pcf \ --asc /build/gateware/e1-tracer/build-tmp/e1-tracer.asc Info: constrained 'e1A_rx_data' to bel 'X7/Y0/io1' Info: constrained 'e1A_rx_clk' to bel 'X6/Y0/io1' Info: constrained 'e1B_rx_data' to bel 'X6/Y0/io0' Info: constrained 'e1B_rx_clk' to bel 'X5/Y0/io0' Info: constrained 'liu_mosi' to bel 'X16/Y31/io1' Info: constrained 'liu_miso' to bel 'X16/Y31/io0' Info: constrained 'liu_clk' to bel 'X13/Y31/io1' Info: constrained 'liu_cs_n[0]' to bel 'X8/Y31/io0' Info: constrained 'liu_cs_n[1]' to bel 'X9/Y31/io0' Info: constrained 'usb_dp' to bel 'X16/Y0/io0' Info: constrained 'usb_dn' to bel 'X15/Y0/io0' Info: constrained 'usb_pu' to bel 'X13/Y0/io1' Info: constrained 'flash_mosi' to bel 'X23/Y0/io0' Info: constrained 'flash_miso' to bel 'X23/Y0/io1' Info: constrained 'flash_clk' to bel 'X24/Y0/io0' Info: constrained 'flash_cs_n' to bel 'X24/Y0/io1' Info: constrained 'vio_pdm' to bel 'X21/Y0/io1' Info: constrained 'btn' to bel 'X19/Y31/io1' Info: constrained 'clk_in' to bel 'X19/Y0/io1' Info: constrained 'dbg_tx' to bel 'X8/Y31/io1' Info: constrained 'rgb[0]' to bel 'X4/Y31/io0' Info: constrained 'rgb[1]' to bel 'X5/Y31/io0' Info: constrained 'rgb[2]' to bel 'X6/Y31/io0' Info: constraining clock net 'clk_sys' to 24.00 MHz Info: constraining clock net 'clk_48m' to 48.00 MHz Info: Packing constants.. Info: Packing IOs.. Info: btn feeds SB_IO misc_I.dfu_I.btn_iob_I, removing $nextpnr_ibuf btn. Info: clk_in feeds SB_IO sys_mgr_I.gb_in, removing $nextpnr_ibuf clk_in. Info: e1A_rx_clk feeds SB_IO e1A_rx_clk_SB_IO_PACKAGE_PIN, removing $nextpnr_ibuf e1A_rx_clk. Info: e1A_rx_data feeds SB_IO e1A_rx_data_SB_IO_PACKAGE_PIN, removing $nextpnr_ibuf e1A_rx_data. Info: e1B_rx_clk feeds SB_IO e1B_rx_clk_SB_IO_PACKAGE_PIN, removing $nextpnr_ibuf e1B_rx_clk. Info: e1B_rx_data feeds SB_IO e1B_rx_data_SB_IO_PACKAGE_PIN, removing $nextpnr_ibuf e1B_rx_data. Info: flash_clk feeds SB_IO spi_io_I[0], removing $nextpnr_iobuf flash_clk. Info: flash_miso feeds SB_IO spi_io_I[1], removing $nextpnr_iobuf flash_miso. Info: flash_mosi feeds SB_IO spi_io_I[2], removing $nextpnr_iobuf flash_mosi. Info: liu_clk feeds SB_IO spi_I.spi_io_I[0], removing $nextpnr_iobuf liu_clk. Info: liu_miso feeds SB_IO spi_I.spi_io_I[1], removing $nextpnr_iobuf liu_miso. Info: liu_mosi feeds SB_IO spi_I.spi_io_I[2], removing $nextpnr_iobuf liu_mosi. Info: usb_dn feeds SB_IO soc_I.usb_I.phy_I.io_dn_I, removing $nextpnr_iobuf usb_dn. Info: usb_dp feeds SB_IO soc_I.usb_I.phy_I.io_dp_I, removing $nextpnr_iobuf usb_dp. Info: rgb[0] use by SB_RGBA_DRV/SB_RGB_DRV soc_I.rgb_I.rgb_drv_I, not creating SB_IO Info: rgb[1] use by SB_RGBA_DRV/SB_RGB_DRV soc_I.rgb_I.rgb_drv_I, not creating SB_IO Info: rgb[2] use by SB_RGBA_DRV/SB_RGB_DRV soc_I.rgb_I.rgb_drv_I, not creating SB_IO Info: Packing LUT-FFs.. Info: 1560 LCs used as LUT4 only Info: 1323 LCs used as LUT4 and DFF Info: Packing non-LUT FFs.. Info: 473 LCs used as DFF only Info: Packing carries.. Info: 194 LCs used as CARRY only Info: Packing RAMs.. Info: Placing PLLs.. Info: constrained PLL 'sys_mgr_I.pll_I' to X12/Y31/pll_3 Info: Packing special functions.. Info: constrained SB_LEDDA_IP 'soc_I.rgb_I.led_I' to X0/Y31/ledda_ip_2 Info: constrained SB_RGBA_DRV 'soc_I.rgb_I.rgb_drv_I' to X0/Y30/rgba_drv_0 Info: constrained SB_SPI 'soc_I.spi_I.spi_I' to X0/Y0/spi_0 Info: constrained SB_SPI 'spi_I.spi_I' to X25/Y0/spi_1 Info: PLL 'sys_mgr_I.pll_I' has LOCK output, need to pass all outputs via LUT Info: constrained 'sys_mgr_I.pll_lock_SB_LUT4_I3_LC' to X1/Y30/lc0 Info: Constraining chains... Info: 135 LCs used to legalise carry chains. Info: Checksum: 0x196753ca Info: Annotating ports with timing budgets for target frequency 12.00 MHz Info: Checksum: 0x33f3e706 Info: Device utilisation: Info: ICESTORM_LC: 3687/ 5280 69% Info: ICESTORM_RAM: 18/ 30 60% Info: SB_IO: 20/ 96 20% Info: SB_GB: 4/ 8 50% Info: ICESTORM_PLL: 1/ 1 100% Info: SB_WARMBOOT: 1/ 1 100% Info: ICESTORM_DSP: 3/ 8 37% Info: ICESTORM_HFOSC: 0/ 1 0% Info: ICESTORM_LFOSC: 0/ 1 0% Info: SB_I2C: 0/ 2 0% Info: SB_SPI: 2/ 2 100% Info: IO_I3C: 0/ 2 0% Info: SB_LEDDA_IP: 1/ 1 100% Info: SB_RGBA_DRV: 1/ 1 100% Info: ICESTORM_SPRAM: 4/ 4 100% Info: Placed 29 cells based on constraints. Info: Creating initial analytic placement for 3036 cells, random placement wirelen = 94398. Info: at initial placer iter 0, wirelen = 3345 Info: at initial placer iter 1, wirelen = 3304 Info: at initial placer iter 2, wirelen = 3249 Info: at initial placer iter 3, wirelen = 3283 Info: Running main analytical placer. Info: at iteration #1, type ALL: wirelen solved = 3251, spread = 31924, legal = 45173; time = 0.08s Info: at iteration #2, type ALL: wirelen solved = 4028, spread = 33020, legal = 39830; time = 0.15s Info: at iteration #3, type ALL: wirelen solved = 5603, spread = 27088, legal = 40623; time = 0.09s Info: at iteration #4, type ALL: wirelen solved = 6144, spread = 26092, legal = 37307; time = 0.07s Info: at iteration #5, type ALL: wirelen solved = 7412, spread = 25458, legal = 38677; time = 0.08s Info: at iteration #6, type ALL: wirelen solved = 7476, spread = 25890, legal = 35320; time = 0.06s Info: at iteration #7, type ALL: wirelen solved = 8353, spread = 25356, legal = 36231; time = 0.07s Info: at iteration #8, type ALL: wirelen solved = 8724, spread = 24389, legal = 33859; time = 0.05s Info: at iteration #9, type ALL: wirelen solved = 9796, spread = 23667, legal = 36655; time = 0.07s Info: at iteration #10, type ALL: wirelen solved = 10394, spread = 23203, legal = 32586; time = 0.06s Info: at iteration #11, type ALL: wirelen solved = 11023, spread = 22735, legal = 33717; time = 0.06s Info: at iteration #12, type ALL: wirelen solved = 11013, spread = 22844, legal = 34304; time = 0.06s Info: at iteration #13, type ALL: wirelen solved = 11130, spread = 22834, legal = 32052; time = 0.05s Info: at iteration #14, type ALL: wirelen solved = 11769, spread = 22654, legal = 32274; time = 0.05s Info: at iteration #15, type ALL: wirelen solved = 12231, spread = 22639, legal = 34492; time = 0.06s Info: at iteration #16, type ALL: wirelen solved = 12718, spread = 23214, legal = 34807; time = 0.07s Info: at iteration #17, type ALL: wirelen solved = 12323, spread = 23238, legal = 34157; time = 0.06s Info: at iteration #18, type ALL: wirelen solved = 13705, spread = 22842, legal = 33655; time = 0.07s Info: HeAP Placer Time: 1.62s Info: of which solving equations: 0.61s Info: of which spreading cells: 0.10s Info: of which strict legalisation: 0.59s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 596, wirelen = 32052 Info: at iteration #5: temp = 0.000000, timing cost = 315, wirelen = 26804 Info: at iteration #10: temp = 0.000000, timing cost = 266, wirelen = 25453 Info: at iteration #15: temp = 0.000000, timing cost = 262, wirelen = 24753 Info: at iteration #20: temp = 0.000000, timing cost = 258, wirelen = 24288 Info: at iteration #25: temp = 0.000000, timing cost = 254, wirelen = 24174 Info: at iteration #30: temp = 0.000000, timing cost = 254, wirelen = 24129 Info: at iteration #32: temp = 0.000000, timing cost = 253, wirelen = 24104 Info: SA placement time 2.53s Info: Max frequency for clock 'clk_sys': 30.40 MHz (PASS at 24.00 MHz) Info: Max frequency for clock 'clk_48m': 50.28 MHz (PASS at 48.00 MHz) Info: Max delay <async> -> posedge clk_sys: 9.50 ns Info: Max delay posedge clk_48m -> <async> : 4.04 ns Info: Max delay posedge clk_48m -> posedge clk_sys: 6.84 ns Info: Max delay posedge clk_sys -> <async> : 10.15 ns Info: Max delay posedge clk_sys -> posedge clk_48m: 16.23 ns Info: Slack histogram: Info: legend: * represents 34 endpoint(s) Info: + represents [1,34) endpoint(s) Info: [ 944, 4906) |*+ Info: [ 4906, 8868) |*****+ Info: [ 8868, 12830) |********+ Info: [ 12830, 16792) |*******************************+ Info: [ 16792, 20754) |*******+ Info: [ 20754, 24716) |***********+ Info: [ 24716, 28678) |************************+ Info: [ 28678, 32640) |**************************************+ Info: [ 32640, 36602) |************************************************************ Info: [ 36602, 40564) |*****************************+ Info: [ 40564, 44526) | Info: [ 44526, 48488) | Info: [ 48488, 52450) | Info: [ 52450, 56412) | Info: [ 56412, 60374) | Info: [ 60374, 64336) | Info: [ 64336, 68298) | Info: [ 68298, 72260) | Info: [ 72260, 76222) |+ Info: [ 76222, 80184) |+ Info: Checksum: 0xdd2eff37 Info: Routing.. Info: Setting up routing queue. Info: Routing 12729 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 1000 | 21 978 | 21 978 | 11752| 0.06 0.06| Info: 2000 | 69 1930 | 48 952 | 10803| 0.10 0.16| Info: 3000 | 156 2843 | 87 913 | 9914| 0.17 0.33| Info: 4000 | 351 3648 | 195 805 | 9174| 0.22 0.55| Info: 5000 | 596 4403 | 245 755 | 8562| 0.25 0.80| Info: 6000 | 791 5208 | 195 805 | 7833| 0.22 1.03| Info: 7000 | 1112 5887 | 321 679 | 7306| 0.27 1.29| Info: 8000 | 1521 6478 | 409 591 | 6941| 0.30 1.59| Info: 9000 | 1849 7150 | 328 672 | 6441| 0.44 2.03| Info: 10000 | 2298 7701 | 449 551 | 6159| 0.44 2.48| Info: 11000 | 2711 8288 | 413 587 | 5893| 0.53 3.01| Info: 12000 | 3188 8811 | 477 523 | 5697| 0.47 3.48| Info: 13000 | 3690 9309 | 502 498 | 5582| 0.48 3.96| Info: 14000 | 4242 9757 | 552 448 | 5401| 0.57 4.54| Info: 15000 | 4638 10361 | 396 604 | 5028| 0.48 5.02| Info: 16000 | 5122 10877 | 484 516 | 4793| 0.46 5.48| Info: 17000 | 5686 11313 | 564 436 | 4688| 0.46 5.93| Info: 18000 | 6189 11810 | 503 497 | 4541| 0.42 6.35| Info: 19000 | 6706 12293 | 517 483 | 4355| 0.56 6.91| Info: 20000 | 7044 12955 | 338 662 | 3830| 0.22 7.13| Info: 21000 | 7519 13480 | 475 525 | 3597| 0.36 7.49| Info: 22000 | 7968 14031 | 449 551 | 3299| 0.80 8.28| Info: 23000 | 8515 14484 | 547 453 | 3210| 0.51 8.80| Info: 24000 | 9042 14957 | 527 473 | 3127| 0.47 9.27| Info: 25000 | 9566 15433 | 524 476 | 3029| 0.56 9.83| Info: 26000 | 10040 15959 | 474 526 | 2873| 0.49 10.32| Info: 27000 | 10587 16412 | 547 453 | 2827| 0.98 11.30| Info: 28000 | 11141 16858 | 554 446 | 2807| 0.51 11.80| Info: 29000 | 11703 17296 | 562 438 | 2740| 0.51 12.31| Info: 30000 | 12198 17801 | 495 505 | 2695| 0.43 12.74| Info: 31000 | 12743 18256 | 545 455 | 2630| 0.50 13.24| Info: 32000 | 13360 18639 | 617 383 | 2602| 0.53 13.78| Info: 33000 | 13939 19060 | 579 421 | 2590| 0.56 14.34| Info: 34000 | 14511 19488 | 572 428 | 2495| 0.50 14.84| Info: 35000 | 15063 19936 | 552 448 | 2420| 0.46 15.31| Info: 36000 | 15673 20326 | 610 390 | 2391| 0.48 15.78| Info: 37000 | 16191 20808 | 518 482 | 2291| 0.42 16.20| Info: 38000 | 16815 21184 | 624 376 | 2252| 0.47 16.67| Info: 39000 | 17398 21601 | 583 417 | 2153| 0.47 17.14| Info: 40000 | 17979 22020 | 581 419 | 2131| 0.69 17.83| Info: 41000 | 18544 22455 | 565 435 | 2030| 0.48 18.31| Info: 42000 | 19153 22846 | 609 391 | 1999| 0.51 18.82| Info: 43000 | 19676 23323 | 523 477 | 1945| 0.55 19.38| Info: 44000 | 20225 23774 | 549 451 | 1894| 0.62 20.00| Info: 45000 | 20625 24374 | 400 600 | 1571| 0.56 20.56| Info: 46000 | 21158 24841 | 533 467 | 1287| 0.47 21.02| Info: 47000 | 21674 25325 | 516 484 | 1040| 0.53 21.55| Info: 48000 | 22042 25957 | 368 632 | 634| 1.12 22.67| Info: 49000 | 22453 26546 | 411 589 | 331| 1.80 24.47| Info: 49433 | 22533 26900 | 80 354 | 0| 0.29 24.76| Info: Routing complete. Info: Router1 time 24.76s Info: Checksum: 0x3710eb61 Info: Critical path report for clock 'clk_sys' (posedge -> posedge): Info: curr total Info: 1.4 1.4 Source soc_I.cpu_I.cpuregs.regs[0].ram_rd_data_SB_LUT4_I2_O_SB_LUT4_O_26_LC.O Info: 4.1 5.5 Net soc_I.cpu_I.alu_out_SB_LUT4_O_30_I2_SB_LUT4_O_I3[1] budget 0.000000 ns (5,10) -> (8,4) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_O_30_LC.I3 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:160.34-160.41 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: 0.9 6.4 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_O_30_LC.O Info: 1.8 8.2 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I2[1] budget 0.000000 ns (8,4) -> (7,3) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_19$CARRY.I2 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1222.14-1222.31 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:49.21-49.23 Info: 0.6 8.8 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_19$CARRY.COUT Info: 0.0 8.8 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[1] budget 0.000000 ns (7,3) -> (7,3) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_8$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 9.1 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_8$CARRY.COUT Info: 0.0 9.1 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[2] budget 0.000000 ns (7,3) -> (7,3) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_6$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 9.3 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_6$CARRY.COUT Info: 0.0 9.3 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[3] budget 0.000000 ns (7,3) -> (7,3) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_5$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 9.6 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_5$CARRY.COUT Info: 0.0 9.6 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[4] budget 0.000000 ns (7,3) -> (7,3) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_4$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 9.9 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_4$CARRY.COUT Info: 0.0 9.9 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[5] budget 0.000000 ns (7,3) -> (7,3) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_3$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 10.2 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_3$CARRY.COUT Info: 0.0 10.2 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[6] budget 0.000000 ns (7,3) -> (7,3) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_2$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 10.4 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_2$CARRY.COUT Info: 0.6 11.0 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[7] budget 0.560000 ns (7,3) -> (7,4) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_1$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 11.3 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_1$CARRY.COUT Info: 0.0 11.3 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[8] budget 0.000000 ns (7,4) -> (7,4) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 11.6 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO$CARRY.COUT Info: 0.0 11.6 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[9] budget 0.000000 ns (7,4) -> (7,4) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_29$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 11.8 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_29$CARRY.COUT Info: 0.0 11.8 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[10] budget 0.000000 ns (7,4) -> (7,4) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_28$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 12.1 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_28$CARRY.COUT Info: 0.0 12.1 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[11] budget 0.000000 ns (7,4) -> (7,4) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_27$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 12.4 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_27$CARRY.COUT Info: 0.0 12.4 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[12] budget 0.000000 ns (7,4) -> (7,4) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_26$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 12.7 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_26$CARRY.COUT Info: 0.0 12.7 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[13] budget 0.000000 ns (7,4) -> (7,4) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_25$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 12.9 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_25$CARRY.COUT Info: 0.0 12.9 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[14] budget 0.000000 ns (7,4) -> (7,4) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_24$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 13.2 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_24$CARRY.COUT Info: 0.6 13.8 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[15] budget 0.560000 ns (7,4) -> (7,5) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_23$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 14.1 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_23$CARRY.COUT Info: 0.0 14.1 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[16] budget 0.000000 ns (7,5) -> (7,5) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_22$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 14.3 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_22$CARRY.COUT Info: 0.0 14.3 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[17] budget 0.000000 ns (7,5) -> (7,5) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_21$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 14.6 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_21$CARRY.COUT Info: 0.0 14.6 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[18] budget 0.000000 ns (7,5) -> (7,5) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_20$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 14.9 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_20$CARRY.COUT Info: 0.0 14.9 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[19] budget 0.000000 ns (7,5) -> (7,5) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_18$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 15.2 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_18$CARRY.COUT Info: 0.0 15.2 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[20] budget 0.000000 ns (7,5) -> (7,5) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_17$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 15.4 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_17$CARRY.COUT Info: 0.0 15.4 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[21] budget 0.000000 ns (7,5) -> (7,5) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_16$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 15.7 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_16$CARRY.COUT Info: 0.0 15.7 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[22] budget 0.000000 ns (7,5) -> (7,5) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_15$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 16.0 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_15$CARRY.COUT Info: 0.6 16.6 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[23] budget 0.560000 ns (7,5) -> (7,6) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_14$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 16.8 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_14$CARRY.COUT Info: 0.0 16.8 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[24] budget 0.000000 ns (7,6) -> (7,6) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_13$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 17.1 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_13$CARRY.COUT Info: 0.0 17.1 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[25] budget 0.000000 ns (7,6) -> (7,6) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_12$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 17.4 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_12$CARRY.COUT Info: 0.0 17.4 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[26] budget 0.000000 ns (7,6) -> (7,6) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_11$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 17.7 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_11$CARRY.COUT Info: 0.0 17.7 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[27] budget 0.000000 ns (7,6) -> (7,6) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_10$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 18.0 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_10$CARRY.COUT Info: 0.0 18.0 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[28] budget 0.000000 ns (7,6) -> (7,6) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_9$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 18.2 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_9$CARRY.COUT Info: 0.0 18.2 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[29] budget 0.000000 ns (7,6) -> (7,6) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_7$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 18.5 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_7$CARRY.COUT Info: 0.0 18.5 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[30] budget 0.000000 ns (7,6) -> (7,6) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 18.8 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_LC.COUT Info: 1.2 20.0 Net $nextpnr_ICESTORM_LC_28$I3 budget 1.220000 ns (7,6) -> (7,7) Info: Sink $nextpnr_ICESTORM_LC_28.I3 Info: 0.9 20.9 Source $nextpnr_ICESTORM_LC_28.O Info: 1.8 22.6 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[31] budget 1.211000 ns (7,7) -> (7,6) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_LC.I0 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:37.23-37.25 Info: 1.3 23.9 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_LC.O Info: 2.3 26.2 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2[3] budget 3.895000 ns (7,6) -> (5,6) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_LC.I3 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.9 27.1 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_LC.O Info: 1.8 28.9 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_O[0] budget 2.337000 ns (5,6) -> (4,7) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_O_SB_LUT4_I1_LC.I1 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 1.2 30.1 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_O_SB_LUT4_I1_LC.O Info: 1.8 31.9 Net soc_I.cpu_I.mem_do_rinst_SB_DFFSS_Q_S_SB_LUT4_O_I0[0] budget 1.948000 ns (4,7) -> (3,6) Info: Sink soc_I.cpu_I.mem_do_rinst_SB_DFFSS_Q_S_SB_LUT4_O_LC.I0 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 1.3 33.1 Source soc_I.cpu_I.mem_do_rinst_SB_DFFSS_Q_S_SB_LUT4_O_LC.O Info: 2.9 36.1 Net soc_I.cpu_I.mem_do_rinst_SB_DFFSS_Q_S budget 1.852000 ns (3,6) -> (2,5) Info: Sink soc_I.cpu_I.mem_do_rinst_SB_DFFSS_Q_D_SB_LUT4_O_LC.SR Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1375.2-1947.5 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: 0.1 36.2 Setup soc_I.cpu_I.mem_do_rinst_SB_DFFSS_Q_D_SB_LUT4_O_LC.SR Info: 16.9 ns logic, 19.3 ns routing Info: Critical path report for clock 'clk_48m' (posedge -> posedge): Info: curr total Info: 1.4 1.4 Source soc_I.usb_I.trans_I.trans_cel_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_LC.O Info: 1.8 3.2 Net soc_I.usb_I.trans_I.mc_a_reg[0] budget 1.276000 ns (20,12) -> (20,11) Info: Sink soc_I.usb_I.trans_I.mc_match_bits_SB_LUT4_O_3_LC.I2 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:82.14-82.22 Info: /build/gateware/common/rtl/soc_base.v:373.4-393.3 Info: 1.2 4.4 Source soc_I.usb_I.trans_I.mc_match_bits_SB_LUT4_O_3_LC.O Info: 1.8 6.1 Net soc_I.usb_I.trans_I.mc_match_bits[0] budget 1.062000 ns (20,11) -> (20,11) Info: Sink soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_I0_SB_LUT4_O_LC.I0 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:85.32-85.45 Info: /build/gateware/common/rtl/soc_base.v:373.4-393.3 Info: 1.3 7.4 Source soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_I0_SB_LUT4_O_LC.O Info: 2.3 9.7 Net soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_I0[0] budget 1.168000 ns (20,11) -> (18,11) Info: Sink soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_LC.I0 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 1.3 11.0 Source soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_LC.O Info: 1.8 12.8 Net soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_O[2] budget 1.168000 ns (18,11) -> (18,10) Info: Sink soc_I.usb_I.trans_I.mc_pc_SB_LUT4_O_7_LC.I2 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 1.2 14.0 Source soc_I.usb_I.trans_I.mc_pc_SB_LUT4_O_7_LC.O Info: 1.8 15.7 Net soc_I.usb_I.trans_I.mc_pc[0] budget 1.168000 ns (18,10) -> (17,11) Info: Sink $nextpnr_ICESTORM_LC_121.I1 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:373.4-393.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.7 16.4 Source $nextpnr_ICESTORM_LC_121.COUT Info: 0.0 16.4 Net $nextpnr_ICESTORM_LC_121$O budget 0.000000 ns (17,11) -> (17,11) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_6_LC.CIN Info: 0.3 16.7 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_6_LC.COUT Info: 0.0 16.7 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[2] budget 0.000000 ns (17,11) -> (17,11) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_5_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:373.4-393.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 16.9 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_5_LC.COUT Info: 0.0 16.9 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[3] budget 0.000000 ns (17,11) -> (17,11) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_4_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:373.4-393.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 17.2 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_4_LC.COUT Info: 0.0 17.2 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[4] budget 0.000000 ns (17,11) -> (17,11) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_3_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:373.4-393.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 17.5 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_3_LC.COUT Info: 0.0 17.5 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[5] budget 0.000000 ns (17,11) -> (17,11) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_2_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:373.4-393.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 17.8 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_2_LC.COUT Info: 0.0 17.8 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[6] budget 0.000000 ns (17,11) -> (17,11) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_1_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:373.4-393.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 18.1 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_1_LC.COUT Info: 0.7 18.7 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[7] budget 0.660000 ns (17,11) -> (17,11) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_LC.I3 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:373.4-393.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.8 19.5 Setup soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_LC.I3 Info: 9.5 ns logic, 10.0 ns routing Info: Critical path report for cross-domain path '<async>' -> 'posedge clk_sys': Info: curr total Info: 0.0 0.0 Source spi_io_I[1].D_IN_0 Info: 8.2 8.2 Net flash_miso_i budget 40.166000 ns (23,0) -> (0,0) Info: Sink soc_I.spi_I.spi_I.MI Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2ice40//rtl/ice40_spi_wb.v:34.21-34.31 Info: /build/gateware/common/rtl/soc_base.v:303.4-323.3 Info: 1.5 9.7 Setup soc_I.spi_I.spi_I.MI Info: 1.5 ns logic, 8.2 ns routing Info: Critical path report for cross-domain path 'posedge clk_48m' -> '<async>': Info: curr total Info: 1.4 1.4 Source soc_I.usb_I.pad_pu_SB_DFFSR_Q_DFFLC.O Info: 2.4 3.8 Net usb_pu$SB_IO_OUT budget 81.943001 ns (13,2) -> (13,0) Info: Sink usb_pu$sb_io.D_OUT_0 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:33.14-33.20 Info: 1.4 ns logic, 2.4 ns routing Info: Critical path report for cross-domain path 'posedge clk_48m' -> 'posedge clk_sys': Info: curr total Info: 1.4 1.4 Source soc_I.wb_48m_xclk_I.xclk_ack.src_SB_LUT4_I3_LC.O Info: 4.2 5.6 Net soc_I.wb_48m_xclk_I.xclk_ack.src budget 39.042000 ns (9,16) -> (13,6) Info: Sink soc_I.wb_48m_xclk_I.xclk_ack.dst_SB_DFFR_Q_1_DFFLC.I0 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2misc//rtl/xclk_wb.v:107.14-113.3 Info: /build/gateware/cores/no2misc//rtl/xclk_strobe.v:25.6-25.9 Info: /build/gateware/common/rtl/soc_base.v:399.4-415.3 Info: 1.2 6.9 Setup soc_I.wb_48m_xclk_I.xclk_ack.dst_SB_DFFR_Q_1_DFFLC.I0 Info: 2.6 ns logic, 4.2 ns routing Info: Critical path report for cross-domain path 'posedge clk_sys' -> '<async>': Info: curr total Info: 1.5 1.5 Source soc_I.spi_I.spi_I.MO Info: 8.3 9.8 Net flash_mosi_o budget 81.833000 ns (0,0) -> (23,0) Info: Sink spi_io_I[2].D_OUT_0 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2ice40//rtl/ice40_spi_wb.v:31.21-31.31 Info: /build/gateware/common/rtl/soc_base.v:303.4-323.3 Info: 1.5 ns logic, 8.3 ns routing Info: Critical path report for cross-domain path 'posedge clk_sys' -> 'posedge clk_48m': Info: curr total Info: 1.4 1.4 Source soc_I.cpu_I.mem_wstrb_SB_DFFE_Q_3_D_SB_LUT4_O_LC.O Info: 1.8 3.2 Net wb_wmsk[0] budget 3.993000 ns (11,7) -> (12,8) Info: Sink misc_I.wb_we_SB_LUT4_O_LC.I0 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:75.18-75.25 Info: 1.3 4.4 Source misc_I.wb_we_SB_LUT4_O_LC.O Info: 4.2 8.7 Net wb_we budget 4.794000 ns (12,8) -> (15,20) Info: Sink soc_I.usb_I.cel_rel_SB_DFFSR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_LC.I2 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:76.18-76.23 Info: 1.2 9.9 Source soc_I.usb_I.cel_rel_SB_DFFSR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_LC.O Info: 1.8 11.6 Net soc_I.usb_I.cel_rel_SB_DFFSR_Q_D_SB_LUT4_O_I2[1] budget 3.702000 ns (15,20) -> (16,21) Info: Sink soc_I.usb_I.cel_rel_SB_DFFSR_Q_D_SB_LUT4_O_LC.I2 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 1.2 12.8 Setup soc_I.usb_I.cel_rel_SB_DFFSR_Q_D_SB_LUT4_O_LC.I2 Info: 5.0 ns logic, 7.8 ns routing Info: Max frequency for clock 'clk_sys': 27.65 MHz (PASS at 24.00 MHz) Info: Max frequency for clock 'clk_48m': 51.17 MHz (PASS at 48.00 MHz) Info: Max delay <async> -> posedge clk_sys: 9.68 ns Info: Max delay posedge clk_48m -> <async> : 3.80 ns Info: Max delay posedge clk_48m -> posedge clk_sys: 6.87 ns Info: Max delay posedge clk_sys -> <async> : 9.76 ns Info: Max delay posedge clk_sys -> posedge clk_48m: 12.80 ns Info: Slack histogram: Info: legend: * represents 33 endpoint(s) Info: + represents [1,33) endpoint(s) Info: [ 1290, 5235) |+ Info: [ 5235, 9180) |****+ Info: [ 9180, 13125) |***********+ Info: [ 13125, 17070) |**********************************+ Info: [ 17070, 21015) |****+ Info: [ 21015, 24960) |***********+ Info: [ 24960, 28905) |*********************+ Info: [ 28905, 32850) |**********************************************+ Info: [ 32850, 36795) |************************************************************ Info: [ 36795, 40740) |***************************+ Info: [ 40740, 44685) | Info: [ 44685, 48630) | Info: [ 48630, 52575) | Info: [ 52575, 56520) | Info: [ 56520, 60465) | Info: [ 60465, 64410) | Info: [ 64410, 68355) | Info: [ 68355, 72300) | Info: [ 72300, 76245) |+ Info: [ 76245, 80190) |+ icepack -s /build/gateware/e1-tracer/build-tmp/e1-tracer.asc /build/gateware/e1-tracer/build-tmp/e1-tracer.bin make: Leaving directory '/build/gateware/e1-tracer' =============== gateware/icE1usb GATEWARE ============== make: Entering directory '/build/gateware/icE1usb' make: Leaving directory '/build/gateware/icE1usb' make: Entering directory '/build/gateware/icE1usb' /build/gateware/cores/no2usb//utils/microcode.py > /build/gateware/icE1usb/build-tmp/usb_trans_mc.hex cp -a /build/gateware/cores/no2usb//data/usb_ep_status.hex /build/gateware/icE1usb/build-tmp/usb_ep_status.hex cp ../common/fw/boot.hex /build/gateware/icE1usb/build-tmp/boot.hex cd /build/gateware/icE1usb/build-tmp && \ yosys -s /build/gateware/icE1usb/build-tmp/icE1usb.ys \ -l /build/gateware/icE1usb/build-tmp/icE1usb.synth.rpt /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9+3568 (open-tool-forge build) (git sha1 859e52af, gcc 9.3.0-10ubuntu2 -Os) -- Executing script file `/build/gateware/icE1usb/build-tmp/icE1usb.ys' -- 1. Executing Verilog-2005 frontend: /build/gateware/icE1usb/rtl/top.v Parsing Verilog input from `/build/gateware/icE1usb/rtl/top.v' to AST representation. Generating RTLIL representation for module `\top'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_crc4.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_crc4.v' to AST representation. Generating RTLIL representation for module `\e1_crc4'. Successfully finished Verilog frontend. 3. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v' to AST representation. Generating RTLIL representation for module `\e1_rx_clock_recovery'. Successfully finished Verilog frontend. 4. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v' to AST representation. Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:68) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:209) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:214) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:215) is not recognized unless read_verilog is called with -sv! Generating RTLIL representation for module `\e1_rx_deframer'. Successfully finished Verilog frontend. 5. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx_filter.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx_filter.v' to AST representation. Generating RTLIL representation for module `\e1_rx_filter'. Successfully finished Verilog frontend. 6. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx_phy.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx_phy.v' to AST representation. Generating RTLIL representation for module `\e1_rx_phy'. Successfully finished Verilog frontend. 7. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx_liu.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx_liu.v' to AST representation. Generating RTLIL representation for module `\e1_rx_liu'. Successfully finished Verilog frontend. 8. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx.v' to AST representation. Generating RTLIL representation for module `\e1_rx'. Successfully finished Verilog frontend. 9. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_tx_framer.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_tx_framer.v' to AST representation. Generating RTLIL representation for module `\e1_tx_framer'. Successfully finished Verilog frontend. 10. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_tx_phy.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_tx_phy.v' to AST representation. Generating RTLIL representation for module `\e1_tx_phy'. Successfully finished Verilog frontend. 11. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_tx_liu.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_tx_liu.v' to AST representation. Generating RTLIL representation for module `\e1_tx_liu'. Successfully finished Verilog frontend. 12. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_tx.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_tx.v' to AST representation. Generating RTLIL representation for module `\e1_tx'. Successfully finished Verilog frontend. 13. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v' to AST representation. Generating RTLIL representation for module `\e1_buf_if_wb'. Warning: Replacing memory \tx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:165 Warning: Replacing memory \tx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:145 Warning: Replacing memory \rx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:103 Warning: Replacing memory \rx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:102 Successfully finished Verilog frontend. 14. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_wb_rx.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_wb_rx.v' to AST representation. Generating RTLIL representation for module `\e1_wb_rx'. Successfully finished Verilog frontend. 15. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_wb_tx.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_wb_tx.v' to AST representation. Generating RTLIL representation for module `\e1_wb_tx'. Successfully finished Verilog frontend. 16. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_wb.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_wb.v' to AST representation. Generating RTLIL representation for module `\e1_wb'. Successfully finished Verilog frontend. 17. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/hdb3_dec.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/hdb3_dec.v' to AST representation. Generating RTLIL representation for module `\hdb3_dec'. Successfully finished Verilog frontend. 18. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/hdb3_enc.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/hdb3_enc.v' to AST representation. Generating RTLIL representation for module `\hdb3_enc'. Successfully finished Verilog frontend. 19. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_ebr.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_ebr.v' to AST representation. Generating RTLIL representation for module `\ice40_ebr'. Successfully finished Verilog frontend. 20. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_i2c_wb.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_i2c_wb.v' to AST representation. Generating RTLIL representation for module `\ice40_i2c_wb'. Successfully finished Verilog frontend. 21. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v' to AST representation. Generating RTLIL representation for module `\ice40_rgb_wb'. Successfully finished Verilog frontend. 22. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_spi_wb.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_spi_wb.v' to AST representation. Generating RTLIL representation for module `\ice40_spi_wb'. Successfully finished Verilog frontend. 23. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v' to AST representation. Generating RTLIL representation for module `\ice40_spram_gen'. ice40_spram_gen: (32768x32) -> 2x2 array of SPRAM Successfully finished Verilog frontend. 24. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v' to AST representation. Generating RTLIL representation for module `\ice40_spram_wb'. Successfully finished Verilog frontend. 25. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_iserdes.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_iserdes.v' to AST representation. Generating RTLIL representation for module `\ice40_iserdes'. Successfully finished Verilog frontend. 26. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_oserdes.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_oserdes.v' to AST representation. Generating RTLIL representation for module `\ice40_oserdes'. Successfully finished Verilog frontend. 27. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_serdes_crg.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_serdes_crg.v' to AST representation. Generating RTLIL representation for module `\ice40_serdes_crg'. Successfully finished Verilog frontend. 28. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_serdes_dff.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_serdes_dff.v' to AST representation. Generating RTLIL representation for module `\ice40_serdes_dff'. Successfully finished Verilog frontend. 29. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_serdes_sync.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_serdes_sync.v' to AST representation. Generating RTLIL representation for module `\ice40_serdes_sync'. Successfully finished Verilog frontend. 30. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/delay.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/delay.v' to AST representation. Generating RTLIL representation for module `\delay_bit'. Generating RTLIL representation for module `\delay_bus'. Warning: Replacing memory \dl with list of registers. See /build/gateware/cores/no2misc//rtl/delay.v:59 Generating RTLIL representation for module `\delay_toggle'. Successfully finished Verilog frontend. 31. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/fifo_sync_ram.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v' to AST representation. Generating RTLIL representation for module `\fifo_sync_ram'. Successfully finished Verilog frontend. 32. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/fifo_sync_shift.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v' to AST representation. Generating RTLIL representation for module `\fifo_sync_shift'. Successfully finished Verilog frontend. 33. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/glitch_filter.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/glitch_filter.v' to AST representation. Generating RTLIL representation for module `\glitch_filter'. Successfully finished Verilog frontend. 34. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/i2c_master.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/i2c_master.v' to AST representation. Generating RTLIL representation for module `\i2c_master'. Successfully finished Verilog frontend. 35. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/i2c_master_wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/i2c_master_wb.v' to AST representation. Generating RTLIL representation for module `\i2c_master_wb'. Successfully finished Verilog frontend. 36. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/muacm2wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/muacm2wb.v' to AST representation. Generating RTLIL representation for module `\muacm2wb'. Successfully finished Verilog frontend. 37. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/prims.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/prims.v' to AST representation. Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:31) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:75) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:117) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:150) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:186) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:237) is not recognized unless read_verilog is called with -sv! Generating RTLIL representation for module `\lut4_n'. Generating RTLIL representation for module `\lut4_carry_n'. Generating RTLIL representation for module `\dff_n'. Generating RTLIL representation for module `\dffe_n'. Generating RTLIL representation for module `\dffer_n'. Generating RTLIL representation for module `\dffesr_n'. Successfully finished Verilog frontend. 38. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/pdm.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/pdm.v' to AST representation. Warning: Yosys has only limited support for tri-state logic at the moment. (/build/gateware/cores/no2misc//rtl/pdm.v:91) Generating RTLIL representation for module `\pdm'. Generating RTLIL representation for module `\pdm_lfsr'. Successfully finished Verilog frontend. 39. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/pwm.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/pwm.v' to AST representation. Warning: Yosys has only limited support for tri-state logic at the moment. (/build/gateware/cores/no2misc//rtl/pwm.v:69) Generating RTLIL representation for module `\pwm'. Successfully finished Verilog frontend. 40. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/ram_sdp.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/ram_sdp.v' to AST representation. Generating RTLIL representation for module `\ram_sdp'. Successfully finished Verilog frontend. 41. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/stream2wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/stream2wb.v' to AST representation. Generating RTLIL representation for module `\stream2wb'. Successfully finished Verilog frontend. 42. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/uart2wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/uart2wb.v' to AST representation. Generating RTLIL representation for module `\uart2wb'. Successfully finished Verilog frontend. 43. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/uart_rx.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/uart_rx.v' to AST representation. Generating RTLIL representation for module `\uart_rx'. Successfully finished Verilog frontend. 44. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/uart_tx.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/uart_tx.v' to AST representation. Generating RTLIL representation for module `\uart_tx'. Successfully finished Verilog frontend. 45. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/uart_wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/uart_wb.v' to AST representation. Generating RTLIL representation for module `\uart_wb'. Successfully finished Verilog frontend. 46. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/xclk_strobe.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/xclk_strobe.v' to AST representation. Generating RTLIL representation for module `\xclk_strobe'. Successfully finished Verilog frontend. 47. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/xclk_wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/xclk_wb.v' to AST representation. Generating RTLIL representation for module `\xclk_wb'. Successfully finished Verilog frontend. 48. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb.v' to AST representation. Generating RTLIL representation for module `\usb'. Successfully finished Verilog frontend. 49. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_crc.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_crc.v' to AST representation. Generating RTLIL representation for module `\usb_crc'. Successfully finished Verilog frontend. 50. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_ep_buf.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_ep_buf.v' to AST representation. Generating RTLIL representation for module `\usb_ep_buf'. READ_MODE : 3 WRITE_MODE : 3 Successfully finished Verilog frontend. 51. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_ep_status.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_ep_status.v' to AST representation. Generating RTLIL representation for module `\usb_ep_status'. Successfully finished Verilog frontend. 52. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_phy.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_phy.v' to AST representation. Generating RTLIL representation for module `\usb_phy'. Successfully finished Verilog frontend. 53. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_rx_ll.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_rx_ll.v' to AST representation. Generating RTLIL representation for module `\usb_rx_ll'. Successfully finished Verilog frontend. 54. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_rx_pkt.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v' to AST representation. Generating RTLIL representation for module `\usb_rx_pkt'. Successfully finished Verilog frontend. 55. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_trans.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_trans.v' to AST representation. Generating RTLIL representation for module `\usb_trans'. Successfully finished Verilog frontend. 56. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_tx_ll.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_tx_ll.v' to AST representation. Generating RTLIL representation for module `\usb_tx_ll'. Successfully finished Verilog frontend. 57. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_tx_pkt.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v' to AST representation. Generating RTLIL representation for module `\usb_tx_pkt'. Successfully finished Verilog frontend. 58. Executing Verilog-2005 frontend: /build/gateware/icE1usb/rtl/led_blinker.v Parsing Verilog input from `/build/gateware/icE1usb/rtl/led_blinker.v' to AST representation. Generating RTLIL representation for module `\led_blinker'. Successfully finished Verilog frontend. 59. Executing Verilog-2005 frontend: /build/gateware/icE1usb/rtl/misc.v Parsing Verilog input from `/build/gateware/icE1usb/rtl/misc.v' to AST representation. Generating RTLIL representation for module `\misc'. Warning: Replacing memory \pdm_e1 with list of registers. See /build/gateware/icE1usb/rtl/misc.v:276 Warning: Replacing memory \pdm_clk with list of registers. See /build/gateware/icE1usb/rtl/misc.v:274 Warning: Replacing memory \tick_e1_sel with list of registers. See /build/gateware/icE1usb/rtl/misc.v:237 Successfully finished Verilog frontend. 60. Executing Verilog-2005 frontend: /build/gateware/icE1usb/rtl/sr_btn_if.v Parsing Verilog input from `/build/gateware/icE1usb/rtl/sr_btn_if.v' to AST representation. Generating RTLIL representation for module `\sr_btn_if'. Successfully finished Verilog frontend. 61. Executing Verilog-2005 frontend: /build/gateware/icE1usb/rtl/sysmgr.v Parsing Verilog input from `/build/gateware/icE1usb/rtl/sysmgr.v' to AST representation. Generating RTLIL representation for module `\sysmgr'. Successfully finished Verilog frontend. 62. Executing Verilog-2005 frontend: /build/gateware/common/rtl/capcnt.v Parsing Verilog input from `/build/gateware/common/rtl/capcnt.v' to AST representation. Generating RTLIL representation for module `\capcnt'. Successfully finished Verilog frontend. 63. Executing Verilog-2005 frontend: /build/gateware/common/rtl/capcnt_sb_mac16.v Parsing Verilog input from `/build/gateware/common/rtl/capcnt_sb_mac16.v' to AST representation. Generating RTLIL representation for module `\capcnt16_sb_mac16'. Generating RTLIL representation for module `\capcnt32_sb_mac16'. Successfully finished Verilog frontend. 64. Executing Verilog-2005 frontend: /build/gateware/common/rtl/dfu_helper.v Parsing Verilog input from `/build/gateware/common/rtl/dfu_helper.v' to AST representation. Generating RTLIL representation for module `\dfu_helper'. Successfully finished Verilog frontend. 65. Executing Verilog-2005 frontend: /build/gateware/common/rtl/picorv32.v Parsing Verilog input from `/build/gateware/common/rtl/picorv32.v' to AST representation. Generating RTLIL representation for module `\picorv32'. Generating RTLIL representation for module `\picorv32_regs'. Generating RTLIL representation for module `\picorv32_pcpi_mul'. Generating RTLIL representation for module `\picorv32_pcpi_fast_mul'. Generating RTLIL representation for module `\picorv32_pcpi_div'. Generating RTLIL representation for module `\picorv32_axi'. Generating RTLIL representation for module `\picorv32_axi_adapter'. Generating RTLIL representation for module `\picorv32_wb'. Successfully finished Verilog frontend. 66. Executing Verilog-2005 frontend: /build/gateware/common/rtl/picorv32_ice40_regs.v Parsing Verilog input from `/build/gateware/common/rtl/picorv32_ice40_regs.v' to AST representation. Generating RTLIL representation for module `\picorv32_ice40_regs'. Successfully finished Verilog frontend. 67. Executing Verilog-2005 frontend: /build/gateware/common/rtl/soc_base.v Parsing Verilog input from `/build/gateware/common/rtl/soc_base.v' to AST representation. Generating RTLIL representation for module `\soc_base'. Successfully finished Verilog frontend. 68. Executing Verilog-2005 frontend: /build/gateware/common/rtl/soc_bram.v Parsing Verilog input from `/build/gateware/common/rtl/soc_bram.v' to AST representation. Generating RTLIL representation for module `\soc_bram'. Successfully finished Verilog frontend. 69. Executing Verilog-2005 frontend: /build/gateware/common/rtl/soc_iobuf.v Parsing Verilog input from `/build/gateware/common/rtl/soc_iobuf.v' to AST representation. Generating RTLIL representation for module `\soc_iobuf'. Successfully finished Verilog frontend. 70. Executing Verilog-2005 frontend: /build/gateware/common/rtl/soc_picorv32_bridge.v Parsing Verilog input from `/build/gateware/common/rtl/soc_picorv32_bridge.v' to AST representation. Generating RTLIL representation for module `\soc_picorv32_bridge'. Successfully finished Verilog frontend. 71. Executing Verilog-2005 frontend: /build/gateware/common/rtl/soc_spram.v Parsing Verilog input from `/build/gateware/common/rtl/soc_spram.v' to AST representation. Generating RTLIL representation for module `\soc_spram'. Successfully finished Verilog frontend. 72. Executing Verilog-2005 frontend: /build/gateware/common/rtl/wb_arbiter.v Parsing Verilog input from `/build/gateware/common/rtl/wb_arbiter.v' to AST representation. Generating RTLIL representation for module `\wb_arbiter'. Successfully finished Verilog frontend. 73. Executing Verilog-2005 frontend: /build/gateware/common/rtl/wb_dma.v Parsing Verilog input from `/build/gateware/common/rtl/wb_dma.v' to AST representation. Generating RTLIL representation for module `\wb_dma'. Successfully finished Verilog frontend. 74. Executing Verilog-2005 frontend: /build/gateware/common/rtl/wb_epbuf.v Parsing Verilog input from `/build/gateware/common/rtl/wb_epbuf.v' to AST representation. Generating RTLIL representation for module `\wb_epbuf'. Successfully finished Verilog frontend. 75. Executing SYNTH_ICE40 pass. 75.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v' to AST representation. Generating RTLIL representation for module `\SB_IO'. Generating RTLIL representation for module `\SB_GB_IO'. Generating RTLIL representation for module `\SB_GB'. Generating RTLIL representation for module `\SB_LUT4'. Generating RTLIL representation for module `\SB_CARRY'. Generating RTLIL representation for module `\SB_DFF'. Generating RTLIL representation for module `\SB_DFFE'. Generating RTLIL representation for module `\SB_DFFSR'. Generating RTLIL representation for module `\SB_DFFR'. Generating RTLIL representation for module `\SB_DFFSS'. Generating RTLIL representation for module `\SB_DFFS'. Generating RTLIL representation for module `\SB_DFFESR'. Generating RTLIL representation for module `\SB_DFFER'. Generating RTLIL representation for module `\SB_DFFESS'. Generating RTLIL representation for module `\SB_DFFES'. Generating RTLIL representation for module `\SB_DFFN'. Generating RTLIL representation for module `\SB_DFFNE'. Generating RTLIL representation for module `\SB_DFFNSR'. Generating RTLIL representation for module `\SB_DFFNR'. Generating RTLIL representation for module `\SB_DFFNSS'. Generating RTLIL representation for module `\SB_DFFNS'. Generating RTLIL representation for module `\SB_DFFNESR'. Generating RTLIL representation for module `\SB_DFFNER'. Generating RTLIL representation for module `\SB_DFFNESS'. Generating RTLIL representation for module `\SB_DFFNES'. Generating RTLIL representation for module `\SB_RAM40_4K'. Generating RTLIL representation for module `\SB_RAM40_4KNR'. Generating RTLIL representation for module `\SB_RAM40_4KNW'. Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. Generating RTLIL representation for module `\ICESTORM_LC'. Generating RTLIL representation for module `\SB_PLL40_CORE'. Generating RTLIL representation for module `\SB_PLL40_PAD'. Generating RTLIL representation for module `\SB_PLL40_2_PAD'. Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. Generating RTLIL representation for module `\SB_WARMBOOT'. Generating RTLIL representation for module `\SB_SPRAM256KA'. Generating RTLIL representation for module `\SB_HFOSC'. Generating RTLIL representation for module `\SB_LFOSC'. Generating RTLIL representation for module `\SB_RGBA_DRV'. Generating RTLIL representation for module `\SB_LED_DRV_CUR'. Generating RTLIL representation for module `\SB_RGB_DRV'. Generating RTLIL representation for module `\SB_I2C'. Generating RTLIL representation for module `\SB_SPI'. Generating RTLIL representation for module `\SB_LEDDA_IP'. Generating RTLIL representation for module `\SB_FILTER_50NS'. Generating RTLIL representation for module `\SB_IO_I3C'. Generating RTLIL representation for module `\SB_IO_OD'. Generating RTLIL representation for module `\SB_MAC16'. Generating RTLIL representation for module `\ICESTORM_RAM'. Successfully finished Verilog frontend. 75.2. Executing HIERARCHY pass (managing design hierarchy). 75.2.1. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: \sr_btn_if Used module: \led_blinker Used module: \i2c_master_wb Used module: \i2c_master Used module: \uart_wb Used module: \fifo_sync_ram Used module: \ram_sdp Used module: \uart_rx Used module: \glitch_filter Used module: \uart_tx Used module: \misc Used module: \pdm Used module: \capcnt Used module: \capcnt16_sb_mac16 Used module: \dfu_helper Used module: \soc_base Used module: \e1_buf_if_wb Used module: \e1_wb Used module: \e1_wb_tx Used module: \e1_tx Used module: \e1_tx_phy Used module: \hdb3_enc Used module: \e1_tx_framer Used module: \e1_crc4 Used module: \fifo_sync_shift Used module: \e1_wb_rx Used module: \e1_rx Used module: \hdb3_dec Used module: \e1_rx_clock_recovery Used module: \e1_rx_filter Used module: \e1_rx_phy Used module: \e1_rx_deframer Used module: \soc_iobuf Used module: \wb_dma Used module: \wb_arbiter Used module: \wb_epbuf Used module: \ice40_spram_wb Used module: \ice40_spram_gen Used module: \xclk_strobe Used module: \xclk_wb Used module: \usb Used module: \usb_ep_status Used module: \usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: \usb_crc Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: \usb_phy Used module: \ice40_rgb_wb Used module: \ice40_spi_wb Used module: \soc_spram Used module: \soc_bram Used module: \soc_picorv32_bridge Used module: \picorv32 Used module: \picorv32_ice40_regs Used module: \ice40_ebr Parameter \TICK_LOG2_DIV = 3 75.2.2. Executing AST frontend in derive mode using pre-parsed AST for module `\sr_btn_if'. Parameter \TICK_LOG2_DIV = 3 Generating RTLIL representation for module `$paramod\sr_btn_if\TICK_LOG2_DIV=3'. Parameter \DW = 4 Parameter \FIFO_DEPTH = 0 75.2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\i2c_master_wb'. Parameter \DW = 4 Parameter \FIFO_DEPTH = 0 Generating RTLIL representation for module `$paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0'. Parameter \DIV_WIDTH = 12 Parameter \DW = 32 75.2.4. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_wb'. Parameter \DIV_WIDTH = 12 Parameter \DW = 32 Generating RTLIL representation for module `$paramod\uart_wb\DIV_WIDTH=12\DW=32'. Parameter \WB_N = 3 Parameter \E1_N = 2 Parameter \E1_UNIT_HAS_RX = 2'01 Parameter \E1_UNIT_HAS_TX = 2'01 Parameter \E1_LIU = 0 75.2.5. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_base'. Parameter \WB_N = 3 Parameter \E1_N = 2 Parameter \E1_UNIT_HAS_RX = 2'01 Parameter \E1_UNIT_HAS_TX = 2'01 Parameter \E1_LIU = 0 Generating RTLIL representation for module `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base'. Parameter \N = 1 Parameter \UNIT_HAS_RX = 1'1 Parameter \UNIT_HAS_TX = 1'1 Parameter \MFW = 7 Parameter \DW = 32 75.2.6. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_buf_if_wb'. Parameter \N = 1 Parameter \UNIT_HAS_RX = 1'1 Parameter \UNIT_HAS_TX = 1'1 Parameter \MFW = 7 Parameter \DW = 32 Generating RTLIL representation for module `$paramod\e1_buf_if_wb\N=1\UNIT_HAS_RX=1'1\UNIT_HAS_TX=1'1\MFW=7\DW=32'. Warning: Replacing memory \tx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:165 Warning: Replacing memory \tx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:145 Warning: Replacing memory \rx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:103 Warning: Replacing memory \rx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:102 Parameter \N = 1 Parameter \UNIT_HAS_RX = 1'1 Parameter \UNIT_HAS_TX = 1'1 Parameter \LIU = 0 Parameter \MFW = 7 75.2.7. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_wb'. Parameter \N = 1 Parameter \UNIT_HAS_RX = 1'1 Parameter \UNIT_HAS_TX = 1'1 Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_wb\N=1\UNIT_HAS_RX=1'1\UNIT_HAS_TX=1'1\LIU=0\MFW=7'. Parameter \DW = 16 Parameter \AW = 12 75.2.8. Executing AST frontend in derive mode using pre-parsed AST for module `\xclk_wb'. Parameter \DW = 16 Parameter \AW = 12 Generating RTLIL representation for module `$paramod\xclk_wb\DW=16\AW=12'. Parameter \EPDW = 32 75.2.9. Executing AST frontend in derive mode using pre-parsed AST for module `\usb'. Parameter \EPDW = 32 Generating RTLIL representation for module `$paramod\usb\EPDW=32'. Parameter \CURRENT_MODE = 24'001100000110001000110001 Parameter \RGB0_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB1_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB2_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 75.2.10. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_rgb_wb'. Parameter \CURRENT_MODE = 24'001100000110001000110001 Parameter \RGB0_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB1_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB2_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Generating RTLIL representation for module `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb'. Parameter \DIV_WIDTH = 12 Parameter \DW = 32 Found cached RTLIL representation for module `$paramod\uart_wb\DIV_WIDTH=12\DW=32'. Parameter \N_CS = 1 Parameter \WITH_IOB = 0 Parameter \UNIT = 0 75.2.11. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_spi_wb'. Parameter \N_CS = 1 Parameter \WITH_IOB = 0 Parameter \UNIT = 0 Generating RTLIL representation for module `$paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0'. Parameter \AW = 14 75.2.12. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_spram'. Parameter \AW = 14 Generating RTLIL representation for module `$paramod\soc_spram\AW=14'. Parameter \AW = 8 Parameter \INIT_FILE = 64'0110001001101111011011110111010000101110011010000110010101111000 75.2.13. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_bram'. Parameter \AW = 8 Parameter \INIT_FILE = 64'0110001001101111011011110111010000101110011010000110010101111000 Generating RTLIL representation for module `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram'. Parameter \WB_N = 9 Parameter \WB_DW = 32 Parameter \WB_AW = 16 Parameter \WB_AI = 2 Parameter \WB_REG = 4 75.2.14. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_picorv32_bridge'. Parameter \WB_N = 9 Parameter \WB_DW = 32 Parameter \WB_AW = 16 Parameter \WB_AI = 2 Parameter \WB_REG = 4 Generating RTLIL representation for module `$paramod\soc_picorv32_bridge\WB_N=9\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4'. Parameter \ENABLE_COUNTERS = 0 Parameter \BARREL_SHIFTER = 0 Parameter \TWO_CYCLE_COMPARE = 0 Parameter \TWO_CYCLE_ALU = 1 Parameter \COMPRESSED_ISA = 0 Parameter \CATCH_MISALIGN = 0 Parameter \CATCH_ILLINSN = 0 Parameter \ENABLE_MUL = 0 Parameter \ENABLE_DIV = 0 Parameter \ENABLE_IRQ = 0 Parameter \ENABLE_IRQ_QREGS = 0 Parameter \PROGADDR_RESET = 0 Parameter \STACKADDR = 1024 75.2.15. Executing AST frontend in derive mode using pre-parsed AST for module `\picorv32'. Parameter \ENABLE_COUNTERS = 0 Parameter \BARREL_SHIFTER = 0 Parameter \TWO_CYCLE_COMPARE = 0 Parameter \TWO_CYCLE_ALU = 1 Parameter \COMPRESSED_ISA = 0 Parameter \CATCH_MISALIGN = 0 Parameter \CATCH_ILLINSN = 0 Parameter \ENABLE_MUL = 0 Parameter \ENABLE_DIV = 0 Parameter \ENABLE_IRQ = 0 Parameter \ENABLE_IRQ_QREGS = 0 Parameter \PROGADDR_RESET = 0 Parameter \STACKADDR = 1024 Generating RTLIL representation for module `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32'. Parameter \WIDTH = 8 Parameter \DITHER = 16'0100111001001111 Parameter \PHY = 40'0100100101000011010001010011010000110000 75.2.16. Executing AST frontend in derive mode using pre-parsed AST for module `\pdm'. Parameter \WIDTH = 8 Parameter \DITHER = 16'0100111001001111 Parameter \PHY = 40'0100100101000011010001010011010000110000 Generating RTLIL representation for module `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm'. Parameter \WIDTH = 8 Parameter \DITHER = 16'0100111001001111 Parameter \PHY = 40'0100100101000011010001010011010000110000 Found cached RTLIL representation for module `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm'. Parameter \WIDTH = 12 Parameter \DITHER = 24'010110010100010101010011 Parameter \PHY = 40'0100100101000011010001010011010000110000 75.2.17. Executing AST frontend in derive mode using pre-parsed AST for module `\pdm'. Parameter \WIDTH = 12 Parameter \DITHER = 24'010110010100010101010011 Parameter \PHY = 40'0100100101000011010001010011010000110000 Generating RTLIL representation for module `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm'. Parameter \WIDTH = 12 Parameter \DITHER = 24'010110010100010101010011 Parameter \PHY = 40'0100100101000011010001010011010000110000 Found cached RTLIL representation for module `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm'. Parameter \W = 16 75.2.18. Executing AST frontend in derive mode using pre-parsed AST for module `\capcnt'. Parameter \W = 16 Generating RTLIL representation for module `$paramod\capcnt\W=16'. Parameter \W = 16 Found cached RTLIL representation for module `$paramod\capcnt\W=16'. Parameter \TIMER_WIDTH = 26 Parameter \BTN_MODE = 0 Parameter \DFU_MODE = 0 75.2.19. Executing AST frontend in derive mode using pre-parsed AST for module `\dfu_helper'. Parameter \TIMER_WIDTH = 26 Parameter \BTN_MODE = 0 Parameter \DFU_MODE = 0 Generating RTLIL representation for module `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0'. Parameter \W = 32 75.2.20. Executing AST frontend in derive mode using pre-parsed AST for module `\capcnt'. Parameter \W = 32 Generating RTLIL representation for module `$paramod\capcnt\W=32'. Parameter \L = 2 Parameter \RST_VAL = 1'0 Parameter \WITH_SYNCHRONIZER = 1 75.2.21. Executing AST frontend in derive mode using pre-parsed AST for module `\glitch_filter'. Parameter \L = 2 Parameter \RST_VAL = 1'0 Parameter \WITH_SYNCHRONIZER = 1 Generating RTLIL representation for module `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1'. Parameter \DEPTH = 512 Parameter \WIDTH = 8 75.2.22. Executing AST frontend in derive mode using pre-parsed AST for module `\fifo_sync_ram'. Parameter \DEPTH = 512 Parameter \WIDTH = 8 Generating RTLIL representation for module `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8'. Parameter \DIV_WIDTH = 8 Parameter \GLITCH_FILTER = 2 75.2.23. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'. Parameter \DIV_WIDTH = 8 Parameter \GLITCH_FILTER = 2 Generating RTLIL representation for module `$paramod\uart_rx\DIV_WIDTH=8\GLITCH_FILTER=2'. Parameter \DEPTH = 512 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8'. Parameter \DIV_WIDTH = 8 75.2.24. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'. Parameter \DIV_WIDTH = 8 Generating RTLIL representation for module `$paramod\uart_tx\DIV_WIDTH=8'. Parameter \L = 2 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 75.2.25. Executing AST frontend in derive mode using pre-parsed AST for module `\glitch_filter'. Parameter \L = 2 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Generating RTLIL representation for module `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1'. Parameter \DW = 3 Parameter \TW = 0 Parameter \CLOCK_STRETCH = 0 75.2.26. Executing AST frontend in derive mode using pre-parsed AST for module `\i2c_master'. Parameter \DW = 3 Parameter \TW = 0 Parameter \CLOCK_STRETCH = 0 Generating RTLIL representation for module `$paramod\i2c_master\DW=3\TW=0\CLOCK_STRETCH=0'. Parameter \LIU = 0 Parameter \MFW = 7 75.2.27. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_rx'. Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_rx\LIU=0\MFW=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 75.2.28. Executing AST frontend in derive mode using pre-parsed AST for module `\fifo_sync_shift'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 Generating RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 75.2.29. Executing AST frontend in derive mode using pre-parsed AST for module `\fifo_sync_shift'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 Generating RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7'. Parameter \LIU = 0 Parameter \MFW = 7 75.2.30. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_tx'. Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_tx\LIU=0\MFW=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9'. Parameter \LIU = 0 Parameter \MFW = 7 75.2.31. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_wb_tx'. Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_wb_tx\LIU=0\MFW=7'. Parameter \LIU = 0 Parameter \MFW = 7 75.2.32. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_wb_rx'. Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_wb_rx\LIU=0\MFW=7'. Parameter \ADDR_WIDTH = 14 Parameter \DATA_WIDTH = 32 75.2.33. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_spram_gen'. Parameter \ADDR_WIDTH = 14 Parameter \DATA_WIDTH = 32 Generating RTLIL representation for module `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32'. ice40_spram_gen: (16384x32) -> 1x2 array of SPRAM Parameter \AWIDTH = 8 Parameter \DWIDTH = 16 75.2.34. Executing AST frontend in derive mode using pre-parsed AST for module `\ram_sdp'. Parameter \AWIDTH = 8 Parameter \DWIDTH = 16 Generating RTLIL representation for module `$paramod\ram_sdp\AWIDTH=8\DWIDTH=16'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 16 Parameter \WWIDTH = 8 75.2.35. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_ep_buf'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 16 Parameter \WWIDTH = 8 Generating RTLIL representation for module `$paramod$7d82212fad3e4929db14b64ca83adffce21ba555\usb_ep_buf'. READ_MODE : 2 WRITE_MODE : 3 Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 8 Parameter \WWIDTH = 16 75.2.36. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_ep_buf'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 8 Parameter \WWIDTH = 16 Generating RTLIL representation for module `$paramod$e9a8417cc0e9fc03e370009e77135e9e1e2b5499\usb_ep_buf'. READ_MODE : 3 WRITE_MODE : 2 Parameter \TARGET = 40'0100100101000011010001010011010000110000 75.2.37. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_phy'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Generating RTLIL representation for module `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000'. Parameter \WIDTH = 16 Parameter \POLY = 16'1000000000000101 Parameter \MATCH = 16'1000000000001101 75.2.38. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_crc'. Parameter \WIDTH = 16 Parameter \POLY = 16'1000000000000101 Parameter \MATCH = 16'1000000000001101 Generating RTLIL representation for module `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101'. Parameter \WIDTH = 16 Parameter \POLY = 16'1000000000000101 Parameter \MATCH = 16'1000000000001101 Found cached RTLIL representation for module `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101'. Parameter \WIDTH = 5 Parameter \POLY = 5'00101 Parameter \MATCH = 5'01100 75.2.39. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_crc'. Parameter \WIDTH = 5 Parameter \POLY = 5'00101 Parameter \MATCH = 5'01100 Generating RTLIL representation for module `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100'. Parameter \L = 4 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Parameter \WITH_SAMP_COND = 1'0 75.2.40. Executing AST frontend in derive mode using pre-parsed AST for module `\glitch_filter'. Parameter \L = 4 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Parameter \WITH_SAMP_COND = 1'0 Generating RTLIL representation for module `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0'. Parameter \READ_MODE = 0 Parameter \WRITE_MODE = 0 Parameter \MASK_WORKAROUND = 0 Parameter \NEG_WR_CLK = 0 Parameter \NEG_RD_CLK = 1 75.2.41. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_ebr'. Parameter \READ_MODE = 0 Parameter \WRITE_MODE = 0 Parameter \MASK_WORKAROUND = 0 Parameter \NEG_WR_CLK = 0 Parameter \NEG_RD_CLK = 1 Generating RTLIL representation for module `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr'. Parameter \READ_MODE = 0 Parameter \WRITE_MODE = 0 Parameter \MASK_WORKAROUND = 0 Parameter \NEG_WR_CLK = 0 Parameter \NEG_RD_CLK = 1 Found cached RTLIL representation for module `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr'. Parameter \READ_MODE = 0 Parameter \WRITE_MODE = 0 Parameter \MASK_WORKAROUND = 0 Parameter \NEG_WR_CLK = 0 Parameter \NEG_RD_CLK = 1 Found cached RTLIL representation for module `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr'. Parameter \READ_MODE = 0 Parameter \WRITE_MODE = 0 Parameter \MASK_WORKAROUND = 0 Parameter \NEG_WR_CLK = 0 Parameter \NEG_RD_CLK = 1 Found cached RTLIL representation for module `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr'. Parameter \ADDR_WIDTH = 14 Parameter \DATA_WIDTH = 32 Found cached RTLIL representation for module `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32'. Parameter \A0W = 14 Parameter \A1W = 9 Parameter \DW = 32 75.2.42. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_dma'. Parameter \A0W = 14 Parameter \A1W = 9 Parameter \DW = 32 Generating RTLIL representation for module `$paramod\wb_dma\A0W=14\A1W=9\DW=32'. Parameter \N = 2 Parameter \DW = 32 Parameter \AW = 9 75.2.43. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_arbiter'. Parameter \N = 2 Parameter \DW = 32 Parameter \AW = 9 Generating RTLIL representation for module `$paramod\wb_arbiter\N=2\DW=32\AW=9'. Parameter \AW = 9 Parameter \DW = 32 75.2.44. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_epbuf'. Parameter \AW = 9 Parameter \DW = 32 Generating RTLIL representation for module `$paramod\wb_epbuf\AW=9\DW=32'. Parameter \N = 3 Parameter \DW = 32 Parameter \AW = 14 75.2.45. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_arbiter'. Parameter \N = 3 Parameter \DW = 32 Parameter \AW = 14 Generating RTLIL representation for module `$paramod\wb_arbiter\N=3\DW=32\AW=14'. Parameter \AW = 14 Parameter \DW = 32 Parameter \ZERO_RDATA = 0 75.2.46. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_spram_wb'. Parameter \AW = 14 Parameter \DW = 32 Parameter \ZERO_RDATA = 0 Generating RTLIL representation for module `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0'. 75.2.47. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: $paramod\sr_btn_if\TICK_LOG2_DIV=3 Used module: \led_blinker Used module: $paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0 Used module: \i2c_master Used module: $paramod\uart_wb\DIV_WIDTH=12\DW=32 Used module: \fifo_sync_ram Used module: $paramod\ram_sdp\AWIDTH=8\DWIDTH=16 Used module: \uart_rx Used module: $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1 Used module: \uart_tx Used module: \misc Used module: $paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm Used module: $paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm Used module: \pdm_lfsr Used module: $paramod\capcnt\W=16 Used module: \capcnt16_sb_mac16 Used module: $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0 Used module: \glitch_filter Used module: $paramod\capcnt\W=32 Used module: \capcnt32_sb_mac16 Used module: $paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1 Used module: $paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base Used module: \e1_buf_if_wb Used module: \e1_wb Used module: $paramod\e1_wb_tx\LIU=0\MFW=7 Used module: \e1_tx Used module: \e1_tx_phy Used module: \hdb3_enc Used module: \e1_tx_framer Used module: \e1_crc4 Used module: \fifo_sync_shift Used module: $paramod\e1_wb_rx\LIU=0\MFW=7 Used module: \e1_rx Used module: \hdb3_dec Used module: \e1_rx_clock_recovery Used module: \e1_rx_filter Used module: \e1_rx_phy Used module: \e1_rx_deframer Used module: \soc_iobuf Used module: $paramod\wb_dma\A0W=14\A1W=9\DW=32 Used module: $paramod\wb_arbiter\N=2\DW=32\AW=9 Used module: $paramod\wb_epbuf\AW=9\DW=32 Used module: $paramod\wb_arbiter\N=3\DW=32\AW=14 Used module: $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0 Used module: \ice40_spram_gen Used module: \xclk_strobe Used module: \xclk_wb Used module: \usb Used module: \usb_ep_status Used module: $paramod$7d82212fad3e4929db14b64ca83adffce21ba555\usb_ep_buf Used module: $paramod$e9a8417cc0e9fc03e370009e77135e9e1e2b5499\usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101 Used module: $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100 Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000 Used module: \ice40_rgb_wb Used module: \uart_wb Used module: $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8 Used module: \ram_sdp Used module: $paramod\uart_rx\DIV_WIDTH=8\GLITCH_FILTER=2 Used module: $paramod\uart_tx\DIV_WIDTH=8 Used module: \ice40_spi_wb Used module: \soc_spram Used module: $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32 Used module: \soc_bram Used module: \soc_picorv32_bridge Used module: \picorv32 Used module: \picorv32_ice40_regs Used module: $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr Parameter \L = 4 Parameter \RST_VAL = 1'0 Parameter \WITH_SYNCHRONIZER = 1 Parameter \WITH_SAMP_COND = 1'0 75.2.48. Executing AST frontend in derive mode using pre-parsed AST for module `\glitch_filter'. Parameter \L = 4 Parameter \RST_VAL = 1'0 Parameter \WITH_SYNCHRONIZER = 1 Parameter \WITH_SAMP_COND = 1'0 Generating RTLIL representation for module `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0'. Parameter \WIDTH = 8 Parameter \POLY = 8'01110001 75.2.49. Executing AST frontend in derive mode using pre-parsed AST for module `\pdm_lfsr'. Parameter \WIDTH = 8 Parameter \POLY = 8'01110001 Generating RTLIL representation for module `$paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001'. Parameter \DW = 4 Parameter \TW = 0 Parameter \CLOCK_STRETCH = 0 75.2.50. Executing AST frontend in derive mode using pre-parsed AST for module `\i2c_master'. Parameter \DW = 4 Parameter \TW = 0 Parameter \CLOCK_STRETCH = 0 Generating RTLIL representation for module `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0'. Parameter \DEPTH = 512 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8'. Parameter \DIV_WIDTH = 12 Parameter \GLITCH_FILTER = 2 75.2.51. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'. Parameter \DIV_WIDTH = 12 Parameter \GLITCH_FILTER = 2 Generating RTLIL representation for module `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2'. Parameter \DEPTH = 512 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8'. Parameter \DIV_WIDTH = 12 75.2.52. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'. Parameter \DIV_WIDTH = 12 Generating RTLIL representation for module `$paramod\uart_tx\DIV_WIDTH=12'. Parameter \N = 2 Parameter \UNIT_HAS_RX = 2'01 Parameter \UNIT_HAS_TX = 2'01 Parameter \MFW = 7 Parameter \DW = 32 75.2.53. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_buf_if_wb'. Parameter \N = 2 Parameter \UNIT_HAS_RX = 2'01 Parameter \UNIT_HAS_TX = 2'01 Parameter \MFW = 7 Parameter \DW = 32 Generating RTLIL representation for module `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32'. Warning: Replacing memory \tx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:165 Warning: Replacing memory \tx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:145 Warning: Replacing memory \rx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:103 Warning: Replacing memory \rx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:102 Parameter \N = 2 Parameter \UNIT_HAS_RX = 2'01 Parameter \UNIT_HAS_TX = 2'01 Parameter \LIU = 0 Parameter \MFW = 7 75.2.54. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_wb'. Parameter \N = 2 Parameter \UNIT_HAS_RX = 2'01 Parameter \UNIT_HAS_TX = 2'01 Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7'. Parameter \DW = 16 Parameter \AW = 12 Found cached RTLIL representation for module `$paramod\xclk_wb\DW=16\AW=12'. Parameter \EPDW = 32 Found cached RTLIL representation for module `$paramod\usb\EPDW=32'. Parameter \CURRENT_MODE = 24'001100000110001000110001 Parameter \RGB0_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB1_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB2_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Found cached RTLIL representation for module `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb'. Parameter \DIV_WIDTH = 12 Parameter \DW = 32 Found cached RTLIL representation for module `$paramod\uart_wb\DIV_WIDTH=12\DW=32'. Parameter \N_CS = 1 Parameter \WITH_IOB = 0 Parameter \UNIT = 0 Found cached RTLIL representation for module `$paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0'. Parameter \AW = 14 Found cached RTLIL representation for module `$paramod\soc_spram\AW=14'. Parameter \AW = 8 Parameter \INIT_FILE = 64'0110001001101111011011110111010000101110011010000110010101111000 Found cached RTLIL representation for module `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram'. Parameter \WB_N = 11 Parameter \WB_DW = 32 Parameter \WB_AW = 16 Parameter \WB_AI = 2 Parameter \WB_REG = 4 75.2.55. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_picorv32_bridge'. Parameter \WB_N = 11 Parameter \WB_DW = 32 Parameter \WB_AW = 16 Parameter \WB_AI = 2 Parameter \WB_REG = 4 Generating RTLIL representation for module `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4'. Parameter \ENABLE_COUNTERS = 0 Parameter \BARREL_SHIFTER = 0 Parameter \TWO_CYCLE_COMPARE = 0 Parameter \TWO_CYCLE_ALU = 1 Parameter \COMPRESSED_ISA = 0 Parameter \CATCH_MISALIGN = 0 Parameter \CATCH_ILLINSN = 0 Parameter \ENABLE_MUL = 0 Parameter \ENABLE_DIV = 0 Parameter \ENABLE_IRQ = 0 Parameter \ENABLE_IRQ_QREGS = 0 Parameter \PROGADDR_RESET = 0 Parameter \STACKADDR = 1024 Found cached RTLIL representation for module `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32'. Parameter \AWIDTH = 9 Parameter \DWIDTH = 8 75.2.56. Executing AST frontend in derive mode using pre-parsed AST for module `\ram_sdp'. Parameter \AWIDTH = 9 Parameter \DWIDTH = 8 Generating RTLIL representation for module `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8'. Parameter \L = 2 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Found cached RTLIL representation for module `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1'. Parameter \LIU = 0 Parameter \MFW = 7 Found cached RTLIL representation for module `$paramod\e1_tx\LIU=0\MFW=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9'. Parameter \LIU = 0 Parameter \MFW = 7 Found cached RTLIL representation for module `$paramod\e1_rx\LIU=0\MFW=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7'. Parameter \ADDR_WIDTH = 14 Parameter \DATA_WIDTH = 32 Found cached RTLIL representation for module `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32'. 75.2.57. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: $paramod\sr_btn_if\TICK_LOG2_DIV=3 Used module: \led_blinker Used module: $paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0 Used module: $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0 Used module: $paramod\uart_wb\DIV_WIDTH=12\DW=32 Used module: $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8 Used module: $paramod\ram_sdp\AWIDTH=9\DWIDTH=8 Used module: $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2 Used module: \glitch_filter Used module: $paramod\uart_tx\DIV_WIDTH=12 Used module: \misc Used module: $paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm Used module: $paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm Used module: $paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001 Used module: $paramod\capcnt\W=16 Used module: \capcnt16_sb_mac16 Used module: $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0 Used module: $paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0 Used module: $paramod\capcnt\W=32 Used module: \capcnt32_sb_mac16 Used module: $paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1 Used module: $paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base Used module: $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32 Used module: $paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7 Used module: \e1_wb_tx Used module: $paramod\e1_tx\LIU=0\MFW=7 Used module: \e1_tx_phy Used module: \hdb3_enc Used module: \e1_tx_framer Used module: \e1_crc4 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9 Used module: \e1_wb_rx Used module: $paramod\e1_rx\LIU=0\MFW=7 Used module: \hdb3_dec Used module: \e1_rx_clock_recovery Used module: \e1_rx_filter Used module: \e1_rx_phy Used module: \e1_rx_deframer Used module: \soc_iobuf Used module: $paramod\wb_dma\A0W=14\A1W=9\DW=32 Used module: $paramod\wb_arbiter\N=2\DW=32\AW=9 Used module: $paramod\wb_epbuf\AW=9\DW=32 Used module: $paramod\wb_arbiter\N=3\DW=32\AW=14 Used module: $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0 Used module: $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32 Used module: \xclk_strobe Used module: $paramod\xclk_wb\DW=16\AW=12 Used module: $paramod\usb\EPDW=32 Used module: \usb_ep_status Used module: \usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101 Used module: $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100 Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: \usb_phy Used module: $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb Used module: $paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0 Used module: $paramod\soc_spram\AW=14 Used module: \ice40_spram_gen Used module: $paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram Used module: $paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4 Used module: $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32 Used module: \picorv32_ice40_regs Used module: $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 32 Parameter \WWIDTH = 8 75.2.58. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_ep_buf'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 32 Parameter \WWIDTH = 8 Generating RTLIL representation for module `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf'. READ_MODE : 1 WRITE_MODE : 3 Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 8 Parameter \WWIDTH = 32 75.2.59. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_ep_buf'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 8 Parameter \WWIDTH = 32 Generating RTLIL representation for module `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf'. READ_MODE : 3 WRITE_MODE : 1 Parameter \TARGET = 40'0100100101000011010001010011010000110000 Found cached RTLIL representation for module `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000'. Parameter \ADDR_WIDTH = 14 Parameter \DATA_WIDTH = 32 Found cached RTLIL representation for module `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32'. Parameter \L = 2 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Found cached RTLIL representation for module `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1'. Parameter \LIU = 0 Parameter \MFW = 7 Found cached RTLIL representation for module `$paramod\e1_wb_tx\LIU=0\MFW=7'. Parameter \LIU = 0 Parameter \MFW = 7 Found cached RTLIL representation for module `$paramod\e1_wb_rx\LIU=0\MFW=7'. 75.2.60. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: $paramod\sr_btn_if\TICK_LOG2_DIV=3 Used module: \led_blinker Used module: $paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0 Used module: $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0 Used module: $paramod\uart_wb\DIV_WIDTH=12\DW=32 Used module: $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8 Used module: $paramod\ram_sdp\AWIDTH=9\DWIDTH=8 Used module: $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2 Used module: $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1 Used module: $paramod\uart_tx\DIV_WIDTH=12 Used module: \misc Used module: $paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm Used module: $paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm Used module: $paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001 Used module: $paramod\capcnt\W=16 Used module: \capcnt16_sb_mac16 Used module: $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0 Used module: $paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0 Used module: $paramod\capcnt\W=32 Used module: \capcnt32_sb_mac16 Used module: $paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1 Used module: $paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base Used module: $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32 Used module: $paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7 Used module: $paramod\e1_wb_tx\LIU=0\MFW=7 Used module: $paramod\e1_tx\LIU=0\MFW=7 Used module: \e1_tx_phy Used module: \hdb3_enc Used module: \e1_tx_framer Used module: \e1_crc4 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9 Used module: $paramod\e1_wb_rx\LIU=0\MFW=7 Used module: $paramod\e1_rx\LIU=0\MFW=7 Used module: \hdb3_dec Used module: \e1_rx_clock_recovery Used module: \e1_rx_filter Used module: \e1_rx_phy Used module: \e1_rx_deframer Used module: \soc_iobuf Used module: $paramod\wb_dma\A0W=14\A1W=9\DW=32 Used module: $paramod\wb_arbiter\N=2\DW=32\AW=9 Used module: $paramod\wb_epbuf\AW=9\DW=32 Used module: $paramod\wb_arbiter\N=3\DW=32\AW=14 Used module: $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0 Used module: $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32 Used module: \xclk_strobe Used module: $paramod\xclk_wb\DW=16\AW=12 Used module: $paramod\usb\EPDW=32 Used module: \usb_ep_status Used module: $paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf Used module: $paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101 Used module: $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100 Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000 Used module: $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb Used module: $paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0 Used module: $paramod\soc_spram\AW=14 Used module: $paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram Used module: $paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4 Used module: $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32 Used module: \picorv32_ice40_regs Used module: $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr 75.2.61. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: $paramod\sr_btn_if\TICK_LOG2_DIV=3 Used module: \led_blinker Used module: $paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0 Used module: $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0 Used module: $paramod\uart_wb\DIV_WIDTH=12\DW=32 Used module: $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8 Used module: $paramod\ram_sdp\AWIDTH=9\DWIDTH=8 Used module: $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2 Used module: $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1 Used module: $paramod\uart_tx\DIV_WIDTH=12 Used module: \misc Used module: $paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm Used module: $paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm Used module: $paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001 Used module: $paramod\capcnt\W=16 Used module: \capcnt16_sb_mac16 Used module: $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0 Used module: $paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0 Used module: $paramod\capcnt\W=32 Used module: \capcnt32_sb_mac16 Used module: $paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1 Used module: $paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base Used module: $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32 Used module: $paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7 Used module: $paramod\e1_wb_tx\LIU=0\MFW=7 Used module: $paramod\e1_tx\LIU=0\MFW=7 Used module: \e1_tx_phy Used module: \hdb3_enc Used module: \e1_tx_framer Used module: \e1_crc4 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9 Used module: $paramod\e1_wb_rx\LIU=0\MFW=7 Used module: $paramod\e1_rx\LIU=0\MFW=7 Used module: \hdb3_dec Used module: \e1_rx_clock_recovery Used module: \e1_rx_filter Used module: \e1_rx_phy Used module: \e1_rx_deframer Used module: \soc_iobuf Used module: $paramod\wb_dma\A0W=14\A1W=9\DW=32 Used module: $paramod\wb_arbiter\N=2\DW=32\AW=9 Used module: $paramod\wb_epbuf\AW=9\DW=32 Used module: $paramod\wb_arbiter\N=3\DW=32\AW=14 Used module: $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0 Used module: $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32 Used module: \xclk_strobe Used module: $paramod\xclk_wb\DW=16\AW=12 Used module: $paramod\usb\EPDW=32 Used module: \usb_ep_status Used module: $paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf Used module: $paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101 Used module: $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100 Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000 Used module: $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb Used module: $paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0 Used module: $paramod\soc_spram\AW=14 Used module: $paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram Used module: $paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4 Used module: $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32 Used module: \picorv32_ice40_regs Used module: $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr Removing unused module `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0'. Removing unused module `$paramod$e9a8417cc0e9fc03e370009e77135e9e1e2b5499\usb_ep_buf'. Removing unused module `$paramod$7d82212fad3e4929db14b64ca83adffce21ba555\usb_ep_buf'. Removing unused module `$paramod\ram_sdp\AWIDTH=8\DWIDTH=16'. Removing unused module `$paramod\i2c_master\DW=3\TW=0\CLOCK_STRETCH=0'. Removing unused module `$paramod\uart_tx\DIV_WIDTH=8'. Removing unused module `$paramod\uart_rx\DIV_WIDTH=8\GLITCH_FILTER=2'. Removing unused module `$paramod\soc_picorv32_bridge\WB_N=9\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4'. Removing unused module `$paramod\e1_wb\N=1\UNIT_HAS_RX=1'1\UNIT_HAS_TX=1'1\LIU=0\MFW=7'. Removing unused module `$paramod\e1_buf_if_wb\N=1\UNIT_HAS_RX=1'1\UNIT_HAS_TX=1'1\MFW=7\DW=32'. Removing unused module `\wb_epbuf'. Removing unused module `\wb_dma'. Removing unused module `\wb_arbiter'. Removing unused module `\soc_spram'. Removing unused module `\soc_picorv32_bridge'. Removing unused module `\soc_bram'. Removing unused module `\soc_base'. Removing unused module `\picorv32_wb'. Removing unused module `\picorv32_axi_adapter'. Removing unused module `\picorv32_axi'. Removing unused module `\picorv32_pcpi_div'. Removing unused module `\picorv32_pcpi_fast_mul'. Removing unused module `\picorv32_pcpi_mul'. Removing unused module `\picorv32_regs'. Removing unused module `\picorv32'. Removing unused module `\dfu_helper'. Removing unused module `\capcnt'. Removing unused module `\sr_btn_if'. Removing unused module `\usb_phy'. Removing unused module `\usb_ep_buf'. Removing unused module `\usb_crc'. Removing unused module `\usb'. Removing unused module `\xclk_wb'. Removing unused module `\uart_wb'. Removing unused module `\uart_tx'. Removing unused module `\uart_rx'. Removing unused module `\uart2wb'. Removing unused module `\stream2wb'. Removing unused module `\ram_sdp'. Removing unused module `\pwm'. Removing unused module `\pdm_lfsr'. Removing unused module `\pdm'. Removing unused module `\dffesr_n'. Removing unused module `\dffer_n'. Removing unused module `\dffe_n'. Removing unused module `\dff_n'. Removing unused module `\lut4_carry_n'. Removing unused module `\lut4_n'. Removing unused module `\muacm2wb'. Removing unused module `\i2c_master_wb'. Removing unused module `\i2c_master'. Removing unused module `\glitch_filter'. Removing unused module `\fifo_sync_shift'. Removing unused module `\fifo_sync_ram'. Removing unused module `\delay_bus'. Removing unused module `\delay_bit'. Removing unused module `\ice40_serdes_sync'. Removing unused module `\ice40_serdes_dff'. Removing unused module `\ice40_serdes_crg'. Removing unused module `\ice40_oserdes'. Removing unused module `\ice40_iserdes'. Removing unused module `\ice40_spram_wb'. Removing unused module `\ice40_spram_gen'. Removing unused module `\ice40_spi_wb'. Removing unused module `\ice40_rgb_wb'. Removing unused module `\ice40_i2c_wb'. Removing unused module `\ice40_ebr'. Removing unused module `\e1_wb'. Removing unused module `\e1_wb_tx'. Removing unused module `\e1_wb_rx'. Removing unused module `\e1_buf_if_wb'. Removing unused module `\e1_tx'. Removing unused module `\e1_tx_liu'. Removing unused module `\e1_rx'. Removing unused module `\e1_rx_liu'. Removed 75 unused modules. 75.3. Executing PROC pass (convert processes to netlists). 75.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5577'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5522'. Removing empty process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4817'. Found and cleaned up 1 empty switch in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4293'. Found and cleaned up 15 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. Found and cleaned up 1 empty switch in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$4086'. Found and cleaned up 6 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:530$3732'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:530$3732'. Found and cleaned up 1 empty switch in `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:0$3538'. Removing empty process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:0$3538'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:471$3448'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:471$3448'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$138'. Cleaned up 26 empty switches. 75.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$3067 in module SB_DFFNES. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1274$3060 in module SB_DFFNESS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$3056 in module SB_DFFNER. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1143$3049 in module SB_DFFNESR. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1074$3046 in module SB_DFFNS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1026$3043 in module SB_DFFNSS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:957$3040 in module SB_DFFNR. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:909$3037 in module SB_DFFNSR. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$3029 in module SB_DFFES. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:697$3022 in module SB_DFFESS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$3018 in module SB_DFFER. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:566$3011 in module SB_DFFESR. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:497$3008 in module SB_DFFS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:449$3005 in module SB_DFFSS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:380$3002 in module SB_DFFR. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:332$2999 in module SB_DFFSR. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$5194 in module $paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$5190 in module $paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$5186 in module $paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$5178 in module $paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v:50$5175 in module $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_arbiter.v:116$5154 in module $paramod\wb_arbiter\N=3\DW=32\AW=14. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_arbiter.v:80$5142 in module $paramod\wb_arbiter\N=3\DW=32\AW=14. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_epbuf.v:51$5111 in module $paramod\wb_epbuf\AW=9\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_arbiter.v:116$5100 in module $paramod\wb_arbiter\N=2\DW=32\AW=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_arbiter.v:80$5090 in module $paramod\wb_arbiter\N=2\DW=32\AW=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_dma.v:190$5058 in module $paramod\wb_dma\A0W=14\A1W=9\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_dma.v:98$5019 in module $paramod\wb_dma\A0W=14\A1W=9\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_dma.v:92$5018 in module $paramod\wb_dma\A0W=14\A1W=9\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_dma.v:86$5014 in module $paramod\wb_dma\A0W=14\A1W=9\DW=32. Removed 2 dead cases from process $proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4935 in module $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4935 in module $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:163$5456 in module $paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4. Marked 16 switch rules as full_case in process $proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660 in module $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:248$4638 in module $paramod\e1_wb_rx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:241$4636 in module $paramod\e1_wb_rx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$4618 in module $paramod\e1_wb_rx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$4617 in module $paramod\e1_wb_rx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$4609 in module $paramod\e1_wb_rx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:265$4603 in module $paramod\e1_wb_tx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:258$4601 in module $paramod\e1_wb_tx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:152$4578 in module $paramod\e1_wb_tx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:122$4577 in module $paramod\e1_wb_tx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:112$4569 in module $paramod\e1_wb_tx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/sysmgr.v:84$1722 in module sysmgr. Marked 1 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/sysmgr.v:76$1717 in module sysmgr. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:160$4564 in module $paramod\e1_tx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:93$4554 in module $paramod\e1_tx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/misc.v:314$1642 in module misc. Marked 1 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/misc.v:272$1641 in module misc. Marked 1 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/misc.v:186$1637 in module misc. Marked 1 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/misc.v:173$1636 in module misc. Marked 2 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/misc.v:134$1635 in module misc. Marked 1 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/misc.v:112$1624 in module misc. Marked 1 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/led_blinker.v:89$1606 in module led_blinker. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:159$1549 in module usb_tx_pkt. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:126$1533 in module usb_tx_pkt. Marked 8 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:86$1531 in module usb_tx_pkt. Removed 1 dead cases from process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1528 in module usb_tx_ll. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1528 in module usb_tx_ll. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1506 in module usb_tx_ll. Marked 4 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1500 in module usb_tx_ll. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:236$1496 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:421$1485 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:387$1469 in module usb_trans. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1454 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:345$1451 in module usb_trans. Marked 5 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1446 in module usb_trans. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1435 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:225$1430 in module usb_trans. Removed 1 dead cases from process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1427 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1427 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:175$1418 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:162$1409 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1346 in module usb_rx_pkt. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:244$1343 in module usb_rx_pkt. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:230$1340 in module usb_rx_pkt. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:220$1337 in module usb_rx_pkt. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:188$1327 in module usb_rx_pkt. Marked 18 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:117$1311 in module usb_rx_pkt. Removed 1 dead cases from process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1306 in module usb_rx_ll. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1306 in module usb_rx_ll. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:137$1305 in module usb_rx_ll. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:124$1304 in module usb_rx_ll. Removed 1 dead cases from process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1288 in module usb_rx_ll. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1288 in module usb_rx_ll. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:67$1278 in module usb_rx_ll. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4544 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4542 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4533 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4531 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4522 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4520 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4511 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4509 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4498 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4496 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4487 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4485 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4476 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4474 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4465 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4463 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:212$4451 in module $paramod\e1_rx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:197$4441 in module $paramod\e1_rx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:124$5378 in module $paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4403 in module $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4399 in module $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4395 in module $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4387 in module $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:40$1106 in module xclk_strobe. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:34$1105 in module xclk_strobe. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:28$1103 in module xclk_strobe. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:153$5353 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5346 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$5335 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32. Marked 5 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5302 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:206$5297 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32. Marked 4 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$5295 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5267 in module $paramod\uart_tx\DIV_WIDTH=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:51$5264 in module $paramod\uart_tx\DIV_WIDTH=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:42$5260 in module $paramod\uart_tx\DIV_WIDTH=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:35$5256 in module $paramod\uart_tx\DIV_WIDTH=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4348 in module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4342 in module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4340 in module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:83$4331 in module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:67$4325 in module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4319 in module $paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4315 in module $paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4311 in module $paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4303 in module $paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/dfu_helper.v:149$4302 in module $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0. Marked 2 switch rules as full_case in process $proc$/build/gateware/common/rtl/dfu_helper.v:120$4293 in module $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/dfu_helper.v:109$4289 in module $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/dfu_helper.v:103$4287 in module $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/pdm.v:42$4280 in module $paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/pdm.v:42$4276 in module $paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm. Marked 37 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:1375$4100 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 2 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:1288$4072 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 2 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:1274$4067 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 8 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:1165$4032 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 3 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:840$3772 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 3 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:791$3770 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 2 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:760$3766 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 47 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:684$3765 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 4 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:549$3741 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:414$3703 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Removed 2 dead cases from process $proc$/build/gateware/common/rtl/picorv32.v:385$3700 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 2 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:385$3700 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:374$3695 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:309$3621 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:88$5246 in module $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:77$5242 in module $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:70$5238 in module $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3502 in module $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:536$3496 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:643$3488 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:636$3484 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:628$3480 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:619$3476 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:514$3462 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3449 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3447 in module $paramod\usb\EPDW=32. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:442$3443 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3425 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:99$3421 in module $paramod\xclk_wb\DW=16\AW=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:73$3414 in module $paramod\xclk_wb\DW=16\AW=12. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:214$5225 in module $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:204$5222 in module $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:159$5218 in module $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0. Removed 1 dead cases from process $proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:141$5214 in module $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:141$5214 in module $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:129$5210 in module $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0. Marked 7 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:87$5204 in module $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:81$5203 in module $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/pdm.v:133$5202 in module $paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/soc_base.v:184$3325 in module $paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:185$3309 in module $paramod\uart_wb\DIV_WIDTH=12\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:177$3299 in module $paramod\uart_wb\DIV_WIDTH=12\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3282 in module $paramod\uart_wb\DIV_WIDTH=12\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:154$3277 in module $paramod\uart_wb\DIV_WIDTH=12\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/i2c_master_wb.v:91$3272 in module $paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0. Marked 9 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:121$3208 in module $paramod\sr_btn_if\TICK_LOG2_DIV=3. Marked 1 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:114$3207 in module $paramod\sr_btn_if\TICK_LOG2_DIV=3. Marked 4 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:45$446 in module hdb3_enc. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:43$442 in module hdb3_dec. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:251$251 in module e1_tx_framer. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:239$249 in module e1_tx_framer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:207$236 in module e1_tx_framer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:197$233 in module e1_tx_framer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:190$229 in module e1_tx_framer. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:165$226 in module e1_tx_framer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:146$222 in module e1_tx_framer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:133$217 in module e1_tx_framer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:118$214 in module e1_tx_framer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:111$212 in module e1_tx_framer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:95$204 in module e1_tx_framer. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:71$166 in module e1_rx_filter. Marked 5 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:46$147 in module e1_rx_filter. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:406$144 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$138 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$112 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$92 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$70 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:274$58 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:266$54 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:258$50 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$40 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:219$36 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:207$32 in module e1_rx_deframer. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:149$24 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:142$22 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:121$17 in module e1_rx_deframer. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:32$15 in module e1_rx_clock_recovery. Removed a total of 9 dead cases. 75.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 154 redundant assignments. Promoted 315 assignments to connections. 75.3.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3070'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3066'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3059'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3055'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3048'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3045'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3042'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3039'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3036'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3034'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3032'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3028'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3021'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3017'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3010'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3007'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3004'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3001'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2998'. Set init value: \Q = 1'0 Found init rule in `\SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2996'. Set init value: \Q = 1'0 Found init rule in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:49$1310'. Set init value: \dec_sym_1 = 2'00 75.3.5. Executing PROC_ARST pass (detect async resets in processes). Found async reset \S in `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$3067'. Found async reset \R in `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$3056'. Found async reset \S in `\SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1074$3046'. Found async reset \R in `\SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:957$3040'. Found async reset \S in `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$3029'. Found async reset \R in `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$3018'. Found async reset \S in `\SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:497$3008'. Found async reset \R in `\SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:380$3002'. Found async reset \rst in `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v:50$5175'. Found async reset \rst in `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5154'. Found async reset \rst in `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5142'. Found async reset \rst in `$paramod\wb_epbuf\AW=9\DW=32.$proc$/build/gateware/common/rtl/wb_epbuf.v:51$5111'. Found async reset \rst in `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5100'. Found async reset \rst in `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5090'. Found async reset \rst in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$5058'. Found async reset \rst in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:92$5018'. Found async reset \rst in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:86$5014'. Found async reset \rst in `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4935'. Found async reset \rst in `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:248$4638'. Found async reset \rst in `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:241$4636'. Found async reset \rst in `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$4617'. Found async reset \rst in `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:265$4603'. Found async reset \rst in `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:258$4601'. Found async reset \rst in `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:122$4577'. Found async reset \rst_30m72_i in `\sysmgr.$proc$/build/gateware/icE1usb/rtl/sysmgr.v:84$1722'. Found async reset \pll_lock in `\sysmgr.$proc$/build/gateware/icE1usb/rtl/sysmgr.v:76$1717'. Found async reset \rst in `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:93$4554'. Found async reset \rst in `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:314$1642'. Found async reset \rst in `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:272$1641'. Found async reset \rst in `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:186$1637'. Found async reset \rst in `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:173$1636'. Found async reset \rst in `\led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:89$1606'. Found async reset \rst in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:126$1533'. Found async reset \rst in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1528'. Found async reset \ll_start in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1506'. Found async reset \rst in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1500'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:387$1469'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:345$1451'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1446'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1435'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:225$1430'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:175$1418'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:162$1409'. Found async reset \rst in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:188$1327'. Found async reset \rst in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:67$1278'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4544'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4542'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4533'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4531'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4522'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4520'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4511'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4509'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4498'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4496'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4487'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4485'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4476'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4474'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4465'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4463'. Found async reset \rst in `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:212$4451'. Found async reset \rst in `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:197$4441'. Found async reset \rst in `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:40$1106'. Found async reset \rst in `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:34$1105'. Found async reset \rst in `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:28$1103'. Found async reset \rst in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:153$5353'. Found async reset \rst in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5346'. Found async reset \rst in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:206$5297'. Found async reset \rst in `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5267'. Found async reset \rst in `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:35$5256'. Found async reset \rst in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4348'. Found async reset \rst in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4342'. Found async reset \rst in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4340'. Found async reset \rst in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:83$4331'. Found async reset \rst in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:67$4325'. Found async reset \rst in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:149$4302'. Found async reset \rst in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4293'. Found async reset \rst in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:109$4289'. Found async reset \rst in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:103$4287'. Found async reset \rst in `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:70$5238'. Found async reset \rst in `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.$proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3502'. Found async reset \rst in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:536$3496'. Found async reset \rst in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:636$3484'. Found async reset \rst in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:514$3462'. Found async reset \rst in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3447'. Found async reset \rst in `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:99$3421'. Found async reset \rst_sys in `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:184$3325'. Found async reset \rst in `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:154$3277'. Found async reset \rst in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:251$251'. Found async reset \rst in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:239$249'. Found async reset \rst in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:207$236'. Found async reset \rst in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:197$233'. Found async reset \rst in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:190$229'. Found async reset \rst in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:146$222'. Found async reset \rst in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:133$217'. Found async reset \rst in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:118$214'. Found async reset \rst in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:111$212'. Found async reset \rst in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:95$204'. 75.3.6. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3070'. Creating decoders for process `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$3067'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3066'. Creating decoders for process `\SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1274$3060'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3059'. Creating decoders for process `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$3056'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3055'. Creating decoders for process `\SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1143$3049'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3048'. Creating decoders for process `\SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1074$3046'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3045'. Creating decoders for process `\SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1026$3043'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3042'. Creating decoders for process `\SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:957$3040'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3039'. Creating decoders for process `\SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:909$3037'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3036'. Creating decoders for process `\SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:866$3035'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3034'. Creating decoders for process `\SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:830$3033'. Creating decoders for process `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3032'. Creating decoders for process `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$3029'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3028'. Creating decoders for process `\SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:697$3022'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3021'. Creating decoders for process `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$3018'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3017'. Creating decoders for process `\SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:566$3011'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3010'. Creating decoders for process `\SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:497$3008'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3007'. Creating decoders for process `\SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:449$3005'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3004'. Creating decoders for process `\SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:380$3002'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3001'. Creating decoders for process `\SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:332$2999'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2998'. Creating decoders for process `\SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:289$2997'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2996'. Creating decoders for process `\SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:253$2995'. Creating decoders for process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$5199'. Creating decoders for process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$5194'. 1/2: $0\fall[0:0] 2/2: $0\rise[0:0] Creating decoders for process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$5190'. 1/1: $0\state[0:0] Creating decoders for process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$5186'. 1/1: $0\cnt[3:0] Creating decoders for process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$5178'. 1/2: $2\cnt_move[3:0] 2/2: $1\cnt_move[3:0] Creating decoders for process `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v:50$5175'. 1/1: $0\ack_i[0:0] Creating decoders for process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5154'. 1/2: $0\busy[0:0] 2/2: $0\sel[2:0] Creating decoders for process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$5145'. 1/3: $0\sel_nxt[2:0] [2] 2/3: $0\sel_nxt[2:0] [0] 3/3: $0\sel_nxt[2:0] [1] Creating decoders for process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5142'. 1/4: $0\m_wmsk[3:0] 2/4: $0\m_we[0:0] 3/4: $0\m_wdata[31:0] 4/4: $0\m_addr[13:0] Creating decoders for process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5123'. Creating decoders for process `$paramod\wb_epbuf\AW=9\DW=32.$proc$/build/gateware/common/rtl/wb_epbuf.v:51$5111'. 1/1: $0\ack_i[0:0] Creating decoders for process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5100'. 1/2: $0\busy[0:0] 2/2: $0\sel[1:0] Creating decoders for process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$5093'. 1/2: $0\sel_nxt[1:0] [1] 2/2: $0\sel_nxt[1:0] [0] Creating decoders for process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5090'. 1/4: $0\m_wmsk[3:0] 2/4: $0\m_we[0:0] 3/4: $0\m_wdata[31:0] 4/4: $0\m_addr[8:0] Creating decoders for process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5077'. Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$5058'. 1/3: $0\ctl_ack_i[0:0] 2/3: $0\ctl_do_read[0:0] 3/3: $0\ctl_do_write[0:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:178$5054'. 1/1: $0\dir[0:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:174$5051'. 1/1: $0\len[12:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:157$5041'. 1/1: $0\m1_addr_i[8:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:153$5037'. 1/1: $0\m0_addr_i[13:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:142$5035'. 1/1: $0\data_reg[31:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:98$5019'. 1/1: $0\state_nxt[1:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:92$5018'. 1/1: $0\state[1:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:86$5014'. 1/1: $0\go[0:0] Creating decoders for process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$5010'. Creating decoders for process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$5006'. Creating decoders for process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$5002'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5573'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5569'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5565'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5561'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5557'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5553'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5549'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5545'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5541'. Creating decoders for process `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4972'. 1/1: $0\state[4:0] Creating decoders for process `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4959'. 1/1: $0\state[15:0] Creating decoders for process `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4935'. 1/2: $0\dn_state[2:0] 2/2: $0\dp_state[2:0] Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5518'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5514'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5510'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5506'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5502'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5498'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5494'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5490'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5486'. Creating decoders for process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5462'. 1/4: $0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 2/4: $0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_DATA[7:0]$5464 3/4: $0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_ADDR[8:0]$5463 4/4: $0\rd_data[7:0] Creating decoders for process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:163$5456'. 1/1: $0\wb_rdata_reg[31:0] Creating decoders for process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:160$5454'. Creating decoders for process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:147$5427'. Creating decoders for process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:91$5424'. Creating decoders for process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4816'. Creating decoders for process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660'. 1/320: $8\mem_dm_w[7:0] [7] 2/320: $8\mem_dm_w[7:0] [4] 3/320: $8\mem_dm_w[7:0] [2] 4/320: $8\mem_dm_w[7:0] [0] 5/320: $8\mem_dm_w[7:0] [6] 6/320: $8\mem_dm_w[7:0] [1] 7/320: $8\mem_dm_w[7:0] [3] 8/320: $8\mem_dm_w[7:0] [5] 9/320: $8\mem_di_w[31:0] [31] 10/320: $8\mem_di_w[31:0] [24] 11/320: $8\mem_di_w[31:0] [22] 12/320: $8\mem_di_w[31:0] [20] 13/320: $8\mem_di_w[31:0] [18] 14/320: $8\mem_di_w[31:0] [16] 15/320: $8\mem_di_w[31:0] [14] 16/320: $8\mem_di_w[31:0] [12] 17/320: $8\mem_di_w[31:0] [10] 18/320: $8\mem_di_w[31:0] [8] 19/320: $8\mem_di_w[31:0] [6] 20/320: $8\mem_di_w[31:0] [4] 21/320: $8\mem_di_w[31:0] [2] 22/320: $8\mem_di_w[31:0] [0] 23/320: $8\mem_di_w[31:0] [30] 24/320: $8\mem_di_w[31:0] [27] 25/320: $8\mem_di_w[31:0] [23] 26/320: $8\mem_di_w[31:0] [21] 27/320: $8\mem_di_w[31:0] [17] 28/320: $8\mem_di_w[31:0] [13] 29/320: $8\mem_di_w[31:0] [9] 30/320: $8\mem_di_w[31:0] [5] 31/320: $8\mem_di_w[31:0] [1] 32/320: $8\mem_di_w[31:0] [28] 33/320: $8\mem_di_w[31:0] [26] 34/320: $8\mem_di_w[31:0] [15] 35/320: $8\mem_di_w[31:0] [3] 36/320: $8\mem_di_w[31:0] [7] 37/320: $8\mem_di_w[31:0] [25] 38/320: $8\mem_di_w[31:0] [19] 39/320: $8\mem_di_w[31:0] [29] 40/320: $8\mem_di_w[31:0] [11] 41/320: $7\mem_dm_w[7:0] [7] 42/320: $7\mem_dm_w[7:0] [4] 43/320: $7\mem_dm_w[7:0] [2] 44/320: $7\mem_dm_w[7:0] [0] 45/320: $7\mem_dm_w[7:0] [6] 46/320: $7\mem_dm_w[7:0] [1] 47/320: $7\mem_dm_w[7:0] [3] 48/320: $7\mem_dm_w[7:0] [5] 49/320: $7\mem_di_w[31:0] [31] 50/320: $7\mem_di_w[31:0] [24] 51/320: $7\mem_di_w[31:0] [22] 52/320: $7\mem_di_w[31:0] [20] 53/320: $7\mem_di_w[31:0] [18] 54/320: $7\mem_di_w[31:0] [16] 55/320: $7\mem_di_w[31:0] [14] 56/320: $7\mem_di_w[31:0] [12] 57/320: $7\mem_di_w[31:0] [10] 58/320: $7\mem_di_w[31:0] [8] 59/320: $7\mem_di_w[31:0] [6] 60/320: $7\mem_di_w[31:0] [4] 61/320: $7\mem_di_w[31:0] [2] 62/320: $7\mem_di_w[31:0] [0] 63/320: $7\mem_di_w[31:0] [30] 64/320: $7\mem_di_w[31:0] [27] 65/320: $7\mem_di_w[31:0] [23] 66/320: $7\mem_di_w[31:0] [21] 67/320: $7\mem_di_w[31:0] [17] 68/320: $7\mem_di_w[31:0] [13] 69/320: $7\mem_di_w[31:0] [9] 70/320: $7\mem_di_w[31:0] [5] 71/320: $7\mem_di_w[31:0] [1] 72/320: $7\mem_di_w[31:0] [28] 73/320: $7\mem_di_w[31:0] [26] 74/320: $7\mem_di_w[31:0] [15] 75/320: $7\mem_di_w[31:0] [3] 76/320: $7\mem_di_w[31:0] [7] 77/320: $7\mem_di_w[31:0] [25] 78/320: $7\mem_di_w[31:0] [19] 79/320: $7\mem_di_w[31:0] [29] 80/320: $7\mem_di_w[31:0] [11] 81/320: $6\mem_dm_w[7:0] [7] 82/320: $6\mem_dm_w[7:0] [4] 83/320: $6\mem_dm_w[7:0] [2] 84/320: $6\mem_dm_w[7:0] [0] 85/320: $6\mem_dm_w[7:0] [6] 86/320: $6\mem_dm_w[7:0] [1] 87/320: $6\mem_dm_w[7:0] [3] 88/320: $6\mem_dm_w[7:0] [5] 89/320: $6\mem_di_w[31:0] [31] 90/320: $6\mem_di_w[31:0] [24] 91/320: $6\mem_di_w[31:0] [22] 92/320: $6\mem_di_w[31:0] [20] 93/320: $6\mem_di_w[31:0] [18] 94/320: $6\mem_di_w[31:0] [16] 95/320: $6\mem_di_w[31:0] [14] 96/320: $6\mem_di_w[31:0] [12] 97/320: $6\mem_di_w[31:0] [10] 98/320: $6\mem_di_w[31:0] [8] 99/320: $6\mem_di_w[31:0] [6] 100/320: $6\mem_di_w[31:0] [4] 101/320: $6\mem_di_w[31:0] [2] 102/320: $6\mem_di_w[31:0] [0] 103/320: $6\mem_di_w[31:0] [30] 104/320: $6\mem_di_w[31:0] [27] 105/320: $6\mem_di_w[31:0] [23] 106/320: $6\mem_di_w[31:0] [21] 107/320: $6\mem_di_w[31:0] [17] 108/320: $6\mem_di_w[31:0] [13] 109/320: $6\mem_di_w[31:0] [9] 110/320: $6\mem_di_w[31:0] [5] 111/320: $6\mem_di_w[31:0] [1] 112/320: $6\mem_di_w[31:0] [28] 113/320: $6\mem_di_w[31:0] [26] 114/320: $6\mem_di_w[31:0] [15] 115/320: $6\mem_di_w[31:0] [3] 116/320: $6\mem_di_w[31:0] [7] 117/320: $6\mem_di_w[31:0] [25] 118/320: $6\mem_di_w[31:0] [19] 119/320: $6\mem_di_w[31:0] [29] 120/320: $6\mem_di_w[31:0] [11] 121/320: $5\mem_dm_w[7:0] [7] 122/320: $5\mem_dm_w[7:0] [4] 123/320: $5\mem_dm_w[7:0] [2] 124/320: $5\mem_dm_w[7:0] [0] 125/320: $5\mem_dm_w[7:0] [6] 126/320: $5\mem_dm_w[7:0] [1] 127/320: $5\mem_dm_w[7:0] [3] 128/320: $5\mem_dm_w[7:0] [5] 129/320: $5\mem_di_w[31:0] [31] 130/320: $5\mem_di_w[31:0] [24] 131/320: $5\mem_di_w[31:0] [22] 132/320: $5\mem_di_w[31:0] [20] 133/320: $5\mem_di_w[31:0] [18] 134/320: $5\mem_di_w[31:0] [16] 135/320: $5\mem_di_w[31:0] [14] 136/320: $5\mem_di_w[31:0] [12] 137/320: $5\mem_di_w[31:0] [10] 138/320: $5\mem_di_w[31:0] [8] 139/320: $5\mem_di_w[31:0] [6] 140/320: $5\mem_di_w[31:0] [4] 141/320: $5\mem_di_w[31:0] [2] 142/320: $5\mem_di_w[31:0] [0] 143/320: $5\mem_di_w[31:0] [30] 144/320: $5\mem_di_w[31:0] [27] 145/320: $5\mem_di_w[31:0] [23] 146/320: $5\mem_di_w[31:0] [21] 147/320: $5\mem_di_w[31:0] [17] 148/320: $5\mem_di_w[31:0] [13] 149/320: $5\mem_di_w[31:0] [9] 150/320: $5\mem_di_w[31:0] [5] 151/320: $5\mem_di_w[31:0] [1] 152/320: $5\mem_di_w[31:0] [28] 153/320: $5\mem_di_w[31:0] [26] 154/320: $5\mem_di_w[31:0] [15] 155/320: $5\mem_di_w[31:0] [3] 156/320: $5\mem_di_w[31:0] [7] 157/320: $5\mem_di_w[31:0] [25] 158/320: $5\mem_di_w[31:0] [19] 159/320: $5\mem_di_w[31:0] [29] 160/320: $5\mem_di_w[31:0] [11] 161/320: $4\mem_dm_w[7:0] [7] 162/320: $4\mem_dm_w[7:0] [4] 163/320: $4\mem_dm_w[7:0] [2] 164/320: $4\mem_dm_w[7:0] [0] 165/320: $4\mem_dm_w[7:0] [6] 166/320: $4\mem_dm_w[7:0] [1] 167/320: $4\mem_dm_w[7:0] [3] 168/320: $4\mem_dm_w[7:0] [5] 169/320: $4\mem_di_w[31:0] [31] 170/320: $4\mem_di_w[31:0] [24] 171/320: $4\mem_di_w[31:0] [22] 172/320: $4\mem_di_w[31:0] [20] 173/320: $4\mem_di_w[31:0] [18] 174/320: $4\mem_di_w[31:0] [16] 175/320: $4\mem_di_w[31:0] [14] 176/320: $4\mem_di_w[31:0] [12] 177/320: $4\mem_di_w[31:0] [10] 178/320: $4\mem_di_w[31:0] [8] 179/320: $4\mem_di_w[31:0] [6] 180/320: $4\mem_di_w[31:0] [4] 181/320: $4\mem_di_w[31:0] [2] 182/320: $4\mem_di_w[31:0] [0] 183/320: $4\mem_di_w[31:0] [30] 184/320: $4\mem_di_w[31:0] [27] 185/320: $4\mem_di_w[31:0] [23] 186/320: $4\mem_di_w[31:0] [21] 187/320: $4\mem_di_w[31:0] [17] 188/320: $4\mem_di_w[31:0] [13] 189/320: $4\mem_di_w[31:0] [9] 190/320: $4\mem_di_w[31:0] [5] 191/320: $4\mem_di_w[31:0] [1] 192/320: $4\mem_di_w[31:0] [28] 193/320: $4\mem_di_w[31:0] [26] 194/320: $4\mem_di_w[31:0] [15] 195/320: $4\mem_di_w[31:0] [3] 196/320: $4\mem_di_w[31:0] [7] 197/320: $4\mem_di_w[31:0] [25] 198/320: $4\mem_di_w[31:0] [19] 199/320: $4\mem_di_w[31:0] [29] 200/320: $4\mem_di_w[31:0] [11] 201/320: $3\mem_dm_w[7:0] [7] 202/320: $3\mem_dm_w[7:0] [4] 203/320: $3\mem_dm_w[7:0] [2] 204/320: $3\mem_dm_w[7:0] [0] 205/320: $3\mem_dm_w[7:0] [6] 206/320: $3\mem_dm_w[7:0] [1] 207/320: $3\mem_dm_w[7:0] [3] 208/320: $3\mem_dm_w[7:0] [5] 209/320: $3\mem_di_w[31:0] [31] 210/320: $3\mem_di_w[31:0] [24] 211/320: $3\mem_di_w[31:0] [22] 212/320: $3\mem_di_w[31:0] [20] 213/320: $3\mem_di_w[31:0] [18] 214/320: $3\mem_di_w[31:0] [16] 215/320: $3\mem_di_w[31:0] [14] 216/320: $3\mem_di_w[31:0] [12] 217/320: $3\mem_di_w[31:0] [10] 218/320: $3\mem_di_w[31:0] [8] 219/320: $3\mem_di_w[31:0] [6] 220/320: $3\mem_di_w[31:0] [4] 221/320: $3\mem_di_w[31:0] [2] 222/320: $3\mem_di_w[31:0] [0] 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[16] 255/320: $2\mem_di_w[31:0] [14] 256/320: $2\mem_di_w[31:0] [12] 257/320: $2\mem_di_w[31:0] [10] 258/320: $2\mem_di_w[31:0] [8] 259/320: $2\mem_di_w[31:0] [6] 260/320: $2\mem_di_w[31:0] [4] 261/320: $2\mem_di_w[31:0] [2] 262/320: $2\mem_di_w[31:0] [0] 263/320: $2\mem_di_w[31:0] [30] 264/320: $2\mem_di_w[31:0] [27] 265/320: $2\mem_di_w[31:0] [23] 266/320: $2\mem_di_w[31:0] [21] 267/320: $2\mem_di_w[31:0] [17] 268/320: $2\mem_di_w[31:0] [13] 269/320: $2\mem_di_w[31:0] [9] 270/320: $2\mem_di_w[31:0] [5] 271/320: $2\mem_di_w[31:0] [1] 272/320: $2\mem_di_w[31:0] [28] 273/320: $2\mem_di_w[31:0] [26] 274/320: $2\mem_di_w[31:0] [15] 275/320: $2\mem_di_w[31:0] [3] 276/320: $2\mem_di_w[31:0] [7] 277/320: $2\mem_di_w[31:0] [25] 278/320: $2\mem_di_w[31:0] [19] 279/320: $2\mem_di_w[31:0] [29] 280/320: $2\mem_di_w[31:0] [11] 281/320: $1\mem_dm_w[7:0] [7] 282/320: $1\mem_dm_w[7:0] [4] 283/320: $1\mem_dm_w[7:0] [2] 284/320: $1\mem_dm_w[7:0] [0] 285/320: $1\mem_dm_w[7:0] [6] 286/320: $1\mem_dm_w[7:0] [1] 287/320: $1\mem_dm_w[7:0] [3] 288/320: $1\mem_dm_w[7:0] [5] 289/320: $1\mem_di_w[31:0] [31] 290/320: $1\mem_di_w[31:0] [24] 291/320: $1\mem_di_w[31:0] [22] 292/320: $1\mem_di_w[31:0] [20] 293/320: $1\mem_di_w[31:0] [18] 294/320: $1\mem_di_w[31:0] [16] 295/320: $1\mem_di_w[31:0] [14] 296/320: $1\mem_di_w[31:0] [12] 297/320: $1\mem_di_w[31:0] [10] 298/320: $1\mem_di_w[31:0] [8] 299/320: $1\mem_di_w[31:0] [6] 300/320: $1\mem_di_w[31:0] [4] 301/320: $1\mem_di_w[31:0] [2] 302/320: $1\mem_di_w[31:0] [0] 303/320: $1\mem_di_w[31:0] [30] 304/320: $1\mem_di_w[31:0] [27] 305/320: $1\mem_di_w[31:0] [23] 306/320: $1\mem_di_w[31:0] [21] 307/320: $1\mem_di_w[31:0] [17] 308/320: $1\mem_di_w[31:0] [13] 309/320: $1\mem_di_w[31:0] [9] 310/320: $1\mem_di_w[31:0] [5] 311/320: $1\mem_di_w[31:0] [1] 312/320: $1\mem_di_w[31:0] [28] 313/320: $1\mem_di_w[31:0] [26] 314/320: $1\mem_di_w[31:0] [15] 315/320: $1\mem_di_w[31:0] [3] 316/320: $1\mem_di_w[31:0] [7] 317/320: $1\mem_di_w[31:0] [25] 318/320: $1\mem_di_w[31:0] [19] 319/320: $1\mem_di_w[31:0] [29] 320/320: $1\mem_di_w[31:0] [11] Creating decoders for process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:73$4659'. 1/1: $0\addr_r[13:0] Creating decoders for process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:255$4642'. Creating decoders for process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:248$4638'. 1/1: $0\rx_overflow[0:0] Creating decoders for process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:241$4636'. 1/1: $0\rx_rst[0:0] Creating decoders for process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$4618'. 1/2: $0\bro_rden[0:0] 2/2: $0\bri_wren[0:0] Creating decoders for process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$4617'. 1/2: $0\rx_mode[1:0] 2/2: $0\rx_enabled[0:0] Creating decoders for process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$4609'. 1/2: $0\crx_clear[0:0] 2/2: $0\crx_wren[0:0] Creating decoders for process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:265$4603'. 1/1: $0\tx_underflow[0:0] Creating decoders for process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:258$4601'. 1/1: $0\tx_rst[0:0] Creating decoders for process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:152$4578'. 1/2: $0\bto_rden[0:0] 2/2: $0\bti_wren[0:0] Creating decoders for process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:122$4577'. 1/5: $0\tx_loopback[1:0] 2/5: $0\tx_alarm[0:0] 3/5: $0\tx_time_src[0:0] 4/5: $0\tx_mode[1:0] 5/5: $0\tx_enabled[0:0] Creating decoders for process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:112$4569'. 1/2: $0\ctx_clear[0:0] 2/2: $0\ctx_wren[0:0] Creating decoders for process `\sysmgr.$proc$/build/gateware/icE1usb/rtl/sysmgr.v:84$1722'. 1/1: $0\rst_48m_i[0:0] Creating decoders for process `\sysmgr.$proc$/build/gateware/icE1usb/rtl/sysmgr.v:76$1717'. 1/1: $0\rst_cnt[3:0] Creating decoders for process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:160$4564'. 1/2: $0\pg_lo[4:0] 2/2: $0\pg_hi[4:0] Creating decoders for process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:100$4556'. Creating decoders for process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:93$4554'. 1/1: $0\mf_valid[0:0] Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1657'. Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1655'. Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1653'. Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1651'. Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1649'. Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1647'. Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1645'. Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1643'. Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:314$1642'. 1/2: $0\boot_now[0:0] 2/2: $0\boot_sel[1:0] Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:272$1641'. 1/4: $0\pdm_e1[1][8:0] 2/4: $0\pdm_e1[0][8:0] 3/4: $0\pdm_clk[1][12:0] 4/4: $0\pdm_clk[0][12:0] Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:235$1638'. 1/2: $0\tick_e1_sel[1][1:0] 2/2: $0\tick_e1_sel[0][1:0] Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:186$1637'. 1/1: $0\e1_led[8:0] Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:173$1636'. 1/2: $0\gpio_out[3:0] 2/2: $0\gpio_oe[3:0] Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:134$1635'. 1/1: $0\wb_rdata[31:0] Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:112$1624'. 1/8: $0\bus_we_pdm_e1[1:0] [1] 2/8: $0\bus_we_pdm_e1[1:0] [0] 3/8: $0\bus_we_pdm_clk[1:0] [1] 4/8: $0\bus_we_pdm_clk[1:0] [0] 5/8: $0\bus_we_tick_sel[0:0] 6/8: $0\bus_we_led[0:0] 7/8: $0\bus_we_gpio[0:0] 8/8: $0\bus_we_boot[0:0] Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:106$1619'. Creating decoders for process `\led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:89$1606'. 1/1: $0\sr_go[0:0] Creating decoders for process `\led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:77$1597'. Creating decoders for process `\led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:65$1593'. Creating decoders for process `\led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:55$1589'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:241$1581'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:229$1578'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:202$1572'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:191$1568'. 1/1: $0\len[10:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:182$1562'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:175$1555'. 1/2: $0\shift_last_byte[0:0] 2/2: $0\shift_data_crc[0:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:170$1553'. 1/1: $0\shift_data[7:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:159$1549'. 1/1: $0\shift_load[7:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:152$1546'. 1/1: $0\shift_bit[3:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:136$1534'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:126$1533'. 1/1: $0\state[3:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:86$1531'. 1/8: $8\state_nxt[3:0] 2/8: $7\state_nxt[3:0] 3/8: $6\state_nxt[3:0] 4/8: $5\state_nxt[3:0] 5/8: $4\state_nxt[3:0] 6/8: $3\state_nxt[3:0] 7/8: $2\state_nxt[3:0] 8/8: $1\state_nxt[3:0] Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:134$1530'. Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1528'. 1/1: $0\out_sym[1:0] Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:110$1521'. Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:102$1516'. Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1506'. 1/2: $0\bs_now[0:0] 2/2: $0\bs_cnt[2:0] Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:79$1503'. Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1500'. 1/1: $0\state[2:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:236$1496'. 1/1: $0\pkt_pid[3:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:428$1488'. Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:421$1485'. 1/1: $0\bd_length[10:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:414$1479'. Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:403$1478'. Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:399$1475'. 1/1: $0\txpkt_pid[3:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:387$1469'. 1/1: $0\cel_state_i[0:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:380$1467'. Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1454'. 1/7: $0\bd_state[2:0] 2/7: $0\ep_data_toggle[0:0] 3/7: $0\ep_bd_idx_nxt[0:0] 4/7: $0\ep_bd_idx_cur[0:0] 5/7: $0\ep_bd_ctrl[0:0] 6/7: $0\ep_bd_dual[0:0] 7/7: $0\ep_type[2:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:345$1451'. 1/1: $0\epfw_cap_dl[5:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1446'. 1/1: $0\epfw_state[3:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1442'. 1/4: $0\trans_cel[0:0] 2/4: $0\trans_dir[0:0] 3/4: $0\trans_endp[3:0] 4/4: $0\trans_is_setup[0:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1435'. 1/1: $0\rto_cnt[9:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:225$1430'. 1/1: $0\evt[3:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1427'. 1/1: $0\mc_a_reg[3:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:175$1418'. 1/1: $0\mc_pc_nxt[7:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:162$1409'. 1/1: $0\mc_rst_n[0:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:374$1406'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:353$1397'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:349$1395'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:340$1392'. 1/1: $0\token_data[10:8] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:336$1389'. 1/1: $0\token_data[7:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1372'. 1/5: $0\pid_is_handshake[0:0] 2/5: $0\pid_is_data[0:0] 3/5: $0\pid_is_token[0:0] 4/5: $0\pid_is_sof[0:0] 5/5: $0\pid[3:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:318$1371'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:304$1350'. 1/1: $0\pid_valid[0:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1346'. 1/2: $0\crc16_ok[0:0] 2/2: $0\crc5_ok[0:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:284$1345'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:244$1343'. 1/1: $0\crc_in_first[0:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:230$1340'. 1/1: $0\bit_eop_ok[0:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:220$1337'. 1/1: $0\bit_cnt[3:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:215$1336'. 1/1: $0\data[7:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:198$1328'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:188$1327'. 1/1: $0\state[3:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:117$1311'. 1/18: $18\state_nxt[3:0] 2/18: $17\state_nxt[3:0] 3/18: $16\state_nxt[3:0] 4/18: $15\state_nxt[3:0] 5/18: $14\state_nxt[3:0] 6/18: $13\state_nxt[3:0] 7/18: $12\state_nxt[3:0] 8/18: $11\state_nxt[3:0] 9/18: $10\state_nxt[3:0] 10/18: $9\state_nxt[3:0] 11/18: $8\state_nxt[3:0] 12/18: $7\state_nxt[3:0] 13/18: $6\state_nxt[3:0] 14/18: $5\state_nxt[3:0] 15/18: $4\state_nxt[3:0] 16/18: $3\state_nxt[3:0] 17/18: $2\state_nxt[3:0] 18/18: $1\state_nxt[3:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:49$1310'. Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:181$1308'. 1/1: $0\dec_bs_skip_1[0:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1306'. 1/1: $0\dec_rep_state_1[3:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:137$1305'. 1/1: $0\dec_sync_state_1[3:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:124$1304'. 1/1: $0\dec_eop_state_1[2:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:120$1303'. Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:111$1296'. 1/2: $0\dec_bit_1[0:0] 2/2: $0\dec_sym_1[1:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:97$1289'. Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1288'. 1/1: $0\samp_cnt[2:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:67$1278'. 1/1: $0\samp_active[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4553'. Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4544'. 1/1: $0\stage[4].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4542'. 1/1: $0\stage[4].l_data[6:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4533'. 1/1: $0\stage[3].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4531'. 1/1: $0\stage[3].l_data[6:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4522'. 1/1: $0\stage[2].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4520'. 1/1: $0\stage[2].l_data[6:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4511'. 1/1: $0\stage[1].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4509'. 1/1: $0\stage[1].l_data[6:0] Creating decoders for process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:80$1274'. 1/1: $0\s_dout_3[15:0] Creating decoders for process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:76$1272'. 1/1: $0\p_dout_3[15:0] Creating decoders for process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1269'. Creating decoders for process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1261'. Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4507'. Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4498'. 1/1: $0\stage[4].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4496'. 1/1: $0\stage[4].l_data[8:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4487'. 1/1: $0\stage[3].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4485'. 1/1: $0\stage[3].l_data[8:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4476'. 1/1: $0\stage[2].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4474'. 1/1: $0\stage[2].l_data[8:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4465'. 1/1: $0\stage[1].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4463'. 1/1: $0\stage[1].l_data[8:0] Creating decoders for process `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:212$4451'. 1/1: $0\bd_crc_e[1:0] Creating decoders for process `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:205$4445'. Creating decoders for process `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:197$4441'. 1/1: $0\mf_valid[0:0] Creating decoders for process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:0$5383'. Creating decoders for process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:124$5378'. 1/1: $0\wb_rdata[15:0] Creating decoders for process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:116$5373'. Creating decoders for process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:105$5368'. Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4408'. Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4403'. 1/2: $0\fall[0:0] 2/2: $0\rise[0:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4399'. 1/1: $0\state[0:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4395'. 1/1: $0\cnt[1:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4387'. 1/2: $2\cnt_move[1:0] 2/2: $1\cnt_move[1:0] Creating decoders for process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:40$1106'. 1/1: $0\out_stb[0:0] Creating decoders for process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:34$1105'. 1/1: $0\dst[1:0] Creating decoders for process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:28$1103'. 1/1: $0\src[0:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5359'. Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:163$5358'. 1/1: $0\tx_data_reg[0][7:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:153$5353'. 1/1: $0\tx_pending[0:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:143$5352'. 1/1: $0\tx_addr_reg[0][15:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:123$5351'. Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5346'. 1/1: $0\rx_pending[0:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5345'. 1/2: $0\rx_addr_reg[0][15:0] 2/2: $0\rx_data_reg[0][7:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$5335'. 1/3: $1\t_done[3:0] 2/3: $1$bitselwrite$data$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:268$5294[3:0]$5339 3/3: $1$bitselwrite$mask$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:268$5293[3:0]$5338 Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5302'. 1/20: $2$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$5288[15:0]$5331 2/20: $2$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$5287[15:0]$5330 3/20: $2$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$5286[15:0]$5328 4/20: $2$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$5285[15:0]$5327 5/20: $2$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$5282[15:0]$5325 6/20: $2$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$5281[15:0]$5324 7/20: $2$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$5280[15:0]$5322 8/20: $2$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$5279[15:0]$5321 9/20: $1\mux.j[31:0] 10/20: $1$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$5288[15:0]$5319 11/20: $1$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$5287[15:0]$5318 12/20: $1$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$5286[15:0]$5317 13/20: $1$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$5285[15:0]$5316 14/20: $1$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$5282[15:0]$5315 15/20: $1$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$5281[15:0]$5314 16/20: $1$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$5280[15:0]$5313 17/20: $1$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$5279[15:0]$5312 18/20: $0\wb_wdata_byte[7:0] 19/20: $0\wb_addr_lsb[1:0] 20/20: $0\wb_addr[13:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:212$5299'. 1/1: $0\t_chan[1:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:206$5297'. 1/1: $0\t_busy[0:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$5295'. 1/4: $4\t_nxt_chan[1:0] 2/4: $3\t_nxt_chan[1:0] 3/4: $2\t_nxt_chan[1:0] 4/4: $1\t_nxt_chan[1:0] Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:67$5268'. Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5267'. 1/1: $0\shift[9:0] Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:51$5264'. 1/1: $0\bit_cnt[4:0] Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:42$5260'. 1/1: $0\div_cnt[12:0] Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:35$5256'. 1/1: $0\active[0:0] Creating decoders for process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4348'. 1/1: $0\rd_valid[0:0] Creating decoders for process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4342'. 1/1: $0\ram_rd_addr[8:0] Creating decoders for process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4340'. 1/1: $0\ram_wr_addr[8:0] Creating decoders for process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:83$4331'. 1/1: $0\full[0:0] Creating decoders for process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:67$4325'. 1/1: $0\level[9:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4324'. Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4319'. 1/2: $0\fall[0:0] 2/2: $0\rise[0:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4315'. 1/1: $0\state[0:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4311'. 1/1: $0\cnt[1:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4303'. 1/2: $2\cnt_move[1:0] 2/2: $1\cnt_move[1:0] Creating decoders for process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:149$4302'. 1/1: $0\wb_now[0:0] Creating decoders for process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4293'. 1/3: $0\wb_req[0:0] 2/3: $0\wb_sel[1:0] 3/3: $0\rst_req[0:0] Creating decoders for process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:109$4289'. 1/1: $0\timer[25:0] Creating decoders for process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:103$4287'. 1/1: $0\armed[0:0] Creating decoders for process `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:67$4283'. Creating decoders for process `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:42$4280'. 1/1: $0\acc[12:0] Creating decoders for process `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:72$4279'. Creating decoders for process `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:42$4276'. 1/1: $0\acc[8:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. 1/82: $0\reg_next_pc[31:0] [31:2] 2/82: $0\reg_next_pc[31:0] [1:0] 3/82: $0\reg_pc[31:0] [1:0] 4/82: $18\next_irq_pending[2:2] 5/82: $17\next_irq_pending[2:2] 6/82: $16\next_irq_pending[2:2] 7/82: $15\next_irq_pending[2:2] 8/82: $14\next_irq_pending[2:2] 9/82: $13\next_irq_pending[2:2] 10/82: $4\next_irq_pending[31:0] [31:2] 11/82: $3\set_mem_do_rdata[0:0] 12/82: $4\next_irq_pending[31:0] [1] 13/82: $3\set_mem_do_wdata[0:0] 14/82: $4\next_irq_pending[31:0] [0] 15/82: $4\set_mem_do_rinst[0:0] 16/82: $3\set_mem_do_rinst[0:0] 17/82: $4\set_mem_do_wdata[0:0] 18/82: $11\next_irq_pending[1:1] 19/82: $10\next_irq_pending[1:1] 20/82: $9\next_irq_pending[1:1] 21/82: $4\set_mem_do_rdata[0:0] 22/82: $7\next_irq_pending[1:1] 23/82: $6\next_irq_pending[1:1] 24/82: $12\next_irq_pending[1:1] 25/82: $5\set_mem_do_rinst[0:0] 26/82: $8\next_irq_pending[1:1] 27/82: $5\next_irq_pending[31:0] 28/82: $3\current_pc[31:0] 29/82: $2\current_pc[31:0] 30/82: $2\set_mem_do_wdata[0:0] 31/82: $2\set_mem_do_rdata[0:0] 32/82: $2\set_mem_do_rinst[0:0] 33/82: $3\next_irq_pending[31:0] 34/82: $1\current_pc[31:0] 35/82: $1\set_mem_do_wdata[0:0] 36/82: $1\set_mem_do_rdata[0:0] 37/82: $1\set_mem_do_rinst[0:0] 38/82: $0\trace_data[35:0] 39/82: $2\next_irq_pending[0:0] 40/82: $1\next_irq_pending[0:0] 41/82: $0\count_instr[63:0] 42/82: $0\count_cycle[63:0] 43/82: $0\trace_valid[0:0] 44/82: $0\do_waitirq[0:0] 45/82: $0\decoder_pseudo_trigger[0:0] 46/82: $0\decoder_trigger[0:0] 47/82: $0\alu_wait_2[0:0] 48/82: $0\alu_wait[0:0] 49/82: $0\reg_out[31:0] 50/82: $0\reg_sh[4:0] 51/82: $0\trap[0:0] 52/82: $0\pcpi_timeout[0:0] 53/82: $0\latched_rd[4:0] 54/82: $0\latched_is_lb[0:0] 55/82: $0\latched_is_lh[0:0] 56/82: $0\latched_is_lu[0:0] 57/82: $0\latched_trace[0:0] 58/82: $0\latched_compr[0:0] 59/82: $0\latched_branch[0:0] 60/82: $0\latched_stalu[0:0] 61/82: $0\latched_store[0:0] 62/82: $0\irq_state[1:0] 63/82: $0\cpu_state[7:0] 64/82: $0\dbg_rs2val_valid[0:0] 65/82: $0\dbg_rs1val_valid[0:0] 66/82: $0\dbg_rs2val[31:0] 67/82: $0\dbg_rs1val[31:0] 68/82: $0\mem_do_wdata[0:0] 69/82: $0\mem_do_rdata[0:0] 70/82: $0\mem_do_rinst[0:0] 71/82: $0\mem_do_prefetch[0:0] 72/82: $0\mem_wordsize[1:0] 73/82: $0\irq_mask[31:0] 74/82: $0\irq_active[0:0] 75/82: $0\irq_delay[0:0] 76/82: $0\reg_op2[31:0] 77/82: $0\reg_op1[31:0] 78/82: $0\reg_pc[31:0] [31:2] 79/82: $19\next_irq_pending[2:2] 80/82: $0\eoi[31:0] 81/82: $0\pcpi_valid[0:0] 82/82: $0\timer[31:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$4086'. Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1288$4072'. 1/4: $2\cpuregs_write[0:0] 2/4: $2\cpuregs_wrdata[31:0] 3/4: $1\cpuregs_wrdata[31:0] 4/4: $1\cpuregs_write[0:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1274$4067'. 1/2: $2\clear_prefetched_high_word[0:0] 2/2: $1\clear_prefetched_high_word[0:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1272$4066'. Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1228$4044'. 1/2: $1\alu_out[31:0] 2/2: $1\alu_out_0[0:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1165$4032'. 1/8: $8\dbg_ascii_state[127:0] 2/8: $7\dbg_ascii_state[127:0] 3/8: $6\dbg_ascii_state[127:0] 4/8: $5\dbg_ascii_state[127:0] 5/8: $4\dbg_ascii_state[127:0] 6/8: $3\dbg_ascii_state[127:0] 7/8: $2\dbg_ascii_state[127:0] 8/8: $1\dbg_ascii_state[127:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. 1/76: $0\decoded_rs1[4:0] [4] 2/76: $0\decoded_imm_uj[31:0] [10] 3/76: $0\decoded_imm_uj[31:0] [7] 4/76: $0\decoded_imm_uj[31:0] [6] 5/76: $0\decoded_imm_uj[31:0] [3:1] 6/76: $0\decoded_imm_uj[31:0] [5] 7/76: $0\decoded_imm_uj[31:0] [9:8] 8/76: $0\decoded_imm_uj[31:0] [31:20] 9/76: $0\decoded_imm_uj[31:0] [4] 10/76: $0\decoded_imm_uj[31:0] [11] 11/76: $0\decoded_imm_uj[31:0] [0] 12/76: $0\decoded_rs1[4:0] [3:0] 13/76: $0\is_lui_auipc_jal_jalr_addi_add_sub[0:0] 14/76: $0\is_alu_reg_reg[0:0] 15/76: $0\is_alu_reg_imm[0:0] 16/76: $0\is_beq_bne_blt_bge_bltu_bgeu[0:0] 17/76: $0\is_sll_srl_sra[0:0] 18/76: $0\is_sb_sh_sw[0:0] 19/76: $0\is_jalr_addi_slti_sltiu_xori_ori_andi[0:0] 20/76: $0\is_slli_srli_srai[0:0] 21/76: $0\is_lb_lh_lw_lbu_lhu[0:0] 22/76: $0\compressed_instr[0:0] 23/76: $0\is_compare[0:0] 24/76: $0\decoded_imm[31:0] 25/76: $0\decoded_rs2[4:0] 26/76: $0\decoded_imm_uj[31:0] [19:12] 27/76: $0\decoded_rd[4:0] 28/76: $0\instr_timer[0:0] 29/76: $0\instr_waitirq[0:0] 30/76: $0\instr_maskirq[0:0] 31/76: $0\instr_retirq[0:0] 32/76: $0\instr_setq[0:0] 33/76: $0\instr_getq[0:0] 34/76: $0\instr_ecall_ebreak[0:0] 35/76: $0\instr_rdinstrh[0:0] 36/76: $0\instr_rdinstr[0:0] 37/76: $0\instr_rdcycleh[0:0] 38/76: $0\instr_rdcycle[0:0] 39/76: $0\instr_and[0:0] 40/76: $0\instr_or[0:0] 41/76: $0\instr_sra[0:0] 42/76: $0\instr_srl[0:0] 43/76: $0\instr_xor[0:0] 44/76: $0\instr_sltu[0:0] 45/76: $0\instr_slt[0:0] 46/76: $0\instr_sll[0:0] 47/76: $0\instr_sub[0:0] 48/76: $0\instr_add[0:0] 49/76: $0\instr_srai[0:0] 50/76: $0\instr_srli[0:0] 51/76: $0\instr_slli[0:0] 52/76: $0\instr_andi[0:0] 53/76: $0\instr_ori[0:0] 54/76: $0\instr_xori[0:0] 55/76: $0\instr_sltiu[0:0] 56/76: $0\instr_slti[0:0] 57/76: $0\instr_addi[0:0] 58/76: $0\instr_sw[0:0] 59/76: $0\instr_sh[0:0] 60/76: $0\instr_sb[0:0] 61/76: $0\instr_lhu[0:0] 62/76: $0\instr_lbu[0:0] 63/76: $0\instr_lw[0:0] 64/76: $0\instr_lh[0:0] 65/76: $0\instr_lb[0:0] 66/76: $0\instr_bgeu[0:0] 67/76: $0\instr_bltu[0:0] 68/76: $0\instr_bge[0:0] 69/76: $0\instr_blt[0:0] 70/76: $0\instr_bne[0:0] 71/76: $0\instr_beq[0:0] 72/76: $0\instr_jalr[0:0] 73/76: $0\instr_jal[0:0] 74/76: $0\instr_auipc[0:0] 75/76: $0\instr_lui[0:0] 76/76: $0\pcpi_insn[31:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3770'. 1/13: $3\dbg_insn_opcode[31:0] 2/13: $2\dbg_insn_rd[4:0] 3/13: $2\dbg_insn_rs2[4:0] 4/13: $2\dbg_insn_rs1[4:0] 5/13: $2\dbg_insn_opcode[31:0] 6/13: $2\dbg_insn_imm[31:0] 7/13: $2\dbg_ascii_instr[63:0] 8/13: $1\dbg_insn_rd[4:0] 9/13: $1\dbg_insn_rs2[4:0] 10/13: $1\dbg_insn_rs1[4:0] 11/13: $1\dbg_insn_imm[31:0] 12/13: $1\dbg_ascii_instr[63:0] 13/13: $1\dbg_insn_opcode[31:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3766'. 1/8: $0\cached_insn_rd[4:0] 2/8: $0\cached_insn_rs2[4:0] 3/8: $0\cached_insn_rs1[4:0] 4/8: $0\cached_insn_opcode[31:0] 5/8: $0\cached_insn_imm[31:0] 6/8: $0\cached_ascii_instr[63:0] 7/8: $0\dbg_valid_insn[0:0] 8/8: $0\dbg_insn_addr[31:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:684$3765'. 1/47: $47\new_ascii_instr[63:0] 2/47: $46\new_ascii_instr[63:0] 3/47: $45\new_ascii_instr[63:0] 4/47: $44\new_ascii_instr[63:0] 5/47: $43\new_ascii_instr[63:0] 6/47: $42\new_ascii_instr[63:0] 7/47: $41\new_ascii_instr[63:0] 8/47: $40\new_ascii_instr[63:0] 9/47: $39\new_ascii_instr[63:0] 10/47: $38\new_ascii_instr[63:0] 11/47: $37\new_ascii_instr[63:0] 12/47: $36\new_ascii_instr[63:0] 13/47: $35\new_ascii_instr[63:0] 14/47: $34\new_ascii_instr[63:0] 15/47: $33\new_ascii_instr[63:0] 16/47: $32\new_ascii_instr[63:0] 17/47: $31\new_ascii_instr[63:0] 18/47: $30\new_ascii_instr[63:0] 19/47: $29\new_ascii_instr[63:0] 20/47: $28\new_ascii_instr[63:0] 21/47: $27\new_ascii_instr[63:0] 22/47: $26\new_ascii_instr[63:0] 23/47: $25\new_ascii_instr[63:0] 24/47: $24\new_ascii_instr[63:0] 25/47: $23\new_ascii_instr[63:0] 26/47: $22\new_ascii_instr[63:0] 27/47: $21\new_ascii_instr[63:0] 28/47: $20\new_ascii_instr[63:0] 29/47: $19\new_ascii_instr[63:0] 30/47: $18\new_ascii_instr[63:0] 31/47: $17\new_ascii_instr[63:0] 32/47: $16\new_ascii_instr[63:0] 33/47: $15\new_ascii_instr[63:0] 34/47: $14\new_ascii_instr[63:0] 35/47: $13\new_ascii_instr[63:0] 36/47: $12\new_ascii_instr[63:0] 37/47: $11\new_ascii_instr[63:0] 38/47: $10\new_ascii_instr[63:0] 39/47: $9\new_ascii_instr[63:0] 40/47: $8\new_ascii_instr[63:0] 41/47: $7\new_ascii_instr[63:0] 42/47: $6\new_ascii_instr[63:0] 43/47: $5\new_ascii_instr[63:0] 44/47: $4\new_ascii_instr[63:0] 45/47: $3\new_ascii_instr[63:0] 46/47: $2\new_ascii_instr[63:0] 47/47: $1\new_ascii_instr[63:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3741'. 1/9: $0\mem_16bit_buffer[15:0] 2/9: $0\prefetched_high_word[0:0] 3/9: $0\mem_la_secondword[0:0] 4/9: $0\mem_state[1:0] 5/9: $0\mem_wstrb[3:0] 6/9: $0\mem_wdata[31:0] 7/9: $0\mem_instr[0:0] 8/9: $0\mem_valid[0:0] 9/9: $0\mem_addr[31:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1209$4265'. Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:414$3703'. 1/9: $0\mem_rdata_q[31:0] [31] 2/9: $0\mem_rdata_q[31:0] [7] 3/9: $0\mem_rdata_q[31:0] [24:20] 4/9: $0\mem_rdata_q[31:0] [19:15] 5/9: $0\mem_rdata_q[31:0] [6:0] 6/9: $0\mem_rdata_q[31:0] [14:12] 7/9: $0\mem_rdata_q[31:0] [11:8] 8/9: $0\mem_rdata_q[31:0] [30:25] 9/9: $0\next_insn_opcode[31:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3700'. 1/5: $3\mem_rdata_word[31:0] 2/5: $2\mem_rdata_word[31:0] 3/5: $1\mem_rdata_word[31:0] 4/5: $1\mem_la_wstrb[3:0] 5/5: $1\mem_la_wdata[31:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:374$3695'. 1/2: $0\last_mem_valid[0:0] 2/2: $0\mem_la_firstword_reg[0:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3621'. 1/2: $1\pcpi_int_rd[31:0] 2/2: $1\pcpi_int_wr[0:0] Creating decoders for process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:102$5250'. Creating decoders for process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:95$5249'. 1/1: $0\shift[8:0] Creating decoders for process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:88$5246'. 1/1: $0\bit_cnt[4:0] Creating decoders for process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:77$5242'. 1/1: $0\div_cnt[12:0] Creating decoders for process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:70$5238'. 1/1: $0\active[0:0] Creating decoders for process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3511'. 1/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3507_EN[31:0]$3514 2/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3507_DATA[31:0]$3513 3/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3507_ADDR[7:0]$3512 4/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3508_EN[31:0]$3517 5/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3508_DATA[31:0]$3516 6/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3508_ADDR[7:0]$3515 7/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3509_EN[31:0]$3520 8/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3509_DATA[31:0]$3519 9/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3509_ADDR[7:0]$3518 10/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3510_EN[31:0]$3523 11/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3510_DATA[31:0]$3522 12/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3510_ADDR[7:0]$3521 Creating decoders for process `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.$proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3502'. 1/1: $0\led_ctrl[4:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:536$3496'. 1/1: $0\evt_cnt[3:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:656$3491'. Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:653$3489'. Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:643$3488'. 1/1: $0\pad_pu[0:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:636$3484'. 1/1: $0\rst_pending[0:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:628$3480'. 1/1: $0\timeout_reset[19:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:619$3476'. 1/1: $0\timeout_suspend[19:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:514$3462'. 1/1: $0\eps_bus_ack_wait[0:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:510$3459'. Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3449'. 1/3: $0\eps_bus_req[0:0] 2/3: $0\eps_bus_write[0:0] 3/3: $0\eps_bus_read[0:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:697$3500'. Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3447'. 1/4: $0\cr_addr[6:0] 2/4: $0\cr_addr_chk[0:0] 3/4: $0\cr_cel_ena[0:0] 4/4: $0\cr_pu_ena[0:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:442$3443'. 1/2: $2\csr_bus_dout[15:0] 2/2: $1\csr_bus_dout[15:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3425'. 1/7: $0\ir_bus_we[0:0] 2/7: $0\evt_rd_ack[0:0] 3/7: $0\sof_clear[0:0] 4/7: $0\rst_clear[0:0] 5/7: $0\cel_rel[0:0] 6/7: $0\cr_bus_we[0:0] 7/7: $0\csr_bus_req[0:0] Creating decoders for process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:99$3421'. 1/1: $0\m_cyc_i[0:0] Creating decoders for process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:83$3417'. Creating decoders for process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:73$3414'. 1/1: $0\s_rdata[15:0] Creating decoders for process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:68$3413'. 1/1: $0\m_rdata_i[15:0] Creating decoders for process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:0$5234'. Creating decoders for process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:0$5233'. Creating decoders for process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:214$5225'. 1/1: $0\sda_oe[0:0] Creating decoders for process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:204$5222'. 1/1: $0\scl_oe[0:0] Creating decoders for process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:159$5218'. 1/1: $0\data_reg[8:0] Creating decoders for process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:141$5214'. 1/1: $0\bit_cnt[3:0] Creating decoders for process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:129$5210'. 1/1: $0\cyc_cnt[4:0] Creating decoders for process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:121$5209'. 1/1: $0\cmd_cur[1:0] Creating decoders for process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:87$5204'. 1/7: $7\state_nxt[2:0] 2/7: $6\state_nxt[2:0] 3/7: $5\state_nxt[2:0] 4/7: $4\state_nxt[2:0] 5/7: $3\state_nxt[2:0] 6/7: $2\state_nxt[2:0] 7/7: $1\state_nxt[2:0] Creating decoders for process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:81$5203'. 1/1: $0\state[2:0] Creating decoders for process `$paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:133$5202'. 1/1: $0\out[7:0] Creating decoders for process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3330'. Creating decoders for process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3328'. Creating decoders for process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3326'. Creating decoders for process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:184$3325'. 1/1: $0\pb_rst_n[0:0] Creating decoders for process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:193$3311'. 1/1: $0\uart_div[11:0] Creating decoders for process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:185$3309'. 1/1: $0\ub_rdata[31:0] Creating decoders for process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:177$3299'. 1/1: $0\ub_ack[0:0] Creating decoders for process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3282'. 1/4: $0\ub_wr_div[0:0] 2/4: $0\ub_wr_data[0:0] 3/4: $0\ub_rd_ctrl[0:0] 4/4: $0\ub_rd_data[0:0] Creating decoders for process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:154$3277'. 1/1: $0\urf_overflow[0:0] Creating decoders for process `$paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master_wb.v:91$3272'. 1/1: $0\wb_rdata[31:0] Creating decoders for process `$paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master_wb.v:85$3264'. Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:291$3262'. 1/4: $0\srio_rclk_oe[0:0] 2/4: $0\srio_rclk_o[0:0] 3/4: $0\srio_dat_o[0:0] 4/4: $0\srio_clk_o[0:0] Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:279$3261'. 1/1: $0\shift_data[7:0] Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:270$3249'. Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:262$3242'. Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:243$3236'. Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:227$3229'. Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:214$3223'. Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:206$3222'. Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:197$3220'. Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:121$3208'. 1/9: $9\state_nxt[2:0] 2/9: $8\state_nxt[2:0] 3/9: $7\state_nxt[2:0] 4/9: $6\state_nxt[2:0] 5/9: $5\state_nxt[2:0] 6/9: $4\state_nxt[2:0] 7/9: $3\state_nxt[2:0] 8/9: $2\state_nxt[2:0] 9/9: $1\state_nxt[2:0] Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:114$3207'. 1/1: $0\state[2:0] Creating decoders for process `\hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:45$446'. 1/9: $0\d_neg[3:0] [3] 2/9: $0\d_pos[3:0] [3] 3/9: $0\d_neg[3:0] [2:1] 4/9: $0\d_neg[3:0] [0] 5/9: $0\d_pos[3:0] [0] 6/9: $0\zcnt[1:0] 7/9: $0\d_pos[3:0] [2:1] 8/9: $0\vstate[0:0] 9/9: $0\pstate[0:0] Creating decoders for process `\hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:41$445'. Creating decoders for process `\hdb3_dec.$proc$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:43$442'. 1/2: $0\pstate[0:0] 2/2: $0\data[3:0] Creating decoders for process `\hdb3_dec.$proc$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:37$437'. Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:251$251'. 1/2: $0\out_valid[0:0] 2/2: $0\out_bit[0:0] Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:239$249'. 1/1: $0\crc_smf[3:0] Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:227$248'. Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:207$236'. 1/3: $0\shift_at_crc[0:0] 2/3: $0\shift_at_last[0:0] 3/3: $0\shift_at_first[0:0] Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:197$233'. 1/1: $0\shift_data[7:0] Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:190$229'. 1/1: $0\bit_cnt[3:0] Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:165$226'. 1/1: $0\shift_data_nxt[7:0] Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:146$222'. 1/1: $0\fetch_done[0:0] Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:142$221'. Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:133$217'. 1/2: $0\in_mf_last[0:0] 2/2: $0\in_mf_first[0:0] Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:118$214'. 1/3: $0\fetch_ts_is31[0:0] 2/3: $0\fetch_ts_is0[0:0] 3/3: $0\fetch_ts[4:0] Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:111$212'. 1/1: $0\fetch_frame[3:0] Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:101$208'. Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:95$204'. 1/1: $0\tick_cnt[4:0] Creating decoders for process `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:71$166'. 1/3: $0\out_stb[0:0] 2/3: $0\out_lo[0:0] 3/3: $0\out_hi[0:0] Creating decoders for process `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:46$147'. 1/2: $0\cnt_lo[1:0] 2/2: $0\cnt_hi[1:0] Creating decoders for process `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:39$146'. Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:406$144'. 1/1: $0\aligned[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$138'. 1/7: $0\out_last[0:0] 2/7: $0\out_first[0:0] 3/7: $0\out_ts_is0[0:0] 4/7: $0\out_ts[4:0] 5/7: $0\out_frame[3:0] 6/7: $0\out_data[7:0] 7/7: $0\out_valid[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:357$130'. Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$112'. 1/4: $0\ec_mfa[1:0] 2/4: $0\ec_crc[1:0] 3/4: $0\ec_nfas[1:0] 4/4: $0\ec_fas[1:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$92'. 1/4: $0\ed_mfa[0:0] 2/4: $0\ep_mfa[0:0] 3/4: $0\ed_crc[0:0] 4/4: $0\ep_crc[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$70'. 1/4: $0\ed_nfas[0:0] 2/4: $0\ep_nfas[0:0] 3/4: $0\ed_fas[0:0] 4/4: $0\ep_fas[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:306$69'. 1/1: $0\crc_smf[3:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:274$58'. 1/3: $0\ts0_msbs_match_crc[0:0] 2/3: $0\ts0_msbs_match_mf[0:0] 3/3: $0\ts0_msbs[15:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:266$54'. 1/1: $0\mfa_timeout[6:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:258$50'. 1/1: $0\fas_pos[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$40'. 1/5: $0\frame_mf_last[0:0] 2/5: $0\frame_mf_first[0:0] 3/5: $0\frame_smf_last[0:0] 4/5: $0\frame_smf_first[0:0] 5/5: $0\frame[3:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:219$36'. 1/3: $0\ts_is_ts31[0:0] 2/3: $0\ts_is_ts0[0:0] 3/3: $0\ts[4:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:207$32'. 1/3: $0\bit_last[0:0] 2/3: $0\bit_first[0:0] 3/3: $0\bit[2:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:149$24'. 1/1: $0\fsm_state_nxt[2:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:142$22'. 1/1: $0\fsm_state[2:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:133$19'. 1/1: $0\data_match_fas[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:128$18'. 1/1: $0\data[7:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:121$17'. 1/1: $0\strobe[0:0] Creating decoders for process `\e1_rx_clock_recovery.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:32$15'. 1/1: $0\cnt[5:0] Creating decoders for process `\e1_crc4.$proc$/build/gateware/cores/no2e1//rtl/e1_crc4.v:38$13'. 1/1: $0\state[3:0] 75.3.7. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\cnt_move' from process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$5178'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\sel_nxt' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$5145'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\prio.i' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$5145'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\mux_addr' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5123'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\mux_wdata' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5123'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\mux_wmsk' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5123'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\mux.i' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5123'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\sel_nxt' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$5093'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\prio.i' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$5093'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\mux_addr' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5077'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\mux_wdata' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5077'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\mux_wmsk' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5077'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\mux.i' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5077'. No latch inferred for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\state_nxt' from process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:98$5019'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:92$4998$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$5010'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:92$5001$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$5010'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:92$5001$\sig' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$5010'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:91$4997$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$5006'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:91$5000$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$5006'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:91$5000$\sig' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$5006'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:81$4996$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$5002'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:81$4999$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$5002'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:81$4999$\sig' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$5002'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5531$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5573'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5540$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5573'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5540$\wdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5573'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5530$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5569'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5539$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5569'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5539$\rdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5569'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5529$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5565'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5538$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5565'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5538$\wdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5565'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5528$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5561'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5537$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5561'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5537$\rdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5561'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5527$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5557'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5536$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5557'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5536$\wdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5557'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5526$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5553'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5535$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5553'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5535$\rdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5553'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5525$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5549'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5534$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5549'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5534$\wdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5549'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5524$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5545'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5533$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5545'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5533$\rdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5545'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:220$5523$\ram_wr_shuffle_32' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5541'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:220$5532$\ram_wr_shuffle_32' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5541'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:220$5532$\src' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5541'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5476$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5518'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5485$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5518'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5485$\wdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5518'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5475$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5514'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5484$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5514'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5484$\rdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5514'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5474$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5510'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5483$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5510'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5483$\wdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5510'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5473$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5506'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5482$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5506'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5482$\rdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5506'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5472$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5502'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5481$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5502'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5481$\wdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5502'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5471$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5498'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5480$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5498'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5480$\rdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5498'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5470$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5494'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5479$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5494'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5479$\wdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5494'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5469$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5490'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5478$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5490'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5478$\rdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5490'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:211$5468$\ram_rd_shuffle_32' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5486'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:211$5477$\ram_rd_shuffle_32' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5486'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:211$5477$\src' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5486'. No latch inferred for signal `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.\wb_rdata_or' from process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:147$5427'. No latch inferred for signal `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.\wb_or.i' from process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:147$5427'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_do_m[0]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4816'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di[0]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4816'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di[1]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4816'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm[0]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4816'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm[1]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4816'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\rd_data' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\map.n' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\map.x' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\map.o' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660'. Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [0]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$16043 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [1]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$16158 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [2]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$16321 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [3]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$16532 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [4]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$16743 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [5]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$16954 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [6]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$17165 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [7]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$17376 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [8]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$17587 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [9]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$17798 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [10]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$18009 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [11]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$18220 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [12]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$18431 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [13]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$18642 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [14]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$18853 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [15]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$19064 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [16]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$19275 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [17]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$19486 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [18]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$19697 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [19]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$19908 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [20]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$20119 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [21]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$20330 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [22]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$20541 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [23]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$20752 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [24]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$20963 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [25]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$21174 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [26]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$21385 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [27]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$21596 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [28]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$21807 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [29]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$22018 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [30]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$22229 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [31]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$22440 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [0]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$22507 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [1]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$22574 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [2]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$22641 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [3]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$22708 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [4]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$22775 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [5]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$22842 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [6]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$22909 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [7]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660': $auto$proc_dlatch.cc:430:proc_dlatch$22976 No latch inferred for signal `\misc.$mem2bits$\pdm_e1$/build/gateware/icE1usb/rtl/misc.v:305$1618' from process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1657'. No latch inferred for signal `\misc.$mem2bits$\pdm_e1$/build/gateware/icE1usb/rtl/misc.v:305$1617' from process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1655'. No latch inferred for signal `\misc.$mem2bits$\pdm_e1$/build/gateware/icE1usb/rtl/misc.v:304$1616' from process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1653'. No latch inferred for signal `\misc.$mem2bits$\pdm_e1$/build/gateware/icE1usb/rtl/misc.v:304$1615' from process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1651'. No latch inferred for signal `\misc.$mem2bits$\pdm_clk$/build/gateware/icE1usb/rtl/misc.v:293$1614' from process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1649'. No latch inferred for signal `\misc.$mem2bits$\pdm_clk$/build/gateware/icE1usb/rtl/misc.v:293$1613' from process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1647'. No latch inferred for signal `\misc.$mem2bits$\pdm_clk$/build/gateware/icE1usb/rtl/misc.v:292$1612' from process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1645'. No latch inferred for signal `\misc.$mem2bits$\pdm_clk$/build/gateware/icE1usb/rtl/misc.v:292$1611' from process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1643'. No latch inferred for signal `\led_blinker.\led' from process `\led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:77$1597'. No latch inferred for signal `\led_blinker.\led_state_proc.i' from process `\led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:77$1597'. No latch inferred for signal `\usb_tx_pkt.\shift_load' from process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:159$1549'. No latch inferred for signal `\usb_tx_pkt.\state_nxt' from process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:86$1531'. No latch inferred for signal `\usb_rx_pkt.\state_nxt' from process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:117$1311'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[0]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4553'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[1]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4553'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[2]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4553'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[3]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4553'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[4]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4553'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[5]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4553'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[0]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4507'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[1]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4507'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[2]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4507'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[3]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4507'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[4]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4507'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[5]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4507'. No latch inferred for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.\bus_rdata_rx[1]' from process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:0$5383'. No latch inferred for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.\bus_rdata_tx[1]' from process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:0$5383'. No latch inferred for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.\bus_rdata' from process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:116$5373'. No latch inferred for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.\rdata_or.j' from process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:116$5373'. No latch inferred for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\cnt_move' from process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4387'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\t_done' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$5335'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$bitselwrite$mask$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:268$5293' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$5335'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$bitselwrite$data$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:268$5294' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$5335'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\t_nxt_busy' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$5295'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\t_nxt_chan' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$5295'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\next_sel.j' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$5295'. No latch inferred for signal `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.\cnt_move' from process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4303'. No latch inferred for signal `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm.\dither' from process `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:72$4279'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cpuregs_rs1' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$4086'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cpuregs_rs2' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$4086'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\decoded_rs' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$4086'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cpuregs_write' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1288$4072'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cpuregs_wrdata' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1288$4072'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\clear_prefetched_high_word' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1274$4067'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_out' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1228$4044'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_out_0' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1228$4044'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_ascii_state' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1165$4032'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_insn_opcode' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3770'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_ascii_instr' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3770'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_insn_imm' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3770'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_insn_rs1' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3770'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_insn_rs2' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3770'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_insn_rd' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3770'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\new_ascii_instr' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:684$3765'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_la_wdata' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3700'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_la_wstrb' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3700'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_rdata_word' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3700'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\pcpi_int_wr' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3621'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\pcpi_int_rd' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3621'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\pcpi_int_wait' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3621'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\pcpi_int_ready' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3621'. No latch inferred for signal `$paramod\usb\EPDW=32.\irq' from process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:697$3500'. No latch inferred for signal `$paramod\usb\EPDW=32.\csr_bus_dout' from process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:442$3443'. No latch inferred for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\scl_ir' from process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:0$5234'. No latch inferred for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\to_cnt' from process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:0$5233'. No latch inferred for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\to_latch' from process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:0$5233'. No latch inferred for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\state_nxt' from process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:87$5204'. No latch inferred for signal `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.\wb_rdata[3] [31:16]' from process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3330'. No latch inferred for signal `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.\wb_rdata[5]' from process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3330'. No latch inferred for signal `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.\wb_rdata[6]' from process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3330'. No latch inferred for signal `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.\wb_rdata[7] [31:16]' from process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3330'. No latch inferred for signal `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$mem2bits$\wb_rdata$/build/gateware/common/rtl/soc_base.v:498$3324' from process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3328'. No latch inferred for signal `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$mem2bits$\wb_rdata$/build/gateware/common/rtl/soc_base.v:401$3323' from process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3326'. No latch inferred for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\state_nxt' from process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:121$3208'. No latch inferred for signal `\e1_rx_deframer.\fsm_state_nxt' from process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:149$24'. 75.3.8. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$3067'. created $adff cell `$procdff$22977' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1274$3060'. created $dff cell `$procdff$22978' with negative edge clock. Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$3056'. created $adff cell `$procdff$22979' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1143$3049'. created $dff cell `$procdff$22980' with negative edge clock. Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1074$3046'. created $adff cell `$procdff$22981' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1026$3043'. created $dff cell `$procdff$22982' with negative edge clock. Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:957$3040'. created $adff cell `$procdff$22983' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:909$3037'. created $dff cell `$procdff$22984' with negative edge clock. Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:866$3035'. created $dff cell `$procdff$22985' with negative edge clock. Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:830$3033'. created $dff cell `$procdff$22986' with negative edge clock. Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$3029'. created $adff cell `$procdff$22987' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:697$3022'. created $dff cell `$procdff$22988' with positive edge clock. Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$3018'. created $adff cell `$procdff$22989' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:566$3011'. created $dff cell `$procdff$22990' with positive edge clock. Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:497$3008'. created $adff cell `$procdff$22991' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:449$3005'. created $dff cell `$procdff$22992' with positive edge clock. Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:380$3002'. created $adff cell `$procdff$22993' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:332$2999'. created $dff cell `$procdff$22994' with positive edge clock. Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:289$2997'. created $dff cell `$procdff$22995' with positive edge clock. Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:253$2995'. created $dff cell `$procdff$22996' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\sync' using process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$5199'. created $dff cell `$procdff$22997' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\rise' using process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$5194'. created $dff cell `$procdff$22998' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\fall' using process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$5194'. created $dff cell `$procdff$22999' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\state' using process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$5190'. created $dff cell `$procdff$23000' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\cnt' using process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$5186'. created $dff cell `$procdff$23001' with positive edge clock. Creating register for signal `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0.\ack_i' using process `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v:50$5175'. created $adff cell `$procdff$23002' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\sel' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5154'. created $adff cell `$procdff$23003' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\busy' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5154'. created $adff cell `$procdff$23004' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\m_addr' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5142'. created $adff cell `$procdff$23005' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\m_wdata' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5142'. created $adff cell `$procdff$23006' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\m_we' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5142'. created $adff cell `$procdff$23007' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\m_wmsk' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5142'. created $adff cell `$procdff$23008' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_epbuf\AW=9\DW=32.\ack_i' using process `$paramod\wb_epbuf\AW=9\DW=32.$proc$/build/gateware/common/rtl/wb_epbuf.v:51$5111'. created $adff cell `$procdff$23009' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\sel' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5100'. created $adff cell `$procdff$23010' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\busy' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5100'. created $adff cell `$procdff$23011' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\m_addr' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5090'. created $adff cell `$procdff$23012' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\m_wdata' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5090'. created $adff cell `$procdff$23013' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\m_we' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5090'. created $adff cell `$procdff$23014' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\m_wmsk' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5090'. created $adff cell `$procdff$23015' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\ctl_do_write' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$5058'. created $adff cell `$procdff$23016' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\ctl_do_read' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$5058'. created $adff cell `$procdff$23017' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\ctl_ack_i' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$5058'. created $adff cell `$procdff$23018' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\dir' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:178$5054'. created $dff cell `$procdff$23019' with positive edge clock. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\len' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:174$5051'. created $dff cell `$procdff$23020' with positive edge clock. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\m1_addr_i' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:157$5041'. created $dff cell `$procdff$23021' with positive edge clock. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\m0_addr_i' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:153$5037'. created $dff cell `$procdff$23022' with positive edge clock. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\data_reg' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:142$5035'. created $dff cell `$procdff$23023' with positive edge clock. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\state' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:92$5018'. created $adff cell `$procdff$23024' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\go' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:86$5014'. created $adff cell `$procdff$23025' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100.\state' using process `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4972'. created $dff cell `$procdff$23026' with positive edge clock. Creating register for signal `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101.\state' using process `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4959'. created $dff cell `$procdff$23027' with positive edge clock. Creating register for signal `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.\dp_state' using process `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4935'. created $adff cell `$procdff$23028' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.\dn_state' using process `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4935'. created $adff cell `$procdff$23029' with positive edge clock and positive level reset. Creating register for signal `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.\rd_data' using process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5462'. created $dff cell `$procdff$23030' with positive edge clock. Creating register for signal `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_ADDR' using process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5462'. created $dff cell `$procdff$23031' with positive edge clock. Creating register for signal `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_DATA' using process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5462'. created $dff cell `$procdff$23032' with positive edge clock. Creating register for signal `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN' using process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5462'. created $dff cell `$procdff$23033' with positive edge clock. Creating register for signal `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.\wb_rdata_reg' using process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:163$5456'. created $dff cell `$procdff$23034' with positive edge clock. Creating register for signal `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.\wb_rdy_reg' using process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:160$5454'. created $dff cell `$procdff$23035' with positive edge clock. Creating register for signal `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.\ram_rdy' using process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:91$5424'. created $dff cell `$procdff$23036' with positive edge clock. Creating register for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\addr_r' using process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:73$4659'. created $dff cell `$procdff$23037' with positive edge clock. Creating register for signal `$paramod\e1_wb_rx\LIU=0\MFW=7.\tx_crc_e_auto' using process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:255$4642'. created $dff cell `$procdff$23038' with positive edge clock. Creating register for signal `$paramod\e1_wb_rx\LIU=0\MFW=7.\rx_overflow' using process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:248$4638'. created $adff cell `$procdff$23039' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_rx\LIU=0\MFW=7.\rx_rst' using process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:241$4636'. created $adff cell `$procdff$23040' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_rx\LIU=0\MFW=7.\bri_wren' using process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$4618'. created $dff cell `$procdff$23041' with positive edge clock. Creating register for signal `$paramod\e1_wb_rx\LIU=0\MFW=7.\bro_rden' using process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$4618'. created $dff cell `$procdff$23042' with positive edge clock. Creating register for signal `$paramod\e1_wb_rx\LIU=0\MFW=7.\rx_enabled' using process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$4617'. created $adff cell `$procdff$23043' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_rx\LIU=0\MFW=7.\rx_mode' using process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$4617'. created $adff cell `$procdff$23044' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_rx\LIU=0\MFW=7.\crx_wren' using process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$4609'. created $dff cell `$procdff$23045' with positive edge clock. Creating register for signal `$paramod\e1_wb_rx\LIU=0\MFW=7.\crx_clear' using process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$4609'. created $dff cell `$procdff$23046' with positive edge clock. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\tx_underflow' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:265$4603'. created $adff cell `$procdff$23047' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\tx_rst' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:258$4601'. created $adff cell `$procdff$23048' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\bti_wren' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:152$4578'. created $dff cell `$procdff$23049' with positive edge clock. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\bto_rden' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:152$4578'. created $dff cell `$procdff$23050' with positive edge clock. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\tx_enabled' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:122$4577'. created $adff cell `$procdff$23051' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\tx_mode' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:122$4577'. created $adff cell `$procdff$23052' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\tx_time_src' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:122$4577'. created $adff cell `$procdff$23053' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\tx_alarm' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:122$4577'. created $adff cell `$procdff$23054' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\tx_loopback' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:122$4577'. created $adff cell `$procdff$23055' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\ctx_wren' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:112$4569'. created $dff cell `$procdff$23056' with positive edge clock. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\ctx_clear' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:112$4569'. created $dff cell `$procdff$23057' with positive edge clock. Creating register for signal `\sysmgr.\rst_48m_i' using process `\sysmgr.$proc$/build/gateware/icE1usb/rtl/sysmgr.v:84$1722'. created $adff cell `$procdff$23058' with positive edge clock and positive level reset. Creating register for signal `\sysmgr.\rst_cnt' using process `\sysmgr.$proc$/build/gateware/icE1usb/rtl/sysmgr.v:76$1717'. created $adff cell `$procdff$23059' with positive edge clock and negative level reset. Creating register for signal `$paramod\e1_tx\LIU=0\MFW=7.\pg_hi' using process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:160$4564'. created $dff cell `$procdff$23060' with positive edge clock. Creating register for signal `$paramod\e1_tx\LIU=0\MFW=7.\pg_lo' using process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:160$4564'. created $dff cell `$procdff$23061' with positive edge clock. Creating register for signal `$paramod\e1_tx\LIU=0\MFW=7.\bd_done' using process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:100$4556'. created $dff cell `$procdff$23062' with positive edge clock. Creating register for signal `$paramod\e1_tx\LIU=0\MFW=7.\bd_miss' using process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:100$4556'. created $dff cell `$procdff$23063' with positive edge clock. Creating register for signal `$paramod\e1_tx\LIU=0\MFW=7.\mf_valid' using process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:93$4554'. created $adff cell `$procdff$23064' with positive edge clock and positive level reset. Creating register for signal `\misc.\boot_sel' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:314$1642'. created $adff cell `$procdff$23065' with positive edge clock and positive level reset. Creating register for signal `\misc.\boot_now' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:314$1642'. created $adff cell `$procdff$23066' with positive edge clock and positive level reset. Creating register for signal `\misc.\pdm_clk[0]' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:272$1641'. created $adff cell `$procdff$23067' with positive edge clock and positive level reset. Creating register for signal `\misc.\pdm_clk[1]' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:272$1641'. created $adff cell `$procdff$23068' with positive edge clock and positive level reset. Creating register for signal `\misc.\pdm_e1[0]' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:272$1641'. created $adff cell `$procdff$23069' with positive edge clock and positive level reset. Creating register for signal `\misc.\pdm_e1[1]' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:272$1641'. created $adff cell `$procdff$23070' with positive edge clock and positive level reset. Creating register for signal `\misc.\tick_e1_sel[0]' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:235$1638'. created $dff cell `$procdff$23071' with positive edge clock. Creating register for signal `\misc.\tick_e1_sel[1]' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:235$1638'. created $dff cell `$procdff$23072' with positive edge clock. Creating register for signal `\misc.\e1_led' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:186$1637'. created $adff cell `$procdff$23073' with positive edge clock and positive level reset. Creating register for signal `\misc.\gpio_oe' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:173$1636'. created $adff cell `$procdff$23074' with positive edge clock and positive level reset. Creating register for signal `\misc.\gpio_out' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:173$1636'. created $adff cell `$procdff$23075' with positive edge clock and positive level reset. Creating register for signal `\misc.\wb_rdata' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:134$1635'. created $dff cell `$procdff$23076' with positive edge clock. Creating register for signal `\misc.\bus_we_boot' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:112$1624'. created $dff cell `$procdff$23077' with positive edge clock. Creating register for signal `\misc.\bus_we_gpio' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:112$1624'. created $dff cell `$procdff$23078' with positive edge clock. Creating register for signal `\misc.\bus_we_led' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:112$1624'. created $dff cell `$procdff$23079' with positive edge clock. Creating register for signal `\misc.\bus_we_tick_sel' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:112$1624'. created $dff cell `$procdff$23080' with positive edge clock. Creating register for signal `\misc.\bus_we_pdm_clk' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:112$1624'. created $dff cell `$procdff$23081' with positive edge clock. Creating register for signal `\misc.\bus_we_pdm_e1' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:112$1624'. created $dff cell `$procdff$23082' with positive edge clock. Creating register for signal `\misc.\wb_ack' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:106$1619'. created $dff cell `$procdff$23083' with positive edge clock. Creating register for signal `\led_blinker.\sr_go' using process `\led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:89$1606'. created $adff cell `$procdff$23084' with positive edge clock and positive level reset. Creating register for signal `\led_blinker.\cycle' using process `\led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:65$1593'. created $dff cell `$procdff$23085' with positive edge clock. Creating register for signal `\led_blinker.\tick_cnt' using process `\led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:55$1589'. created $dff cell `$procdff$23086' with positive edge clock. Creating register for signal `\usb_tx_pkt.\pkt_done' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:241$1581'. created $dff cell `$procdff$23087' with positive edge clock. Creating register for signal `\usb_tx_pkt.\pkt_data_ack' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:241$1581'. created $dff cell `$procdff$23088' with positive edge clock. Creating register for signal `\usb_tx_pkt.\ll_start' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:229$1578'. created $dff cell `$procdff$23089' with positive edge clock. Creating register for signal `\usb_tx_pkt.\crc_in_first' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:202$1572'. created $dff cell `$procdff$23090' with positive edge clock. Creating register for signal `\usb_tx_pkt.\len' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:191$1568'. created $dff cell `$procdff$23091' with positive edge clock. Creating register for signal `\usb_tx_pkt.\shift_new_bit' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:182$1562'. created $dff cell `$procdff$23092' with positive edge clock. Creating register for signal `\usb_tx_pkt.\shift_data_crc' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:175$1555'. created $dff cell `$procdff$23093' with positive edge clock. Creating register for signal `\usb_tx_pkt.\shift_last_byte' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:175$1555'. created $dff cell `$procdff$23094' with positive edge clock. Creating register for signal `\usb_tx_pkt.\shift_data' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:170$1553'. created $dff cell `$procdff$23095' with positive edge clock. Creating register for signal `\usb_tx_pkt.\shift_bit' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:152$1546'. created $dff cell `$procdff$23096' with positive edge clock. Creating register for signal `\usb_tx_pkt.\pid_is_handshake' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:136$1534'. created $dff cell `$procdff$23097' with positive edge clock. Creating register for signal `\usb_tx_pkt.\state' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:126$1533'. created $adff cell `$procdff$23098' with positive edge clock and positive level reset. Creating register for signal `\usb_tx_ll.\out_active' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:134$1530'. created $dff cell `$procdff$23099' with positive edge clock. Creating register for signal `\usb_tx_ll.\out_sym' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1528'. created $adff cell `$procdff$23100' with positive edge clock and positive level reset. Creating register for signal `\usb_tx_ll.\ll_ack' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:110$1521'. created $dff cell `$procdff$23101' with positive edge clock. Creating register for signal `\usb_tx_ll.\lvl_prev' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:102$1516'. created $dff cell `$procdff$23102' with positive edge clock. Creating register for signal `\usb_tx_ll.\bs_cnt' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1506'. created $adff cell `$procdff$23103' with positive edge clock and positive level reset. Creating register for signal `\usb_tx_ll.\bs_now' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1506'. created $adff cell `$procdff$23104' with positive edge clock and positive level reset. Creating register for signal `\usb_tx_ll.\br_cnt' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:79$1503'. created $dff cell `$procdff$23105' with positive edge clock. Creating register for signal `\usb_tx_ll.\state' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1500'. created $adff cell `$procdff$23106' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\pkt_pid' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:236$1496'. created $dff cell `$procdff$23107' with positive edge clock. Creating register for signal `\usb_trans.\xfer_length' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:428$1488'. created $dff cell `$procdff$23108' with positive edge clock. Creating register for signal `\usb_trans.\bd_length' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:421$1485'. created $dff cell `$procdff$23109' with positive edge clock. Creating register for signal `\usb_trans.\addr' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:414$1479'. created $dff cell `$procdff$23110' with positive edge clock. Creating register for signal `\usb_trans.\txpkt_start_i' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:403$1478'. created $dff cell `$procdff$23111' with positive edge clock. Creating register for signal `\usb_trans.\txpkt_pid' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:399$1475'. created $dff cell `$procdff$23112' with positive edge clock. Creating register for signal `\usb_trans.\cel_state_i' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:387$1469'. created $adff cell `$procdff$23113' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\epfw_issue_wb' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:380$1467'. created $dff cell `$procdff$23114' with positive edge clock. Creating register for signal `\usb_trans.\ep_type' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1454'. created $dff cell `$procdff$23115' with positive edge clock. Creating register for signal `\usb_trans.\ep_bd_dual' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1454'. created $dff cell `$procdff$23116' with positive edge clock. Creating register for signal `\usb_trans.\ep_bd_ctrl' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1454'. created $dff cell `$procdff$23117' with positive edge clock. Creating register for signal `\usb_trans.\ep_bd_idx_cur' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1454'. created $dff cell `$procdff$23118' with positive edge clock. Creating register for signal `\usb_trans.\ep_bd_idx_nxt' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1454'. created $dff cell `$procdff$23119' with positive edge clock. Creating register for signal `\usb_trans.\ep_data_toggle' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1454'. created $dff cell `$procdff$23120' with positive edge clock. Creating register for signal `\usb_trans.\bd_state' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1454'. created $dff cell `$procdff$23121' with positive edge clock. Creating register for signal `\usb_trans.\epfw_cap_dl' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:345$1451'. created $adff cell `$procdff$23122' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\epfw_state' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1446'. created $adff cell `$procdff$23123' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\trans_is_setup' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1442'. created $dff cell `$procdff$23124' with positive edge clock. Creating register for signal `\usb_trans.\trans_endp' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1442'. created $dff cell `$procdff$23125' with positive edge clock. Creating register for signal `\usb_trans.\trans_dir' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1442'. created $dff cell `$procdff$23126' with positive edge clock. Creating register for signal `\usb_trans.\trans_cel' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1442'. created $dff cell `$procdff$23127' with positive edge clock. Creating register for signal `\usb_trans.\rto_cnt' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1435'. created $adff cell `$procdff$23128' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\evt' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:225$1430'. created $adff cell `$procdff$23129' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\mc_a_reg' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1427'. created $dff cell `$procdff$23130' with positive edge clock. Creating register for signal `\usb_trans.\mc_pc_nxt' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:175$1418'. created $adff cell `$procdff$23131' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\mc_rst_n' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:162$1409'. created $adff cell `$procdff$23132' with positive edge clock and positive level reset. Creating register for signal `\usb_rx_pkt.\pkt_data_stb' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:374$1406'. created $dff cell `$procdff$23133' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pkt_done_ok' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:353$1397'. created $dff cell `$procdff$23134' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pkt_done_err' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:353$1397'. created $dff cell `$procdff$23135' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pkt_start' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:349$1395'. created $dff cell `$procdff$23136' with positive edge clock. Creating register for signal `\usb_rx_pkt.\token_data [10:8]' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:340$1392'. created $dff cell `$procdff$23137' with positive edge clock. Creating register for signal `\usb_rx_pkt.\token_data [7:0]' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:336$1389'. created $dff cell `$procdff$23138' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1372'. created $dff cell `$procdff$23139' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_is_sof' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1372'. created $dff cell `$procdff$23140' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_is_token' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1372'. created $dff cell `$procdff$23141' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_is_data' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1372'. created $dff cell `$procdff$23142' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_is_handshake' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1372'. created $dff cell `$procdff$23143' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_cap_r' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:318$1371'. created $dff cell `$procdff$23144' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_valid' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:304$1350'. created $dff cell `$procdff$23145' with positive edge clock. Creating register for signal `\usb_rx_pkt.\crc5_ok' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1346'. created $dff cell `$procdff$23146' with positive edge clock. Creating register for signal `\usb_rx_pkt.\crc16_ok' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1346'. created $dff cell `$procdff$23147' with positive edge clock. Creating register for signal `\usb_rx_pkt.\crc_cap' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:284$1345'. created $dff cell `$procdff$23148' with positive edge clock. Creating register for signal `\usb_rx_pkt.\crc_in_first' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:244$1343'. created $dff cell `$procdff$23149' with positive edge clock. Creating register for signal `\usb_rx_pkt.\bit_eop_ok' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:230$1340'. created $dff cell `$procdff$23150' with positive edge clock. Creating register for signal `\usb_rx_pkt.\bit_cnt' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:220$1337'. created $dff cell `$procdff$23151' with positive edge clock. Creating register for signal `\usb_rx_pkt.\data' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:215$1336'. created $dff cell `$procdff$23152' with positive edge clock. Creating register for signal `\usb_rx_pkt.\state_prev_idle' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:198$1328'. created $dff cell `$procdff$23153' with positive edge clock. Creating register for signal `\usb_rx_pkt.\state_prev_error' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:198$1328'. created $dff cell `$procdff$23154' with positive edge clock. Creating register for signal `\usb_rx_pkt.\state' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:188$1327'. created $adff cell `$procdff$23155' with positive edge clock and positive level reset. Creating register for signal `\usb_rx_ll.\dec_bs_skip_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:181$1308'. created $dff cell `$procdff$23156' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_rep_state_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1306'. created $dff cell `$procdff$23157' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_sync_state_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:137$1305'. created $dff cell `$procdff$23158' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_eop_state_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:124$1304'. created $dff cell `$procdff$23159' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_valid_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:120$1303'. created $dff cell `$procdff$23160' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_sym_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:111$1296'. created $dff cell `$procdff$23161' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_bit_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:111$1296'. created $dff cell `$procdff$23162' with positive edge clock. Creating register for signal `\usb_rx_ll.\samp_valid_0' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:97$1289'. created $dff cell `$procdff$23163' with positive edge clock. Creating register for signal `\usb_rx_ll.\samp_cnt' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1288'. created $dff cell `$procdff$23164' with positive edge clock. Creating register for signal `\usb_rx_ll.\samp_active' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:67$1278'. created $adff cell `$procdff$23165' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[4].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4544'. created $adff cell `$procdff$23166' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[4].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4542'. created $adff cell `$procdff$23167' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[3].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4533'. created $adff cell `$procdff$23168' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[3].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4531'. created $adff cell `$procdff$23169' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[2].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4522'. created $adff cell `$procdff$23170' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[2].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4520'. created $adff cell `$procdff$23171' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[1].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4511'. created $adff cell `$procdff$23172' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[1].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4509'. created $adff cell `$procdff$23173' with positive edge clock and positive level reset. Creating register for signal `\usb_ep_status.\s_dout_3' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:80$1274'. created $dff cell `$procdff$23174' with positive edge clock. Creating register for signal `\usb_ep_status.\p_dout_3' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:76$1272'. created $dff cell `$procdff$23175' with positive edge clock. Creating register for signal `\usb_ep_status.\p_read_2' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1269'. created $dff cell `$procdff$23176' with positive edge clock. Creating register for signal `\usb_ep_status.\p_zero_2' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1269'. created $dff cell `$procdff$23177' with positive edge clock. Creating register for signal `\usb_ep_status.\s_read_2' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1269'. created $dff cell `$procdff$23178' with positive edge clock. Creating register for signal `\usb_ep_status.\s_zero_2' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1269'. created $dff cell `$procdff$23179' with positive edge clock. Creating register for signal `\usb_ep_status.\addr_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1261'. created $dff cell `$procdff$23180' with positive edge clock. Creating register for signal `\usb_ep_status.\din_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1261'. created $dff cell `$procdff$23181' with positive edge clock. Creating register for signal `\usb_ep_status.\we_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1261'. created $dff cell `$procdff$23182' with positive edge clock. Creating register for signal `\usb_ep_status.\p_read_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1261'. created $dff cell `$procdff$23183' with positive edge clock. Creating register for signal `\usb_ep_status.\p_zero_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1261'. created $dff cell `$procdff$23184' with positive edge clock. Creating register for signal `\usb_ep_status.\s_read_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1261'. created $dff cell `$procdff$23185' with positive edge clock. Creating register for signal `\usb_ep_status.\s_zero_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1261'. created $dff cell `$procdff$23186' with positive edge clock. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[4].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4498'. created $adff cell `$procdff$23187' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[4].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4496'. created $adff cell `$procdff$23188' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[3].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4487'. created $adff cell `$procdff$23189' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[3].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4485'. created $adff cell `$procdff$23190' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[2].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4476'. created $adff cell `$procdff$23191' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[2].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4474'. created $adff cell `$procdff$23192' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[1].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4465'. created $adff cell `$procdff$23193' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[1].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4463'. created $adff cell `$procdff$23194' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_rx\LIU=0\MFW=7.\bd_crc_e' using process `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:212$4451'. created $adff cell `$procdff$23195' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_rx\LIU=0\MFW=7.\bd_done' using process `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:205$4445'. created $dff cell `$procdff$23196' with positive edge clock. Creating register for signal `$paramod\e1_rx\LIU=0\MFW=7.\bd_miss' using process `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:205$4445'. created $dff cell `$procdff$23197' with positive edge clock. Creating register for signal `$paramod\e1_rx\LIU=0\MFW=7.\mf_valid' using process `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:197$4441'. created $adff cell `$procdff$23198' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.\wb_rdata' using process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:124$5378'. created $dff cell `$procdff$23199' with positive edge clock. Creating register for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.\wb_ack' using process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:105$5368'. created $dff cell `$procdff$23200' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\sync' using process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4408'. created $dff cell `$procdff$23201' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\rise' using process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4403'. created $dff cell `$procdff$23202' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\fall' using process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4403'. created $dff cell `$procdff$23203' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\state' using process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4399'. created $dff cell `$procdff$23204' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\cnt' using process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4395'. created $dff cell `$procdff$23205' with positive edge clock. Creating register for signal `\xclk_strobe.\out_stb' using process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:40$1106'. created $adff cell `$procdff$23206' with positive edge clock and positive level reset. Creating register for signal `\xclk_strobe.\dst' using process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:34$1105'. created $adff cell `$procdff$23207' with positive edge clock and positive level reset. Creating register for signal `\xclk_strobe.\src' using process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:28$1103'. created $adff cell `$procdff$23208' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\tx_pending [1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5359'. created $dff cell `$procdff$23209' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\tx_addr_reg[1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5359'. created $dff cell `$procdff$23210' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\tx_data_reg[1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5359'. created $dff cell `$procdff$23211' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\tx_data_reg[0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:163$5358'. created $dff cell `$procdff$23212' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\tx_pending [0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:153$5353'. created $adff cell `$procdff$23213' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\tx_addr_reg[0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:143$5352'. created $dff cell `$procdff$23214' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\rx_pending [1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:123$5351'. created $dff cell `$procdff$23215' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\rx_data_reg[1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:123$5351'. created $dff cell `$procdff$23216' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\rx_addr_reg[1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:123$5351'. created $dff cell `$procdff$23217' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\rx_pending [0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5346'. created $adff cell `$procdff$23218' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\rx_data_reg[0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5345'. created $dff cell `$procdff$23219' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\rx_addr_reg[0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5345'. created $dff cell `$procdff$23220' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\wb_addr' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5302'. created $dff cell `$procdff$23221' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\wb_addr_lsb' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5302'. created $dff cell `$procdff$23222' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\wb_wdata_byte' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5302'. created $dff cell `$procdff$23223' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\mux.j' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5302'. created $dff cell `$procdff$23224' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$5279' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5302'. created $dff cell `$procdff$23225' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$5280' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5302'. created $dff cell `$procdff$23226' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$5281' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5302'. created $dff cell `$procdff$23227' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$5282' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5302'. created $dff cell `$procdff$23228' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$5285' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5302'. created $dff cell `$procdff$23229' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$5286' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5302'. created $dff cell `$procdff$23230' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$5287' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5302'. created $dff cell `$procdff$23231' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$5288' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5302'. created $dff cell `$procdff$23232' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\t_chan' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:212$5299'. created $dff cell `$procdff$23233' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\t_busy' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:206$5297'. created $adff cell `$procdff$23234' with positive edge clock and positive level reset. Creating register for signal `$paramod\uart_tx\DIV_WIDTH=12.\ack' using process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:67$5268'. created $dff cell `$procdff$23235' with positive edge clock. Creating register for signal `$paramod\uart_tx\DIV_WIDTH=12.\shift' using process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5267'. created $adff cell `$procdff$23236' with positive edge clock and positive level reset. Creating register for signal `$paramod\uart_tx\DIV_WIDTH=12.\bit_cnt' using process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:51$5264'. created $dff cell `$procdff$23237' with positive edge clock. Creating register for signal `$paramod\uart_tx\DIV_WIDTH=12.\div_cnt' using process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:42$5260'. created $dff cell `$procdff$23238' with positive edge clock. Creating register for signal `$paramod\uart_tx\DIV_WIDTH=12.\active' using process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:35$5256'. created $adff cell `$procdff$23239' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.\rd_valid' using process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4348'. created $adff cell `$procdff$23240' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.\ram_rd_addr' using process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4342'. created $adff cell `$procdff$23241' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.\ram_wr_addr' using process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4340'. created $adff cell `$procdff$23242' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.\full' using process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:83$4331'. created $adff cell `$procdff$23243' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.\level' using process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:67$4325'. created $adff cell `$procdff$23244' with positive edge clock and positive level reset. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.\sync' using process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4324'. created $dff cell `$procdff$23245' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.\rise' using process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4319'. created $dff cell `$procdff$23246' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.\fall' using process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4319'. created $dff cell `$procdff$23247' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.\state' using process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4315'. created $dff cell `$procdff$23248' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.\cnt' using process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4311'. created $dff cell `$procdff$23249' with positive edge clock. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.\wb_now' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:149$4302'. created $adff cell `$procdff$23250' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.\rst_req' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4293'. created $adff cell `$procdff$23251' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.\wb_sel' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4293'. created $adff cell `$procdff$23252' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.\wb_req' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4293'. created $adff cell `$procdff$23253' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.\timer' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:109$4289'. created $adff cell `$procdff$23254' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.\armed' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:103$4287'. created $adff cell `$procdff$23255' with positive edge clock and positive level reset. Creating register for signal `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm.\dither' using process `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:67$4283'. created $dff cell `$procdff$23256' with positive edge clock. Creating register for signal `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm.\acc' using process `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:42$4280'. created $dff cell `$procdff$23257' with positive edge clock. Creating register for signal `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm.\acc' using process `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:42$4276'. created $dff cell `$procdff$23258' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\timer' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23259' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\trap' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23260' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\pcpi_valid' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23261' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\eoi' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23262' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\trace_valid' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23263' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\trace_data' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23264' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\count_cycle' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23265' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\count_instr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23266' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\reg_pc' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23267' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\reg_next_pc' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23268' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\reg_op1' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23269' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\reg_op2' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23270' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\reg_out' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23271' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\reg_sh' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23272' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\irq_delay' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23273' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\irq_active' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23274' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\irq_mask' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23275' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\irq_pending' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23276' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_wordsize' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23277' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_do_prefetch' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23278' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_do_rinst' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23279' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_do_rdata' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23280' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_do_wdata' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23281' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\decoder_trigger' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23282' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\decoder_trigger_q' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23283' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\decoder_pseudo_trigger' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23284' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\decoder_pseudo_trigger_q' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23285' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_rs1val' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23286' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_rs2val' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23287' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_rs1val_valid' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23288' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_rs2val_valid' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23289' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cpu_state' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23290' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\irq_state' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23291' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\set_mem_do_rinst' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23292' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\set_mem_do_rdata' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23293' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\set_mem_do_wdata' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23294' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\latched_store' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23295' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\latched_stalu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23296' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\latched_branch' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23297' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\latched_compr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23298' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\latched_trace' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23299' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\latched_is_lu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23300' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\latched_is_lh' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23301' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\latched_is_lb' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23302' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\latched_rd' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23303' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\current_pc' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23304' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\pcpi_timeout' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23305' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\next_irq_pending' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23306' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\do_waitirq' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23307' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_out_q' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23308' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_out_0_q' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23309' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_wait' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23310' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_wait_2' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. created $dff cell `$procdff$23311' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\clear_prefetched_high_word_q' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1272$4066'. created $dff cell `$procdff$23312' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\pcpi_insn' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23313' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_lui' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23314' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_auipc' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23315' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_jal' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23316' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_jalr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23317' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_beq' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23318' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_bne' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23319' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_blt' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23320' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_bge' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23321' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_bltu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23322' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_bgeu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23323' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_lb' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23324' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_lh' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23325' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_lw' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23326' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_lbu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23327' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_lhu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23328' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_sb' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23329' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_sh' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23330' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_sw' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23331' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_addi' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23332' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_slti' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23333' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_sltiu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23334' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_xori' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23335' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_ori' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23336' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_andi' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23337' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_slli' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23338' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_srli' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23339' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_srai' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23340' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_add' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23341' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_sub' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23342' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_sll' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23343' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_slt' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23344' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_sltu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23345' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_xor' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23346' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_srl' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23347' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_sra' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23348' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_or' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23349' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_and' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23350' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_rdcycle' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23351' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_rdcycleh' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23352' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_rdinstr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23353' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_rdinstrh' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23354' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_ecall_ebreak' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23355' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_getq' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23356' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_setq' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23357' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_retirq' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23358' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_maskirq' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23359' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_waitirq' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23360' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_timer' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23361' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\decoded_rd' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23362' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\decoded_rs1' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23363' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\decoded_rs2' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23364' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\decoded_imm' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23365' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\decoded_imm_uj' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23366' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\compressed_instr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23367' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_lui_auipc_jal' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23368' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_lb_lh_lw_lbu_lhu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23369' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_slli_srli_srai' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23370' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_jalr_addi_slti_sltiu_xori_ori_andi' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23371' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_sb_sh_sw' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23372' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_sll_srl_sra' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23373' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_lui_auipc_jal_jalr_addi_add_sub' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23374' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_slti_blt_slt' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23375' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_sltiu_bltu_sltu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23376' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_beq_bne_blt_bge_bltu_bgeu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23377' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_lbu_lhu_lw' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23378' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_alu_reg_imm' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23379' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_alu_reg_reg' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23380' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_compare' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. created $dff cell `$procdff$23381' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_insn_addr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3766'. created $dff cell `$procdff$23382' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\q_ascii_instr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3766'. created $dff cell `$procdff$23383' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\q_insn_imm' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3766'. created $dff cell `$procdff$23384' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\q_insn_opcode' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3766'. created $dff cell `$procdff$23385' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\q_insn_rs1' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3766'. created $dff cell `$procdff$23386' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\q_insn_rs2' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3766'. created $dff cell `$procdff$23387' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\q_insn_rd' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3766'. created $dff cell `$procdff$23388' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_next' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3766'. created $dff cell `$procdff$23389' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_valid_insn' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3766'. created $dff cell `$procdff$23390' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cached_ascii_instr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3766'. created $dff cell `$procdff$23391' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cached_insn_imm' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3766'. created $dff cell `$procdff$23392' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cached_insn_opcode' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3766'. created $dff cell `$procdff$23393' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cached_insn_rs1' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3766'. created $dff cell `$procdff$23394' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cached_insn_rs2' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3766'. created $dff cell `$procdff$23395' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cached_insn_rd' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3766'. created $dff cell `$procdff$23396' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_addr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3741'. created $dff cell `$procdff$23397' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_valid' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3741'. created $dff cell `$procdff$23398' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_instr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3741'. created $dff cell `$procdff$23399' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_wdata' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3741'. created $dff cell `$procdff$23400' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_wstrb' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3741'. created $dff cell `$procdff$23401' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_state' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3741'. created $dff cell `$procdff$23402' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_la_secondword' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3741'. created $dff cell `$procdff$23403' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\prefetched_high_word' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3741'. created $dff cell `$procdff$23404' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_16bit_buffer' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3741'. created $dff cell `$procdff$23405' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_add_sub' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1209$4265'. created $dff cell `$procdff$23406' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_shl' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1209$4265'. created $dff cell `$procdff$23407' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_shr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1209$4265'. created $dff cell `$procdff$23408' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_eq' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1209$4265'. created $dff cell `$procdff$23409' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_ltu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1209$4265'. created $dff cell `$procdff$23410' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_lts' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1209$4265'. created $dff cell `$procdff$23411' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\next_insn_opcode' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:414$3703'. created $dff cell `$procdff$23412' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_rdata_q' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:414$3703'. created $dff cell `$procdff$23413' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_la_firstword_reg' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:374$3695'. created $dff cell `$procdff$23414' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\last_mem_valid' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:374$3695'. created $dff cell `$procdff$23415' with positive edge clock. Creating register for signal `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.\stb' using process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:102$5250'. created $dff cell `$procdff$23416' with positive edge clock. Creating register for signal `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.\shift' using process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:95$5249'. created $dff cell `$procdff$23417' with positive edge clock. Creating register for signal `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.\bit_cnt' using process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:88$5246'. created $dff cell `$procdff$23418' with positive edge clock. Creating register for signal `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.\div_cnt' using process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:77$5242'. created $dff cell `$procdff$23419' with positive edge clock. Creating register for signal `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.\active' using process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:70$5238'. created $adff cell `$procdff$23420' with positive edge clock and positive level reset. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.\rdata' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3511'. created $dff cell `$procdff$23421' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3507_ADDR' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3511'. created $dff cell `$procdff$23422' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3507_DATA' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3511'. created $dff cell `$procdff$23423' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3507_EN' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3511'. created $dff cell `$procdff$23424' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3508_ADDR' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3511'. created $dff cell `$procdff$23425' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3508_DATA' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3511'. created $dff cell `$procdff$23426' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3508_EN' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3511'. created $dff cell `$procdff$23427' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3509_ADDR' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3511'. created $dff cell `$procdff$23428' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3509_DATA' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3511'. created $dff cell `$procdff$23429' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3509_EN' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3511'. created $dff cell `$procdff$23430' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3510_ADDR' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3511'. created $dff cell `$procdff$23431' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3510_DATA' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3511'. created $dff cell `$procdff$23432' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3510_EN' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3511'. created $dff cell `$procdff$23433' with positive edge clock. Creating register for signal `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.\led_ctrl' using process `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.$proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3502'. created $adff cell `$procdff$23434' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\evt_cnt' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:536$3496'. created $adff cell `$procdff$23435' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\sof_pending' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:656$3491'. created $dff cell `$procdff$23436' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\sof_ind' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:653$3489'. created $dff cell `$procdff$23437' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\pad_pu' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:643$3488'. created $dff cell `$procdff$23438' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\rst_pending' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:636$3484'. created $adff cell `$procdff$23439' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\timeout_reset' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:628$3480'. created $dff cell `$procdff$23440' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\timeout_suspend' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:619$3476'. created $dff cell `$procdff$23441' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\eps_bus_ack_wait' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:514$3462'. created $adff cell `$procdff$23442' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\eps_bus_req_ok_dly' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:510$3459'. created $dff cell `$procdff$23443' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\eps_bus_read' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3449'. created $dff cell `$procdff$23444' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\eps_bus_write' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3449'. created $dff cell `$procdff$23445' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\eps_bus_req' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3449'. created $dff cell `$procdff$23446' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\cr_pu_ena' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3447'. created $adff cell `$procdff$23447' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\cr_cel_ena' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3447'. created $adff cell `$procdff$23448' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\cr_addr_chk' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3447'. created $adff cell `$procdff$23449' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\cr_addr' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3447'. created $adff cell `$procdff$23450' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\cel_rel' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3425'. created $dff cell `$procdff$23451' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\csr_bus_req' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3425'. created $dff cell `$procdff$23452' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\cr_bus_we' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3425'. created $dff cell `$procdff$23453' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\ir_bus_we' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3425'. created $dff cell `$procdff$23454' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\evt_rd_ack' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3425'. created $dff cell `$procdff$23455' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\rst_clear' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3425'. created $dff cell `$procdff$23456' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\sof_clear' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3425'. created $dff cell `$procdff$23457' with positive edge clock. Creating register for signal `$paramod\xclk_wb\DW=16\AW=12.\m_cyc_i' using process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:99$3421'. created $adff cell `$procdff$23458' with positive edge clock and positive level reset. Creating register for signal `$paramod\xclk_wb\DW=16\AW=12.\s_cyc_d' using process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:83$3417'. created $dff cell `$procdff$23459' with positive edge clock. Creating register for signal `$paramod\xclk_wb\DW=16\AW=12.\s_ack_d' using process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:83$3417'. created $dff cell `$procdff$23460' with positive edge clock. Creating register for signal `$paramod\xclk_wb\DW=16\AW=12.\s_rdata' using process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:73$3414'. created $dff cell `$procdff$23461' with positive edge clock. Creating register for signal `$paramod\xclk_wb\DW=16\AW=12.\m_rdata_i' using process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:68$3413'. created $dff cell `$procdff$23462' with positive edge clock. Creating register for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\sda_oe' using process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:214$5225'. created $dff cell `$procdff$23463' with positive edge clock. Creating register for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\scl_oe' using process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:204$5222'. created $dff cell `$procdff$23464' with positive edge clock. Creating register for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\data_reg' using process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:159$5218'. created $dff cell `$procdff$23465' with positive edge clock. Creating register for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\bit_cnt' using process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:141$5214'. created $dff cell `$procdff$23466' with positive edge clock. Creating register for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\cyc_cnt' using process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:129$5210'. created $dff cell `$procdff$23467' with positive edge clock. Creating register for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\cmd_cur' using process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:121$5209'. created $dff cell `$procdff$23468' with positive edge clock. Creating register for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\state' using process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:81$5203'. created $dff cell `$procdff$23469' with positive edge clock. Creating register for signal `$paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001.\out' using process `$paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:133$5202'. created $dff cell `$procdff$23470' with positive edge clock. Creating register for signal `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.\pb_rst_n' using process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:184$3325'. created $adff cell `$procdff$23471' with positive edge clock and positive level reset. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\uart_div' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:193$3311'. created $dff cell `$procdff$23472' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_rdata' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:185$3309'. created $dff cell `$procdff$23473' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_ack' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:177$3299'. created $dff cell `$procdff$23474' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_rd_data' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3282'. created $dff cell `$procdff$23475' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_rd_ctrl' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3282'. created $dff cell `$procdff$23476' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_wr_data' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3282'. created $dff cell `$procdff$23477' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_wr_div' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3282'. created $dff cell `$procdff$23478' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\urf_overflow' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:154$3277'. created $adff cell `$procdff$23479' with positive edge clock and positive level reset. Creating register for signal `$paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0.\wb_rdata' using process `$paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master_wb.v:91$3272'. created $dff cell `$procdff$23480' with positive edge clock. Creating register for signal `$paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0.\wb_ack' using process `$paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master_wb.v:85$3264'. created $dff cell `$procdff$23481' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\srio_clk_o' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:291$3262'. created $dff cell `$procdff$23482' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\srio_dat_o' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:291$3262'. created $dff cell `$procdff$23483' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\srio_rclk_o' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:291$3262'. created $dff cell `$procdff$23484' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\srio_rclk_oe' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:291$3262'. created $dff cell `$procdff$23485' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\shift_data' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:279$3261'. created $dff cell `$procdff$23486' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\btn_stb' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:270$3249'. created $dff cell `$procdff$23487' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\btn_val' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:262$3242'. created $dff cell `$procdff$23488' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\sense_cnt_in' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:243$3236'. created $dff cell `$procdff$23489' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\sense_cnt' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:243$3236'. created $dff cell `$procdff$23490' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\bit_cnt' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:227$3229'. created $dff cell `$procdff$23491' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\tick_cnt' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:214$3223'. created $dff cell `$procdff$23492' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\btn_sync' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:206$3222'. created $dff cell `$procdff$23493' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\sio_sel' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:197$3220'. created $dff cell `$procdff$23494' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\state' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:114$3207'. created $dff cell `$procdff$23495' with positive edge clock. Creating register for signal `\hdb3_enc.\pstate' using process `\hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:45$446'. created $dff cell `$procdff$23496' with positive edge clock. Creating register for signal `\hdb3_enc.\d_pos' using process `\hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:45$446'. created $dff cell `$procdff$23497' with positive edge clock. Creating register for signal `\hdb3_enc.\d_neg' using process `\hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:45$446'. created $dff cell `$procdff$23498' with positive edge clock. Creating register for signal `\hdb3_enc.\zcnt' using process `\hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:45$446'. created $dff cell `$procdff$23499' with positive edge clock. Creating register for signal `\hdb3_enc.\vstate' using process `\hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:45$446'. created $dff cell `$procdff$23500' with positive edge clock. Creating register for signal `\hdb3_enc.\out_valid' using process `\hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:41$445'. created $dff cell `$procdff$23501' with positive edge clock. Creating register for signal `\hdb3_dec.\data' using process `\hdb3_dec.$proc$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:43$442'. created $dff cell `$procdff$23502' with positive edge clock. Creating register for signal `\hdb3_dec.\pstate' using process `\hdb3_dec.$proc$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:43$442'. created $dff cell `$procdff$23503' with positive edge clock. Creating register for signal `\hdb3_dec.\out_valid' using process `\hdb3_dec.$proc$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:37$437'. created $dff cell `$procdff$23504' with positive edge clock. Creating register for signal `\e1_tx_framer.\out_valid' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:251$251'. created $adff cell `$procdff$23505' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\out_bit' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:251$251'. created $adff cell `$procdff$23506' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\crc_smf' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:239$249'. created $adff cell `$procdff$23507' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\crc_capture' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:227$248'. created $dff cell `$procdff$23508' with positive edge clock. Creating register for signal `\e1_tx_framer.\shift_at_first' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:207$236'. created $adff cell `$procdff$23509' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\shift_at_last' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:207$236'. created $adff cell `$procdff$23510' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\shift_at_crc' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:207$236'. created $adff cell `$procdff$23511' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\shift_data' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:197$233'. created $adff cell `$procdff$23512' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\bit_cnt' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:190$229'. created $adff cell `$procdff$23513' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\shift_data_nxt' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:165$226'. created $dff cell `$procdff$23514' with positive edge clock. Creating register for signal `\e1_tx_framer.\fetch_done' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:146$222'. created $adff cell `$procdff$23515' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\in_req' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:142$221'. created $dff cell `$procdff$23516' with positive edge clock. Creating register for signal `\e1_tx_framer.\in_mf_first' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:133$217'. created $adff cell `$procdff$23517' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\in_mf_last' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:133$217'. created $adff cell `$procdff$23518' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\fetch_ts' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:118$214'. created $adff cell `$procdff$23519' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\fetch_ts_is0' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:118$214'. created $adff cell `$procdff$23520' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\fetch_ts_is31' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:118$214'. created $adff cell `$procdff$23521' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\fetch_frame' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:111$212'. created $adff cell `$procdff$23522' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\strobe' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:101$208'. created $dff cell `$procdff$23523' with positive edge clock. Creating register for signal `\e1_tx_framer.\tick_cnt' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:95$204'. created $adff cell `$procdff$23524' with positive edge clock and positive level reset. Creating register for signal `\e1_rx_filter.\out_hi' using process `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:71$166'. created $dff cell `$procdff$23525' with positive edge clock. Creating register for signal `\e1_rx_filter.\out_lo' using process `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:71$166'. created $dff cell `$procdff$23526' with positive edge clock. Creating register for signal `\e1_rx_filter.\out_stb' using process `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:71$166'. created $dff cell `$procdff$23527' with positive edge clock. Creating register for signal `\e1_rx_filter.\cnt_hi' using process `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:46$147'. created $dff cell `$procdff$23528' with positive edge clock. Creating register for signal `\e1_rx_filter.\cnt_lo' using process `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:46$147'. created $dff cell `$procdff$23529' with positive edge clock. Creating register for signal `\e1_rx_filter.\in_hi_r' using process `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:39$146'. created $dff cell `$procdff$23530' with positive edge clock. Creating register for signal `\e1_rx_filter.\in_lo_r' using process `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:39$146'. created $dff cell `$procdff$23531' with positive edge clock. Creating register for signal `\e1_rx_deframer.\aligned' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:406$144'. created $dff cell `$procdff$23532' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_data' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$138'. created $dff cell `$procdff$23533' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_frame' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$138'. created $dff cell `$procdff$23534' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_ts' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$138'. created $dff cell `$procdff$23535' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_ts_is0' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$138'. created $dff cell `$procdff$23536' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_first' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$138'. created $dff cell `$procdff$23537' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_last' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$138'. created $dff cell `$procdff$23538' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_valid' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$138'. created $dff cell `$procdff$23539' with positive edge clock. Creating register for signal `\e1_rx_deframer.\error' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:357$130'. created $dff cell `$procdff$23540' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ec_fas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$112'. created $dff cell `$procdff$23541' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ec_nfas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$112'. created $dff cell `$procdff$23542' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ec_crc' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$112'. created $dff cell `$procdff$23543' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ec_mfa' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$112'. created $dff cell `$procdff$23544' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ed_crc' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$92'. created $dff cell `$procdff$23545' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ep_crc' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$92'. created $dff cell `$procdff$23546' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ed_mfa' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$92'. created $dff cell `$procdff$23547' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ep_mfa' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$92'. created $dff cell `$procdff$23548' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ed_fas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$70'. created $dff cell `$procdff$23549' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ep_fas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$70'. created $dff cell `$procdff$23550' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ed_nfas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$70'. created $dff cell `$procdff$23551' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ep_nfas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$70'. created $dff cell `$procdff$23552' with positive edge clock. Creating register for signal `\e1_rx_deframer.\crc_smf' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:306$69'. created $dff cell `$procdff$23553' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts0_msbs' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:274$58'. created $dff cell `$procdff$23554' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts0_msbs_match_mf' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:274$58'. created $dff cell `$procdff$23555' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts0_msbs_match_crc' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:274$58'. created $dff cell `$procdff$23556' with positive edge clock. Creating register for signal `\e1_rx_deframer.\mfa_timeout' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:266$54'. created $dff cell `$procdff$23557' with positive edge clock. Creating register for signal `\e1_rx_deframer.\fas_pos' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:258$50'. created $dff cell `$procdff$23558' with positive edge clock. Creating register for signal `\e1_rx_deframer.\frame' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$40'. created $dff cell `$procdff$23559' with positive edge clock. Creating register for signal `\e1_rx_deframer.\frame_smf_first' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$40'. created $dff cell `$procdff$23560' with positive edge clock. Creating register for signal `\e1_rx_deframer.\frame_smf_last' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$40'. created $dff cell `$procdff$23561' with positive edge clock. Creating register for signal `\e1_rx_deframer.\frame_mf_first' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$40'. created $dff cell `$procdff$23562' with positive edge clock. Creating register for signal `\e1_rx_deframer.\frame_mf_last' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$40'. created $dff cell `$procdff$23563' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:219$36'. created $dff cell `$procdff$23564' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts_is_ts0' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:219$36'. created $dff cell `$procdff$23565' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts_is_ts31' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:219$36'. created $dff cell `$procdff$23566' with positive edge clock. Creating register for signal `\e1_rx_deframer.\bit' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:207$32'. created $dff cell `$procdff$23567' with positive edge clock. Creating register for signal `\e1_rx_deframer.\bit_first' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:207$32'. created $dff cell `$procdff$23568' with positive edge clock. Creating register for signal `\e1_rx_deframer.\bit_last' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:207$32'. created $dff cell `$procdff$23569' with positive edge clock. Creating register for signal `\e1_rx_deframer.\fsm_state' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:142$22'. created $dff cell `$procdff$23570' with positive edge clock. Creating register for signal `\e1_rx_deframer.\data_match_fas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:133$19'. created $dff cell `$procdff$23571' with positive edge clock. Creating register for signal `\e1_rx_deframer.\data' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:128$18'. created $dff cell `$procdff$23572' with positive edge clock. Creating register for signal `\e1_rx_deframer.\strobe' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:121$17'. created $dff cell `$procdff$23573' with positive edge clock. Creating register for signal `\e1_rx_clock_recovery.\cnt' using process `\e1_rx_clock_recovery.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:32$15'. created $dff cell `$procdff$23574' with positive edge clock. Creating register for signal `\e1_crc4.\state' using process `\e1_crc4.$proc$/build/gateware/cores/no2e1//rtl/e1_crc4.v:38$13'. created $dff cell `$procdff$23575' with positive edge clock. 75.3.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3070'. Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$3067'. Removing empty process `SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$3067'. Removing empty process `SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3066'. Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1274$3060'. Removing empty process `SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1274$3060'. Removing empty process `SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3059'. Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$3056'. Removing empty process `SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$3056'. Removing empty process `SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3055'. Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1143$3049'. Removing empty process `SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1143$3049'. Removing empty process `SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3048'. Removing empty process `SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1074$3046'. Removing empty process `SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3045'. Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1026$3043'. Removing empty process `SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1026$3043'. Removing empty process `SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3042'. Removing empty process `SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:957$3040'. Removing empty process `SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3039'. Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:909$3037'. Removing empty process `SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:909$3037'. Removing empty process `SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3036'. Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:866$3035'. Removing empty process `SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:866$3035'. Removing empty process `SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3034'. Removing empty process `SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:830$3033'. Removing empty process `SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3032'. Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$3029'. Removing empty process `SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$3029'. Removing empty process `SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3028'. Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:697$3022'. Removing empty process `SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:697$3022'. Removing empty process `SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3021'. Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$3018'. Removing empty process `SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$3018'. Removing empty process `SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3017'. Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:566$3011'. Removing empty process `SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:566$3011'. Removing empty process `SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3010'. Removing empty process `SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:497$3008'. Removing empty process `SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3007'. Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:449$3005'. Removing empty process `SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:449$3005'. Removing empty process `SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3004'. Removing empty process `SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:380$3002'. Removing empty process `SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3001'. Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:332$2999'. Removing empty process `SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:332$2999'. Removing empty process `SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2998'. Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:289$2997'. Removing empty process `SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:289$2997'. Removing empty process `SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2996'. Removing empty process `SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:253$2995'. Removing empty process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$5199'. Found and cleaned up 1 empty switch in `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$5194'. Removing empty process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$5194'. Found and cleaned up 3 empty switches in `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$5190'. Removing empty process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$5190'. Found and cleaned up 1 empty switch in `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$5186'. Removing empty process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$5186'. Found and cleaned up 2 empty switches in `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$5178'. Removing empty process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$5178'. Removing empty process `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v:50$5175'. Found and cleaned up 1 empty switch in `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5154'. Removing empty process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5154'. Found and cleaned up 3 empty switches in `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$5145'. Removing empty process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$5145'. Found and cleaned up 1 empty switch in `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5142'. Removing empty process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5142'. Removing empty process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5123'. Removing empty process `$paramod\wb_epbuf\AW=9\DW=32.$proc$/build/gateware/common/rtl/wb_epbuf.v:51$5111'. Found and cleaned up 1 empty switch in `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5100'. Removing empty process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5100'. Found and cleaned up 2 empty switches in `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$5093'. Removing empty process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$5093'. Found and cleaned up 1 empty switch in `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5090'. Removing empty process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5090'. Removing empty process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5077'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$5058'. Found and cleaned up 1 empty switch in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:178$5054'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:178$5054'. Found and cleaned up 1 empty switch in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:174$5051'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:174$5051'. Found and cleaned up 1 empty switch in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:157$5041'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:157$5041'. Found and cleaned up 1 empty switch in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:153$5037'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:153$5037'. Found and cleaned up 1 empty switch in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:142$5035'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:142$5035'. Found and cleaned up 4 empty switches in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:98$5019'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:98$5019'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:92$5018'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:86$5014'. Removing empty process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$5010'. Removing empty process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$5006'. Removing empty process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$5002'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5573'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5569'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5565'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5561'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5557'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5553'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5549'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5545'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5541'. Found and cleaned up 1 empty switch in `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4972'. Removing empty process `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4972'. Found and cleaned up 1 empty switch in `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4959'. Removing empty process `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4959'. Found and cleaned up 2 empty switches in `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4935'. Removing empty process `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4935'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5518'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5514'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5510'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5506'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5502'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5498'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5494'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5490'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5486'. Found and cleaned up 2 empty switches in `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5462'. Removing empty process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5462'. Found and cleaned up 1 empty switch in `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:163$5456'. Removing empty process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:163$5456'. Removing empty process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:160$5454'. Removing empty process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:147$5427'. Removing empty process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:91$5424'. Removing empty process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4816'. Found and cleaned up 16 empty switches in `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660'. Removing empty process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4660'. Found and cleaned up 1 empty switch in `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:73$4659'. Removing empty process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:73$4659'. Removing empty process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:255$4642'. Removing empty process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:248$4638'. Removing empty process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:241$4636'. Found and cleaned up 1 empty switch in `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$4618'. Removing empty process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$4618'. Found and cleaned up 1 empty switch in `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$4617'. Removing empty process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$4617'. Found and cleaned up 1 empty switch in `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$4609'. Removing empty process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$4609'. Removing empty process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:265$4603'. Removing empty process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:258$4601'. Found and cleaned up 1 empty switch in `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:152$4578'. Removing empty process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:152$4578'. Found and cleaned up 1 empty switch in `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:122$4577'. Removing empty process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:122$4577'. Found and cleaned up 1 empty switch in `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:112$4569'. Removing empty process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:112$4569'. Removing empty process `sysmgr.$proc$/build/gateware/icE1usb/rtl/sysmgr.v:84$1722'. Found and cleaned up 1 empty switch in `\sysmgr.$proc$/build/gateware/icE1usb/rtl/sysmgr.v:76$1717'. Removing empty process `sysmgr.$proc$/build/gateware/icE1usb/rtl/sysmgr.v:76$1717'. Found and cleaned up 2 empty switches in `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:160$4564'. Removing empty process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:160$4564'. Removing empty process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:100$4556'. Found and cleaned up 1 empty switch in `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:93$4554'. Removing empty process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:93$4554'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1657'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1655'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1653'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1651'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1649'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1647'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1645'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1643'. Found and cleaned up 1 empty switch in `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:314$1642'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:314$1642'. Found and cleaned up 4 empty switches in `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:272$1641'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:272$1641'. Found and cleaned up 1 empty switch in `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:235$1638'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:235$1638'. Found and cleaned up 1 empty switch in `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:186$1637'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:186$1637'. Found and cleaned up 1 empty switch in `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:173$1636'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:173$1636'. Found and cleaned up 2 empty switches in `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:134$1635'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:134$1635'. Found and cleaned up 1 empty switch in `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:112$1624'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:112$1624'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:106$1619'. Removing empty process `led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:89$1606'. Removing empty process `led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:77$1597'. Removing empty process `led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:65$1593'. Removing empty process `led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:55$1589'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:241$1581'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:229$1578'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:202$1572'. Found and cleaned up 1 empty switch in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:191$1568'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:191$1568'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:182$1562'. Found and cleaned up 1 empty switch in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:175$1555'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:175$1555'. Found and cleaned up 1 empty switch in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:170$1553'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:170$1553'. Found and cleaned up 1 empty switch in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:159$1549'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:159$1549'. Found and cleaned up 1 empty switch in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:152$1546'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:152$1546'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:136$1534'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:126$1533'. Found and cleaned up 8 empty switches in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:86$1531'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:86$1531'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:134$1530'. Found and cleaned up 2 empty switches in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1528'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1528'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:110$1521'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:102$1516'. Found and cleaned up 1 empty switch in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1506'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1506'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:79$1503'. Found and cleaned up 4 empty switches in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1500'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1500'. Found and cleaned up 2 empty switches in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:236$1496'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:236$1496'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:428$1488'. Found and cleaned up 1 empty switch in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:421$1485'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:421$1485'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:414$1479'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:403$1478'. Found and cleaned up 1 empty switch in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:399$1475'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:399$1475'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:387$1469'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:380$1467'. Found and cleaned up 2 empty switches in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1454'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1454'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:345$1451'. Found and cleaned up 4 empty switches in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1446'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1446'. Found and cleaned up 1 empty switch in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1442'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1442'. Found and cleaned up 1 empty switch in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1435'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1435'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:225$1430'. Found and cleaned up 2 empty switches in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1427'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1427'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:175$1418'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:162$1409'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:374$1406'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:353$1397'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:349$1395'. Found and cleaned up 1 empty switch in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:340$1392'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:340$1392'. Found and cleaned up 1 empty switch in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:336$1389'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:336$1389'. Found and cleaned up 1 empty switch in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1372'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1372'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:318$1371'. Found and cleaned up 1 empty switch in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:304$1350'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:304$1350'. Found and cleaned up 2 empty switches in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1346'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1346'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:284$1345'. Found and cleaned up 2 empty switches in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:244$1343'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:244$1343'. Found and cleaned up 2 empty switches in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:230$1340'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:230$1340'. Found and cleaned up 2 empty switches in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:220$1337'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:220$1337'. Found and cleaned up 1 empty switch in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:215$1336'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:215$1336'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:198$1328'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:188$1327'. Found and cleaned up 18 empty switches in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:117$1311'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:117$1311'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:49$1310'. Found and cleaned up 1 empty switch in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:181$1308'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:181$1308'. Found and cleaned up 3 empty switches in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1306'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1306'. Found and cleaned up 3 empty switches in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:137$1305'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:137$1305'. Found and cleaned up 2 empty switches in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:124$1304'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:124$1304'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:120$1303'. Found and cleaned up 1 empty switch in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:111$1296'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:111$1296'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:97$1289'. Found and cleaned up 2 empty switches in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1288'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1288'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:67$1278'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4553'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4544'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4544'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4542'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4542'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4533'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4533'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4531'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4531'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4522'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4522'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4520'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4520'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4511'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4511'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4509'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4509'. Found and cleaned up 1 empty switch in `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:80$1274'. Removing empty process `usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:80$1274'. Found and cleaned up 1 empty switch in `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:76$1272'. Removing empty process `usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:76$1272'. Removing empty process `usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1269'. Removing empty process `usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1261'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4507'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4498'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4498'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4496'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4496'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4487'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4487'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4485'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4485'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4476'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4476'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4474'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4474'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4465'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4465'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4463'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4463'. Removing empty process `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:212$4451'. Removing empty process `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:205$4445'. Removing empty process `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:197$4441'. Removing empty process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:0$5383'. Found and cleaned up 1 empty switch in `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:124$5378'. Removing empty process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:124$5378'. Removing empty process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:116$5373'. Removing empty process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:105$5368'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4408'. Found and cleaned up 1 empty switch in `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4403'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4403'. Found and cleaned up 3 empty switches in `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4399'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4399'. Found and cleaned up 1 empty switch in `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4395'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4395'. Found and cleaned up 2 empty switches in `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4387'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4387'. Removing empty process `xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:40$1106'. Removing empty process `xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:34$1105'. Removing empty process `xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:28$1103'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5359'. Found and cleaned up 1 empty switch in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:163$5358'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:163$5358'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:153$5353'. Found and cleaned up 1 empty switch in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:143$5352'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:143$5352'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:123$5351'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5346'. Found and cleaned up 1 empty switch in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5345'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5345'. Found and cleaned up 1 empty switch in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$5335'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$5335'. Found and cleaned up 5 empty switches in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5302'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5302'. Found and cleaned up 1 empty switch in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:212$5299'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:212$5299'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:206$5297'. Found and cleaned up 4 empty switches in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$5295'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$5295'. Removing empty process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:67$5268'. Found and cleaned up 2 empty switches in `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5267'. Removing empty process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5267'. Found and cleaned up 2 empty switches in `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:51$5264'. Removing empty process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:51$5264'. Found and cleaned up 1 empty switch in `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:42$5260'. Removing empty process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:42$5260'. Removing empty process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:35$5256'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4348'. Removing empty process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4348'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4342'. Removing empty process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4342'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4340'. Removing empty process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4340'. Removing empty process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:83$4331'. Removing empty process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:67$4325'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4324'. Found and cleaned up 1 empty switch in `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4319'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4319'. Found and cleaned up 3 empty switches in `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4315'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4315'. Found and cleaned up 1 empty switch in `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4311'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4311'. Found and cleaned up 2 empty switches in `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4303'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4303'. Removing empty process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:149$4302'. Found and cleaned up 2 empty switches in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4293'. Removing empty process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4293'. Removing empty process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:109$4289'. Removing empty process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:103$4287'. Removing empty process `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:67$4283'. Found and cleaned up 1 empty switch in `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:42$4280'. Removing empty process `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:42$4280'. Removing empty process `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:72$4279'. Found and cleaned up 1 empty switch in `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:42$4276'. Removing empty process `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:42$4276'. Found and cleaned up 55 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4100'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$4086'. Found and cleaned up 2 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1288$4072'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1288$4072'. Found and cleaned up 2 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1274$4067'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1274$4067'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1272$4066'. Found and cleaned up 2 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1228$4044'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1228$4044'. Found and cleaned up 8 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1165$4032'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1165$4032'. Found and cleaned up 22 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3772'. Found and cleaned up 3 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3770'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3770'. Found and cleaned up 5 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3766'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3766'. Found and cleaned up 47 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:684$3765'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:684$3765'. Found and cleaned up 16 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3741'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3741'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1209$4265'. Found and cleaned up 19 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:414$3703'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:414$3703'. Found and cleaned up 3 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3700'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3700'. Found and cleaned up 2 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:374$3695'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:374$3695'. Found and cleaned up 1 empty switch in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3621'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3621'. Removing empty process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:102$5250'. Found and cleaned up 1 empty switch in `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:95$5249'. Removing empty process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:95$5249'. Found and cleaned up 2 empty switches in `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:88$5246'. Removing empty process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:88$5246'. Found and cleaned up 2 empty switches in `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:77$5242'. Removing empty process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:77$5242'. Removing empty process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:70$5238'. Found and cleaned up 4 empty switches in `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3511'. Removing empty process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3511'. Found and cleaned up 1 empty switch in `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.$proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3502'. Removing empty process `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.$proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3502'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:536$3496'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:656$3491'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:653$3489'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:643$3488'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:643$3488'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:636$3484'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:628$3480'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:628$3480'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:619$3476'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:619$3476'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:514$3462'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:510$3459'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3449'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3449'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:697$3500'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3447'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3447'. Found and cleaned up 2 empty switches in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:442$3443'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:442$3443'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3425'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3425'. Removing empty process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:99$3421'. Removing empty process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:83$3417'. Found and cleaned up 1 empty switch in `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:73$3414'. Removing empty process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:73$3414'. Found and cleaned up 1 empty switch in `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:68$3413'. Removing empty process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:68$3413'. Removing empty process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:0$5234'. Removing empty process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:0$5233'. Found and cleaned up 6 empty switches in `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:214$5225'. Removing empty process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:214$5225'. Found and cleaned up 4 empty switches in `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:204$5222'. Removing empty process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:204$5222'. Found and cleaned up 2 empty switches in `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:159$5218'. Removing empty process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:159$5218'. Found and cleaned up 3 empty switches in `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:141$5214'. Removing empty process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:141$5214'. Found and cleaned up 1 empty switch in `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:129$5210'. Removing empty process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:129$5210'. Found and cleaned up 1 empty switch in `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:121$5209'. Removing empty process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:121$5209'. Found and cleaned up 7 empty switches in `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:87$5204'. Removing empty process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:87$5204'. Found and cleaned up 1 empty switch in `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:81$5203'. Removing empty process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:81$5203'. Found and cleaned up 1 empty switch in `$paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:133$5202'. Removing empty process `$paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:133$5202'. Removing empty process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3330'. Removing empty process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3328'. Removing empty process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3326'. Removing empty process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:184$3325'. Found and cleaned up 1 empty switch in `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:193$3311'. Removing empty process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:193$3311'. Found and cleaned up 1 empty switch in `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:185$3309'. Removing empty process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:185$3309'. Found and cleaned up 1 empty switch in `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:177$3299'. Removing empty process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:177$3299'. Found and cleaned up 1 empty switch in `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3282'. Removing empty process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3282'. Removing empty process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:154$3277'. Found and cleaned up 1 empty switch in `$paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master_wb.v:91$3272'. Removing empty process `$paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master_wb.v:91$3272'. Removing empty process `$paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master_wb.v:85$3264'. Found and cleaned up 1 empty switch in `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:291$3262'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:291$3262'. Found and cleaned up 1 empty switch in `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:279$3261'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:279$3261'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:270$3249'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:262$3242'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:243$3236'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:227$3229'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:214$3223'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:206$3222'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:197$3220'. Found and cleaned up 9 empty switches in `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:121$3208'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:121$3208'. Found and cleaned up 1 empty switch in `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:114$3207'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:114$3207'. Found and cleaned up 5 empty switches in `\hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:45$446'. Removing empty process `hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:45$446'. Removing empty process `hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:41$445'. Found and cleaned up 4 empty switches in `\hdb3_dec.$proc$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:43$442'. Removing empty process `hdb3_dec.$proc$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:43$442'. Removing empty process `hdb3_dec.$proc$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:37$437'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:251$251'. Found and cleaned up 2 empty switches in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:239$249'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:239$249'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:227$248'. Found and cleaned up 1 empty switch in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:207$236'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:207$236'. Found and cleaned up 1 empty switch in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:197$233'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:197$233'. Found and cleaned up 1 empty switch in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:190$229'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:190$229'. Found and cleaned up 2 empty switches in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:165$226'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:165$226'. Found and cleaned up 1 empty switch in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:146$222'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:146$222'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:142$221'. Found and cleaned up 1 empty switch in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:133$217'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:133$217'. Found and cleaned up 1 empty switch in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:118$214'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:118$214'. Found and cleaned up 1 empty switch in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:111$212'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:111$212'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:101$208'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:95$204'. Found and cleaned up 4 empty switches in `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:71$166'. Removing empty process `e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:71$166'. Found and cleaned up 5 empty switches in `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:46$147'. Removing empty process `e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:46$147'. Removing empty process `e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:39$146'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:406$144'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:406$144'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$138'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$138'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:357$130'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$112'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$112'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$92'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$92'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$70'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$70'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:306$69'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:306$69'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:274$58'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:274$58'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:266$54'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:266$54'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:258$50'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:258$50'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$40'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$40'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:219$36'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:219$36'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:207$32'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:207$32'. Found and cleaned up 10 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:149$24'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:149$24'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:142$22'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:142$22'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:133$19'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:133$19'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:128$18'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:128$18'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:121$17'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:121$17'. Found and cleaned up 3 empty switches in `\e1_rx_clock_recovery.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:32$15'. Removing empty process `e1_rx_clock_recovery.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:32$15'. Found and cleaned up 1 empty switch in `\e1_crc4.$proc$/build/gateware/cores/no2e1//rtl/e1_crc4.v:38$13'. Removing empty process `e1_crc4.$proc$/build/gateware/cores/no2e1//rtl/e1_crc4.v:38$13'. Cleaned up 539 empty switches. 75.4. Executing FLATTEN pass (flatten design). Deleting now unused module $paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0. Deleting now unused module $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0. Deleting now unused module $paramod\wb_arbiter\N=3\DW=32\AW=14. Deleting now unused module $paramod\wb_epbuf\AW=9\DW=32. Deleting now unused module $paramod\wb_arbiter\N=2\DW=32\AW=9. Deleting now unused module soc_iobuf. Deleting now unused module $paramod\wb_dma\A0W=14\A1W=9\DW=32. Deleting now unused module $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr. Deleting now unused module picorv32_ice40_regs. Deleting now unused module $paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf. Deleting now unused module $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100. Deleting now unused module $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101. Deleting now unused module $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000. Deleting now unused module $paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf. Deleting now unused module $paramod\ram_sdp\AWIDTH=9\DWIDTH=8. Deleting now unused module $paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4. Deleting now unused module $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32. Deleting now unused module $paramod\e1_wb_rx\LIU=0\MFW=7. Deleting now unused module capcnt32_sb_mac16. Deleting now unused module capcnt16_sb_mac16. Deleting now unused module $paramod\e1_wb_tx\LIU=0\MFW=7. Deleting now unused module sysmgr. Deleting now unused module $paramod\e1_tx\LIU=0\MFW=7. Deleting now unused module misc. Deleting now unused module led_blinker. Deleting now unused module usb_tx_pkt. Deleting now unused module usb_tx_ll. Deleting now unused module usb_trans. Deleting now unused module usb_rx_pkt. Deleting now unused module usb_rx_ll. Deleting now unused module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Deleting now unused module usb_ep_status. Deleting now unused module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Deleting now unused module $paramod\e1_rx\LIU=0\MFW=7. Deleting now unused module $paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7. Deleting now unused module $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1. Deleting now unused module xclk_strobe. Deleting now unused module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32. Deleting now unused module $paramod\uart_tx\DIV_WIDTH=12. Deleting now unused module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Deleting now unused module $paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1. Deleting now unused module $paramod\capcnt\W=32. Deleting now unused module $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0. Deleting now unused module $paramod\capcnt\W=16. Deleting now unused module $paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm. Deleting now unused module $paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm. Deleting now unused module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Deleting now unused module $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2. Deleting now unused module $paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram. Deleting now unused module $paramod\soc_spram\AW=14. Deleting now unused module $paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0. Deleting now unused module $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb. Deleting now unused module $paramod\usb\EPDW=32. Deleting now unused module $paramod\xclk_wb\DW=16\AW=12. Deleting now unused module $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0. Deleting now unused module $paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001. Deleting now unused module $paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base. Deleting now unused module $paramod\uart_wb\DIV_WIDTH=12\DW=32. Deleting now unused module $paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0. Deleting now unused module $paramod\sr_btn_if\TICK_LOG2_DIV=3. Deleting now unused module hdb3_enc. Deleting now unused module hdb3_dec. Deleting now unused module e1_tx_phy. Deleting now unused module e1_tx_framer. Deleting now unused module e1_rx_phy. Deleting now unused module e1_rx_filter. Deleting now unused module e1_rx_deframer. Deleting now unused module e1_rx_clock_recovery. Deleting now unused module e1_crc4. <suppressed ~84 debug messages> 75.5. Executing TRIBUF pass. 75.6. Executing DEMINOUT pass (demote inout ports to input or output). Demoting inout port top.flash_cs_n to output. 75.7. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~10794 debug messages> 75.8. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 965 unused cells and 14474 unused wires. <suppressed ~1090 debug messages> 75.9. Executing CHECK pass (checking for obvious problems). checking module top.. found and reported 0 problems. 75.10. Executing OPT pass (performing simple optimizations). 75.10.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.10.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~1542 debug messages> Removed a total of 514 cells. 75.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port B of cell $flatten\misc_I.\dfu_I.$procmux$12503: \misc_I.dfu_I.wb_req -> 1'1 Replacing known input bits on port B of cell $flatten\sys_mgr_I.$procmux$11677: \sys_mgr_I.rst_cnt -> { 1'1 \sys_mgr_I.rst_cnt [2:0] } Analyzing evaluation results. dead port 1/2 on $mux $flatten\gps_uart_I.\uart_rx_I.\gf_I.$procmux$12305. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12633. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12639. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12642. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12654. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12661. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12664. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12677. dead port 1/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12687. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12689. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12692. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12701. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12704. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12712. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12714. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12717. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12778. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12780. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12783. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12865. dead port 1/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12868. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12870. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12873. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12912. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12915. dead port 1/3 on $pmux $flatten\soc_I.\cpu_I.$procmux$12926. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12958. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12971. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12984. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$13023. dead port 3/4 on $pmux $flatten\soc_I.\cpu_I.$procmux$13118. dead port 4/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13132. dead port 5/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13132. dead port 6/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13132. dead port 7/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13132. dead port 8/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13132. dead port 10/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13132. dead port 11/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13132. dead port 3/4 on $pmux $flatten\soc_I.\cpu_I.$procmux$13161. dead port 4/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13174. dead port 5/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13174. dead port 6/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13174. dead port 7/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13174. dead port 8/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13174. dead port 10/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13174. dead port 11/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13174. dead port 1/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13220. dead port 2/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13220. dead port 3/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13220. dead port 4/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13220. dead port 5/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13220. dead port 6/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13220. dead port 1/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$13226. dead port 2/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$13226. dead port 3/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$13226. dead port 4/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$13226. dead port 5/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$13226. dead port 4/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13259. dead port 5/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13259. dead port 6/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13259. dead port 7/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13259. dead port 8/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13259. dead port 10/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13259. dead port 11/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13259. dead port 1/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13464. dead port 2/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13464. dead port 3/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13464. dead port 4/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13464. dead port 5/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13464. dead port 6/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13464. dead port 3/4 on $pmux $flatten\soc_I.\cpu_I.$procmux$13528. dead port 4/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13547. dead port 5/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13547. dead port 6/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13547. dead port 7/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13547. dead port 8/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13547. dead port 10/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13547. dead port 11/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13547. dead port 3/4 on $pmux $flatten\soc_I.\cpu_I.$procmux$13729. dead port 4/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13745. dead port 5/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13745. dead port 6/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13745. dead port 7/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13745. dead port 8/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13745. dead port 10/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13745. dead port 11/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13745. dead port 4/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13907. dead port 5/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13907. dead port 6/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13907. dead port 7/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13907. dead port 8/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13907. dead port 10/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13907. dead port 11/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13907. dead port 1/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13958. dead port 2/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13958. dead port 3/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13958. dead port 4/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13958. dead port 5/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13958. dead port 7/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13958. dead port 8/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13958. dead port 1/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$14055. dead port 2/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$14055. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$14060. dead port 1/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$14064. dead port 2/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$14064. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$14069. dead port 1/8 on $pmux $flatten\soc_I.\cpu_I.$procmux$14084. dead port 2/8 on $pmux $flatten\soc_I.\cpu_I.$procmux$14084. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$15215. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$15222. dead port 2/2 on $mux $flatten\i2c_I.\core_I.$procmux$15407. dead port 2/2 on $mux $flatten\i2c_I.\core_I.$procmux$15414. dead port 2/2 on $mux $flatten\i2c_I.\core_I.$procmux$15423. dead port 2/2 on $mux $flatten\i2c_I.\core_I.$procmux$15425. dead port 2/2 on $mux $flatten\i2c_I.\core_I.$procmux$15433. dead port 2/2 on $mux $flatten\i2c_I.\core_I.$procmux$15442. dead port 2/2 on $mux $flatten\i2c_I.\core_I.$procmux$15452. dead port 1/2 on $mux $flatten\soc_I.\e1_buf_I.$procmux$12450. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10003. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10003. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10003. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10003. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10003. dead 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on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10267. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10286. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10286. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10286. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10286. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10307. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10307. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10307. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10307. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10330. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10330. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10330. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10330. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10330. dead 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port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10574. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10574. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10590. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10590. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10590. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10590. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10590. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10610. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10610. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10610. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10610. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10634. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10634. dead port 3/5 on $pmux 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on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10730. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10737. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10737. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10737. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10737. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10737. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10748. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10748. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10748. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10748. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10748. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10770. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10770. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10770. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10770. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10770. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10804. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10804. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10804. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10804. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10834. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10834. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10834. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10834. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10834. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10846. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10846. dead port 3/5 on $pmux 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on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10898. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10898. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10898. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10956. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10956. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10956. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10956. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10956. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10969. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10969. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10969. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10969. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10969. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10984. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10984. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10984. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10984. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10984. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11001. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11001. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11001. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11001. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11001. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11020. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11020. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11020. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11020. dead port 5/5 on $pmux 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on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11089. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11089. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11116. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11116. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11116. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11116. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11116. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11145. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11145. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11145. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11145. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11145. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11176. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11176. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11176. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11176. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11176. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11209. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11209. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11209. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11209. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11209. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11244. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11244. dead port 4/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11244. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11284. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11284. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11284. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11284. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11284. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11294. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11294. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11294. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11294. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11294. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11308. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11308. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11308. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11308. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11308. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11324. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11324. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11324. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11324. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11324. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11344. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11344. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11344. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11344. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11344. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11368. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11368. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11368. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11368. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11368. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11396. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11396. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11396. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11396. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11396. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11428. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11428. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11428. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11428. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11428. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11464. dead port 3/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11464. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11471. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11471. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11471. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11471. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11471. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11482. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11482. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11482. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11482. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11482. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11504. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11504. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11504. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11504. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11504. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11538. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11538. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11538. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11538. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11568. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11568. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11568. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11568. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11568. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11580. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11580. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11580. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11580. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11580. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11598. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11598. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11598. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11598. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11598. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11606. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11606. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11606. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11606. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11606. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11632. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11632. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11632. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11632. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11632. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5818. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5818. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5818. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5818. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5831. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5831. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5831. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5831. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5846. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5846. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5846. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5846. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5863. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5863. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5863. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5863. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5882. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5882. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5882. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5882. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5903. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5903. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5903. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5903. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5926. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5926. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5926. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5926. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5951. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5951. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5951. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5951. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5978. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5978. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5978. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5978. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6007. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6007. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6007. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6007. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6038. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6038. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6038. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6038. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6071. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6071. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6071. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6071. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6106. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6106. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6106. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6146. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6146. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6146. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6146. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6156. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6156. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6156. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6156. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6170. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6170. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6170. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6170. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6186. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6186. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6186. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6186. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6206. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6206. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6206. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6206. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6230. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6230. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6230. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6230. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6258. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6258. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6258. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6258. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6290. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6290. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6290. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6290. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6326. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6326. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6333. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6333. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6333. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6333. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6344. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6344. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6344. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6344. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6366. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6366. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6366. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6366. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6400. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6400. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6400. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6400. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6430. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6430. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6430. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6430. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6442. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6442. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6442. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6442. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6460. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6460. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6460. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6460. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6468. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6468. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6468. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6468. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6494. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6494. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6494. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6494. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6552. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6552. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6552. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6552. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6552. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6565. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6565. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6565. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6565. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6580. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6580. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6580. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6580. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6597. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6597. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6597. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6597. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6616. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6616. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6616. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6616. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6637. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6637. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6637. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6637. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6660. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6660. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6660. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6660. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6685. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6685. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6685. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6685. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6712. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6712. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6712. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6712. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6741. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6741. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6741. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6741. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6772. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6772. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6772. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6772. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6805. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6805. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6805. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6805. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6840. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6840. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6840. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6880. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6880. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6880. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6880. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6880. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6890. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6890. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6890. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6890. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6904. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6904. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6904. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6904. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6920. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6920. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6920. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6920. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6940. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6940. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6940. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6940. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6964. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6964. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6964. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6964. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6992. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6992. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6992. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6992. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7024. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7024. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7024. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7024. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7060. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7060. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7067. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7067. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7067. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7067. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7067. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7078. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7078. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7078. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7078. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7100. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7100. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7100. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7100. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7134. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7134. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7134. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7134. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7164. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7164. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7164. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7164. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7176. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7176. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7176. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7176. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7194. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7194. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7194. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7194. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7202. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7202. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7202. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7202. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7202. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7228. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7228. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7228. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7228. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7286. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7286. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7286. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7286. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7286. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7299. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7299. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7299. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7299. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7314. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7314. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7314. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7314. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7331. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7331. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7331. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7331. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7350. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7350. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7350. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7350. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7371. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7371. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7371. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7371. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7394. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7394. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7394. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7394. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7394. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7419. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7419. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7419. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7419. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7419. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7446. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7446. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7446. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7446. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7475. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7475. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7475. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7475. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7506. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7506. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7506. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7506. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7539. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7539. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7539. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7539. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7574. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7574. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7574. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7614. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7614. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7614. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7614. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7614. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7624. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7624. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7624. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7624. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7638. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7638. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7638. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7638. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7654. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7654. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7654. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7654. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7674. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7674. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7674. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7674. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7698. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7698. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7698. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7698. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7698. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7726. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7726. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7726. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7726. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7758. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7758. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7758. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7758. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7794. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7794. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7801. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7801. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7801. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7801. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7801. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7812. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7812. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7812. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7812. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7834. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7834. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7834. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7834. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7834. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7868. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7868. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7868. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7868. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7898. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7898. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7898. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7898. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7910. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7910. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7910. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7910. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7928. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7928. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7928. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7928. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7936. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7936. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7936. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7936. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7936. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7962. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7962. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7962. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7962. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8020. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8020. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8020. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8020. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8020. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8033. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8033. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8033. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8033. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8033. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8048. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8048. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8048. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8048. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8065. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8065. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8065. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8065. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8084. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8084. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8084. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8084. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8105. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8105. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8105. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8105. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8128. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8128. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8128. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8128. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8128. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8153. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8153. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8153. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8153. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8153. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8180. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8180. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8180. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8180. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8209. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8209. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8209. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8209. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8240. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8240. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8240. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8240. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8273. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8273. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8273. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8273. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8308. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8308. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8308. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8348. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8348. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8348. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8348. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8348. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8358. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8358. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8358. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8358. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8358. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8372. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8372. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8372. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8372. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8388. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8388. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8388. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8388. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8408. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8408. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8408. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8408. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8432. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8432. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8432. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8432. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8432. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8460. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8460. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8460. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8460. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8492. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8492. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8492. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8492. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8528. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8528. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8535. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8535. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8535. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8535. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8535. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8546. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8546. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8546. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8546. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8546. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8568. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8568. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8568. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8568. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8568. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8602. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8602. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8602. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8602. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8632. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8632. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8632. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8632. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8644. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8644. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8644. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8644. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8644. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8662. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8662. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8662. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8662. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8670. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8670. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8670. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8670. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8670. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8696. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8696. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8696. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8696. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8754. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8754. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8754. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8754. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8754. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8767. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8767. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8767. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8767. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8767. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8782. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8782. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8782. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8782. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8799. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8799. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8799. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8799. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8818. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8818. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8818. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8818. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8839. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8839. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8839. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8839. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8862. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8862. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8862. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8862. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8862. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8887. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8887. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8887. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8887. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8887. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8914. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8914. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8914. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8914. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8914. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8943. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8943. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8943. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8943. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8943. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8974. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8974. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8974. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8974. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9007. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9007. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9007. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9007. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9042. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9042. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9042. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9082. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9082. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9082. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9082. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9082. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9092. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9092. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9092. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9092. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9092. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9106. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9106. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9106. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9106. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9122. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9122. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9122. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9122. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9142. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9142. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9142. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9142. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9166. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9166. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9166. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9166. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9166. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9194. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9194. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9194. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9194. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9194. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9226. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9226. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9226. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9226. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9262. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9262. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9269. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9269. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9269. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9269. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9269. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9280. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9280. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9280. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9280. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9280. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9302. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9302. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9302. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9302. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9302. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9336. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9336. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9336. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9336. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9366. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9366. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9366. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9366. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9378. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9378. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9378. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9378. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9378. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9396. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9396. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9396. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9396. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9404. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9404. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9404. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9404. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9404. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9430. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9430. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9430. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9430. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9430. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9488. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9488. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9488. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9488. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9488. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9501. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9501. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9501. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9501. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9501. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9516. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9516. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9516. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9516. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9516. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9533. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9533. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9533. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9533. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9533. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9552. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9552. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9552. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9552. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9573. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9573. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9573. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9573. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9596. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9596. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9596. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9596. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9596. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9621. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9621. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9621. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9621. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9621. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9648. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9648. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9648. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9648. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9648. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9677. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9677. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9677. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9677. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9677. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9708. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9708. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9708. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9708. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9741. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9741. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9741. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9741. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9776. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9776. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9776. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9816. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9816. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9816. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9816. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9816. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9826. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9826. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9826. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9826. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9826. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9840. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9840. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9840. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9840. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9840. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9856. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9856. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9856. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9856. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9856. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9876. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9876. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9876. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9876. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9900. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9900. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9900. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9900. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9900. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9928. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9928. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9928. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9928. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9928. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9960. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9960. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9960. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9960. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9996. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9996. dead port 1/2 on $mux $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procmux$12305. dead port 2/2 on $mux $flatten\soc_I.\usb_I.$procmux$15327. dead port 1/2 on $mux $flatten\misc_I.\dfu_I.\btn_flt_I.$procmux$5644. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11979. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11981. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11983. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11990. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11992. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11998. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12006. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12008. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12015. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12024. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12026. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12034. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12044. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12046. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12055. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12065. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12078. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12081. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12084. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12086. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12088. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12101. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12104. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12106. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12108. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12121. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12123. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12125. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12137. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12139. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12150. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12162. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12175. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11770. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11777. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11785. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11796. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11798. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11800. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11810. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11812. dead port 1/2 on $mux $flatten\misc_I.\pps_flt_I.$procmux$12495. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11821. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11832. dead port 2/2 on $mux $flatten\spi_mux_I.$procmux$15514. dead port 2/2 on $mux $flatten\spi_mux_I.$procmux$15521. dead port 2/2 on $mux $flatten\spi_mux_I.$procmux$15529. dead port 2/2 on $mux $flatten\spi_mux_I.$procmux$15538. dead port 2/2 on $mux $flatten\spi_mux_I.$procmux$15548. dead port 2/2 on $mux $flatten\spi_mux_I.$procmux$15559. dead port 1/2 on $mux $flatten\spi_mux_I.$procmux$15572. dead port 2/2 on $mux $flatten\spi_mux_I.$procmux$15574. dead port 2/2 on $mux $flatten\spi_mux_I.$procmux$15586. Removed 2334 multiplexer ports. <suppressed ~615 debug messages> 75.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $flatten\soc_I.\e1_buf_I.$reduce_or$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:195$5296: { \soc_I.cpu_I.do_waitirq \soc_I.e1_buf_I.tx_pending [0] \soc_I.e1_buf_I.rx_pending [0] } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13547: { \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu \soc_I.cpu_I.is_slli_srli_srai $auto$opt_reduce.cc:134:opt_mux$23577 } Consolidated identical input bits for $mux cell $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$procmux$5754: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 New ports: A=1'0, B=1'1, Y=$flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] New connections: $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [7:1] = { $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13729: \soc_I.cpu_I.is_sb_sh_sw New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13741: \soc_I.cpu_I.is_sb_sh_sw New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13745: { \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu $auto$opt_reduce.cc:134:opt_mux$23579 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13907: { $auto$opt_reduce.cc:134:opt_mux$23583 $auto$opt_reduce.cc:134:opt_mux$23581 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$14055: $auto$opt_reduce.cc:134:opt_mux$23585 New ctrl vector for $pmux cell $flatten\i2c_I.\core_I.$procmux$15388: { $auto$opt_reduce.cc:134:opt_mux$23589 $auto$opt_reduce.cc:134:opt_mux$23587 } Consolidated identical input bits for $mux cell $flatten\soc_I.\bram_I.$procmux$15275: Old ports: A=0, B=65280, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3508_EN[31:0]$3517 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3508_EN[31:0]$3517 [8] New connections: { $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3508_EN[31:0]$3517 [31:9] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3508_EN[31:0]$3517 [7:0] } = { 16'0000000000000000 $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3508_EN[31:0]$3517 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3508_EN[31:0]$3517 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3508_EN[31:0]$3517 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3508_EN[31:0]$3517 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3508_EN[31:0]$3517 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3508_EN[31:0]$3517 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3508_EN[31:0]$3517 [8] 8'00000000 } Consolidated identical input bits for $mux cell $flatten\soc_I.\bram_I.$procmux$15281: Old ports: A=0, B=16711680, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3509_EN[31:0]$3520 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3509_EN[31:0]$3520 [16] New connections: { $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3509_EN[31:0]$3520 [31:17] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3509_EN[31:0]$3520 [15:0] } = { 8'00000000 $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3509_EN[31:0]$3520 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3509_EN[31:0]$3520 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3509_EN[31:0]$3520 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3509_EN[31:0]$3520 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3509_EN[31:0]$3520 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3509_EN[31:0]$3520 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3509_EN[31:0]$3520 [16] 16'0000000000000000 } New ctrl vector for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$procmux$15677: { } Consolidated identical input bits for $mux cell $flatten\soc_I.\bram_I.$procmux$15287: Old ports: A=0, B=32'11111111000000000000000000000000, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3510_EN[31:0]$3523 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3510_EN[31:0]$3523 [24] New connections: { $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3510_EN[31:0]$3523 [31:25] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3510_EN[31:0]$3523 [23:0] } = { $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3510_EN[31:0]$3523 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3510_EN[31:0]$3523 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3510_EN[31:0]$3523 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3510_EN[31:0]$3523 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3510_EN[31:0]$3523 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3510_EN[31:0]$3523 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3510_EN[31:0]$3523 [24] 24'000000000000000000000000 } Consolidated identical input bits for $mux cell $flatten\soc_I.\bram_I.$procmux$15269: Old ports: A=0, B=255, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3507_EN[31:0]$3514 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3507_EN[31:0]$3514 [0] New connections: $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3507_EN[31:0]$3514 [31:1] = { 24'000000000000000000000000 $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3507_EN[31:0]$3514 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3507_EN[31:0]$3514 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3507_EN[31:0]$3514 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3507_EN[31:0]$3514 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3507_EN[31:0]$3514 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3507_EN[31:0]$3514 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3507_EN[31:0]$3514 [0] } New ctrl vector for $mux cell $flatten\soc_I.\cpu_I.$procmux$12630: { } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12649: { } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12667: $auto$opt_reduce.cc:134:opt_mux$23591 New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12948: { $flatten\soc_I.\cpu_I.$procmux$12662_CMP $auto$opt_reduce.cc:134:opt_mux$23593 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12961: { $auto$opt_reduce.cc:134:opt_mux$23595 $flatten\soc_I.\cpu_I.$procmux$12640_CMP } Consolidated identical input bits for $mux cell $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$procmux$5754: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 New ports: A=1'0, B=1'1, Y=$flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] New connections: $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [7:1] = { $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12974: { $flatten\soc_I.\cpu_I.$procmux$12671_CMP $auto$opt_reduce.cc:134:opt_mux$23597 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13118: { } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13122: $flatten\soc_I.\cpu_I.$procmux$12651_CMP New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13128: { } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13132: { } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13161: $auto$opt_reduce.cc:134:opt_mux$23599 New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13170: $auto$opt_reduce.cc:134:opt_mux$23601 New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13174: { $auto$opt_reduce.cc:134:opt_mux$23605 $auto$opt_reduce.cc:134:opt_mux$23603 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13200: { $flatten\soc_I.\cpu_I.$procmux$12671_CMP $flatten\soc_I.\cpu_I.$procmux$12670_CMP $flatten\soc_I.\cpu_I.$procmux$12640_CMP } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13259: { \soc_I.cpu_I.is_slli_srli_srai $auto$opt_reduce.cc:134:opt_mux$23607 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13301: { $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4073_Y $flatten\soc_I.\cpu_I.$procmux$12671_CMP } Consolidated identical input bits for $mux cell $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$procmux$5754: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] New connections: $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [7:1] = { $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] } Consolidated identical input bits for $mux cell $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$procmux$5754: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] New connections: $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [7:1] = { $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN[7:0]$5465 [0] } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.$procmux$15323: { $flatten\gps_uart_I.$eq$/build/gateware/cores/no2misc//rtl/uart_wb.v:171$3285_Y $flatten\soc_I.\iobuf_I.\dma_I.$eq$/build/gateware/common/rtl/wb_dma.v:164$5047_Y } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.\phy_I.$procmux$5720: { $auto$opt_reduce.cc:134:opt_mux$23615 $auto$opt_reduce.cc:134:opt_mux$23613 $flatten\soc_I.\usb_I.\phy_I.$procmux$5729_CMP $flatten\soc_I.\usb_I.\phy_I.$procmux$5728_CMP $auto$opt_reduce.cc:134:opt_mux$23611 $auto$opt_reduce.cc:134:opt_mux$23609 } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.\phy_I.$procmux$5737: { $auto$opt_reduce.cc:134:opt_mux$23623 $auto$opt_reduce.cc:134:opt_mux$23621 $flatten\soc_I.\usb_I.\phy_I.$procmux$5746_CMP $flatten\soc_I.\usb_I.\phy_I.$procmux$5745_CMP $auto$opt_reduce.cc:134:opt_mux$23619 $auto$opt_reduce.cc:134:opt_mux$23617 } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12189: { $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12197_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12196_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12195_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12194_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12193_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12192_CMP $auto$opt_reduce.cc:134:opt_mux$23625 } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12221: { $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12225_CMP $auto$opt_reduce.cc:134:opt_mux$23627 $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12222_CMP } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12232: { $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12239_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12238_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12237_CMP $auto$opt_reduce.cc:134:opt_mux$23629 $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12235_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12234_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12233_CMP } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13398: { $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4073_Y $flatten\soc_I.\cpu_I.$procmux$12671_CMP } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13441: { $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4073_Y $flatten\soc_I.\cpu_I.$procmux$12671_CMP $auto$opt_reduce.cc:134:opt_mux$23631 } New ctrl vector for $pmux cell $flatten\spi_mux_I.$procmux$15490: $auto$opt_reduce.cc:134:opt_mux$23633 New ctrl vector for $pmux cell $flatten\spi_mux_I.$procmux$15494: $auto$opt_reduce.cc:134:opt_mux$23635 New ctrl vector for $pmux cell $flatten\spi_mux_I.$procmux$15500: $auto$opt_reduce.cc:134:opt_mux$23637 New ctrl vector for $mux cell $flatten\soc_I.\cpu_I.$procmux$13122: { } New ctrl vector for $mux cell $flatten\soc_I.\cpu_I.$procmux$13146: { } Optimizing cells in module \top. Performed a total of 46 changes. 75.10.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~54 debug messages> Removed a total of 18 cells. 75.10.6. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$23184 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\cpu_I.$procdff$23307 ($dff) from module top. Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22708 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22641 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22574 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22507 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22440 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22229 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22018 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21807 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21596 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21385 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21174 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20963 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20752 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20541 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20330 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20119 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19908 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19697 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19486 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19275 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19064 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18853 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18642 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18431 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18220 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18009 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17798 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17587 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17376 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17165 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16954 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16743 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16532 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16321 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16158 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16043 ($dlatch) from module top (changing to combinatorial circuit). Setting constant 0-bit at position 0 on $flatten\soc_I.\cpu_I.$procdff$23268 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\cpu_I.$procdff$23268 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\cpu_I.$procdff$23267 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\cpu_I.$procdff$23267 ($dff) from module top. Setting constant 1-bit at position 0 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 1 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 2 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 3 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 4 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 5 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 6 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 7 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 8 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 9 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 10 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 11 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 12 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 13 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 14 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 15 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 16 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 17 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 18 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 19 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 20 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 21 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 22 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 23 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 24 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 25 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 26 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 27 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 28 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 29 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 30 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 31 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 32 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 33 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 34 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 35 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 36 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 37 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 38 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 39 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 40 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 41 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 42 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 43 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 44 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 45 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 46 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 47 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 48 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 49 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 50 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 51 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 52 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 53 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 54 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 55 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 56 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 57 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 58 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 59 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 60 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 61 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 62 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Setting constant 1-bit at position 63 on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top. Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22775 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22708 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22641 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22574 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22507 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22440 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22229 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22018 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21807 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21596 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21385 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21174 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20963 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20752 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20541 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20330 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20119 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19908 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19697 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19486 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19275 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19064 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18853 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18642 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18431 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18220 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18009 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17798 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17587 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17376 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17165 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16954 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16743 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16532 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16321 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16158 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16043 ($dlatch) from module top (changing to combinatorial circuit). Setting constant 0-bit at position 0 on $flatten\soc_I.\e1_buf_I.$procdff$23216 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\e1_buf_I.$procdff$23216 ($dff) from module top. Setting constant 0-bit at position 2 on $flatten\soc_I.\e1_buf_I.$procdff$23216 ($dff) from module top. Setting constant 0-bit at position 3 on $flatten\soc_I.\e1_buf_I.$procdff$23216 ($dff) from module top. Setting constant 0-bit at position 4 on $flatten\soc_I.\e1_buf_I.$procdff$23216 ($dff) from module top. Setting constant 0-bit at position 5 on $flatten\soc_I.\e1_buf_I.$procdff$23216 ($dff) from module top. Setting constant 0-bit at position 6 on $flatten\soc_I.\e1_buf_I.$procdff$23216 ($dff) from module top. Setting constant 0-bit at position 7 on $flatten\soc_I.\e1_buf_I.$procdff$23216 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\e1_buf_I.$procdff$23210 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\e1_buf_I.$procdff$23210 ($dff) from module top. Setting constant 0-bit at position 2 on $flatten\soc_I.\e1_buf_I.$procdff$23210 ($dff) from module top. Setting constant 0-bit at position 3 on $flatten\soc_I.\e1_buf_I.$procdff$23210 ($dff) from module top. Setting constant 0-bit at position 4 on $flatten\soc_I.\e1_buf_I.$procdff$23210 ($dff) from module top. Setting constant 0-bit at position 5 on $flatten\soc_I.\e1_buf_I.$procdff$23210 ($dff) from module top. Setting constant 0-bit at position 6 on $flatten\soc_I.\e1_buf_I.$procdff$23210 ($dff) from module top. Setting constant 0-bit at position 7 on $flatten\soc_I.\e1_buf_I.$procdff$23210 ($dff) from module top. Setting constant 0-bit at position 8 on $flatten\soc_I.\e1_buf_I.$procdff$23210 ($dff) from module top. Setting constant 0-bit at position 9 on $flatten\soc_I.\e1_buf_I.$procdff$23210 ($dff) from module top. Setting constant 0-bit at position 10 on $flatten\soc_I.\e1_buf_I.$procdff$23210 ($dff) from module top. Setting constant 0-bit at position 11 on $flatten\soc_I.\e1_buf_I.$procdff$23210 ($dff) from module top. Setting constant 0-bit at position 12 on $flatten\soc_I.\e1_buf_I.$procdff$23210 ($dff) from module top. Setting constant 0-bit at position 13 on $flatten\soc_I.\e1_buf_I.$procdff$23210 ($dff) from module top. Setting constant 0-bit at position 14 on $flatten\soc_I.\e1_buf_I.$procdff$23210 ($dff) from module top. Setting constant 0-bit at position 15 on $flatten\soc_I.\e1_buf_I.$procdff$23210 ($dff) from module top. 75.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 31 unused cells and 684 unused wires. <suppressed ~59 debug messages> 75.10.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~7 debug messages> 75.10.9. Rerunning OPT passes. (Maybe there is more to do..) 75.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~545 debug messages> 75.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $flatten\soc_I.\e1_buf_I.$reduce_or$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:195$5296: { \soc_I.e1_buf_I.tx_pending [0] \soc_I.e1_buf_I.rx_pending [0] } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13071: $auto$opt_reduce.cc:134:opt_mux$23639 New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13088: { $flatten\soc_I.\cpu_I.$procmux$12671_CMP $auto$opt_reduce.cc:134:opt_mux$23641 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13155: { $flatten\soc_I.\cpu_I.$procmux$12651_CMP $flatten\soc_I.\cpu_I.$procmux$12650_CMP } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13506: { $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4073_Y $flatten\soc_I.\cpu_I.$procmux$12651_CMP $flatten\soc_I.\cpu_I.$procmux$12650_CMP $flatten\soc_I.\cpu_I.$procmux$12671_CMP $flatten\soc_I.\cpu_I.$procmux$12670_CMP $auto$opt_reduce.cc:134:opt_mux$23643 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$14969: { $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:364$3670_Y $auto$opt_reduce.cc:134:opt_mux$23645 } Optimizing cells in module \top. Performed a total of 6 changes. 75.10.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 75.10.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$23177 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$23433 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$23433 ($dff) from module top. Setting constant 0-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$23433 ($dff) from module top. Setting constant 0-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$23433 ($dff) from module top. Setting constant 0-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$23433 ($dff) from module top. Setting constant 0-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$23433 ($dff) from module top. Setting constant 0-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$23433 ($dff) from module top. Setting constant 0-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$23433 ($dff) from module top. Setting constant 0-bit at position 8 on $flatten\soc_I.\bram_I.$procdff$23433 ($dff) from module top. Setting constant 0-bit at position 9 on $flatten\soc_I.\bram_I.$procdff$23433 ($dff) from module top. Setting constant 0-bit at position 10 on $flatten\soc_I.\bram_I.$procdff$23433 ($dff) from module top. Setting constant 0-bit at position 11 on $flatten\soc_I.\bram_I.$procdff$23433 ($dff) from module top. Setting constant 0-bit at position 12 on $flatten\soc_I.\bram_I.$procdff$23433 ($dff) from module top. Setting constant 0-bit at position 13 on $flatten\soc_I.\bram_I.$procdff$23433 ($dff) from module top. Setting constant 0-bit at position 14 on $flatten\soc_I.\bram_I.$procdff$23433 ($dff) from module top. Setting constant 0-bit at position 15 on $flatten\soc_I.\bram_I.$procdff$23433 ($dff) from module top. Setting constant 0-bit at position 16 on $flatten\soc_I.\bram_I.$procdff$23433 ($dff) from module top. Setting constant 0-bit at position 17 on $flatten\soc_I.\bram_I.$procdff$23433 ($dff) from module top. Setting constant 0-bit at position 18 on $flatten\soc_I.\bram_I.$procdff$23433 ($dff) from module top. Setting constant 0-bit at position 19 on $flatten\soc_I.\bram_I.$procdff$23433 ($dff) from module top. Setting constant 0-bit at position 20 on $flatten\soc_I.\bram_I.$procdff$23433 ($dff) from module top. Setting constant 0-bit at position 21 on $flatten\soc_I.\bram_I.$procdff$23433 ($dff) from module top. Setting constant 0-bit at position 22 on $flatten\soc_I.\bram_I.$procdff$23433 ($dff) from module top. Setting constant 0-bit at position 23 on $flatten\soc_I.\bram_I.$procdff$23433 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$23430 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$23430 ($dff) from module top. Setting constant 0-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$23430 ($dff) from module top. Setting constant 0-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$23430 ($dff) from module top. Setting constant 0-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$23430 ($dff) from module top. Setting constant 0-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$23430 ($dff) from module top. Setting constant 0-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$23430 ($dff) from module top. Setting constant 0-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$23430 ($dff) from module top. Setting constant 0-bit at position 8 on $flatten\soc_I.\bram_I.$procdff$23430 ($dff) from module top. Setting constant 0-bit at position 9 on $flatten\soc_I.\bram_I.$procdff$23430 ($dff) from module top. Setting constant 0-bit at position 10 on $flatten\soc_I.\bram_I.$procdff$23430 ($dff) from module top. Setting constant 0-bit at position 11 on $flatten\soc_I.\bram_I.$procdff$23430 ($dff) from module top. Setting constant 0-bit at position 12 on $flatten\soc_I.\bram_I.$procdff$23430 ($dff) from module top. Setting constant 0-bit at position 13 on $flatten\soc_I.\bram_I.$procdff$23430 ($dff) from module top. Setting constant 0-bit at position 14 on $flatten\soc_I.\bram_I.$procdff$23430 ($dff) from module top. Setting constant 0-bit at position 15 on $flatten\soc_I.\bram_I.$procdff$23430 ($dff) from module top. Setting constant 0-bit at position 24 on $flatten\soc_I.\bram_I.$procdff$23430 ($dff) from module top. Setting constant 0-bit at position 25 on $flatten\soc_I.\bram_I.$procdff$23430 ($dff) from module top. Setting constant 0-bit at position 26 on $flatten\soc_I.\bram_I.$procdff$23430 ($dff) from module top. Setting constant 0-bit at position 27 on $flatten\soc_I.\bram_I.$procdff$23430 ($dff) from module top. Setting constant 0-bit at position 28 on $flatten\soc_I.\bram_I.$procdff$23430 ($dff) from module top. Setting constant 0-bit at position 29 on $flatten\soc_I.\bram_I.$procdff$23430 ($dff) from module top. Setting constant 0-bit at position 30 on $flatten\soc_I.\bram_I.$procdff$23430 ($dff) from module top. Setting constant 0-bit at position 31 on $flatten\soc_I.\bram_I.$procdff$23430 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$23427 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$23427 ($dff) from module top. Setting constant 0-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$23427 ($dff) from module top. Setting constant 0-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$23427 ($dff) from module top. Setting constant 0-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$23427 ($dff) from module top. Setting constant 0-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$23427 ($dff) from module top. Setting constant 0-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$23427 ($dff) from module top. Setting constant 0-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$23427 ($dff) from module top. Setting constant 0-bit at position 16 on $flatten\soc_I.\bram_I.$procdff$23427 ($dff) from module top. Setting constant 0-bit at position 17 on $flatten\soc_I.\bram_I.$procdff$23427 ($dff) from module top. Setting constant 0-bit at position 18 on $flatten\soc_I.\bram_I.$procdff$23427 ($dff) from module top. Setting constant 0-bit at position 19 on $flatten\soc_I.\bram_I.$procdff$23427 ($dff) from module top. Setting constant 0-bit at position 20 on $flatten\soc_I.\bram_I.$procdff$23427 ($dff) from module top. Setting constant 0-bit at position 21 on $flatten\soc_I.\bram_I.$procdff$23427 ($dff) from module top. Setting constant 0-bit at position 22 on $flatten\soc_I.\bram_I.$procdff$23427 ($dff) from module top. Setting constant 0-bit at position 23 on $flatten\soc_I.\bram_I.$procdff$23427 ($dff) from module top. Setting constant 0-bit at position 24 on $flatten\soc_I.\bram_I.$procdff$23427 ($dff) from module top. Setting constant 0-bit at position 25 on $flatten\soc_I.\bram_I.$procdff$23427 ($dff) from module top. Setting constant 0-bit at position 26 on $flatten\soc_I.\bram_I.$procdff$23427 ($dff) from module top. Setting constant 0-bit at position 27 on $flatten\soc_I.\bram_I.$procdff$23427 ($dff) from module top. Setting constant 0-bit at position 28 on $flatten\soc_I.\bram_I.$procdff$23427 ($dff) from module top. Setting constant 0-bit at position 29 on $flatten\soc_I.\bram_I.$procdff$23427 ($dff) from module top. Setting constant 0-bit at position 30 on $flatten\soc_I.\bram_I.$procdff$23427 ($dff) from module top. Setting constant 0-bit at position 31 on $flatten\soc_I.\bram_I.$procdff$23427 ($dff) from module top. Setting constant 0-bit at position 8 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 0-bit at position 9 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 0-bit at position 10 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 0-bit at position 11 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 0-bit at position 12 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 0-bit at position 13 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 0-bit at position 14 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 0-bit at position 15 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 0-bit at position 16 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 0-bit at position 17 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 0-bit at position 18 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 0-bit at position 19 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 0-bit at position 20 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 0-bit at position 21 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 0-bit at position 22 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 0-bit at position 23 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 0-bit at position 24 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 0-bit at position 25 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 0-bit at position 26 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 0-bit at position 27 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 0-bit at position 28 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 0-bit at position 29 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 0-bit at position 30 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 0-bit at position 31 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. 75.10.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 9 unused wires. <suppressed ~1 debug messages> 75.10.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~1 debug messages> 75.10.16. Rerunning OPT passes. (Maybe there is more to do..) 75.10.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~545 debug messages> 75.10.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 75.10.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.10.20. Executing OPT_DFF pass (perform DFF optimizations). 75.10.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 1 unused wires. <suppressed ~1 debug messages> 75.10.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.10.23. Rerunning OPT passes. (Maybe there is more to do..) 75.10.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~545 debug messages> 75.10.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 75.10.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.10.27. Executing OPT_DFF pass (perform DFF optimizations). 75.10.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.10.29. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.10.30. Finished OPT passes. (There is nothing left to do.) 75.11. Executing FSM pass (extract and optimize FSM). 75.11.1. Executing FSM_DETECT pass (finding FSMs in design). Not marking top.$flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.$flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.fsm_state. Not marking top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5461_EN as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register top.i2c_I.core_I.state. Found FSM state register top.soc_I.cpu_I.cpu_state. Not marking top.soc_I.cpu_I.mem_state as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register top.soc_I.cpu_I.mem_wordsize. Not marking top.soc_I.e1_buf_I.t_chan as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.iobuf_I.dma_I.state as FSM state register: Users of register don't seem to benefit from recoding. Circuit seems to be self-resetting. Not marking top.soc_I.iobuf_I.epbam_arb_I.sel as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.iobuf_I.spram_arb_I.sel as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.phy_I.dn_state as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.phy_I.dp_state as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.rx_ll_I.dec_eop_state_1 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.rx_ll_I.dec_rep_state_1 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.rx_ll_I.dec_sync_state_1 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.rx_ll_I.samp_cnt as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register top.soc_I.usb_I.rx_pkt_I.state. Not marking top.soc_I.usb_I.trans_I.epfw_state as FSM state register: Users of register don't seem to benefit from recoding. Circuit seems to be self-resetting. Not marking top.soc_I.usb_I.tx_ll_I.out_sym as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.tx_ll_I.state as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register top.soc_I.usb_I.tx_pkt_I.state. Not marking top.spi_mux_I.state as FSM state register: Users of register don't seem to benefit from recoding. 75.11.2. Executing FSM_EXTRACT pass (extracting FSM from design). Extracting FSM `$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.fsm_state' from module `\top'. found $dff cell for state register: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23570 root of input selection tree: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] found reset state: 3'000 (guessed from mux tree) found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$or$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:143$23_Y found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.crc_I.in_valid found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procmux$15936_CMP found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$48_Y found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$47_Y found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.align_frame found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:166$25_Y found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.mfa_timeout [6] found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:191$31_Y found state code: 3'100 found state code: 3'000 found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf found state code: 3'011 found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.fas_pos found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.data [6] found state code: 3'001 found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.data_match_fas found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.ctrl_mode_mf found state code: 3'010 found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procmux$15936_CMP found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:389$140_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$72_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$71_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$48_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$47_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.align_frame ctrl inputs: { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.data [6] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.data_match_fas $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.fas_pos $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.mfa_timeout [6] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$or$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:143$23_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:166$25_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:191$31_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.crc_I.in_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.ctrl_mode_mf } ctrl outputs: { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.align_frame $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$47_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$48_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$71_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$72_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:389$140_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procmux$15936_CMP } transition: 3'000 10'-----0--0- -> 3'000 10'1000001100 transition: 3'000 10'-0---0--1- -> 3'000 10'1000001100 transition: 3'000 10'-1---0--1- -> 3'001 10'1001001100 transition: 3'000 10'-----1---- -> 3'000 10'1000001100 transition: 3'100 10'-----0--0- -> 3'100 10'0100001010 transition: 3'100 10'-----0--1- -> 3'100 10'0100001010 transition: 3'100 10'-----1---- -> 3'000 10'0000001010 transition: 3'010 10'-----0--0- -> 3'010 10'0010010100 transition: 3'010 10'-----00-1- -> 3'010 10'0010010100 transition: 3'010 10'---0001-1- -> 3'010 10'0010010100 transition: 3'010 10'---0101-1- -> 3'011 10'0011010100 transition: 3'010 10'---1-01-1- -> 3'000 10'0000010100 transition: 3'010 10'-----1---- -> 3'000 10'0000010100 transition: 3'001 10'-----0--0- -> 3'001 10'0001101100 transition: 3'001 10'-----00-1- -> 3'001 10'0001101100 transition: 3'001 10'0-0--01-1- -> 3'000 10'0000101100 transition: 3'001 10'1-0--01-1- -> 3'001 10'0001101100 transition: 3'001 10'-01--01-1- -> 3'000 10'0000101100 transition: 3'001 10'-11--01-10 -> 3'100 10'0100101100 transition: 3'001 10'-11--01-11 -> 3'010 10'0010101100 transition: 3'001 10'-----1---- -> 3'000 10'0000101100 transition: 3'011 10'-----0--0- -> 3'011 10'0011001101 transition: 3'011 10'-----00-1- -> 3'011 10'0011001101 transition: 3'011 10'---0-0101- -> 3'011 10'0011001101 transition: 3'011 10'---0-0111- -> 3'100 10'0100001101 transition: 3'011 10'---1-01-1- -> 3'000 10'0000001101 transition: 3'011 10'-----1---- -> 3'000 10'0000001101 Extracting FSM `\i2c_I.core_I.state' from module `\top'. found $dff cell for state register: $flatten\i2c_I.\core_I.$procdff$23469 root of input selection tree: $flatten\i2c_I.\core_I.$0\state[2:0] found reset state: 3'000 (guessed from mux tree) found ctrl input: \blinker_I.rst found ctrl input: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:142$5215_Y found ctrl input: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:160$5219_Y found ctrl input: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:210$5224_Y found ctrl input: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:219$5227_Y found ctrl input: \i2c_I.ready found ctrl input: \i2c_I.core_I.cyc_cnt [4] found ctrl input: \i2c_I.core_I.bit_cnt [3] found state code: 3'010 found state code: 3'000 found ctrl input: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:109$5206_Y found state code: 3'001 found state code: 3'100 found state code: 3'011 found ctrl input: \i2c_I.core_I.stb found ctrl output: \i2c_I.ready found ctrl output: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:142$5215_Y found ctrl output: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:160$5219_Y found ctrl output: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:210$5224_Y found ctrl output: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:219$5227_Y ctrl inputs: { \blinker_I.rst $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:109$5206_Y \i2c_I.core_I.bit_cnt [3] \i2c_I.core_I.cyc_cnt [4] \i2c_I.core_I.stb } ctrl outputs: { \i2c_I.ready $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:219$5227_Y $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:210$5224_Y $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:160$5219_Y $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:142$5215_Y $flatten\i2c_I.\core_I.$0\state[2:0] } transition: 3'000 5'0---0 -> 3'000 8'10000000 transition: 3'000 5'0---1 -> 3'010 8'10000010 transition: 3'000 5'1---- -> 3'000 8'10000000 transition: 3'100 5'0--0- -> 3'100 8'00010100 transition: 3'100 5'00-1- -> 3'001 8'00010001 transition: 3'100 5'01-1- -> 3'000 8'00010000 transition: 3'100 5'1---- -> 3'000 8'00010000 transition: 3'010 5'0--0- -> 3'010 8'01000010 transition: 3'010 5'0--1- -> 3'011 8'01000011 transition: 3'010 5'1---- -> 3'000 8'01000000 transition: 3'001 5'0--0- -> 3'001 8'00001001 transition: 3'001 5'0-01- -> 3'010 8'00001010 transition: 3'001 5'0-11- -> 3'000 8'00001000 transition: 3'001 5'1---- -> 3'000 8'00001000 transition: 3'011 5'0--0- -> 3'011 8'00100011 transition: 3'011 5'0--1- -> 3'100 8'00100100 transition: 3'011 5'1---- -> 3'000 8'00100000 Extracting FSM `\soc_I.cpu_I.cpu_state' from module `\top'. found $dff cell for state register: $flatten\soc_I.\cpu_I.$procdff$23290 root of input selection tree: $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] found reset state: 8'10000000 (guessed from mux tree) found ctrl input: $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1917$4261_Y found ctrl input: \soc_I.pb_rst_n found state code: 8'01000000 found ctrl input: $auto$opt_reduce.cc:134:opt_mux$23639 found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12670_CMP found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12671_CMP found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12650_CMP found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12651_CMP found ctrl input: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4073_Y found ctrl input: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4220_Y found ctrl input: $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1851$4224_Y found ctrl input: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1810$4202_Y found ctrl input: \soc_I.cpu_I.alu_wait found ctrl input: \soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu found ctrl input: \soc_I.cpu_I.mem_done found ctrl input: \soc_I.cpu_I.is_sll_srl_sra found ctrl input: \soc_I.cpu_I.is_sb_sh_sw found state code: 8'00001000 found state code: 8'00000100 found state code: 8'00000010 found ctrl input: $auto$opt_reduce.cc:134:opt_mux$23577 found ctrl input: \soc_I.cpu_I.is_slli_srli_srai found ctrl input: \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu found state code: 8'00000001 found ctrl input: \soc_I.cpu_I.decoder_trigger found ctrl input: \soc_I.cpu_I.instr_jal found state code: 8'00100000 found state code: 8'10000000 found ctrl output: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4073_Y found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12640_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12650_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12651_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12662_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12670_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12671_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12675_CMP ctrl inputs: { $auto$opt_reduce.cc:134:opt_mux$23577 $auto$opt_reduce.cc:134:opt_mux$23639 \soc_I.pb_rst_n $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1917$4261_Y $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1851$4224_Y $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4220_Y $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1810$4202_Y \soc_I.cpu_I.alu_wait \soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu \soc_I.cpu_I.is_sll_srl_sra \soc_I.cpu_I.is_sb_sh_sw \soc_I.cpu_I.is_slli_srli_srai \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu \soc_I.cpu_I.decoder_trigger \soc_I.cpu_I.instr_jal \soc_I.cpu_I.mem_done } ctrl outputs: { $flatten\soc_I.\cpu_I.$procmux$12675_CMP $flatten\soc_I.\cpu_I.$procmux$12671_CMP $flatten\soc_I.\cpu_I.$procmux$12670_CMP $flatten\soc_I.\cpu_I.$procmux$12662_CMP $flatten\soc_I.\cpu_I.$procmux$12651_CMP $flatten\soc_I.\cpu_I.$procmux$12650_CMP $flatten\soc_I.\cpu_I.$procmux$12640_CMP $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4073_Y } transition: 8'10000000 16'--00------------ -> 8'01000000 16'1000000010000000 transition: 8'10000000 16'--10------------ -> 8'10000000 16'1000000100000000 transition: 8'10000000 16'---1------------ -> 8'10000000 16'1000000100000000 transition: 8'01000000 16'--00------------ -> 8'01000000 16'0000000010000001 transition: 8'01000000 16'--10---------0-- -> 8'01000000 16'0000000010000001 transition: 8'01000000 16'--10---------10- -> 8'00100000 16'0000000001000001 transition: 8'01000000 16'--10---------11- -> 8'01000000 16'0000000010000001 transition: 8'01000000 16'---1------------ -> 8'10000000 16'0000000100000001 transition: 8'00100000 16'--00------------ -> 8'01000000 16'0000100010000000 transition: 8'00100000 16'0-10-----0000--- -> 8'00001000 16'0000100000010000 transition: 8'00100000 16'0-10------100--- -> 8'00000010 16'0000100000000100 transition: 8'00100000 16'0-10-----1-00--- -> 8'00000100 16'0000100000001000 transition: 8'00100000 16'--10--------1--- -> 8'00000001 16'0000100000000010 transition: 8'00100000 16'--10-------1---- -> 8'00000100 16'0000100000001000 transition: 8'00100000 16'1-10------------ -> 8'00001000 16'0000100000010000 transition: 8'00100000 16'---1------------ -> 8'10000000 16'0000100100000000 transition: 8'00001000 16'--00------------ -> 8'01000000 16'0100000010000000 transition: 8'00001000 16'--10---00------- -> 8'01000000 16'0100000010000000 transition: 8'00001000 16'--10---01------0 -> 8'00001000 16'0100000000010000 transition: 8'00001000 16'--10---01------1 -> 8'01000000 16'0100000010000000 transition: 8'00001000 16'--10---1-------- -> 8'00001000 16'0100000000010000 transition: 8'00001000 16'---1------------ -> 8'10000000 16'0100000100000000 transition: 8'00000100 16'--00------------ -> 8'01000000 16'0010000010000000 transition: 8'00000100 16'--10--0--------- -> 8'00000100 16'0010000000001000 transition: 8'00000100 16'--10--1--------- -> 8'01000000 16'0010000010000000 transition: 8'00000100 16'---1------------ -> 8'10000000 16'0010000100000000 transition: 8'00000010 16'--00------------ -> 8'01000000 16'0001000010000000 transition: 8'00000010 16'--10-0---------- -> 8'00000010 16'0001000000000100 transition: 8'00000010 16'--1001---------- -> 8'00000010 16'0001000000000100 transition: 8'00000010 16'--1011---------- -> 8'01000000 16'0001000010000000 transition: 8'00000010 16'---1------------ -> 8'10000000 16'0001000100000000 transition: 8'00000001 16'--00------------ -> 8'01000000 16'0000001010000000 transition: 8'00000001 16'--10-0---------- -> 8'00000001 16'0000001000000010 transition: 8'00000001 16'--1001---------- -> 8'00000001 16'0000001000000010 transition: 8'00000001 16'--1011---------- -> 8'01000000 16'0000001010000000 transition: 8'00000001 16'---1------------ -> 8'10000000 16'0000001100000000 Extracting FSM `\soc_I.cpu_I.mem_wordsize' from module `\top'. found $dff cell for state register: $flatten\soc_I.\cpu_I.$procdff$23277 root of input selection tree: $flatten\soc_I.\cpu_I.$0\mem_wordsize[1:0] found ctrl input: \soc_I.pb_rst_n found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12640_CMP found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12662_CMP found ctrl input: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4073_Y found ctrl input: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4220_Y found ctrl input: \soc_I.cpu_I.mem_do_rdata found ctrl input: \soc_I.cpu_I.instr_lw found ctrl input: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1866$4229_Y found ctrl input: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1865$4228_Y found state code: 2'00 found state code: 2'01 found state code: 2'10 found ctrl input: \soc_I.cpu_I.mem_do_wdata found ctrl input: \soc_I.cpu_I.instr_sw found ctrl input: \soc_I.cpu_I.instr_sh found ctrl input: \soc_I.cpu_I.instr_sb found ctrl output: $flatten\soc_I.\cpu_I.$procmux$15216_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$15223_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$15228_CMP ctrl inputs: { \soc_I.pb_rst_n $flatten\soc_I.\cpu_I.$procmux$12662_CMP $flatten\soc_I.\cpu_I.$procmux$12640_CMP $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1866$4229_Y $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1865$4228_Y $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4220_Y $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4073_Y \soc_I.cpu_I.instr_sw \soc_I.cpu_I.instr_sh \soc_I.cpu_I.instr_sb \soc_I.cpu_I.instr_lw \soc_I.cpu_I.mem_do_wdata \soc_I.cpu_I.mem_do_rdata } ctrl outputs: { $flatten\soc_I.\cpu_I.$procmux$15228_CMP $flatten\soc_I.\cpu_I.$procmux$15223_CMP $flatten\soc_I.\cpu_I.$procmux$15216_CMP $flatten\soc_I.\cpu_I.$0\mem_wordsize[1:0] } transition: 2'00 13'0------------ -> 2'00 5'10000 transition: 2'00 13'100---0------ -> 2'00 5'10000 transition: 2'00 13'1-----1------ -> 2'00 5'10000 transition: 2'00 13'11---0------- -> 2'00 5'10000 transition: 2'00 13'11---1-000-0- -> INVALID_STATE(2'xx) 5'100xx <ignored invalid transition!> transition: 2'00 13'11---1---1-0- -> 2'10 5'10010 transition: 2'00 13'11---1--1--0- -> 2'01 5'10001 transition: 2'00 13'11---1-1---0- -> 2'00 5'10000 transition: 2'00 13'11---1-----1- -> 2'00 5'10000 transition: 2'00 13'1-1--0------- -> 2'00 5'10000 transition: 2'00 13'1-1001----0-0 -> INVALID_STATE(2'xx) 5'100xx <ignored invalid transition!> transition: 2'00 13'1-1-11------0 -> 2'10 5'10010 transition: 2'00 13'1-11-1------0 -> 2'01 5'10001 transition: 2'00 13'1-1--1----1-0 -> 2'00 5'10000 transition: 2'00 13'1-1--1------1 -> 2'00 5'10000 transition: 2'10 13'0------------ -> 2'10 5'00110 transition: 2'10 13'100---0------ -> 2'10 5'00110 transition: 2'10 13'1-----1------ -> 2'00 5'00100 transition: 2'10 13'11---0------- -> 2'10 5'00110 transition: 2'10 13'11---1-000-0- -> INVALID_STATE(2'xx) 5'001xx <ignored invalid transition!> transition: 2'10 13'11---1---1-0- -> 2'10 5'00110 transition: 2'10 13'11---1--1--0- -> 2'01 5'00101 transition: 2'10 13'11---1-1---0- -> 2'00 5'00100 transition: 2'10 13'11---1-----1- -> 2'10 5'00110 transition: 2'10 13'1-1--0------- -> 2'10 5'00110 transition: 2'10 13'1-1001----0-0 -> INVALID_STATE(2'xx) 5'001xx <ignored invalid transition!> transition: 2'10 13'1-1-11------0 -> 2'10 5'00110 transition: 2'10 13'1-11-1------0 -> 2'01 5'00101 transition: 2'10 13'1-1--1----1-0 -> 2'00 5'00100 transition: 2'10 13'1-1--1------1 -> 2'10 5'00110 transition: 2'01 13'0------------ -> 2'01 5'01001 transition: 2'01 13'100---0------ -> 2'01 5'01001 transition: 2'01 13'1-----1------ -> 2'00 5'01000 transition: 2'01 13'11---0------- -> 2'01 5'01001 transition: 2'01 13'11---1-000-0- -> INVALID_STATE(2'xx) 5'010xx <ignored invalid transition!> transition: 2'01 13'11---1---1-0- -> 2'10 5'01010 transition: 2'01 13'11---1--1--0- -> 2'01 5'01001 transition: 2'01 13'11---1-1---0- -> 2'00 5'01000 transition: 2'01 13'11---1-----1- -> 2'01 5'01001 transition: 2'01 13'1-1--0------- -> 2'01 5'01001 transition: 2'01 13'1-1001----0-0 -> INVALID_STATE(2'xx) 5'010xx <ignored invalid transition!> transition: 2'01 13'1-1-11------0 -> 2'10 5'01010 transition: 2'01 13'1-11-1------0 -> 2'01 5'01001 transition: 2'01 13'1-1--1----1-0 -> 2'00 5'01000 transition: 2'01 13'1-1--1------1 -> 2'01 5'01001 Extracting FSM `\soc_I.usb_I.rx_pkt_I.state' from module `\top'. found $adff cell for state register: $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23155 root of input selection tree: \soc_I.usb_I.rx_pkt_I.state_nxt found reset state: 4'0000 (from async reset) found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:375$1407_Y found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12009_CMP found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:341$1393_Y found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:337$1390_Y found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_error[0:0] found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12089_CMP found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:245$1344_Y found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_idle[0:0] found ctrl input: \soc_I.usb_I.rx_ll_I.dec_valid_1 found ctrl input: \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [2] found ctrl input: \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [3] found state code: 4'0011 found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:180$1325_Y found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:158$1319_Y found ctrl input: \soc_I.usb_I.rx_pkt_I.llu_byte_stb found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:173$1323_Y found state code: 4'0110 found state code: 4'0101 found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:153$1318_Y found ctrl input: \soc_I.usb_I.rx_pkt_I.pid_valid found ctrl input: \soc_I.usb_I.rx_pkt_I.pid_is_sof found ctrl input: \soc_I.usb_I.rx_pkt_I.pid_is_token found ctrl input: \soc_I.usb_I.rx_pkt_I.pid_is_data found ctrl input: \soc_I.usb_I.rx_pkt_I.pid_is_handshake found state code: 4'0111 found state code: 4'0100 found state code: 4'0010 found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:126$1314_Y found state code: 4'0001 found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12089_CMP found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12009_CMP found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:375$1407_Y found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:341$1393_Y found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:337$1390_Y found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:245$1344_Y found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_error[0:0] found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_idle[0:0] ctrl inputs: { \soc_I.usb_I.rx_pkt_I.llu_byte_stb \soc_I.usb_I.rx_pkt_I.pid_valid \soc_I.usb_I.rx_pkt_I.pid_is_sof \soc_I.usb_I.rx_pkt_I.pid_is_token \soc_I.usb_I.rx_pkt_I.pid_is_data \soc_I.usb_I.rx_pkt_I.pid_is_handshake $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:126$1314_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:153$1318_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:158$1319_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:173$1323_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:180$1325_Y \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [2] \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [3] \soc_I.usb_I.rx_ll_I.dec_valid_1 } ctrl outputs: { \soc_I.usb_I.rx_pkt_I.state_nxt $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_idle[0:0] $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_error[0:0] $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:245$1344_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:337$1390_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:341$1393_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:375$1407_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12009_CMP $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12089_CMP } transition: 4'0000 14'------0------- -> 4'0000 12'000010000000 transition: 4'0000 14'------1------- -> 4'0001 12'000110000000 transition: 4'0100 14'0-------0----- -> 4'0100 12'010000010000 transition: 4'0100 14'1-------0----- -> 4'0101 12'010100010000 transition: 4'0100 14'--------1----- -> 4'0011 12'001100010000 transition: 4'0010 14'-0------------ -> 4'0011 12'001100000001 transition: 4'0010 14'-10000-------- -> 4'0011 12'001100000001 transition: 4'0010 14'-10001-------- -> 4'0110 12'011000000001 transition: 4'0010 14'-1001--------- -> 4'0111 12'011100000001 transition: 4'0010 14'-101---------- -> 4'0100 12'010000000001 transition: 4'0010 14'-11----------- -> 4'0100 12'010000000001 transition: 4'0110 14'0-------0----- -> 4'0110 12'011000000010 transition: 4'0110 14'1-------0----- -> 4'0011 12'001100000010 transition: 4'0110 14'--------10---- -> 4'0011 12'001100000010 transition: 4'0110 14'--------11---- -> 4'0000 12'000000000010 transition: 4'0001 14'0------------- -> 4'0001 12'000100100000 transition: 4'0001 14'1------------- -> 4'0010 12'001000100000 transition: 4'0101 14'0-------0----- -> 4'0101 12'010100001000 transition: 4'0101 14'1-------0----- -> 4'0110 12'011000001000 transition: 4'0101 14'--------1----- -> 4'0011 12'001100001000 transition: 4'0011 14'-------0------ -> 4'0011 12'001101000000 transition: 4'0011 14'-------1------ -> 4'0000 12'000001000000 transition: 4'0111 14'-------------0 -> 4'0111 12'011100000100 transition: 4'0111 14'-----------001 -> 4'0111 12'011100000100 transition: 4'0111 14'-----------011 -> 4'0011 12'001100000100 transition: 4'0111 14'----------01-1 -> 4'0011 12'001100000100 transition: 4'0111 14'----------11-1 -> 4'0000 12'000000000100 Extracting FSM `\soc_I.usb_I.tx_pkt_I.state' from module `\top'. found $adff cell for state register: $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$23098 root of input selection tree: \soc_I.usb_I.tx_pkt_I.state_nxt found reset state: 4'0000 (from async reset) found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1558_Y found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11760_CMP found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:177$1557_Y found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1559_Y found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$0\ll_start[0:0] found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:203$1575_Y found ctrl input: \soc_I.usb_I.tx_pkt_I.next found state code: 4'0101 found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:112$1532_Y found state code: 4'0100 found ctrl input: \soc_I.usb_I.tx_pkt_I.pid_is_handshake found ctrl input: \soc_I.usb_I.tx_pkt_I.len [10] found state code: 4'0011 found state code: 4'0010 found ctrl input: \soc_I.usb_I.trans_I.txpkt_start_i found state code: 4'0001 found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11760_CMP found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:203$1575_Y found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1559_Y found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1558_Y found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:177$1557_Y found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$0\ll_start[0:0] ctrl inputs: { \soc_I.usb_I.trans_I.txpkt_start_i \soc_I.usb_I.tx_pkt_I.pid_is_handshake \soc_I.usb_I.tx_pkt_I.next \soc_I.usb_I.tx_pkt_I.len [10] $flatten\soc_I.\usb_I.\tx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:112$1532_Y } ctrl outputs: { \soc_I.usb_I.tx_pkt_I.state_nxt $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:177$1557_Y $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1558_Y $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1559_Y $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:203$1575_Y $flatten\soc_I.\usb_I.\tx_pkt_I.$0\ll_start[0:0] $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11760_CMP } transition: 4'0000 5'0---- -> 4'0000 10'0000000100 transition: 4'0000 5'1---- -> 4'0001 10'0001000100 transition: 4'0100 5'--0-- -> 4'0100 10'0100000001 transition: 4'0100 5'--1-- -> 4'0101 10'0101000001 transition: 4'0010 5'--0-- -> 4'0010 10'0010001000 transition: 4'0010 5'-010- -> 4'0011 10'0011001000 transition: 4'0010 5'-011- -> 4'0100 10'0100001000 transition: 4'0010 5'-11-- -> 4'0000 10'0000001000 transition: 4'0001 5'----- -> 4'0010 10'0010000010 transition: 4'0101 5'--0-- -> 4'0101 10'0101010000 transition: 4'0101 5'--1-- -> 4'0000 10'0000010000 transition: 4'0011 5'----0 -> 4'0011 10'0011100000 transition: 4'0011 5'----1 -> 4'0100 10'0100100000 75.11.3. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\soc_I.usb_I.tx_pkt_I.state$23687' from module `\top'. Optimizing FSM `$fsm$\soc_I.usb_I.rx_pkt_I.state$23677' from module `\top'. Optimizing FSM `$fsm$\soc_I.cpu_I.mem_wordsize$23672' from module `\top'. Optimizing FSM `$fsm$\soc_I.cpu_I.cpu_state$23662' from module `\top'. Removing unused input signal $auto$opt_reduce.cc:134:opt_mux$23639. Optimizing FSM `$fsm$\i2c_I.core_I.state$23655' from module `\top'. Optimizing FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.fsm_state$23646' from module `\top'. Merging pattern 10'-----0--0- and 10'-----0--1- from group (1 1 10'0100001010). Merging pattern 10'-----0--1- and 10'-----0--0- from group (1 1 10'0100001010). 75.11.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 116 unused cells and 116 unused wires. <suppressed ~118 debug messages> 75.11.5. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.fsm_state$23646' from module `\top'. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procmux$15936_CMP. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] [0]. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] [1]. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] [2]. Optimizing FSM `$fsm$\i2c_I.core_I.state$23655' from module `\top'. Removing unused output signal $flatten\i2c_I.\core_I.$0\state[2:0] [0]. Removing unused output signal $flatten\i2c_I.\core_I.$0\state[2:0] [1]. Removing unused output signal $flatten\i2c_I.\core_I.$0\state[2:0] [2]. Optimizing FSM `$fsm$\soc_I.cpu_I.cpu_state$23662' from module `\top'. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [0]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [1]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [2]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [3]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [4]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [5]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [6]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [7]. Optimizing FSM `$fsm$\soc_I.cpu_I.mem_wordsize$23672' from module `\top'. Removing unused output signal $flatten\soc_I.\cpu_I.$0\mem_wordsize[1:0] [0]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\mem_wordsize[1:0] [1]. Optimizing FSM `$fsm$\soc_I.usb_I.rx_pkt_I.state$23677' from module `\top'. Removing unused output signal $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12089_CMP. Removing unused output signal $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12009_CMP. Removing unused output signal \soc_I.usb_I.rx_pkt_I.state_nxt [0]. Removing unused output signal \soc_I.usb_I.rx_pkt_I.state_nxt [1]. Removing unused output signal \soc_I.usb_I.rx_pkt_I.state_nxt [2]. Removing unused output signal \soc_I.usb_I.rx_pkt_I.state_nxt [3]. Optimizing FSM `$fsm$\soc_I.usb_I.tx_pkt_I.state$23687' from module `\top'. Removing unused output signal \soc_I.usb_I.tx_pkt_I.state_nxt [0]. Removing unused output signal \soc_I.usb_I.tx_pkt_I.state_nxt [1]. Removing unused output signal \soc_I.usb_I.tx_pkt_I.state_nxt [2]. Removing unused output signal \soc_I.usb_I.tx_pkt_I.state_nxt [3]. 75.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). Recoding FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.fsm_state$23646' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 000 -> ----1 100 -> ---1- 010 -> --1-- 001 -> -1--- 011 -> 1---- Recoding FSM `$fsm$\i2c_I.core_I.state$23655' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 000 -> ----1 100 -> ---1- 010 -> --1-- 001 -> -1--- 011 -> 1---- Recoding FSM `$fsm$\soc_I.cpu_I.cpu_state$23662' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 10000000 -> ------1 01000000 -> -----1- 00100000 -> ----1-- 00001000 -> ---1--- 00000100 -> --1---- 00000010 -> -1----- 00000001 -> 1------ Recoding FSM `$fsm$\soc_I.cpu_I.mem_wordsize$23672' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 00 -> --1 10 -> -1- 01 -> 1-- Recoding FSM `$fsm$\soc_I.usb_I.rx_pkt_I.state$23677' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 0000 -> -------1 0100 -> ------1- 0010 -> -----1-- 0110 -> ----1--- 0001 -> ---1---- 0101 -> --1----- 0011 -> -1------ 0111 -> 1------- Recoding FSM `$fsm$\soc_I.usb_I.tx_pkt_I.state$23687' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 0000 -> -----1 0100 -> ----1- 0010 -> ---1-- 0001 -> --1--- 0101 -> -1---- 0011 -> 1----- 75.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells). FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.fsm_state$23646' from module `top': ------------------------------------- Information on FSM $fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.fsm_state$23646 ($flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.fsm_state): Number of input signals: 10 Number of output signals: 6 Number of state bits: 5 Input signals: 0: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.ctrl_mode_mf 1: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.crc_I.in_valid 2: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:191$31_Y 3: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:166$25_Y 4: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$or$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:143$23_Y 5: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf 6: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.mfa_timeout [6] 7: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.fas_pos 8: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.data_match_fas 9: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.data [6] Output signals: 0: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:389$140_Y 1: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$72_Y 2: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$71_Y 3: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$48_Y 4: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$47_Y 5: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.align_frame State encoding: 0: 5'----1 <RESET STATE> 1: 5'---1- 2: 5'--1-- 3: 5'-1--- 4: 5'1---- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 10'-----0--0- -> 0 6'100110 1: 0 10'-0---0--1- -> 0 6'100110 2: 0 10'-----1---- -> 0 6'100110 3: 0 10'-1---0--1- -> 3 6'100110 4: 1 10'-----1---- -> 0 6'000101 5: 1 10'-----0---- -> 1 6'000101 6: 2 10'---1-01-1- -> 0 6'001010 7: 2 10'-----1---- -> 0 6'001010 8: 2 10'-----0--0- -> 2 6'001010 9: 2 10'-----00-1- -> 2 6'001010 10: 2 10'---0001-1- -> 2 6'001010 11: 2 10'---0101-1- -> 4 6'001010 12: 3 10'0-0--01-1- -> 0 6'010110 13: 3 10'-01--01-1- -> 0 6'010110 14: 3 10'-----1---- -> 0 6'010110 15: 3 10'-11--01-10 -> 1 6'010110 16: 3 10'-11--01-11 -> 2 6'010110 17: 3 10'-----0--0- -> 3 6'010110 18: 3 10'-----00-1- -> 3 6'010110 19: 3 10'1-0--01-1- -> 3 6'010110 20: 4 10'---1-01-1- -> 0 6'000110 21: 4 10'-----1---- -> 0 6'000110 22: 4 10'---0-0111- -> 1 6'000110 23: 4 10'-----0--0- -> 4 6'000110 24: 4 10'---0-0101- -> 4 6'000110 25: 4 10'-----00-1- -> 4 6'000110 ------------------------------------- FSM `$fsm$\i2c_I.core_I.state$23655' from module `top': ------------------------------------- Information on FSM $fsm$\i2c_I.core_I.state$23655 (\i2c_I.core_I.state): Number of input signals: 5 Number of output signals: 5 Number of state bits: 5 Input signals: 0: \i2c_I.core_I.stb 1: \i2c_I.core_I.cyc_cnt [4] 2: \i2c_I.core_I.bit_cnt [3] 3: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:109$5206_Y 4: \blinker_I.rst Output signals: 0: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:142$5215_Y 1: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:160$5219_Y 2: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:210$5224_Y 3: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:219$5227_Y 4: \i2c_I.ready State encoding: 0: 5'----1 <RESET STATE> 1: 5'---1- 2: 5'--1-- 3: 5'-1--- 4: 5'1---- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 5'0---0 -> 0 5'10000 1: 0 5'1---- -> 0 5'10000 2: 0 5'0---1 -> 2 5'10000 3: 1 5'01-1- -> 0 5'00010 4: 1 5'1---- -> 0 5'00010 5: 1 5'0--0- -> 1 5'00010 6: 1 5'00-1- -> 3 5'00010 7: 2 5'1---- -> 0 5'01000 8: 2 5'0--0- -> 2 5'01000 9: 2 5'0--1- -> 4 5'01000 10: 3 5'0-11- -> 0 5'00001 11: 3 5'1---- -> 0 5'00001 12: 3 5'0-01- -> 2 5'00001 13: 3 5'0--0- -> 3 5'00001 14: 4 5'1---- -> 0 5'00100 15: 4 5'0--1- -> 1 5'00100 16: 4 5'0--0- -> 4 5'00100 ------------------------------------- FSM `$fsm$\soc_I.cpu_I.cpu_state$23662' from module `top': ------------------------------------- Information on FSM $fsm$\soc_I.cpu_I.cpu_state$23662 (\soc_I.cpu_I.cpu_state): Number of input signals: 15 Number of output signals: 8 Number of state bits: 7 Input signals: 0: \soc_I.cpu_I.mem_done 1: \soc_I.cpu_I.instr_jal 2: \soc_I.cpu_I.decoder_trigger 3: \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu 4: \soc_I.cpu_I.is_slli_srli_srai 5: \soc_I.cpu_I.is_sb_sh_sw 6: \soc_I.cpu_I.is_sll_srl_sra 7: \soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu 8: \soc_I.cpu_I.alu_wait 9: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1810$4202_Y 10: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4220_Y 11: $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1851$4224_Y 12: $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1917$4261_Y 13: \soc_I.pb_rst_n 14: $auto$opt_reduce.cc:134:opt_mux$23577 Output signals: 0: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4073_Y 1: $flatten\soc_I.\cpu_I.$procmux$12640_CMP 2: $flatten\soc_I.\cpu_I.$procmux$12650_CMP 3: $flatten\soc_I.\cpu_I.$procmux$12651_CMP 4: $flatten\soc_I.\cpu_I.$procmux$12662_CMP 5: $flatten\soc_I.\cpu_I.$procmux$12670_CMP 6: $flatten\soc_I.\cpu_I.$procmux$12671_CMP 7: $flatten\soc_I.\cpu_I.$procmux$12675_CMP State encoding: 0: 7'------1 <RESET STATE> 1: 7'-----1- 2: 7'----1-- 3: 7'---1--- 4: 7'--1---- 5: 7'-1----- 6: 7'1------ Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 15'-10------------ -> 0 8'10000000 1: 0 15'--1------------ -> 0 8'10000000 2: 0 15'-00------------ -> 1 8'10000000 3: 1 15'--1------------ -> 0 8'00000001 4: 1 15'-10---------11- -> 1 8'00000001 5: 1 15'-10---------0-- -> 1 8'00000001 6: 1 15'-00------------ -> 1 8'00000001 7: 1 15'-10---------10- -> 2 8'00000001 8: 2 15'--1------------ -> 0 8'00001000 9: 2 15'-00------------ -> 1 8'00001000 10: 2 15'010-----0000--- -> 3 8'00001000 11: 2 15'110------------ -> 3 8'00001000 12: 2 15'010-----1-00--- -> 4 8'00001000 13: 2 15'-10-------1---- -> 4 8'00001000 14: 2 15'010------100--- -> 5 8'00001000 15: 2 15'-10--------1--- -> 6 8'00001000 16: 3 15'--1------------ -> 0 8'01000000 17: 3 15'-10---01------1 -> 1 8'01000000 18: 3 15'-10---00------- -> 1 8'01000000 19: 3 15'-00------------ -> 1 8'01000000 20: 3 15'-10---01------0 -> 3 8'01000000 21: 3 15'-10---1-------- -> 3 8'01000000 22: 4 15'--1------------ -> 0 8'00100000 23: 4 15'-10--1--------- -> 1 8'00100000 24: 4 15'-00------------ -> 1 8'00100000 25: 4 15'-10--0--------- -> 4 8'00100000 26: 5 15'--1------------ -> 0 8'00010000 27: 5 15'-1011---------- -> 1 8'00010000 28: 5 15'-00------------ -> 1 8'00010000 29: 5 15'-10-0---------- -> 5 8'00010000 30: 5 15'-1001---------- -> 5 8'00010000 31: 6 15'--1------------ -> 0 8'00000010 32: 6 15'-1011---------- -> 1 8'00000010 33: 6 15'-00------------ -> 1 8'00000010 34: 6 15'-10-0---------- -> 6 8'00000010 35: 6 15'-1001---------- -> 6 8'00000010 ------------------------------------- FSM `$fsm$\soc_I.cpu_I.mem_wordsize$23672' from module `top': ------------------------------------- Information on FSM $fsm$\soc_I.cpu_I.mem_wordsize$23672 (\soc_I.cpu_I.mem_wordsize): Number of input signals: 13 Number of output signals: 3 Number of state bits: 3 Input signals: 0: \soc_I.cpu_I.mem_do_rdata 1: \soc_I.cpu_I.mem_do_wdata 2: \soc_I.cpu_I.instr_lw 3: \soc_I.cpu_I.instr_sb 4: \soc_I.cpu_I.instr_sh 5: \soc_I.cpu_I.instr_sw 6: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4073_Y 7: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4220_Y 8: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1865$4228_Y 9: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1866$4229_Y 10: $flatten\soc_I.\cpu_I.$procmux$12640_CMP 11: $flatten\soc_I.\cpu_I.$procmux$12662_CMP 12: \soc_I.pb_rst_n Output signals: 0: $flatten\soc_I.\cpu_I.$procmux$15216_CMP 1: $flatten\soc_I.\cpu_I.$procmux$15223_CMP 2: $flatten\soc_I.\cpu_I.$procmux$15228_CMP State encoding: 0: 3'--1 1: 3'-1- 2: 3'1-- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 13'1-1--1----1-0 -> 0 3'100 1: 0 13'1-1--1------1 -> 0 3'100 2: 0 13'11---1-1---0- -> 0 3'100 3: 0 13'11---1-----1- -> 0 3'100 4: 0 13'100---0------ -> 0 3'100 5: 0 13'1-----1------ -> 0 3'100 6: 0 13'1-1--0------- -> 0 3'100 7: 0 13'11---0------- -> 0 3'100 8: 0 13'0------------ -> 0 3'100 9: 0 13'1-1-11------0 -> 1 3'100 10: 0 13'11---1---1-0- -> 1 3'100 11: 0 13'1-11-1------0 -> 2 3'100 12: 0 13'11---1--1--0- -> 2 3'100 13: 1 13'1-1--1----1-0 -> 0 3'001 14: 1 13'11---1-1---0- -> 0 3'001 15: 1 13'1-----1------ -> 0 3'001 16: 1 13'1-1-11------0 -> 1 3'001 17: 1 13'1-1--1------1 -> 1 3'001 18: 1 13'11---1---1-0- -> 1 3'001 19: 1 13'11---1-----1- -> 1 3'001 20: 1 13'100---0------ -> 1 3'001 21: 1 13'1-1--0------- -> 1 3'001 22: 1 13'11---0------- -> 1 3'001 23: 1 13'0------------ -> 1 3'001 24: 1 13'1-11-1------0 -> 2 3'001 25: 1 13'11---1--1--0- -> 2 3'001 26: 2 13'1-1--1----1-0 -> 0 3'010 27: 2 13'11---1-1---0- -> 0 3'010 28: 2 13'1-----1------ -> 0 3'010 29: 2 13'1-1-11------0 -> 1 3'010 30: 2 13'11---1---1-0- -> 1 3'010 31: 2 13'1-11-1------0 -> 2 3'010 32: 2 13'1-1--1------1 -> 2 3'010 33: 2 13'11---1--1--0- -> 2 3'010 34: 2 13'11---1-----1- -> 2 3'010 35: 2 13'100---0------ -> 2 3'010 36: 2 13'1-1--0------- -> 2 3'010 37: 2 13'11---0------- -> 2 3'010 38: 2 13'0------------ -> 2 3'010 ------------------------------------- FSM `$fsm$\soc_I.usb_I.rx_pkt_I.state$23677' from module `top': ------------------------------------- Information on FSM $fsm$\soc_I.usb_I.rx_pkt_I.state$23677 (\soc_I.usb_I.rx_pkt_I.state): Number of input signals: 14 Number of output signals: 6 Number of state bits: 8 Input signals: 0: \soc_I.usb_I.rx_ll_I.dec_valid_1 1: \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [3] 2: \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [2] 3: $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:180$1325_Y 4: $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:173$1323_Y 5: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:158$1319_Y 6: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:153$1318_Y 7: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:126$1314_Y 8: \soc_I.usb_I.rx_pkt_I.pid_is_handshake 9: \soc_I.usb_I.rx_pkt_I.pid_is_data 10: \soc_I.usb_I.rx_pkt_I.pid_is_token 11: \soc_I.usb_I.rx_pkt_I.pid_is_sof 12: \soc_I.usb_I.rx_pkt_I.pid_valid 13: \soc_I.usb_I.rx_pkt_I.llu_byte_stb Output signals: 0: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:375$1407_Y 1: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:341$1393_Y 2: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:337$1390_Y 3: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:245$1344_Y 4: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_error[0:0] 5: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_idle[0:0] State encoding: 0: 8'-------1 <RESET STATE> 1: 8'------1- 2: 8'-----1-- 3: 8'----1--- 4: 8'---1---- 5: 8'--1----- 6: 8'-1------ 7: 8'1------- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 14'------0------- -> 0 6'100000 1: 0 14'------1------- -> 4 6'100000 2: 1 14'0-------0----- -> 1 6'000100 3: 1 14'1-------0----- -> 5 6'000100 4: 1 14'--------1----- -> 6 6'000100 5: 2 14'-101---------- -> 1 6'000000 6: 2 14'-11----------- -> 1 6'000000 7: 2 14'-10001-------- -> 3 6'000000 8: 2 14'-10000-------- -> 6 6'000000 9: 2 14'-0------------ -> 6 6'000000 10: 2 14'-1001--------- -> 7 6'000000 11: 3 14'--------11---- -> 0 6'000000 12: 3 14'0-------0----- -> 3 6'000000 13: 3 14'--------10---- -> 6 6'000000 14: 3 14'1-------0----- -> 6 6'000000 15: 4 14'1------------- -> 2 6'001000 16: 4 14'0------------- -> 4 6'001000 17: 5 14'1-------0----- -> 3 6'000010 18: 5 14'0-------0----- -> 5 6'000010 19: 5 14'--------1----- -> 6 6'000010 20: 6 14'-------1------ -> 0 6'010000 21: 6 14'-------0------ -> 6 6'010000 22: 7 14'----------11-1 -> 0 6'000001 23: 7 14'-----------011 -> 6 6'000001 24: 7 14'----------01-1 -> 6 6'000001 25: 7 14'-------------0 -> 7 6'000001 26: 7 14'-----------001 -> 7 6'000001 ------------------------------------- FSM `$fsm$\soc_I.usb_I.tx_pkt_I.state$23687' from module `top': ------------------------------------- Information on FSM $fsm$\soc_I.usb_I.tx_pkt_I.state$23687 (\soc_I.usb_I.tx_pkt_I.state): Number of input signals: 5 Number of output signals: 6 Number of state bits: 6 Input signals: 0: $flatten\soc_I.\usb_I.\tx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:112$1532_Y 1: \soc_I.usb_I.tx_pkt_I.len [10] 2: \soc_I.usb_I.tx_pkt_I.next 3: \soc_I.usb_I.tx_pkt_I.pid_is_handshake 4: \soc_I.usb_I.trans_I.txpkt_start_i Output signals: 0: $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11760_CMP 1: $flatten\soc_I.\usb_I.\tx_pkt_I.$0\ll_start[0:0] 2: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:203$1575_Y 3: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1559_Y 4: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1558_Y 5: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:177$1557_Y State encoding: 0: 6'-----1 <RESET STATE> 1: 6'----1- 2: 6'---1-- 3: 6'--1--- 4: 6'-1---- 5: 6'1----- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 5'0---- -> 0 6'000100 1: 0 5'1---- -> 3 6'000100 2: 1 5'--0-- -> 1 6'000001 3: 1 5'--1-- -> 4 6'000001 4: 2 5'-11-- -> 0 6'001000 5: 2 5'-011- -> 1 6'001000 6: 2 5'--0-- -> 2 6'001000 7: 2 5'-010- -> 5 6'001000 8: 3 5'----- -> 2 6'000010 9: 4 5'--1-- -> 0 6'010000 10: 4 5'--0-- -> 4 6'010000 11: 5 5'----1 -> 1 6'100000 12: 5 5'----0 -> 5 6'100000 ------------------------------------- 75.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic). Mapping FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.fsm_state$23646' from module `\top'. Mapping FSM `$fsm$\i2c_I.core_I.state$23655' from module `\top'. Mapping FSM `$fsm$\soc_I.cpu_I.cpu_state$23662' from module `\top'. Mapping FSM `$fsm$\soc_I.cpu_I.mem_wordsize$23672' from module `\top'. Mapping FSM `$fsm$\soc_I.usb_I.rx_pkt_I.state$23677' from module `\top'. Mapping FSM `$fsm$\soc_I.usb_I.tx_pkt_I.state$23687' from module `\top'. 75.12. Executing OPT pass (performing simple optimizations). 75.12.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~38 debug messages> 75.12.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~93 debug messages> Removed a total of 31 cells. 75.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 1/3 on $pmux $flatten\soc_I.\cpu_I.$procmux$13155. dead port 2/4 on $pmux $flatten\soc_I.\cpu_I.$procmux$13255. dead port 3/6 on $pmux $flatten\soc_I.\cpu_I.$procmux$13719. dead port 1/3 on $pmux $flatten\soc_I.\cpu_I.$procmux$13904. Removed 4 multiplexer ports. <suppressed ~538 debug messages> 75.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$23596: { \soc_I.cpu_I.cpu_state [6:4] \soc_I.cpu_I.cpu_state [2:0] } New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$23594: \soc_I.cpu_I.cpu_state [5:0] New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$23592: { \soc_I.cpu_I.cpu_state [6] \soc_I.cpu_I.cpu_state [4:0] } Optimizing cells in module \top. Performed a total of 3 changes. 75.12.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.12.6. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $flatten\sys_mgr_I.$procdff$23059 ($adff) from module top (D = $flatten\sys_mgr_I.$add$/build/gateware/icE1usb/rtl/sysmgr.v:80$1720_Y [2:0], Q = \sys_mgr_I.rst_cnt [2:0]). Adding SRST signal on $flatten\spi_mux_I.$procdff$23495 ($dff) from module top (D = \spi_mux_I.state_nxt, Q = \spi_mux_I.state, rval = 3'000). Adding EN signal on $flatten\spi_mux_I.$procdff$23486 ($dff) from module top (D = \spi_mux_I.shift_data_nxt, Q = \spi_mux_I.shift_data). Adding SRST signal on $flatten\spi_mux_I.$procdff$23483 ($dff) from module top (D = \spi_mux_I.shift_data [7], Q = \spi_mux_I.srio_dat_o, rval = 1'0). Adding EN signal on $flatten\soc_I.\wb_48m_xclk_I.$procdff$23462 ($dff) from module top (D = \soc_I.wb_48m_xclk_I.m_rdata, Q = \soc_I.wb_48m_xclk_I.m_rdata_i). Adding SRST signal on $flatten\soc_I.\wb_48m_xclk_I.$procdff$23461 ($dff) from module top (D = \soc_I.wb_48m_xclk_I.m_rdata_i, Q = \soc_I.wb_48m_xclk_I.s_rdata, rval = 16'0000000000000000). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.\crc_16_I.$procdff$23027 ($dff) from module top (D = \soc_I.usb_I.tx_pkt_I.crc_16_I.state_nxt, Q = \soc_I.usb_I.tx_pkt_I.crc_16_I.state). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$23096 ($dff) from module top (D = $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1548_Y [3:0], Q = \soc_I.usb_I.tx_pkt_I.shift_bit). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$23095 ($dff) from module top (D = $flatten\soc_I.\usb_I.\tx_pkt_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:172$1554_Y, Q = \soc_I.usb_I.tx_pkt_I.shift_data). Adding SRST signal on $auto$opt_dff.cc:764:run$24224 ($dffe) from module top (D = \soc_I.usb_I.tx_pkt_I.shift_load [7], Q = \soc_I.usb_I.tx_pkt_I.shift_data [7], rval = 1'0). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$23094 ($dff) from module top (D = $flatten\soc_I.\usb_I.\tx_pkt_I.$or$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1561_Y, Q = \soc_I.usb_I.tx_pkt_I.shift_last_byte). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$23093 ($dff) from module top (D = \soc_I.usb_I.tx_pkt_I.state [5], Q = \soc_I.usb_I.tx_pkt_I.shift_data_crc). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$23091 ($dff) from module top (D = $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1571_Y [10:0], Q = \soc_I.usb_I.tx_pkt_I.len). Adding EN signal on $flatten\soc_I.\usb_I.\tx_ll_I.$procdff$23106 ($adff) from module top (D = $flatten\soc_I.\usb_I.\tx_ll_I.$0\state[2:0], Q = \soc_I.usb_I.tx_ll_I.state). Adding EN signal on $flatten\soc_I.\usb_I.\tx_ll_I.$procdff$23104 ($adff) from module top (D = $flatten\soc_I.\usb_I.\tx_ll_I.$and$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:95$1513_Y, Q = \soc_I.usb_I.tx_ll_I.bs_now). Adding EN signal on $flatten\soc_I.\usb_I.\tx_ll_I.$procdff$23103 ($adff) from module top (D = $flatten\soc_I.\usb_I.\tx_ll_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1511_Y [2:0], Q = \soc_I.usb_I.tx_ll_I.bs_cnt). Adding SRST signal on $flatten\soc_I.\usb_I.\tx_ll_I.$procdff$23102 ($dff) from module top (D = $flatten\soc_I.\usb_I.\tx_ll_I.$xor$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:103$1519_Y, Q = \soc_I.usb_I.tx_ll_I.lvl_prev, rval = 1'1). Adding EN signal on $flatten\soc_I.\usb_I.\tx_ll_I.$procdff$23100 ($adff) from module top (D = $flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11842_Y, Q = \soc_I.usb_I.tx_ll_I.out_sym). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23130 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$procmux$11923_Y, Q = \soc_I.usb_I.trans_I.mc_a_reg). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23127 ($dff) from module top (D = \soc_I.usb_I.trans_I.cel_state_i, Q = \soc_I.usb_I.trans_I.trans_cel). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23126 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:286$1445_Y, Q = \soc_I.usb_I.trans_I.trans_dir). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23125 ($dff) from module top (D = \soc_I.usb_I.rx_pkt_I.token_data [10:7], Q = \soc_I.usb_I.trans_I.trans_endp). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23124 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:284$1444_Y, Q = \soc_I.usb_I.trans_I.trans_is_setup). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23121 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$0\bd_state[2:0], Q = \soc_I.usb_I.trans_I.bd_state). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23118 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_trans.v:363$1456_Y, Q = \soc_I.usb_I.trans_I.ep_bd_idx_cur). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23117 ($dff) from module top (D = \soc_I.usb_I.ep_status_I.p_dout_3 [5], Q = \soc_I.usb_I.trans_I.ep_bd_ctrl). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23116 ($dff) from module top (D = \soc_I.usb_I.ep_status_I.p_dout_3 [4], Q = \soc_I.usb_I.trans_I.ep_bd_dual). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23115 ($dff) from module top (D = \soc_I.usb_I.ep_status_I.p_dout_3 [2:0], Q = \soc_I.usb_I.trans_I.ep_type). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23112 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$xor$/build/gateware/cores/no2usb//rtl/usb_trans.v:401$1477_Y, Q = \soc_I.usb_I.trans_I.txpkt_pid). Adding SRST signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23109 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_trans.v:425$1487_Y, Q = \soc_I.usb_I.trans_I.bd_length, rval = 11'00000000000). Adding SRST signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23108 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:429$1489_Y, Q = \soc_I.usb_I.trans_I.xfer_length, rval = 10'0000000000). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23107 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$procmux$11867_Y, Q = \soc_I.usb_I.trans_I.pkt_pid). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.\crc_5_I.$procdff$23026 ($dff) from module top (D = \soc_I.usb_I.rx_pkt_I.crc_5_I.state_nxt, Q = \soc_I.usb_I.rx_pkt_I.crc_5_I.state). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.\crc_16_I.$procdff$23027 ($dff) from module top (D = \soc_I.usb_I.rx_pkt_I.crc_16_I.state_nxt, Q = \soc_I.usb_I.rx_pkt_I.crc_16_I.state). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23152 ($dff) from module top (D = { \soc_I.usb_I.rx_ll_I.dec_bit_1 \soc_I.usb_I.rx_pkt_I.data [7:1] }, Q = \soc_I.usb_I.rx_pkt_I.data). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23151 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11966_Y, Q = \soc_I.usb_I.rx_pkt_I.bit_cnt, rval = 4'0110). Adding EN signal on $auto$opt_dff.cc:702:run$24259 ($sdff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1339_Y [3:0], Q = \soc_I.usb_I.rx_pkt_I.bit_cnt). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23150 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11961_Y, Q = \soc_I.usb_I.rx_pkt_I.bit_eop_ok, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24261 ($sdff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:234$1342_Y, Q = \soc_I.usb_I.rx_pkt_I.bit_eop_ok). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23149 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11956_Y, Q = \soc_I.usb_I.rx_pkt_I.crc_in_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24263 ($sdff) from module top (D = 1'0, Q = \soc_I.usb_I.rx_pkt_I.crc_in_first). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23147 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11946_Y, Q = \soc_I.usb_I.rx_pkt_I.crc16_ok, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24265 ($sdff) from module top (D = \soc_I.usb_I.rx_pkt_I.crc16_match, Q = \soc_I.usb_I.rx_pkt_I.crc16_ok). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23146 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11951_Y, Q = \soc_I.usb_I.rx_pkt_I.crc5_ok, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24267 ($sdff) from module top (D = \soc_I.usb_I.rx_pkt_I.crc5_match, Q = \soc_I.usb_I.rx_pkt_I.crc5_ok). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23145 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:306$1370_Y, Q = \soc_I.usb_I.rx_pkt_I.pid_valid). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23143 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_or$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:329$1388_Y, Q = \soc_I.usb_I.rx_pkt_I.pid_is_handshake). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23142 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_or$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:328$1383_Y, Q = \soc_I.usb_I.rx_pkt_I.pid_is_data). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23141 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_or$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:327$1380_Y, Q = \soc_I.usb_I.rx_pkt_I.pid_is_token). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23140 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:307$1353_Y, Q = \soc_I.usb_I.rx_pkt_I.pid_is_sof). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23139 ($dff) from module top (D = \soc_I.usb_I.rx_pkt_I.data [4:1], Q = \soc_I.usb_I.rx_pkt_I.pid). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23138 ($dff) from module top (D = { \soc_I.usb_I.rx_ll_I.dec_bit_1 \soc_I.usb_I.rx_pkt_I.data [7:1] }, Q = \soc_I.usb_I.rx_pkt_I.token_data [7:0]). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23137 ($dff) from module top (D = \soc_I.usb_I.rx_pkt_I.data [3:1], Q = \soc_I.usb_I.rx_pkt_I.token_data [10:8]). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$23164 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12232_Y, Q = \soc_I.usb_I.rx_ll_I.samp_cnt, rval = 3'101). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$23162 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:115$1302_Y, Q = \soc_I.usb_I.rx_ll_I.dec_bit_1). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$23161 ($dff) from module top (D = { \soc_I.usb_I.phy_I.dp_state [1] \soc_I.usb_I.phy_I.dn_state [1] }, Q = \soc_I.usb_I.rx_ll_I.dec_sym_1). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$23159 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12221_Y, Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$23158 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12216_Y, Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1). Adding SRST signal on $auto$opt_dff.cc:764:run$24281 ($dffe) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12206_Y, Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1, rval = 4'0000). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$23157 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12199_Y, Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1). Adding SRST signal on $auto$opt_dff.cc:764:run$24283 ($dffe) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12189_Y, Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1, rval = 4'0000). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$23156 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:183$1309_Y, Q = \soc_I.usb_I.rx_ll_I.dec_bs_skip_1). Adding EN signal on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$23175 ($dff) from module top (D = \soc_I.usb_I.ep_status_I.dout_2, Q = \soc_I.usb_I.ep_status_I.p_dout_3). Adding EN signal on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$23174 ($dff) from module top (D = $flatten\soc_I.\usb_I.\ep_status_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:82$1275_Y, Q = \soc_I.usb_I.ep_status_I.s_dout_3). Adding SRST signal on $auto$opt_dff.cc:764:run$24287 ($dffe) from module top (D = \soc_I.usb_I.ep_status_I.dout_2, Q = \soc_I.usb_I.ep_status_I.s_dout_3, rval = 16'0000000000000000). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23457 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:413$3436_Y, Q = \soc_I.usb_I.sof_clear, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23456 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:412$3433_Y, Q = \soc_I.usb_I.rst_clear, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23455 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:414$3439_Y, Q = \soc_I.usb_I.evt_rd_ack, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23453 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:410$3427_Y, Q = \soc_I.usb_I.cr_bus_we, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23451 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:411$3430_Y, Q = \soc_I.usb_I.cel_rel, rval = 1'0). Adding EN signal on $flatten\soc_I.\usb_I.$procdff$23450 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [6:0], Q = \soc_I.usb_I.cr_addr). Adding EN signal on $flatten\soc_I.\usb_I.$procdff$23449 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [7], Q = \soc_I.usb_I.cr_addr_chk). Adding EN signal on $flatten\soc_I.\usb_I.$procdff$23448 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [12], Q = \soc_I.usb_I.cr_cel_ena). Adding EN signal on $flatten\soc_I.\usb_I.$procdff$23447 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [15], Q = \soc_I.usb_I.cr_pu_ena). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23446 ($dff) from module top (D = \soc_I.cpu_I.mem_addr [13], Q = \soc_I.usb_I.eps_bus_req, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23445 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:498$3452_Y, Q = \soc_I.usb_I.eps_bus_write, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23444 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:497$3451_Y, Q = \soc_I.usb_I.eps_bus_read, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23441 ($dff) from module top (D = $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:623$3478_Y, Q = \soc_I.usb_I.timeout_suspend, rval = 20'11011100110110000000). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23440 ($dff) from module top (D = $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:632$3482_Y, Q = \soc_I.usb_I.timeout_reset, rval = 20'10001010110100000000). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23438 ($dff) from module top (D = \soc_I.usb_I.cr_pu_ena, Q = \soc_I.usb_I.pad_pu, rval = 1'0). Adding EN signal on $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$procdff$23030 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5466_DATA, Q = \soc_I.uart_I.uart_tx_fifo_I.ram_I.rd_data). Adding EN signal on $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$procdff$23242 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4341_Y [8:0], Q = \soc_I.uart_I.uart_tx_fifo_I.ram_wr_addr). Adding EN signal on $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$procdff$23241 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4343_Y [8:0], Q = \soc_I.uart_I.uart_tx_fifo_I.ram_rd_addr). Adding EN signal on $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$procdff$23240 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$not$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:114$4346_Y, Q = \soc_I.uart_I.uart_tx_fifo_I.rd_valid). Adding SRST signal on $flatten\soc_I.\uart_I.\uart_tx_I.$procdff$23238 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5263_Y [12], Q = \soc_I.uart_I.uart_tx_I.div_cnt [12], rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.\uart_tx_I.$procdff$23237 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_I.$procmux$12459_Y, Q = \soc_I.uart_I.uart_tx_I.bit_cnt, rval = 5'01000). Adding EN signal on $auto$opt_dff.cc:702:run$24309 ($sdff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5266_Y [4:0], Q = \soc_I.uart_I.uart_tx_I.bit_cnt). Adding EN signal on $flatten\soc_I.\uart_I.\uart_tx_I.$procdff$23236 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_I.$0\shift[9:0], Q = \soc_I.uart_I.uart_tx_I.shift). Adding EN signal on $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$procdff$23030 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5466_DATA, Q = \soc_I.uart_I.uart_rx_fifo_I.ram_I.rd_data). Adding EN signal on $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$procdff$23242 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4341_Y [8:0], Q = \soc_I.uart_I.uart_rx_fifo_I.ram_wr_addr). Adding EN signal on $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$procdff$23241 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4343_Y [8:0], Q = \soc_I.uart_I.uart_rx_fifo_I.ram_rd_addr). Adding EN signal on $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$procdff$23240 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$not$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:114$4346_Y, Q = \soc_I.uart_I.uart_rx_fifo_I.rd_valid). Adding SRST signal on $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procdff$23205 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4396_Y, Q = \soc_I.uart_I.uart_rx_I.gf_I.cnt, rval = 2'11). Adding SRST signal on $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procdff$23204 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procmux$12293_Y, Q = \soc_I.uart_I.uart_rx_I.gf_I.state, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24319 ($sdff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procmux$12293_Y, Q = \soc_I.uart_I.uart_rx_I.gf_I.state). Adding SRST signal on $flatten\soc_I.\uart_I.\uart_rx_I.$procdff$23418 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_I.$procmux$15258_Y, Q = \soc_I.uart_I.uart_rx_I.bit_cnt, rval = 5'01000). Adding EN signal on $auto$opt_dff.cc:702:run$24323 ($sdff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5248_Y [4:0], Q = \soc_I.uart_I.uart_rx_I.bit_cnt). Adding EN signal on $flatten\soc_I.\uart_I.\uart_rx_I.$procdff$23417 ($dff) from module top (D = { \soc_I.uart_I.uart_rx_I.gf_I.state \soc_I.uart_I.uart_rx_I.shift [8:1] }, Q = \soc_I.uart_I.uart_rx_I.shift). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$23478 ($dff) from module top (D = $flatten\soc_I.\uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:174$3298_Y, Q = \soc_I.uart_I.ub_wr_div, rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$23477 ($dff) from module top (D = $flatten\soc_I.\uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:173$3295_Y, Q = \soc_I.uart_I.ub_wr_data, rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$23476 ($dff) from module top (D = $flatten\soc_I.\uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:172$3290_Y, Q = \soc_I.uart_I.ub_rd_ctrl, rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$23475 ($dff) from module top (D = $flatten\soc_I.\uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:171$3286_Y, Q = \soc_I.uart_I.ub_rd_data, rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$23474 ($dff) from module top (D = $flatten\soc_I.\uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:181$3305_Y, Q = \soc_I.uart_I.ub_ack, rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$23473 ($dff) from module top (D = { $flatten\soc_I.\uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3310_Y [31] $flatten\soc_I.\uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3310_Y [27:12] $flatten\soc_I.\uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3310_Y [7:0] }, Q = { \soc_I.uart_I.ub_rdata [31] \soc_I.uart_I.ub_rdata [27:12] \soc_I.uart_I.ub_rdata [7:0] }, rval = 25'0000000000000000000000000). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$23473 ($dff) from module top (D = { \soc_I.uart_I.urf_overflow \soc_I.uart_I.uart_tx_fifo_I.rd_empty \soc_I.uart_I.uart_tx_fifo_I.full \soc_I.uart_I.uart_div [11:8] }, Q = { \soc_I.uart_I.ub_rdata [30:28] \soc_I.uart_I.ub_rdata [11:8] }, rval = 7'0000000). Adding EN signal on $flatten\soc_I.\uart_I.$procdff$23472 ($dff) from module top (D = \soc_I.cpu_I.mem_wdata [11:0], Q = \soc_I.uart_I.uart_div). Adding EN signal on $flatten\soc_I.\rgb_I.$procdff$23434 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [4:0], Q = \soc_I.rgb_I.led_ctrl). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$23008 ($adff) from module top (D = \soc_I.iobuf_I.spram_arb_I.mux_wmsk, Q = \soc_I.iobuf_I.spram_arb_I.m_wmsk). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$23007 ($adff) from module top (D = $flatten\soc_I.\iobuf_I.\spram_arb_I.$reduce_or$/build/gateware/common/rtl/wb_arbiter.v:91$5144_Y, Q = \soc_I.iobuf_I.spram_arb_I.m_we). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$23006 ($adff) from module top (D = \soc_I.iobuf_I.spram_arb_I.mux_wdata, Q = \soc_I.iobuf_I.spram_arb_I.m_wdata). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$23005 ($adff) from module top (D = \soc_I.iobuf_I.spram_arb_I.mux_addr, Q = \soc_I.iobuf_I.spram_arb_I.m_addr). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$23004 ($adff) from module top (D = $flatten\soc_I.\iobuf_I.\spram_arb_I.$reduce_or$/build/gateware/common/rtl/wb_arbiter.v:121$5157_Y, Q = \soc_I.iobuf_I.spram_arb_I.busy). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$23003 ($adff) from module top (D = \soc_I.iobuf_I.spram_arb_I.sel_nxt, Q = \soc_I.iobuf_I.spram_arb_I.sel). Adding EN signal on $flatten\soc_I.\iobuf_I.\epbam_arb_I.$procdff$23014 ($adff) from module top (D = $flatten\soc_I.\iobuf_I.\epbam_arb_I.$reduce_or$/build/gateware/common/rtl/wb_arbiter.v:91$5092_Y, Q = \soc_I.iobuf_I.epbam_arb_I.m_we). Adding EN signal on $flatten\soc_I.\iobuf_I.\epbam_arb_I.$procdff$23013 ($adff) from module top (D = \soc_I.iobuf_I.epbam_arb_I.mux_wdata, Q = \soc_I.iobuf_I.epbam_arb_I.m_wdata). Adding EN signal on $flatten\soc_I.\iobuf_I.\epbam_arb_I.$procdff$23012 ($adff) from module top (D = \soc_I.iobuf_I.epbam_arb_I.mux_addr, Q = \soc_I.iobuf_I.epbam_arb_I.m_addr). Adding EN signal on $flatten\soc_I.\iobuf_I.\epbam_arb_I.$procdff$23011 ($adff) from module top (D = $flatten\soc_I.\iobuf_I.\epbam_arb_I.$reduce_or$/build/gateware/common/rtl/wb_arbiter.v:121$5103_Y, Q = \soc_I.iobuf_I.epbam_arb_I.busy). Adding EN signal on $flatten\soc_I.\iobuf_I.\epbam_arb_I.$procdff$23010 ($adff) from module top (D = \soc_I.iobuf_I.epbam_arb_I.sel_nxt, Q = \soc_I.iobuf_I.epbam_arb_I.sel). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$23024 ($adff) from module top (D = \soc_I.iobuf_I.dma_I.state_nxt, Q = \soc_I.iobuf_I.dma_I.state). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$23023 ($dff) from module top (D = $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:144$5036_Y, Q = \soc_I.iobuf_I.dma_I.data_reg). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$23022 ($dff) from module top (D = $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:155$5040_Y [13:0], Q = \soc_I.iobuf_I.dma_I.m0_addr_i). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$23021 ($dff) from module top (D = $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:159$5044_Y [8:0], Q = \soc_I.iobuf_I.dma_I.m1_addr_i). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$23020 ($dff) from module top (D = $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:176$5053_Y [12:0], Q = \soc_I.iobuf_I.dma_I.len). Adding SRST signal on $auto$opt_dff.cc:764:run$24362 ($dffe) from module top (D = $flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$5052_Y [12], Q = \soc_I.iobuf_I.dma_I.len [12], rval = 1'0). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$23019 ($dff) from module top (D = \soc_I.cpu_I.mem_wdata [14], Q = \soc_I.iobuf_I.dma_I.dir). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$23233 ($dff) from module top (D = \soc_I.e1_buf_I.t_nxt_chan, Q = \soc_I.e1_buf_I.t_chan). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$23223 ($dff) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$12407_Y, Q = \soc_I.e1_buf_I.wb_wdata_byte). Adding SRST signal on $auto$opt_dff.cc:764:run$24366 ($dffe) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$12404_Y, Q = \soc_I.e1_buf_I.wb_wdata_byte, rval = 8'00000000). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$23222 ($dff) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$12422_Y, Q = \soc_I.e1_buf_I.wb_addr_lsb). Adding SRST signal on $auto$opt_dff.cc:764:run$24368 ($dffe) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$12419_Y, Q = \soc_I.e1_buf_I.wb_addr_lsb, rval = 2'00). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$23221 ($dff) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$12437_Y, Q = \soc_I.e1_buf_I.wb_addr). Adding SRST signal on $auto$opt_dff.cc:764:run$24370 ($dffe) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$12434_Y, Q = \soc_I.e1_buf_I.wb_addr, rval = 14'00000000000000). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$23220 ($dff) from module top (D = { \soc_I.e1_buf_I.buf_rx_mf [6:0] \soc_I.e1_buf_I.buf_rx_frame [3:0] \soc_I.e1_buf_I.buf_rx_ts [4:0] }, Q = \soc_I.e1_buf_I.rx_addr_reg[0]). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$23219 ($dff) from module top (D = \soc_I.e1_buf_I.buf_rx_data [7:0], Q = \soc_I.e1_buf_I.rx_data_reg[0]). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$23214 ($dff) from module top (D = { \soc_I.e1_buf_I.buf_tx_mf [6:0] \soc_I.e1_buf_I.buf_tx_frame [3:0] \soc_I.e1_buf_I.buf_tx_ts [4:0] }, Q = \soc_I.e1_buf_I.tx_addr_reg[0]). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$23212 ($dff) from module top (D = \soc_I.e1_buf_I.wb_rdata_mux, Q = \soc_I.e1_buf_I.tx_data_reg[0]). Adding SRST signal on $flatten\soc_I.\e1_I.$procdff$23199 ($dff) from module top (D = \soc_I.e1_I.bus_rdata, Q = \soc_I.e1_I.wb_rdata, rval = 16'0000000000000000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$procdff$23500 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$procmux$15681_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.hdb3_I.vstate, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24377 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$procmux$15677_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.hdb3_I.vstate). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$procdff$23499 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$procmux$15661_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.hdb3_I.zcnt, rval = 2'00). Adding EN signal on $auto$opt_dff.cc:702:run$24381 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$procmux$15659_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.hdb3_I.zcnt). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$procdff$23498 ($dff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$procmux$15606_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$procmux$15626_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$procmux$15637_Y }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.hdb3_I.d_neg, rval = 4'0000). Adding EN signal on $auto$opt_dff.cc:702:run$24383 ($sdff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$procmux$15604_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.hdb3_I.d_neg [1:0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$procmux$15635_Y }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.hdb3_I.d_neg). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$procdff$23497 ($dff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$procmux$15617_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$procmux$15670_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$procmux$15648_Y }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.hdb3_I.d_pos, rval = 4'0000). Adding EN signal on $auto$opt_dff.cc:702:run$24385 ($sdff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$procmux$15615_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.hdb3_I.d_pos [1:0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$procmux$15646_Y }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.hdb3_I.d_pos). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$procdff$23496 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$procmux$15692_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.hdb3_I.pstate, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24387 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$procmux$15690_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.hdb3_I.pstate). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.\crc_I.$procdff$23575 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.\crc_I.$xor$/build/gateware/cores/no2e1//rtl/e1_crc4.v:40$14_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.framer_I.crc_I.out_crc4). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$procdff$23522 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:115$213_Y, Q = \soc_I.e1_buf_I.buf_tx_frame [3:0]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$procdff$23521 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:126$216_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.framer_I.fetch_ts_is31). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$procdff$23520 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.framer_I.fetch_ts_is31, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.framer_I.fetch_ts_is0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$procdff$23519 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:124$215_Y [4:0], Q = \soc_I.e1_buf_I.buf_tx_ts [4:0]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$procdff$23518 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$logic_and$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:139$220_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.f_mf_last). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$procdff$23517 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.f_mf_last, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.f_mf_first). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$procdff$23515 ($adff) from module top (D = 1'1, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.framer_I.fetch_done). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$procdff$23513 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:194$232_Y [3:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.framer_I.bit_cnt). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$procdff$23512 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:201$234_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.framer_I.shift_data). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$procdff$23511 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$and$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:215$246_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.framer_I.shift_at_crc). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$procdff$23510 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$and$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:214$243_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.framer_I.shift_at_last). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$procdff$23509 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$and$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:213$239_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.framer_I.crc_I.in_first). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$procdff$23507 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$0\crc_smf[3:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.framer_I.crc_smf). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.$procdff$23064 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bd_tx_in_I.stage[1].l_valid, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.mf_valid). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.$procdff$23061 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.$procmux$11680_Y, Q = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.ll_raw_lo $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.pg_lo [3:0] }, rval = 5'00000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.$procdff$23060 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.$procmux$11686_Y, Q = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.ll_raw_hi $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.pg_hi [3:0] }, rval = 5'00000). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\bd_tx_out_I.$procdff$23173 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\bd_tx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4510_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bd_tx_out_I.data[1]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\bd_tx_out_I.$procdff$23172 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\bd_tx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4515_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bd_tx_out_I.stage[1].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\bd_tx_out_I.$procdff$23171 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\bd_tx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4521_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bd_tx_out_I.data[2]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\bd_tx_out_I.$procdff$23170 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\bd_tx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4526_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bd_tx_out_I.stage[2].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\bd_tx_out_I.$procdff$23169 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\bd_tx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4532_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bd_tx_out_I.data[3]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\bd_tx_out_I.$procdff$23168 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\bd_tx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4537_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bd_tx_out_I.stage[3].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\bd_tx_out_I.$procdff$23167 ($adff) from module top (D = \soc_I.e1_buf_I.buf_tx_mf [6:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bd_tx_out_I.data[4]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\bd_tx_out_I.$procdff$23166 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\bd_tx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4548_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bd_tx_out_I.stage[4].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\bd_tx_in_I.$procdff$23194 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\bd_tx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4464_Y, Q = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bd_tx_in_I.data[1] [8:7] \soc_I.e1_buf_I.buf_tx_mf [6:0] }). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\bd_tx_in_I.$procdff$23193 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\bd_tx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4469_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bd_tx_in_I.stage[1].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\bd_tx_in_I.$procdff$23192 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\bd_tx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4475_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bd_tx_in_I.data[2]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\bd_tx_in_I.$procdff$23191 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\bd_tx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4480_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bd_tx_in_I.stage[2].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\bd_tx_in_I.$procdff$23190 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\bd_tx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4486_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bd_tx_in_I.data[3]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\bd_tx_in_I.$procdff$23189 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\bd_tx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4491_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bd_tx_in_I.stage[3].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\bd_tx_in_I.$procdff$23188 ($adff) from module top (D = { \soc_I.cpu_I.mem_wdata [14:13] \soc_I.cpu_I.mem_wdata [6:0] }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bd_tx_in_I.data[4]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\bd_tx_in_I.$procdff$23187 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\bd_tx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4502_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bd_tx_in_I.stage[4].l_valid). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.$procdff$23057 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:118$4576_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.ctx_clear, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.$procdff$23056 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:117$4573_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.$procmux$11662_CMP, rval = 1'0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.$procdff$23055 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [6:5], Q = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_loopback [1] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.ctrl_loopback }). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.$procdff$23054 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [4], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.alarm). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.$procdff$23053 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [3], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.ctrl_time_src). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.$procdff$23052 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [2:1], Q = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.ctrl_do_crc4 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_mode [0] }). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.$procdff$23051 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bus_rd_tx_status [0]). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.$procdff$23050 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:158$4589_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bd_tx_out_I.rd_ena, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.$procdff$23049 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:157$4583_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bd_tx_in_I.wr_ena, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\hdb3_I.$procdff$23503 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\hdb3_I.$procmux$15703_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.hdb3_I.pstate, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24437 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\hdb3_I.$xor$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:62$444_Y [0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.hdb3_I.pstate). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\hdb3_I.$procdff$23502 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\hdb3_I.$procmux$15714_Y, Q = { \soc_I.e1_I.lb_bit [0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.hdb3_I.data [2:0] }, rval = 4'0000). Adding EN signal on $auto$opt_dff.cc:702:run$24443 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\hdb3_I.$procmux$15712_Y, Q = { \soc_I.e1_I.lb_bit [0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.hdb3_I.data [2:0] }). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$procdff$23529 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$procmux$15774_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.filter_I.cnt_lo, rval = 2'00). Adding EN signal on $auto$opt_dff.cc:702:run$24445 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$procmux$15774_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.filter_I.cnt_lo). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$procdff$23528 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$procmux$15783_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.filter_I.cnt_hi, rval = 2'00). Adding EN signal on $auto$opt_dff.cc:702:run$24449 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$procmux$15783_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.filter_I.cnt_hi). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$procdff$23527 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$procmux$15755_Y, Q = \misc_I.tick_e1 [1], rval = 1'1). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$procdff$23526 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$procmux$15760_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.clock_I.in_lo, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24454 ($sdff) from module top (D = 1'0, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.clock_I.in_lo). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$procdff$23525 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$procmux$15765_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.clock_I.in_hi, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24456 ($sdff) from module top (D = 1'0, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.clock_I.in_hi). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.\crc_I.$procdff$23575 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.\crc_I.$xor$/build/gateware/cores/no2e1//rtl/e1_crc4.v:40$14_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.crc_I.out_crc4). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23573 ($dff) from module top (D = \misc_I.tick_e1 [2], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.crc_I.in_valid, rval = 1'0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23572 ($dff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.data [6:0] \soc_I.e1_I.lb_bit [0] }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.data). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23571 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:135$21_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.data_match_fas). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23569 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procmux$15913_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.bit_last, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24462 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:215$35_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.bit_last). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23568 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procmux$15918_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.bit_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24464 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:214$34_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.bit_first). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23567 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procmux$15923_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.bit, rval = 3'000). Adding EN signal on $auto$opt_dff.cc:702:run$24466 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$33_Y [2:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.bit). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23566 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procmux$15898_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.ts_is_ts31, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24468 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:227$39_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.ts_is_ts31). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23565 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procmux$15903_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.ts_is_ts0, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24470 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.ts_is_ts31, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.ts_is_ts0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23564 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procmux$15908_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.ts, rval = 5'00001). Adding EN signal on $auto$opt_dff.cc:702:run$24472 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$38_Y [4:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.ts). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23563 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procmux$15873_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.frame_mf_last, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24474 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:243$45_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.frame_mf_last). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23562 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procmux$15878_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.frame_mf_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24476 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.frame_mf_last, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.frame_mf_first). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23561 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procmux$15883_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.frame_smf_last, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24478 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:241$44_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.frame_smf_last). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23560 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procmux$15888_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.frame_smf_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24480 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.frame_smf_last, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.frame_smf_first). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23559 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procmux$15893_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.frame, rval = 4'0000). Adding EN signal on $auto$opt_dff.cc:702:run$24482 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$43_Y [3:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.frame). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23558 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$xor$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:262$53_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.fas_pos, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23557 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procmux$15865_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.mfa_timeout, rval = 7'0111111). Adding EN signal on $auto$opt_dff.cc:702:run$24485 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$57_Y [6:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.mfa_timeout). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23556 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procmux$15850_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_crc, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24487 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:285$63_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_crc). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23555 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procmux$15855_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24489 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:284$62_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23554 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procmux$15860_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.ts0_msbs, rval = 16'1111111111111111). Adding EN signal on $auto$opt_dff.cc:702:run$24491 ($sdff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.ts0_msbs [14:0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.data [0] }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.ts0_msbs). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23553 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.crc_I.out_crc4, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.crc_smf). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23552 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:325$85_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.ep_nfas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23551 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:326$91_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.ed_nfas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23550 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:323$76_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.ep_fas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23549 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:324$81_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.ed_fas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23548 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:340$106_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.ep_mfa, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23547 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:341$111_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.ed_mfa, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23546 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:338$98_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.ep_crc, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23545 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:339$103_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.ed_crc, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23544 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$128_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.ec_mfa, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23543 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$124_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.ec_crc, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23542 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$120_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.ec_nfas, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23541 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$116_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.ec_fas, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23539 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:389$141_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.out_valid, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23538 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:396$143_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.out_last, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23537 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:395$142_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.out_first, rval = 1'1). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23535 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.ts, Q = \soc_I.e1_buf_I.buf_rx_ts [4:0], rval = 5'00000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23534 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.frame, Q = \soc_I.e1_buf_I.buf_rx_frame [3:0], rval = 4'0000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23533 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.data, Q = \soc_I.e1_buf_I.buf_rx_data [7:0], rval = 8'00000000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$procdff$23532 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:389$140_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.aligned, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\clock_I.$procdff$23574 ($dff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\clock_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:42$16_Y [5:4] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\clock_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:42$16_Y [0] }, Q = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.clock_I.cnt [5:4] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.clock_I.cnt [0] }, rval = 3'001). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\clock_I.$procdff$23574 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\clock_I.$procmux$15970_Y [3:1], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.clock_I.cnt [3:1], rval = 3'111). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\bd_rx_out_I.$procdff$23194 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\bd_rx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4464_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_out_I.data[1]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\bd_rx_out_I.$procdff$23193 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4469_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_out_I.stage[1].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\bd_rx_out_I.$procdff$23192 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\bd_rx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4475_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_out_I.data[2]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\bd_rx_out_I.$procdff$23191 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4480_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_out_I.stage[2].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\bd_rx_out_I.$procdff$23190 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\bd_rx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4486_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_out_I.data[3]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\bd_rx_out_I.$procdff$23189 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4491_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_out_I.stage[3].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\bd_rx_out_I.$procdff$23188 ($adff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_out_I.data[5] [8:7] \soc_I.e1_buf_I.buf_rx_mf [6:0] }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_out_I.data[4]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\bd_rx_out_I.$procdff$23187 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4502_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_out_I.stage[4].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\bd_rx_in_I.$procdff$23173 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\bd_rx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4510_Y, Q = \soc_I.e1_buf_I.buf_rx_mf [6:0]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\bd_rx_in_I.$procdff$23172 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4515_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_in_I.stage[1].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\bd_rx_in_I.$procdff$23171 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\bd_rx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4521_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_in_I.data[2]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\bd_rx_in_I.$procdff$23170 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4526_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_in_I.stage[2].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\bd_rx_in_I.$procdff$23169 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\bd_rx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4532_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_in_I.data[3]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\bd_rx_in_I.$procdff$23168 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4537_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_in_I.stage[3].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\bd_rx_in_I.$procdff$23167 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [6:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_in_I.data[4]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\bd_rx_in_I.$procdff$23166 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4548_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_in_I.stage[4].l_valid). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.$procdff$23046 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:114$4616_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.crx_clear, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.$procdff$23045 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:113$4613_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.$procmux$11646_CMP, rval = 1'0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.$procdff$23044 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [2:1], Q = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_mode [1] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.ctrl_mode_mf }). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.$procdff$23043 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bus_rd_rx_status [0]). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.$procdff$23042 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:149$4629_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_out_I.rd_ena, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.$procdff$23041 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:148$4623_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_in_I.wr_ena, rval = 1'0). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23413 ($dff) from module top (D = \soc_I.cpu_I.mem_rdata, Q = \soc_I.cpu_I.mem_rdata_q). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23402 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$0\mem_state[1:0], Q = \soc_I.cpu_I.mem_state). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23401 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14944_Y, Q = \soc_I.cpu_I.mem_wstrb). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23400 ($dff) from module top (D = \soc_I.cpu_I.mem_la_wdata, Q = \soc_I.cpu_I.mem_wdata). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23398 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$0\mem_valid[0:0], Q = \soc_I.cpu_I.mem_valid). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23397 ($dff) from module top (D = \soc_I.cpu_I.mem_la_addr, Q = \soc_I.cpu_I.mem_addr). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23381 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$reduce_or$/build/gateware/common/rtl/picorv32.v:846$3778_Y, Q = \soc_I.cpu_I.is_compare, rval = 1'0). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23380 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:860$3798_Y, Q = \soc_I.cpu_I.is_alu_reg_reg). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23379 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:859$3797_Y, Q = \soc_I.cpu_I.is_alu_reg_imm). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23377 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14325_Y, Q = \soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24592 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:856$3794_Y, Q = \soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23374 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$reduce_or$/build/gateware/common/rtl/picorv32.v:842$3774_Y, Q = \soc_I.cpu_I.is_lui_auipc_jal_jalr_addi_add_sub, rval = 1'0). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23373 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1091$4027_Y, Q = \soc_I.cpu_I.is_sll_srl_sra). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23372 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:858$3796_Y, Q = \soc_I.cpu_I.is_sb_sh_sw). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23371 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1082$4016_Y, Q = \soc_I.cpu_I.is_jalr_addi_slti_sltiu_xori_ori_andi). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23370 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1076$4007_Y, Q = \soc_I.cpu_I.is_slli_srli_srai). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23369 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:857$3795_Y, Q = \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23367 ($dff) from module top (D = 1'0, Q = \soc_I.cpu_I.compressed_instr). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$24600 ($dffe) from module top. Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23366 ($dff) from module top (D = { \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [19:12] \soc_I.cpu_I.mem_rdata_latched [20] \soc_I.cpu_I.mem_rdata_latched [30:21] 1'0 }, Q = \soc_I.cpu_I.decoded_imm_uj). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$24601 ($dffe) from module top. Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23365 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371_Y, Q = \soc_I.cpu_I.decoded_imm). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23364 ($dff) from module top (D = \soc_I.cpu_I.mem_rdata_latched [24:20], Q = \soc_I.cpu_I.decoded_rs2). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23363 ($dff) from module top (D = \soc_I.cpu_I.mem_rdata_latched [19:15], Q = \soc_I.cpu_I.decoded_rs1). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23362 ($dff) from module top (D = \soc_I.cpu_I.mem_rdata_latched [11:7], Q = \soc_I.cpu_I.decoded_rd). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23358 ($dff) from module top (D = 1'0, Q = \soc_I.cpu_I.instr_retirq). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$24606 ($dffe) from module top. Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23355 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1068$3974_Y, Q = \soc_I.cpu_I.instr_ecall_ebreak). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23350 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14481_Y, Q = \soc_I.cpu_I.instr_and, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24608 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1059$3943_Y, Q = \soc_I.cpu_I.instr_and). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23349 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14485_Y, Q = \soc_I.cpu_I.instr_or, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24610 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1058$3939_Y, Q = \soc_I.cpu_I.instr_or). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23348 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14489_Y, Q = \soc_I.cpu_I.instr_sra, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24612 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1057$3935_Y, Q = \soc_I.cpu_I.instr_sra). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23347 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14493_Y, Q = \soc_I.cpu_I.instr_srl, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24614 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1056$3931_Y, Q = \soc_I.cpu_I.instr_srl). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23346 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14497_Y, Q = \soc_I.cpu_I.instr_xor, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24616 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1055$3927_Y, Q = \soc_I.cpu_I.instr_xor). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23345 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14501_Y, Q = \soc_I.cpu_I.instr_sltu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24618 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1054$3923_Y, Q = \soc_I.cpu_I.instr_sltu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23344 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14505_Y, Q = \soc_I.cpu_I.instr_slt, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24620 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1053$3919_Y, Q = \soc_I.cpu_I.instr_slt). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23343 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14509_Y, Q = \soc_I.cpu_I.instr_sll, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24622 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1052$3915_Y, Q = \soc_I.cpu_I.instr_sll). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23342 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14513_Y, Q = \soc_I.cpu_I.instr_sub, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24624 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1051$3911_Y, Q = \soc_I.cpu_I.instr_sub). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23341 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14517_Y, Q = \soc_I.cpu_I.instr_add, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24626 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1050$3907_Y, Q = \soc_I.cpu_I.instr_add). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23340 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1048$3903_Y, Q = \soc_I.cpu_I.instr_srai). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23339 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1047$3899_Y, Q = \soc_I.cpu_I.instr_srli). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23338 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1046$3895_Y, Q = \soc_I.cpu_I.instr_slli). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23337 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14527_Y, Q = \soc_I.cpu_I.instr_andi, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24631 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1044$3891_Y, Q = \soc_I.cpu_I.instr_andi). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23336 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14531_Y, Q = \soc_I.cpu_I.instr_ori, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24633 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1043$3889_Y, Q = \soc_I.cpu_I.instr_ori). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23335 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14535_Y, Q = \soc_I.cpu_I.instr_xori, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24635 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1042$3887_Y, Q = \soc_I.cpu_I.instr_xori). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23334 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14539_Y, Q = \soc_I.cpu_I.instr_sltiu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24637 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1041$3885_Y, Q = \soc_I.cpu_I.instr_sltiu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23333 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14543_Y, Q = \soc_I.cpu_I.instr_slti, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24639 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1040$3883_Y, Q = \soc_I.cpu_I.instr_slti). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23332 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14547_Y, Q = \soc_I.cpu_I.instr_addi, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24641 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1039$3881_Y, Q = \soc_I.cpu_I.instr_addi). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23331 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1037$3879_Y, Q = \soc_I.cpu_I.instr_sw). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23330 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1036$3877_Y, Q = \soc_I.cpu_I.instr_sh). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23329 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1035$3875_Y, Q = \soc_I.cpu_I.instr_sb). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23328 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1033$3873_Y, Q = \soc_I.cpu_I.instr_lhu). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23327 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1032$3871_Y, Q = \soc_I.cpu_I.instr_lbu). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23326 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1031$3869_Y, Q = \soc_I.cpu_I.instr_lw). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23325 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1030$3867_Y, Q = \soc_I.cpu_I.instr_lh). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23324 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1029$3865_Y, Q = \soc_I.cpu_I.instr_lb). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23323 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14567_Y, Q = \soc_I.cpu_I.instr_bgeu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24651 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1027$3863_Y, Q = \soc_I.cpu_I.instr_bgeu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23322 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14571_Y, Q = \soc_I.cpu_I.instr_bltu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24653 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1026$3861_Y, Q = \soc_I.cpu_I.instr_bltu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23321 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14575_Y, Q = \soc_I.cpu_I.instr_bge, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24655 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1025$3859_Y, Q = \soc_I.cpu_I.instr_bge). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23320 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14579_Y, Q = \soc_I.cpu_I.instr_blt, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24657 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1024$3857_Y, Q = \soc_I.cpu_I.instr_blt). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23319 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14583_Y, Q = \soc_I.cpu_I.instr_bne, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24659 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1023$3855_Y, Q = \soc_I.cpu_I.instr_bne). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23318 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14587_Y, Q = \soc_I.cpu_I.instr_beq, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24661 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1022$3853_Y, Q = \soc_I.cpu_I.instr_beq). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23317 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:852$3785_Y, Q = \soc_I.cpu_I.instr_jalr). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23316 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:851$3782_Y, Q = \soc_I.cpu_I.instr_jal). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23315 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:850$3781_Y, Q = \soc_I.cpu_I.instr_auipc). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23314 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:849$3780_Y, Q = \soc_I.cpu_I.instr_lui). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23310 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13174_Y, Q = \soc_I.cpu_I.alu_wait, rval = 1'0). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23303 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13301_Y, Q = \soc_I.cpu_I.latched_rd, rval = 5'00010). Adding EN signal on $auto$opt_dff.cc:702:run$24670 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13301_Y, Q = \soc_I.cpu_I.latched_rd). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23302 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13327_Y, Q = \soc_I.cpu_I.latched_is_lb, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24680 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13327_Y, Q = \soc_I.cpu_I.latched_is_lb). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23301 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13340_Y, Q = \soc_I.cpu_I.latched_is_lh, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24690 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13340_Y, Q = \soc_I.cpu_I.latched_is_lh). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23300 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13353_Y, Q = \soc_I.cpu_I.latched_is_lu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24700 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13353_Y, Q = \soc_I.cpu_I.latched_is_lu). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23298 ($dff) from module top (D = \soc_I.cpu_I.compressed_instr, Q = \soc_I.cpu_I.latched_compr). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23297 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13398_Y, Q = \soc_I.cpu_I.latched_branch, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24713 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13398_Y, Q = \soc_I.cpu_I.latched_branch). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23296 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13434_Y, Q = \soc_I.cpu_I.latched_stalu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24721 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13434_Y, Q = \soc_I.cpu_I.latched_stalu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23295 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13441_Y, Q = \soc_I.cpu_I.latched_store, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24731 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13441_Y, Q = \soc_I.cpu_I.latched_store). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23284 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13067_Y, Q = \soc_I.cpu_I.decoder_pseudo_trigger, rval = 1'0). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23281 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13705_Y, Q = \soc_I.cpu_I.mem_do_wdata, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24742 ($sdff) from module top (D = 1'0, Q = \soc_I.cpu_I.mem_do_wdata). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23280 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13709_Y, Q = \soc_I.cpu_I.mem_do_rdata, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24744 ($sdff) from module top (D = 1'0, Q = \soc_I.cpu_I.mem_do_rdata). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23279 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13780_Y, Q = \soc_I.cpu_I.mem_do_rinst, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24746 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13780_Y, Q = \soc_I.cpu_I.mem_do_rinst). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23278 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13805_Y, Q = \soc_I.cpu_I.mem_do_prefetch, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24762 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1552$4156_Y, Q = \soc_I.cpu_I.mem_do_prefetch). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23271 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13200_Y, Q = \soc_I.cpu_I.reg_out, rval = 1024). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23270 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13907_Y, Q = \soc_I.cpu_I.reg_op2). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23269 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13930_Y [31], Q = \soc_I.cpu_I.reg_op1 [31]). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23269 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13930_Y [30:0], Q = \soc_I.cpu_I.reg_op1 [30:0]). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23268 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12542_Y, Q = \soc_I.cpu_I.reg_next_pc [31:2], rval = 30'000000000000000000000000000000). Adding EN signal on $auto$opt_dff.cc:702:run$24806 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12531_Y, Q = \soc_I.cpu_I.reg_next_pc [31:2]). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23267 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13978_Y, Q = \soc_I.cpu_I.reg_pc [31:2], rval = 30'000000000000000000000000000000). Adding EN signal on $auto$opt_dff.cc:702:run$24808 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$3\current_pc[31:0] [31:2], Q = \soc_I.cpu_I.reg_pc [31:2]). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23260 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13283_Y, Q = \soc_I.cpu_I.trap, rval = 1'0). Adding SRST signal on $flatten\soc_I.\bridge_I.$procdff$23034 ($dff) from module top (D = \soc_I.bridge_I.wb_rdata_or, Q = \soc_I.bridge_I.wb_rdata_reg, rval = 0). Adding SRST signal on $flatten\soc_I.\bram_I.$procdff$23429 ($dff) from module top (D = 8'xxxxxxxx, Q = $flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3509_DATA [31:24], rval = 8'00000000). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$24812 ($sdff) from module top. Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$24812 ($sdff) from module top. Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$24812 ($sdff) from module top. Setting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$24812 ($sdff) from module top. Setting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$24812 ($sdff) from module top. Setting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$24812 ($sdff) from module top. Setting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$24812 ($sdff) from module top. Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$24812 ($sdff) from module top. Adding SRST signal on $flatten\soc_I.\bram_I.$procdff$23426 ($dff) from module top (D = 16'xxxxxxxxxxxxxxxx, Q = $flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3508_DATA [31:16], rval = 16'0000000000000000). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$24813 ($sdff) from module top. Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$24813 ($sdff) from module top. Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$24813 ($sdff) from module top. Setting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$24813 ($sdff) from module top. Setting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$24813 ($sdff) from module top. Setting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$24813 ($sdff) from module top. Setting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$24813 ($sdff) from module top. Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$24813 ($sdff) from module top. Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$24813 ($sdff) from module top. Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$24813 ($sdff) from module top. Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$24813 ($sdff) from module top. Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$24813 ($sdff) from module top. Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$24813 ($sdff) from module top. Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$24813 ($sdff) from module top. Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$24813 ($sdff) from module top. Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$24813 ($sdff) from module top. Adding SRST signal on $flatten\soc_I.\bram_I.$procdff$23423 ($dff) from module top (D = 24'xxxxxxxxxxxxxxxxxxxxxxxx, Q = $flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3507_DATA [31:8], rval = 24'000000000000000000000000). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$24814 ($sdff) from module top. Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$24814 ($sdff) from module top. Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$24814 ($sdff) from module top. Setting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$24814 ($sdff) from module top. Setting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$24814 ($sdff) from module top. Setting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$24814 ($sdff) from module top. Setting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$24814 ($sdff) from module top. Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$24814 ($sdff) from module top. Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$24814 ($sdff) from module top. Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$24814 ($sdff) from module top. Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$24814 ($sdff) from module top. Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$24814 ($sdff) from module top. Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$24814 ($sdff) from module top. Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$24814 ($sdff) from module top. Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$24814 ($sdff) from module top. Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$24814 ($sdff) from module top. Setting constant 0-bit at position 16 on $auto$opt_dff.cc:702:run$24814 ($sdff) from module top. Setting constant 0-bit at position 17 on $auto$opt_dff.cc:702:run$24814 ($sdff) from module top. Setting constant 0-bit at position 18 on $auto$opt_dff.cc:702:run$24814 ($sdff) from module top. Setting constant 0-bit at position 19 on $auto$opt_dff.cc:702:run$24814 ($sdff) from module top. Setting constant 0-bit at position 20 on $auto$opt_dff.cc:702:run$24814 ($sdff) from module top. Setting constant 0-bit at position 21 on $auto$opt_dff.cc:702:run$24814 ($sdff) from module top. Setting constant 0-bit at position 22 on $auto$opt_dff.cc:702:run$24814 ($sdff) from module top. Setting constant 0-bit at position 23 on $auto$opt_dff.cc:702:run$24814 ($sdff) from module top. Adding SRST signal on $flatten\misc_I.\pps_flt_I.$procdff$23248 ($dff) from module top (D = $flatten\misc_I.\pps_flt_I.$procmux$12480_Y, Q = \misc_I.pps_flt_I.state, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24815 ($sdff) from module top (D = 1'1, Q = \misc_I.pps_flt_I.state). Adding SRST signal on $flatten\misc_I.\pdm_e1_I[1].$procdff$23258 ($dff) from module top (D = $flatten\misc_I.\pdm_e1_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4277_Y, Q = \misc_I.pdm_e1_I[1].acc, rval = 9'000000000). Adding SRST signal on $flatten\misc_I.\pdm_e1_I[0].$procdff$23258 ($dff) from module top (D = $flatten\misc_I.\pdm_e1_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4277_Y, Q = \misc_I.pdm_e1_I[0].acc, rval = 9'000000000). Adding SRST signal on $flatten\misc_I.\pdm_clk_I[1].\lfsr_I.$procdff$23470 ($dff) from module top (D = { \misc_I.pdm_clk_I[1].lfsr_I.fb \misc_I.pdm_clk_I[1].lfsr_I.out [7:1] }, Q = \misc_I.pdm_clk_I[1].lfsr_I.out, rval = 8'00000001). Adding SRST signal on $flatten\misc_I.\pdm_clk_I[1].$procdff$23257 ($dff) from module top (D = $flatten\misc_I.\pdm_clk_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4282_Y, Q = \misc_I.pdm_clk_I[1].acc, rval = 13'0000000000000). Adding SRST signal on $flatten\misc_I.\pdm_clk_I[0].\lfsr_I.$procdff$23470 ($dff) from module top (D = { \misc_I.pdm_clk_I[0].lfsr_I.fb \misc_I.pdm_clk_I[0].lfsr_I.out [7:1] }, Q = \misc_I.pdm_clk_I[0].lfsr_I.out, rval = 8'00000001). Adding SRST signal on $flatten\misc_I.\pdm_clk_I[0].$procdff$23257 ($dff) from module top (D = $flatten\misc_I.\pdm_clk_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4282_Y, Q = \misc_I.pdm_clk_I[0].acc, rval = 13'0000000000000). Adding SRST signal on $flatten\misc_I.\dfu_I.\btn_flt_I.$procdff$23000 ($dff) from module top (D = $flatten\misc_I.\dfu_I.\btn_flt_I.$procmux$5629_Y, Q = \misc_I.dfu_I.btn_flt_I.state, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24823 ($sdff) from module top (D = 1'1, Q = \misc_I.dfu_I.btn_flt_I.state). Adding EN signal on $flatten\misc_I.\dfu_I.$procdff$23252 ($adff) from module top (D = $flatten\misc_I.\dfu_I.$procmux$12506_Y, Q = \misc_I.dfu_I.wb_sel). Adding EN signal on $flatten\misc_I.\dfu_I.$procdff$23251 ($adff) from module top (D = $flatten\misc_I.\dfu_I.$procmux$12511_Y, Q = \misc_I.dfu_I.rst_req). Adding SRST signal on $flatten\misc_I.$procdff$23082 ($dff) from module top (D = { $flatten\misc_I.$eq$/build/gateware/icE1usb/rtl/misc.v:130$1634_Y $flatten\misc_I.$eq$/build/gateware/icE1usb/rtl/misc.v:129$1633_Y }, Q = \misc_I.bus_we_pdm_e1, rval = 2'00). Adding SRST signal on $flatten\misc_I.$procdff$23081 ($dff) from module top (D = { $flatten\misc_I.$eq$/build/gateware/icE1usb/rtl/misc.v:128$1632_Y $flatten\misc_I.$eq$/build/gateware/icE1usb/rtl/misc.v:127$1631_Y }, Q = \misc_I.bus_we_pdm_clk, rval = 2'00). Adding SRST signal on $flatten\misc_I.$procdff$23080 ($dff) from module top (D = $flatten\misc_I.$eq$/build/gateware/icE1usb/rtl/misc.v:126$1630_Y, Q = \misc_I.bus_we_tick_sel, rval = 1'0). Adding SRST signal on $flatten\misc_I.$procdff$23079 ($dff) from module top (D = $flatten\misc_I.$eq$/build/gateware/icE1usb/rtl/misc.v:125$1629_Y, Q = \misc_I.bus_we_led, rval = 1'0). Adding SRST signal on $flatten\misc_I.$procdff$23078 ($dff) from module top (D = $flatten\misc_I.$eq$/build/gateware/icE1usb/rtl/misc.v:124$1628_Y, Q = \misc_I.bus_we_gpio, rval = 1'0). Adding SRST signal on $flatten\misc_I.$procdff$23077 ($dff) from module top (D = $flatten\misc_I.$eq$/build/gateware/icE1usb/rtl/misc.v:123$1627_Y, Q = \misc_I.bus_we_boot, rval = 1'0). Adding SRST signal on $flatten\misc_I.$procdff$23076 ($dff) from module top (D = $flatten\misc_I.$procmux$11716_Y, Q = \misc_I.wb_rdata, rval = 0). Adding EN signal on $flatten\misc_I.$procdff$23075 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [3:0], Q = \misc_I.gpio_out). Adding EN signal on $flatten\misc_I.$procdff$23074 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [11:8], Q = \misc_I.gpio_oe). Adding EN signal on $flatten\misc_I.$procdff$23073 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [8:0], Q = \misc_I.e1_led). Adding EN signal on $flatten\misc_I.$procdff$23072 ($dff) from module top (D = \soc_I.cpu_I.mem_wdata [17:16], Q = \misc_I.tick_e1_sel[1]). Adding EN signal on $flatten\misc_I.$procdff$23071 ($dff) from module top (D = \soc_I.cpu_I.mem_wdata [1:0], Q = \misc_I.tick_e1_sel[0]). Adding EN signal on $flatten\misc_I.$procdff$23070 ($adff) from module top (D = { \soc_I.cpu_I.mem_wdata [31] \soc_I.cpu_I.mem_wdata [7:0] }, Q = \misc_I.pdm_e1[1]). Adding EN signal on $flatten\misc_I.$procdff$23069 ($adff) from module top (D = { \soc_I.cpu_I.mem_wdata [31] \soc_I.cpu_I.mem_wdata [7:0] }, Q = \misc_I.pdm_e1[0]). Adding EN signal on $flatten\misc_I.$procdff$23068 ($adff) from module top (D = { \soc_I.cpu_I.mem_wdata [31] \soc_I.cpu_I.mem_wdata [11:0] }, Q = \misc_I.pdm_clk[1]). Adding EN signal on $flatten\misc_I.$procdff$23067 ($adff) from module top (D = { \soc_I.cpu_I.mem_wdata [31] \soc_I.cpu_I.mem_wdata [11:0] }, Q = \misc_I.pdm_clk[0]). Adding EN signal on $flatten\misc_I.$procdff$23066 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [2], Q = \misc_I.boot_now). Adding EN signal on $flatten\misc_I.$procdff$23065 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [1:0], Q = \misc_I.boot_sel). Adding EN signal on $flatten\i2c_I.\core_I.$procdff$23468 ($dff) from module top (D = \soc_I.cpu_I.mem_wdata [13:12], Q = \i2c_I.core_I.cmd_cur). Adding SRST signal on $flatten\i2c_I.\core_I.$procdff$23467 ($dff) from module top (D = $flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:133$5212_Y [4:0], Q = \i2c_I.core_I.cyc_cnt, rval = 5'00000). Adding EN signal on $flatten\i2c_I.\core_I.$procdff$23466 ($dff) from module top (D = $flatten\i2c_I.\core_I.$0\bit_cnt[3:0], Q = \i2c_I.core_I.bit_cnt). Adding EN signal on $flatten\i2c_I.\core_I.$procdff$23465 ($dff) from module top (D = $flatten\i2c_I.\core_I.$0\data_reg[8:0], Q = \i2c_I.core_I.data_reg). Adding SRST signal on $flatten\i2c_I.\core_I.$procdff$23464 ($dff) from module top (D = $flatten\i2c_I.\core_I.$procmux$15378_Y, Q = \i2c_I.core_I.scl_oe, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24855 ($sdff) from module top (D = $flatten\i2c_I.\core_I.$procmux$15376_Y, Q = \i2c_I.core_I.scl_oe). Adding SRST signal on $flatten\i2c_I.\core_I.$procdff$23463 ($dff) from module top (D = $flatten\i2c_I.\core_I.$procmux$15368_Y, Q = \i2c_I.core_I.sda_oe, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24861 ($sdff) from module top (D = $flatten\i2c_I.\core_I.$procmux$15366_Y, Q = \i2c_I.core_I.sda_oe). Adding SRST signal on $flatten\i2c_I.$procdff$23480 ($dff) from module top (D = { \i2c_I.ready \i2c_I.ready \i2c_I.core_I.data_reg [0] \i2c_I.core_I.data_reg [8:1] }, Q = { \i2c_I.wb_rdata [31:30] \i2c_I.wb_rdata [8:0] }, rval = 11'00000000000). Adding EN signal on $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$procdff$23030 ($dff) from module top (D = $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5466_DATA, Q = \gps_uart_I.uart_tx_fifo_I.ram_I.rd_data). Adding EN signal on $flatten\gps_uart_I.\uart_tx_fifo_I.$procdff$23242 ($adff) from module top (D = $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4341_Y [8:0], Q = \gps_uart_I.uart_tx_fifo_I.ram_wr_addr). Adding EN signal on $flatten\gps_uart_I.\uart_tx_fifo_I.$procdff$23241 ($adff) from module top (D = $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4343_Y [8:0], Q = \gps_uart_I.uart_tx_fifo_I.ram_rd_addr). Adding EN signal on $flatten\gps_uart_I.\uart_tx_fifo_I.$procdff$23240 ($adff) from module top (D = $flatten\gps_uart_I.\uart_tx_fifo_I.$not$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:114$4346_Y, Q = \gps_uart_I.uart_tx_fifo_I.rd_valid). Adding SRST signal on $flatten\gps_uart_I.\uart_tx_I.$procdff$23238 ($dff) from module top (D = $flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5263_Y [12], Q = \gps_uart_I.uart_tx_I.div_cnt [12], rval = 1'0). Adding SRST signal on $flatten\gps_uart_I.\uart_tx_I.$procdff$23237 ($dff) from module top (D = $flatten\gps_uart_I.\uart_tx_I.$procmux$12459_Y, Q = \gps_uart_I.uart_tx_I.bit_cnt, rval = 5'01000). Adding EN signal on $auto$opt_dff.cc:702:run$24875 ($sdff) from module top (D = $flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5266_Y [4:0], Q = \gps_uart_I.uart_tx_I.bit_cnt). Adding EN signal on $flatten\gps_uart_I.\uart_tx_I.$procdff$23236 ($adff) from module top (D = $flatten\gps_uart_I.\uart_tx_I.$0\shift[9:0], Q = \gps_uart_I.uart_tx_I.shift). Adding EN signal on $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$procdff$23030 ($dff) from module top (D = $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5466_DATA, Q = \gps_uart_I.uart_rx_fifo_I.ram_I.rd_data). Adding EN signal on $flatten\gps_uart_I.\uart_rx_fifo_I.$procdff$23242 ($adff) from module top (D = $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4341_Y [8:0], Q = \gps_uart_I.uart_rx_fifo_I.ram_wr_addr). Adding EN signal on $flatten\gps_uart_I.\uart_rx_fifo_I.$procdff$23241 ($adff) from module top (D = $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4343_Y [8:0], Q = \gps_uart_I.uart_rx_fifo_I.ram_rd_addr). Adding EN signal on $flatten\gps_uart_I.\uart_rx_fifo_I.$procdff$23240 ($adff) from module top (D = $flatten\gps_uart_I.\uart_rx_fifo_I.$not$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:114$4346_Y, Q = \gps_uart_I.uart_rx_fifo_I.rd_valid). Adding SRST signal on $flatten\gps_uart_I.\uart_rx_I.\gf_I.$procdff$23205 ($dff) from module top (D = $flatten\gps_uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4396_Y, Q = \gps_uart_I.uart_rx_I.gf_I.cnt, rval = 2'11). Adding SRST signal on $flatten\gps_uart_I.\uart_rx_I.\gf_I.$procdff$23204 ($dff) from module top (D = $flatten\gps_uart_I.\uart_rx_I.\gf_I.$procmux$12293_Y, Q = \gps_uart_I.uart_rx_I.gf_I.state, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24885 ($sdff) from module top (D = $flatten\gps_uart_I.\uart_rx_I.\gf_I.$procmux$12293_Y, Q = \gps_uart_I.uart_rx_I.gf_I.state). Adding SRST signal on $flatten\gps_uart_I.\uart_rx_I.$procdff$23418 ($dff) from module top (D = $flatten\gps_uart_I.\uart_rx_I.$procmux$15258_Y, Q = \gps_uart_I.uart_rx_I.bit_cnt, rval = 5'01000). Adding EN signal on $auto$opt_dff.cc:702:run$24889 ($sdff) from module top (D = $flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5248_Y [4:0], Q = \gps_uart_I.uart_rx_I.bit_cnt). Adding EN signal on $flatten\gps_uart_I.\uart_rx_I.$procdff$23417 ($dff) from module top (D = { \gps_uart_I.uart_rx_I.gf_I.state \gps_uart_I.uart_rx_I.shift [8:1] }, Q = \gps_uart_I.uart_rx_I.shift). Adding SRST signal on $flatten\gps_uart_I.$procdff$23478 ($dff) from module top (D = $flatten\gps_uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:174$3298_Y, Q = \gps_uart_I.ub_wr_div, rval = 1'0). Adding SRST signal on $flatten\gps_uart_I.$procdff$23477 ($dff) from module top (D = $flatten\gps_uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:173$3295_Y, Q = \gps_uart_I.ub_wr_data, rval = 1'0). Adding SRST signal on $flatten\gps_uart_I.$procdff$23476 ($dff) from module top (D = $flatten\gps_uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:172$3290_Y, Q = \gps_uart_I.ub_rd_ctrl, rval = 1'0). Adding SRST signal on $flatten\gps_uart_I.$procdff$23475 ($dff) from module top (D = $flatten\gps_uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:171$3286_Y, Q = \gps_uart_I.ub_rd_data, rval = 1'0). Adding SRST signal on $flatten\gps_uart_I.$procdff$23474 ($dff) from module top (D = $flatten\gps_uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:181$3305_Y, Q = \gps_uart_I.ub_ack, rval = 1'0). Adding SRST signal on $flatten\gps_uart_I.$procdff$23473 ($dff) from module top (D = { \gps_uart_I.urf_overflow \gps_uart_I.uart_tx_fifo_I.rd_empty \gps_uart_I.uart_tx_fifo_I.full \gps_uart_I.uart_div [11:8] }, Q = { \gps_uart_I.ub_rdata [30:28] \gps_uart_I.ub_rdata [11:8] }, rval = 7'0000000). Adding SRST signal on $flatten\gps_uart_I.$procdff$23473 ($dff) from module top (D = { $flatten\gps_uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3310_Y [31] $flatten\gps_uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3310_Y [27:12] $flatten\gps_uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3310_Y [7:0] }, Q = { \gps_uart_I.ub_rdata [31] \gps_uart_I.ub_rdata [27:12] \gps_uart_I.ub_rdata [7:0] }, rval = 25'0000000000000000000000000). Adding EN signal on $flatten\gps_uart_I.$procdff$23472 ($dff) from module top (D = \soc_I.cpu_I.mem_wdata [11:0], Q = \gps_uart_I.uart_div). 75.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 480 unused cells and 549 unused wires. <suppressed ~483 debug messages> 75.12.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~28 debug messages> 75.12.9. Rerunning OPT passes. (Maybe there is more to do..) 75.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~223 debug messages> 75.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 75.12.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~81 debug messages> Removed a total of 27 cells. 75.12.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$24712 ($dffe) from module top. 75.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 31 unused wires. <suppressed ~2 debug messages> 75.12.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~1 debug messages> 75.12.16. Rerunning OPT passes. (Maybe there is more to do..) 75.12.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~222 debug messages> 75.12.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 75.12.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.12.20. Executing OPT_DFF pass (perform DFF optimizations). 75.12.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 1 unused wires. <suppressed ~1 debug messages> 75.12.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.12.23. Rerunning OPT passes. (Maybe there is more to do..) 75.12.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~222 debug messages> 75.12.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 75.12.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.12.27. Executing OPT_DFF pass (perform DFF optimizations). 75.12.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.12.29. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.12.30. Finished OPT passes. (There is nothing left to do.) 75.13. Executing WREDUCE pass (reducing word size of cells). Removed top 24 address bits (of 32) from memory init port top.$flatten\soc_I.\bram_I.$meminit$\mem$/build/gateware/common/rtl/soc_bram.v:0$3533 (soc_I.bram_I.mem). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24686 ($ne). Removed top 2 bits (of 3) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24674 ($ne). Removed top 2 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23776 ($eq). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24576 ($ne). Removed top 2 bits (of 3) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24572 ($ne). Removed top 1 bits (of 6) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24750 ($ne). Removed top 1 bits (of 3) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24725 ($ne). Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23803 ($eq). Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23799 ($eq). Removed top 1 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23784 ($eq). Removed top 2 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23780 ($eq). Removed top 2 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23729 ($eq). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24783 ($ne). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24351 ($ne). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24353 ($ne). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24355 ($ne). Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$24112 ($eq). Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$24116 ($eq). Removed top 2 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$24151 ($eq). Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$24181 ($eq). Removed top 3 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23750 ($eq). Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$24212 ($eq). Removed top 2 bits (of 4) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24551 ($ne). Removed top 2 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23718 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\e1_buf_I.$eq$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:233$5323 ($eq). Removed top 26 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_buf_I.$shiftx$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5334 ($shiftx). Removed top 3 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5341 ($shl). Removed top 3 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_buf_I.$and$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5343 ($and). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\e1_buf_I.$ne$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:253$5361 ($ne). Removed top 1 bits (of 4) from mux cell top.$flatten\soc_I.\e1_buf_I.$procmux$12319 ($mux). Removed cell top.$flatten\soc_I.\e1_buf_I.$procmux$12404 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\e1_I.$eq$/build/gateware/cores/no2e1//rtl/e1_wb.v:148$5380 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\clock_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:42$16 ($sub). Removed top 26 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\clock_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:42$16 ($sub). Removed top 30 bits (of 32) from mux cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$12 ($mux). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.\crc_I.$xor$/build/gateware/cores/no2e1//rtl/e1_crc4.v:40$14 ($xor). Removed top 1 bits (of 16) from FF cell top.$auto$opt_dff.cc:764:run$24492 ($sdffe). Removed top 1 bits (of 6) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23924 ($eq). Removed top 1 bits (of 6) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23911 ($eq). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$128 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$124 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$120 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$116 ($add). Removed top 3 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.\crc_I.$and$/build/gateware/cores/no2e1//rtl/e1_crc4.v:35$6 ($and). Removed top 2 bits (of 6) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:284$62 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$57 ($sub). Removed top 25 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$57 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$43 ($add). Removed top 28 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$43 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$38 ($add). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$38 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$33 ($add). Removed top 29 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$33 ($add). Removed cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$procmux$15780 ($mux). Removed cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$procmux$15771 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:64$165 ($sub). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:64$165 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:62$161 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:62$161 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:56$156 ($sub). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:56$156 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:54$152 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:54$152 ($add). Removed top 2 bits (of 6) from mux cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\clock_I.$procmux$15970 ($mux). Removed top 2 bits (of 6) from mux cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\clock_I.$procmux$15967 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\hdb3_I.$xor$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:62$444 ($xor). Removed top 31 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\hdb3_I.$xor$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:62$444 ($xor). Removed top 1 bits (of 2) from FF cell top.$auto$opt_dff.cc:764:run$24543 ($adffe). Removed top 2 bits (of 6) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:135$20 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:99$205 ($sub). Removed top 26 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:99$205 ($sub). Removed top 30 bits (of 32) from mux cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$12 ($mux). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.\crc_I.$xor$/build/gateware/cores/no2e1//rtl/e1_crc4.v:40$14 ($xor). Removed cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$procmux$15719 ($mux). Removed top 3 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.\crc_I.$and$/build/gateware/cores/no2e1//rtl/e1_crc4.v:35$6 ($and). Removed top 28 bits (of 32) from mux cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:194$232 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:194$230 ($sub). Removed top 28 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:194$230 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:124$215 ($add). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:124$215 ($add). Removed top 27 bits (of 32) from mux cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:99$207 ($mux). Removed cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$procmux$15688 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$add$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:120$461 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$add$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:120$461 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$xor$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:106$456 ($xor). Removed top 31 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$xor$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:106$456 ($xor). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$xor$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:103$455 ($xor). Removed top 31 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$xor$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:103$455 ($xor). Removed top 16 bits (of 32) from port B of cell top.$flatten\soc_I.\iobuf_I.$or$/build/gateware/common/rtl/soc_iobuf.v:250$2651 ($or). Removed cell top.$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5713 ($mux). Removed cell top.$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5710 ($mux). Removed cell top.$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5706 ($mux). Removed top 20 bits (of 32) from mux cell top.$flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:176$5053 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$5052 ($sub). Removed top 19 bits (of 32) from port Y of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$5052 ($sub). Removed top 23 bits (of 32) from mux cell top.$flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:159$5044 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$5042 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$5042 ($add). Removed top 18 bits (of 32) from mux cell top.$flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:155$5040 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$5038 ($add). Removed top 18 bits (of 32) from port Y of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$5038 ($add). Removed top 3 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5752_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5751_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5750_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5749_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5748_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5747_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5746_CMP0 ($eq). Removed top 3 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5735_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5734_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5733_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5732_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5731_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5730_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5729_CMP0 ($eq). Removed cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11861 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11845_CMP0 ($eq). Removed top 29 bits (of 32) from mux cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1511 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1509 ($add). Removed top 29 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1509 ($add). Removed top 30 bits (of 32) from port A of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1505 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1505 ($add). Removed top 29 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1505 ($add). Removed top 16 bits (of 32) from mux cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.\crc_16_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4957 ($mux). Removed top 1 bits (of 7) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23898 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1571 ($sub). Removed top 21 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1571 ($sub). Removed top 21 bits (of 32) from port A of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1571 ($sub). Removed top 21 bits (of 32) from mux cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1570 ($mux). Removed top 1 bits (of 8) from mux cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:172$1554 ($mux). Removed top 28 bits (of 32) from port A of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1548 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1548 ($sub). Removed top 28 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1548 ($sub). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:137$1535 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12239_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12238_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12237_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12224_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12213_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12212_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12211_CMP0 ($eq). Removed top 3 bits (of 4) from mux cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12204 ($mux). Removed top 2 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12196_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12195_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12194_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:98$1290 ($eq). Removed top 16 bits (of 32) from mux cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.\crc_16_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4957 ($mux). Removed top 1 bits (of 16) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.\crc_16_I.$eq$/build/gateware/cores/no2usb//rtl/usb_crc.v:44$4960 ($eq). Removed top 29 bits (of 32) from mux cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.\crc_5_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4970 ($mux). Removed top 2 bits (of 5) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.\crc_5_I.$xor$/build/gateware/cores/no2usb//rtl/usb_crc.v:38$4971 ($xor). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:313$1364 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:311$1360 ($eq). Removed top 3 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:308$1354 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:307$1353 ($eq). Removed top 29 bits (of 32) from port A of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1339 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1339 ($sub). Removed top 28 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1339 ($sub). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$procmux$11926_CMP0 ($eq). Removed top 1 bits (of 4) from mux cell top.$flatten\soc_I.\usb_I.\trans_I.$procmux$11903 ($mux). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$procmux$11901_CMP0 ($eq). Removed cell top.$flatten\soc_I.\usb_I.\trans_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_trans.v:375$1466 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:303$1448 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:207$1426 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:206$1425 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:205$1424 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:204$1423 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:203$1422 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:202$1421 ($eq). Removed top 3 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:201$1420 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:179$1419 ($add). Removed top 24 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:179$1419 ($add). Removed top 24 bits (of 32) from mux cell top.$flatten\soc_I.\uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3310 ($mux). Removed top 1 bits (of 5) from FF cell top.$auto$opt_dff.cc:764:run$24338 ($adffe). Removed top 1 bits (of 13) from mux cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$procmux$12465 ($mux). Removed cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$procmux$12454 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5266 ($sub). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5266 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5263 ($sub). Removed top 19 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5263 ($sub). Removed cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$procmux$5756 ($mux). Removed cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$procmux$5758 ($mux). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$procdff$23033 ($dff). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4343 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4343 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4341 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4341 ($add). Removed top 1 bits (of 10) from port B of cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$eq$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:81$4330 ($eq). Removed cell top.$flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procmux$12290 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5248 ($sub). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5248 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5245 ($sub). Removed top 19 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5245 ($sub). Removed top 21 bits (of 32) from port A of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5244 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5244 ($sub). Removed top 20 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5244 ($sub). Removed cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$procmux$5756 ($mux). Removed cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$procmux$5758 ($mux). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$procdff$23033 ($dff). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4343 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4343 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4341 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4341 ($add). Removed top 1 bits (of 10) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$eq$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:81$4330 ($eq). Removed cell top.$flatten\soc_I.\bram_I.$procmux$15271 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$15273 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$15277 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$15279 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$15283 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$15285 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$15289 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$15291 ($mux). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\bram_I.$procdff$23424 ($dff). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\bram_I.$procdff$23427 ($dff). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\bram_I.$procdff$23430 ($dff). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\bram_I.$procdff$23433 ($dff). Removed top 24 bits (of 32) from port A of cell top.$flatten\soc_I.\bridge_I.$or$/build/gateware/common/rtl/soc_picorv32_bridge.v:152$5429 ($or). Removed top 16 bits (of 32) from port B of cell top.$flatten\soc_I.\bridge_I.$or$/build/gateware/common/rtl/soc_picorv32_bridge.v:152$5431 ($or). Removed top 16 bits (of 32) from port B of cell top.$flatten\soc_I.\bridge_I.$or$/build/gateware/common/rtl/soc_picorv32_bridge.v:152$5435 ($or). Removed top 3 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5442 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5443 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5444 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5445 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5446 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5447 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5448 ($eq). Removed top 3 bits (of 4) from port A of cell top.$flatten\soc_I.\cpu_I.$shl$/build/gateware/common/rtl/picorv32.v:403$3702 ($shl). Removed top 30 bits (of 32) from mux cell top.$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:601$3761 ($mux). Removed top 1 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:849$3780 ($eq). Removed top 2 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:850$3781 ($eq). Removed top 5 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:857$3795 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:858$3796 ($eq). Removed top 2 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:859$3797 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:860$3798 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1023$3854 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1031$3868 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1041$3884 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1048$3902 ($eq). Removed top 29 bits (of 32) from port B of cell top.$flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1296$4075 ($add). Removed top 29 bits (of 32) from port B of cell top.$flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1539$4152 ($add). Removed top 29 bits (of 32) from port B of cell top.$flatten\soc_I.\cpu_I.$ge$/build/gateware/common/rtl/picorv32.v:1814$4203 ($ge). Removed top 29 bits (of 32) from port B of cell top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4211 ($sub). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4211 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4218 ($sub). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4218 ($sub). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12929 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12932 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13196 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13198 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13203 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13253 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13273 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13296 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13299 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13323 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13325 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13336 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13338 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13349 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13351 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13396 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13429 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13432 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13448 ($mux). Removed top 1 bits (of 2) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23845 ($eq). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13717 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13722 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13729 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13745 ($pmux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13778 ($mux). Removed top 2 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23836 ($eq). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13926 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13928 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13934 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13936 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13951 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14072 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14914 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14918 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14924 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\cpu_I.$procmux$14926_CMP0 ($eq). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14927 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14933 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14967 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14977 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14979 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14983 ($mux). Removed top 24 bits (of 32) from mux cell top.$flatten\soc_I.\cpu_I.$procmux$15210 ($pmux). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\cpu_I.$procmux$15213_CMP0 ($eq). Removed top 16 bits (of 32) from mux cell top.$flatten\soc_I.\cpu_I.$procmux$15219 ($pmux). Removed top 2 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23827 ($eq). Removed top 11 bits (of 31) from FF cell top.$auto$opt_dff.cc:764:run$24601 ($dffe). Removed top 1 bits (of 8) from port B of cell top.$flatten\misc_I.\pdm_clk_I[1].\lfsr_I.$and$/build/gateware/cores/no2misc//rtl/pdm.v:130$5200 ($and). Removed top 1 bits (of 8) from port B of cell top.$flatten\misc_I.\pdm_clk_I[0].\lfsr_I.$and$/build/gateware/cores/no2misc//rtl/pdm.v:130$5200 ($and). Removed top 25 bits (of 26) from port B of cell top.$flatten\misc_I.\dfu_I.$add$/build/gateware/common/rtl/dfu_helper.v:113$4291 ($add). Removed top 3 bits (of 4) from port B of cell top.$flatten\misc_I.$procmux$11721_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\misc_I.$procmux$11720_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\misc_I.$procmux$11719_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\misc_I.$procmux$11718_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\misc_I.$procmux$11717_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\misc_I.$shiftx$/build/gateware/icE1usb/rtl/misc.v:0$1639 ($shiftx). Removed top 1 bits (of 4) from port B of cell top.$flatten\misc_I.$eq$/build/gateware/icE1usb/rtl/misc.v:126$1630 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\misc_I.$eq$/build/gateware/icE1usb/rtl/misc.v:125$1629 ($eq). Removed top 3 bits (of 4) from port B of cell top.$flatten\misc_I.$eq$/build/gateware/icE1usb/rtl/misc.v:124$1628 ($eq). Removed top 3 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23710 ($eq). Removed top 1 bits (of 10) from port B of cell top.$flatten\gps_uart_I.\uart_rx_fifo_I.$eq$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:81$4330 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4341 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4341 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4343 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4343 ($add). Removed top 7 bits (of 8) from FF cell top.$flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$procdff$23033 ($dff). Removed cell top.$flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$procmux$5758 ($mux). Removed cell top.$flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$procmux$5756 ($mux). Removed top 21 bits (of 32) from port A of cell top.$flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5244 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5244 ($sub). Removed top 20 bits (of 32) from port Y of cell top.$flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5244 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5245 ($sub). Removed top 19 bits (of 32) from port Y of cell top.$flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5245 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5248 ($sub). Removed top 27 bits (of 32) from port Y of cell top.$flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5248 ($sub). Removed cell top.$flatten\gps_uart_I.\uart_rx_I.\gf_I.$procmux$12290 ($mux). Removed top 1 bits (of 10) from port B of cell top.$flatten\gps_uart_I.\uart_tx_fifo_I.$eq$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:81$4330 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4341 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4341 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4343 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4343 ($add). Removed top 7 bits (of 8) from FF cell top.$flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$procdff$23033 ($dff). Removed cell top.$flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$procmux$5758 ($mux). Removed cell top.$flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$procmux$5756 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5263 ($sub). Removed top 19 bits (of 32) from port Y of cell top.$flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5263 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5266 ($sub). Removed top 27 bits (of 32) from port Y of cell top.$flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5266 ($sub). Removed cell top.$flatten\gps_uart_I.\uart_tx_I.$procmux$12454 ($mux). Removed top 1 bits (of 10) from mux cell top.$flatten\gps_uart_I.\uart_tx_I.$procmux$12457 ($mux). Removed top 1 bits (of 13) from mux cell top.$flatten\gps_uart_I.\uart_tx_I.$procmux$12465 ($mux). Removed top 24 bits (of 32) from mux cell top.$flatten\gps_uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3310 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\gps_uart_I.$eq$/build/gateware/cores/no2misc//rtl/uart_wb.v:172$3289 ($eq). Removed top 2 bits (of 4) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24230 ($ne). Removed top 1 bits (of 2) from port B of cell top.$flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:109$5206 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:133$5212 ($add). Removed top 27 bits (of 32) from port Y of cell top.$flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:133$5212 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:143$5217 ($add). Removed top 28 bits (of 32) from port Y of cell top.$flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:143$5217 ($add). Removed top 1 bits (of 2) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23819 ($eq). Removed cell top.$flatten\i2c_I.\core_I.$procmux$15358 ($mux). Removed cell top.$flatten\i2c_I.\core_I.$procmux$15361 ($mux). Removed cell top.$flatten\i2c_I.\core_I.$procmux$15373 ($mux). Removed cell top.$flatten\i2c_I.\core_I.$procmux$15383 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\i2c_I.\core_I.$procmux$15391_CMP0 ($eq). Removed cell top.$flatten\i2c_I.\core_I.$procmux$15393 ($mux). Removed top 1 bits (of 11) from FF cell top.$auto$opt_dff.cc:702:run$24869 ($sdff). Removed cell top.$flatten\i2c_I.$procmux$15488 ($mux). Removed top 16 bits (of 32) from port B of cell top.$flatten\blinker_I.$and$/build/gateware/icE1usb/rtl/led_blinker.v:57$1592 ($and). Removed top 16 bits (of 32) from port Y of cell top.$flatten\blinker_I.$and$/build/gateware/icE1usb/rtl/led_blinker.v:57$1592 ($and). Removed top 16 bits (of 32) from port A of cell top.$flatten\blinker_I.$and$/build/gateware/icE1usb/rtl/led_blinker.v:57$1592 ($and). Removed top 31 bits (of 32) from port B of cell top.$flatten\blinker_I.$add$/build/gateware/icE1usb/rtl/led_blinker.v:57$1590 ($add). Removed top 16 bits (of 32) from port Y of cell top.$flatten\blinker_I.$add$/build/gateware/icE1usb/rtl/led_blinker.v:57$1590 ($add). Removed top 2 bits (of 3) from port B of cell top.$flatten\spi_mux_I.$procmux$15560_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23714 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\spi_mux_I.$procmux$15502_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\spi_mux_I.$eq$/build/gateware/icE1usb/rtl/sr_btn_if.v:277$3258 ($eq). Removed top 3 bits (of 4) from port Y of cell top.$flatten\spi_mux_I.$and$/build/gateware/icE1usb/rtl/sr_btn_if.v:247$3239 ($and). Removed top 3 bits (of 4) from port B of cell top.$flatten\spi_mux_I.$and$/build/gateware/icE1usb/rtl/sr_btn_if.v:229$3232 ($and). Removed top 3 bits (of 4) from port Y of cell top.$flatten\spi_mux_I.$and$/build/gateware/icE1usb/rtl/sr_btn_if.v:229$3232 ($and). Removed top 1 bits (of 3) from port B of cell top.$flatten\spi_mux_I.$eq$/build/gateware/icE1usb/rtl/sr_btn_if.v:229$3231 ($eq). Removed top 28 bits (of 32) from port A of cell top.$flatten\spi_mux_I.$and$/build/gateware/icE1usb/rtl/sr_btn_if.v:216$3228 ($and). Removed top 28 bits (of 32) from port Y of cell top.$flatten\spi_mux_I.$and$/build/gateware/icE1usb/rtl/sr_btn_if.v:216$3228 ($and). Removed top 28 bits (of 32) from port B of cell top.$flatten\spi_mux_I.$and$/build/gateware/icE1usb/rtl/sr_btn_if.v:216$3228 ($and). Removed top 31 bits (of 32) from port B of cell top.$flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:216$3227 ($add). Removed top 28 bits (of 32) from port Y of cell top.$flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:216$3227 ($add). Removed top 2 bits (of 3) from port B of cell top.$flatten\spi_mux_I.$eq$/build/gateware/icE1usb/rtl/sr_btn_if.v:198$3221 ($eq). Removed top 29 bits (of 32) from mux cell top.$flatten\spi_mux_I.$ternary$/build/gateware/icE1usb/rtl/sr_btn_if.v:144$3210 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\sys_mgr_I.$add$/build/gateware/icE1usb/rtl/sysmgr.v:80$1720 ($add). Removed top 28 bits (of 32) from port Y of cell top.$flatten\sys_mgr_I.$add$/build/gateware/icE1usb/rtl/sysmgr.v:80$1720 ($add). Removed top 1 bits (of 4) from port Y of cell top.$flatten\soc_I.\e1_buf_I.$or$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5344 ($or). Removed top 1 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_buf_I.$or$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5344 ($or). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\e1_buf_I.$or$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5344 ($or). Removed top 1 bits (of 6) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:99$205 ($sub). Removed top 1 bits (of 4) from port Y of cell top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5341 ($shl). Removed top 1 bits (of 4) from port Y of cell top.$flatten\soc_I.\e1_buf_I.$and$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5343 ($and). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\e1_buf_I.$and$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5343 ($and). Removed top 1 bits (of 4) from port Y of cell top.$flatten\soc_I.\e1_buf_I.$not$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5342 ($not). Removed top 1 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_buf_I.$not$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5342 ($not). Removed top 1 bits (of 4) from port Y of cell top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5340 ($shl). Removed top 16 bits (of 32) from wire top.$flatten\blinker_I.$add$/build/gateware/icE1usb/rtl/led_blinker.v:57$1590_Y. Removed top 19 bits (of 32) from wire top.$flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5244_Y. Removed top 19 bits (of 32) from wire top.$flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5245_Y. Removed top 23 bits (of 32) from wire top.$flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4343_Y. Removed top 23 bits (of 32) from wire top.$flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4341_Y. Removed top 1 bits (of 13) from wire top.$flatten\gps_uart_I.\uart_tx_I.$0\div_cnt[12:0]. Removed top 1 bits (of 10) from wire top.$flatten\gps_uart_I.\uart_tx_I.$0\shift[9:0]. Removed top 1 bits (of 10) from wire top.$flatten\gps_uart_I.\uart_tx_I.$procmux$12454_Y. Removed top 19 bits (of 32) from wire top.$flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5263_Y. Removed top 27 bits (of 32) from wire top.$flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5266_Y. Removed top 23 bits (of 32) from wire top.$flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4343_Y. Removed top 23 bits (of 32) from wire top.$flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4341_Y. Removed top 27 bits (of 32) from wire top.$flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:133$5212_Y. Removed top 28 bits (of 32) from wire top.$flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:143$5217_Y. Removed top 24 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3507_EN[31:0]$3514. Removed top 16 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3508_DATA[31:0]$3516. Removed top 8 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3509_DATA[31:0]$3519. Removed top 8 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3509_EN[31:0]$3520. Removed top 24 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3507_DATA. Removed top 16 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3508_DATA. Removed top 8 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3509_DATA. Removed top 16 bits (of 32) from wire top.$flatten\soc_I.\cpu_I.$2\mem_rdata_word[31:0]. Removed top 24 bits (of 32) from wire top.$flatten\soc_I.\cpu_I.$3\mem_rdata_word[31:0]. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4211_Y. Removed top 2 bits (of 6) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\clock_I.$procmux$15967_Y. Removed top 2 bits (of 6) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\clock_I.$procmux$15970_Y. Removed top 26 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\clock_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:42$16_Y. Removed top 29 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$33_Y. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$38_Y. Removed top 28 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$43_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$116_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$120_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$124_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$128_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$12_Y. Removed top 3 bits (of 16) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bus_rd_rx_status. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:124$215_Y. Removed top 28 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:194$230_Y. Removed top 28 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:194$232_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$12_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$add$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:120$461_Y. Removed top 3 bits (of 16) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bus_rd_tx_status. Removed top 1 bits (of 4) from wire top.$flatten\soc_I.\e1_buf_I.$and$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5343_Y. Removed top 1 bits (of 4) from wire top.$flatten\soc_I.\e1_buf_I.$not$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5342_Y. Removed top 1 bits (of 4) from wire top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5340_Y. Removed top 1 bits (of 4) from wire top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5341_Y. Removed top 18 bits (of 32) from wire top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$5038_Y. Removed top 23 bits (of 32) from wire top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$5042_Y. Removed top 19 bits (of 32) from wire top.$flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$5052_Y. Removed top 18 bits (of 32) from wire top.$flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:155$5040_Y. Removed top 23 bits (of 32) from wire top.$flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:159$5044_Y. Removed top 20 bits (of 32) from wire top.$flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:176$5053_Y. Removed top 19 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5244_Y. Removed top 19 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5245_Y. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5248_Y. Removed top 23 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4343_Y. Removed top 23 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4341_Y. Removed top 1 bits (of 13) from wire top.$flatten\soc_I.\uart_I.\uart_tx_I.$0\div_cnt[12:0]. Removed top 1 bits (of 10) from wire top.$flatten\soc_I.\uart_I.\uart_tx_I.$procmux$12454_Y. Removed top 19 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5263_Y. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5266_Y. Removed top 23 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4343_Y. Removed top 23 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4341_Y. Removed top 3 bits (of 4) from wire top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12204_Y. Removed top 28 bits (of 32) from wire top.$flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1339_Y. Removed top 29 bits (of 32) from wire top.$flatten\soc_I.\usb_I.\rx_pkt_I.\crc_5_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4970_Y. Removed top 1 bits (of 4) from wire top.$flatten\soc_I.\usb_I.\trans_I.$procmux$11903_Y. Removed top 29 bits (of 32) from wire top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1509_Y. Removed top 29 bits (of 32) from wire top.$flatten\soc_I.\usb_I.\tx_ll_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1511_Y. Removed top 28 bits (of 32) from wire top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1548_Y. Removed top 21 bits (of 32) from wire top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1571_Y. Removed top 1 bits (of 8) from wire top.$flatten\soc_I.\usb_I.\tx_pkt_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:172$1554_Y. Removed top 21 bits (of 32) from wire top.$flatten\soc_I.\usb_I.\tx_pkt_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1570_Y. Removed top 28 bits (of 32) from wire top.$flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:216$3227_Y. Removed top 29 bits (of 32) from wire top.$flatten\spi_mux_I.$ternary$/build/gateware/icE1usb/rtl/sr_btn_if.v:144$3210_Y. Removed top 28 bits (of 32) from wire top.$flatten\sys_mgr_I.$add$/build/gateware/icE1usb/rtl/sysmgr.v:80$1720_Y. Removed top 4 bits (of 8) from wire top.tick_e1. 75.14. Executing PEEPOPT pass (run peephole optimizers). 75.15. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 165 unused wires. <suppressed ~1 debug messages> 75.16. Executing SHARE pass (SAT-based resource sharing). 75.17. Executing TECHMAP pass (map to technology primitives). 75.17.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/cmp2lut.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 75.17.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~88 debug messages> 75.18. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~3 debug messages> 75.19. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 3 unused wires. <suppressed ~1 debug messages> 75.20. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module top: creating $macc model for $flatten\blinker_I.$add$/build/gateware/icE1usb/rtl/led_blinker.v:57$1590 ($add). creating $macc model for $flatten\blinker_I.$add$/build/gateware/icE1usb/rtl/led_blinker.v:66$1594 ($add). creating $macc model for $flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5244 ($sub). creating $macc model for $flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5245 ($sub). creating $macc model for $flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5248 ($sub). creating $macc model for $flatten\gps_uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4396 ($add). creating $macc model for $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4343 ($add). creating $macc model for $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4326 ($add). creating $macc model for $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4341 ($add). creating $macc model for $flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5263 ($sub). creating $macc model for $flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5266 ($sub). creating $macc model for $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4343 ($add). creating $macc model for $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4326 ($add). creating $macc model for $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4341 ($add). creating $macc model for $flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:133$5212 ($add). creating $macc model for $flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:143$5217 ($add). creating $macc model for $flatten\misc_I.\dfu_I.$add$/build/gateware/common/rtl/dfu_helper.v:113$4291 ($add). creating $macc model for $flatten\misc_I.\dfu_I.\btn_flt_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$5187 ($add). creating $macc model for $flatten\misc_I.\pdm_clk_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4281 ($add). creating $macc model for $flatten\misc_I.\pdm_clk_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4282 ($add). creating $macc model for $flatten\misc_I.\pdm_clk_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4281 ($add). creating $macc model for $flatten\misc_I.\pdm_clk_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4282 ($add). creating $macc model for $flatten\misc_I.\pdm_e1_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4277 ($add). creating $macc model for $flatten\misc_I.\pdm_e1_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4277 ($add). creating $macc model for $flatten\misc_I.\pps_flt_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4312 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1210$4267 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1296$4075 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1539$4152 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1548$4153 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1785$4197 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1848$4222 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1210$4266 ($sub). creating $macc model for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4211 ($sub). creating $macc model for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4218 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\clock_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:42$16 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$33 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$38 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$43 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$116 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$120 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$124 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$128 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$57 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:54$152 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:62$161 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:56$156 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:64$165 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx.v:170$4567 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx.v:171$4568 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:115$213 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:124$215 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:194$230 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:99$205 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$add$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:120$461 ($add). creating $macc model for $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$5038 ($add). creating $macc model for $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$5042 ($add). creating $macc model for $flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$5052 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5244 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5245 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5248 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4396 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4343 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4326 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4341 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5263 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5266 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4343 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4326 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4341 ($add). creating $macc model for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:540$3497 ($add). creating $macc model for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:623$3478 ($add). creating $macc model for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:632$3482 ($add). creating $macc model for $flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1339 ($sub). creating $macc model for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:179$1419 ($add). creating $macc model for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:415$1480 ($add). creating $macc model for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:429$1489 ($add). creating $macc model for $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:258$1436 ($sub). creating $macc model for $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:425$1486 ($sub). creating $macc model for $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1505 ($add). creating $macc model for $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1509 ($add). creating $macc model for $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1548 ($sub). creating $macc model for $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1571 ($sub). creating $macc model for $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:216$3227 ($add). creating $macc model for $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:229$3233 ($add). creating $macc model for $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:246$3237 ($add). creating $macc model for $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:247$3240 ($add). creating $macc model for $flatten\sys_mgr_I.$add$/build/gateware/icE1usb/rtl/sysmgr.v:80$1720 ($add). merging $macc model for $flatten\misc_I.\pdm_clk_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4281 into $flatten\misc_I.\pdm_clk_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4282. merging $macc model for $flatten\misc_I.\pdm_clk_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4281 into $flatten\misc_I.\pdm_clk_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4282. creating $alu model for $macc $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:246$3237. creating $alu model for $macc $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:229$3233. creating $alu model for $macc $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:216$3227. creating $alu model for $macc $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1571. creating $alu model for $macc $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1548. creating $alu model for $macc $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1509. creating $alu model for $macc $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1505. creating $alu model for $macc $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:425$1486. creating $alu model for $macc $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:258$1436. creating $alu model for $macc $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:429$1489. creating $alu model for $macc $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:415$1480. creating $alu model for $macc $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:179$1419. creating $alu model for $macc $flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1339. creating $alu model for $macc $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:632$3482. creating $alu model for $macc $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:623$3478. creating $alu model for $macc $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:540$3497. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4341. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4326. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4343. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5266. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5263. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4341. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4326. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4343. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4396. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5248. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5245. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5244. creating $alu model for $macc $flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$5052. creating $alu model for $macc $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$5042. creating $alu model for $macc $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$5038. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$add$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:120$461. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:99$205. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:194$230. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:124$215. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:115$213. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx.v:171$4568. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx.v:170$4567. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:64$165. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:56$156. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:62$161. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:54$152. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$57. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$128. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$124. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$120. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$116. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$43. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$38. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$33. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\clock_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:42$16. creating $alu model for $macc $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4218. creating $alu model for $macc $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4211. creating $alu model for $macc $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1210$4266. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1848$4222. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1785$4197. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1548$4153. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1539$4152. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1296$4075. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1210$4267. creating $alu model for $macc $flatten\misc_I.\pps_flt_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4312. creating $alu model for $macc $flatten\misc_I.\pdm_e1_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4277. creating $alu model for $macc $flatten\misc_I.\pdm_e1_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4277. creating $alu model for $macc $flatten\misc_I.\pdm_clk_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4282. creating $alu model for $macc $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:247$3240. creating $alu model for $macc $flatten\misc_I.\pdm_clk_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4282. creating $alu model for $macc $flatten\sys_mgr_I.$add$/build/gateware/icE1usb/rtl/sysmgr.v:80$1720. creating $alu model for $macc $flatten\misc_I.\dfu_I.\btn_flt_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$5187. creating $alu model for $macc $flatten\misc_I.\dfu_I.$add$/build/gateware/common/rtl/dfu_helper.v:113$4291. creating $alu model for $macc $flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:143$5217. creating $alu model for $macc $flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:133$5212. creating $alu model for $macc $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4341. creating $alu model for $macc $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4326. creating $alu model for $macc $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4343. creating $alu model for $macc $flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5266. creating $alu model for $macc $flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5263. creating $alu model for $macc $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4341. creating $alu model for $macc $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4326. creating $alu model for $macc $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4343. creating $alu model for $macc $flatten\gps_uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4396. creating $alu model for $macc $flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5248. creating $alu model for $macc $flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5245. creating $alu model for $macc $flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5244. creating $alu model for $macc $flatten\blinker_I.$add$/build/gateware/icE1usb/rtl/led_blinker.v:66$1594. creating $alu model for $macc $flatten\blinker_I.$add$/build/gateware/icE1usb/rtl/led_blinker.v:57$1590. creating $alu model for $flatten\soc_I.\cpu_I.$ge$/build/gateware/common/rtl/picorv32.v:1814$4203 ($ge): new $alu creating $alu model for $flatten\soc_I.\cpu_I.$lt$/build/gateware/common/rtl/picorv32.v:1212$4270 ($lt): new $alu creating $alu model for $flatten\soc_I.\cpu_I.$lt$/build/gateware/common/rtl/picorv32.v:1213$4271 ($lt): merged with $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1210$4266. creating $alu model for $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1211$4269 ($eq): merged with $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1210$4266. creating $alu cell for $flatten\soc_I.\cpu_I.$ge$/build/gateware/common/rtl/picorv32.v:1814$4203: $auto$alumacc.cc:485:replace_alu$24989 creating $alu cell for $flatten\blinker_I.$add$/build/gateware/icE1usb/rtl/led_blinker.v:57$1590: $auto$alumacc.cc:485:replace_alu$24998 creating $alu cell for $flatten\blinker_I.$add$/build/gateware/icE1usb/rtl/led_blinker.v:66$1594: $auto$alumacc.cc:485:replace_alu$25001 creating $alu cell for $flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5244: $auto$alumacc.cc:485:replace_alu$25004 creating $alu cell for $flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5245: $auto$alumacc.cc:485:replace_alu$25007 creating $alu cell for $flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5248: $auto$alumacc.cc:485:replace_alu$25010 creating $alu cell for $flatten\gps_uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4396: $auto$alumacc.cc:485:replace_alu$25013 creating $alu cell for $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4343: $auto$alumacc.cc:485:replace_alu$25016 creating $alu cell for $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4326: $auto$alumacc.cc:485:replace_alu$25019 creating $alu cell for $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4341: $auto$alumacc.cc:485:replace_alu$25022 creating $alu cell for $flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5263: $auto$alumacc.cc:485:replace_alu$25025 creating $alu cell for $flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5266: $auto$alumacc.cc:485:replace_alu$25028 creating $alu cell for $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4343: $auto$alumacc.cc:485:replace_alu$25031 creating $alu cell for $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4326: $auto$alumacc.cc:485:replace_alu$25034 creating $alu cell for $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4341: $auto$alumacc.cc:485:replace_alu$25037 creating $alu cell for $flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:133$5212: $auto$alumacc.cc:485:replace_alu$25040 creating $alu cell for $flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:143$5217: $auto$alumacc.cc:485:replace_alu$25043 creating $alu cell for $flatten\misc_I.\dfu_I.$add$/build/gateware/common/rtl/dfu_helper.v:113$4291: $auto$alumacc.cc:485:replace_alu$25046 creating $alu cell for $flatten\misc_I.\dfu_I.\btn_flt_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$5187: $auto$alumacc.cc:485:replace_alu$25049 creating $alu cell for $flatten\sys_mgr_I.$add$/build/gateware/icE1usb/rtl/sysmgr.v:80$1720: $auto$alumacc.cc:485:replace_alu$25052 creating $alu cell for $flatten\misc_I.\pdm_clk_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4282: $auto$alumacc.cc:485:replace_alu$25055 creating $alu cell for $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:247$3240: $auto$alumacc.cc:485:replace_alu$25058 creating $alu cell for $flatten\misc_I.\pdm_clk_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4282: $auto$alumacc.cc:485:replace_alu$25061 creating $alu cell for $flatten\misc_I.\pdm_e1_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4277: $auto$alumacc.cc:485:replace_alu$25064 creating $alu cell for $flatten\misc_I.\pdm_e1_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4277: $auto$alumacc.cc:485:replace_alu$25067 creating $alu cell for $flatten\misc_I.\pps_flt_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4312: $auto$alumacc.cc:485:replace_alu$25070 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1296$4075: $auto$alumacc.cc:485:replace_alu$25073 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1539$4152: $auto$alumacc.cc:485:replace_alu$25076 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1548$4153: $auto$alumacc.cc:485:replace_alu$25079 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1785$4197: $auto$alumacc.cc:485:replace_alu$25082 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1848$4222: $auto$alumacc.cc:485:replace_alu$25085 creating $alu cell for $flatten\soc_I.\cpu_I.$lt$/build/gateware/common/rtl/picorv32.v:1212$4270: $auto$alumacc.cc:485:replace_alu$25088 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1210$4267: $auto$alumacc.cc:485:replace_alu$25095 creating $alu cell for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1210$4266, $flatten\soc_I.\cpu_I.$lt$/build/gateware/common/rtl/picorv32.v:1213$4271, $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1211$4269: $auto$alumacc.cc:485:replace_alu$25098 creating $alu cell for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4211: $auto$alumacc.cc:485:replace_alu$25105 creating $alu cell for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4218: $auto$alumacc.cc:485:replace_alu$25108 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\clock_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:42$16: $auto$alumacc.cc:485:replace_alu$25111 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$33: $auto$alumacc.cc:485:replace_alu$25114 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$38: $auto$alumacc.cc:485:replace_alu$25117 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$43: $auto$alumacc.cc:485:replace_alu$25120 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$116: $auto$alumacc.cc:485:replace_alu$25123 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$120: $auto$alumacc.cc:485:replace_alu$25126 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$124: $auto$alumacc.cc:485:replace_alu$25129 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$128: $auto$alumacc.cc:485:replace_alu$25132 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$57: $auto$alumacc.cc:485:replace_alu$25135 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:54$152: $auto$alumacc.cc:485:replace_alu$25138 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:62$161: $auto$alumacc.cc:485:replace_alu$25141 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:56$156: $auto$alumacc.cc:485:replace_alu$25144 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\filter_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:64$165: $auto$alumacc.cc:485:replace_alu$25147 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx.v:170$4567: $auto$alumacc.cc:485:replace_alu$25150 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx.v:171$4568: $auto$alumacc.cc:485:replace_alu$25153 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:115$213: $auto$alumacc.cc:485:replace_alu$25156 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:124$215: $auto$alumacc.cc:485:replace_alu$25159 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:194$230: $auto$alumacc.cc:485:replace_alu$25162 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:99$205: $auto$alumacc.cc:485:replace_alu$25165 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\hdb3_I.$add$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:120$461: $auto$alumacc.cc:485:replace_alu$25168 creating $alu cell for $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$5038: $auto$alumacc.cc:485:replace_alu$25171 creating $alu cell for $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$5042: $auto$alumacc.cc:485:replace_alu$25174 creating $alu cell for $flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$5052: $auto$alumacc.cc:485:replace_alu$25177 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5244: $auto$alumacc.cc:485:replace_alu$25180 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5245: $auto$alumacc.cc:485:replace_alu$25183 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5248: $auto$alumacc.cc:485:replace_alu$25186 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4396: $auto$alumacc.cc:485:replace_alu$25189 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4343: $auto$alumacc.cc:485:replace_alu$25192 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4326: $auto$alumacc.cc:485:replace_alu$25195 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4341: $auto$alumacc.cc:485:replace_alu$25198 creating $alu cell for $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5263: $auto$alumacc.cc:485:replace_alu$25201 creating $alu cell for $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5266: $auto$alumacc.cc:485:replace_alu$25204 creating $alu cell for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4343: $auto$alumacc.cc:485:replace_alu$25207 creating $alu cell for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4326: $auto$alumacc.cc:485:replace_alu$25210 creating $alu cell for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4341: $auto$alumacc.cc:485:replace_alu$25213 creating $alu cell for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:540$3497: $auto$alumacc.cc:485:replace_alu$25216 creating $alu cell for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:623$3478: $auto$alumacc.cc:485:replace_alu$25219 creating $alu cell for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:632$3482: $auto$alumacc.cc:485:replace_alu$25222 creating $alu cell for $flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1339: $auto$alumacc.cc:485:replace_alu$25225 creating $alu cell for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:179$1419: $auto$alumacc.cc:485:replace_alu$25228 creating $alu cell for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:415$1480: $auto$alumacc.cc:485:replace_alu$25231 creating $alu cell for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:429$1489: $auto$alumacc.cc:485:replace_alu$25234 creating $alu cell for $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:258$1436: $auto$alumacc.cc:485:replace_alu$25237 creating $alu cell for $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:425$1486: $auto$alumacc.cc:485:replace_alu$25240 creating $alu cell for $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1505: $auto$alumacc.cc:485:replace_alu$25243 creating $alu cell for $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1509: $auto$alumacc.cc:485:replace_alu$25246 creating $alu cell for $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1548: $auto$alumacc.cc:485:replace_alu$25249 creating $alu cell for $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1571: $auto$alumacc.cc:485:replace_alu$25252 creating $alu cell for $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:216$3227: $auto$alumacc.cc:485:replace_alu$25255 creating $alu cell for $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:229$3233: $auto$alumacc.cc:485:replace_alu$25258 creating $alu cell for $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:246$3237: $auto$alumacc.cc:485:replace_alu$25261 created 87 $alu and 0 $macc cells. 75.21. Executing OPT pass (performing simple optimizations). 75.21.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.21.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~24 debug messages> Removed a total of 8 cells. 75.21.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~204 debug messages> 75.21.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13719: { \soc_I.cpu_I.cpu_state [1] \soc_I.cpu_I.cpu_state [2] $auto$opt_reduce.cc:134:opt_mux$25265 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13930: { \soc_I.cpu_I.cpu_state [2] \soc_I.cpu_I.cpu_state [4] $auto$opt_reduce.cc:134:opt_mux$25267 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$14916: { $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:364$3670_Y $flatten\soc_I.\cpu_I.$procmux$14926_CMP $auto$opt_reduce.cc:134:opt_mux$25269 } Optimizing cells in module \top. Performed a total of 3 changes. 75.21.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~3 debug messages> Removed a total of 1 cells. 75.21.6. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 1-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$23432 ($dff) from module top. Setting constant 1-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$23432 ($dff) from module top. Setting constant 1-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$23432 ($dff) from module top. Setting constant 1-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$23432 ($dff) from module top. Setting constant 1-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$23432 ($dff) from module top. Setting constant 1-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$23432 ($dff) from module top. Setting constant 1-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$23432 ($dff) from module top. Setting constant 1-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$23432 ($dff) from module top. Setting constant 1-bit at position 8 on $flatten\soc_I.\bram_I.$procdff$23432 ($dff) from module top. Setting constant 1-bit at position 9 on $flatten\soc_I.\bram_I.$procdff$23432 ($dff) from module top. Setting constant 1-bit at position 10 on $flatten\soc_I.\bram_I.$procdff$23432 ($dff) from module top. Setting constant 1-bit at position 11 on $flatten\soc_I.\bram_I.$procdff$23432 ($dff) from module top. Setting constant 1-bit at position 12 on $flatten\soc_I.\bram_I.$procdff$23432 ($dff) from module top. Setting constant 1-bit at position 13 on $flatten\soc_I.\bram_I.$procdff$23432 ($dff) from module top. Setting constant 1-bit at position 14 on $flatten\soc_I.\bram_I.$procdff$23432 ($dff) from module top. Setting constant 1-bit at position 15 on $flatten\soc_I.\bram_I.$procdff$23432 ($dff) from module top. Setting constant 1-bit at position 16 on $flatten\soc_I.\bram_I.$procdff$23432 ($dff) from module top. Setting constant 1-bit at position 17 on $flatten\soc_I.\bram_I.$procdff$23432 ($dff) from module top. Setting constant 1-bit at position 18 on $flatten\soc_I.\bram_I.$procdff$23432 ($dff) from module top. Setting constant 1-bit at position 19 on $flatten\soc_I.\bram_I.$procdff$23432 ($dff) from module top. Setting constant 1-bit at position 20 on $flatten\soc_I.\bram_I.$procdff$23432 ($dff) from module top. Setting constant 1-bit at position 21 on $flatten\soc_I.\bram_I.$procdff$23432 ($dff) from module top. Setting constant 1-bit at position 22 on $flatten\soc_I.\bram_I.$procdff$23432 ($dff) from module top. Setting constant 1-bit at position 23 on $flatten\soc_I.\bram_I.$procdff$23432 ($dff) from module top. Setting constant 1-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$23429 ($dff) from module top. Setting constant 1-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$23429 ($dff) from module top. Setting constant 1-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$23429 ($dff) from module top. Setting constant 1-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$23429 ($dff) from module top. Setting constant 1-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$23429 ($dff) from module top. Setting constant 1-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$23429 ($dff) from module top. Setting constant 1-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$23429 ($dff) from module top. Setting constant 1-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$23429 ($dff) from module top. Setting constant 1-bit at position 8 on $flatten\soc_I.\bram_I.$procdff$23429 ($dff) from module top. Setting constant 1-bit at position 9 on $flatten\soc_I.\bram_I.$procdff$23429 ($dff) from module top. Setting constant 1-bit at position 10 on $flatten\soc_I.\bram_I.$procdff$23429 ($dff) from module top. Setting constant 1-bit at position 11 on $flatten\soc_I.\bram_I.$procdff$23429 ($dff) from module top. Setting constant 1-bit at position 12 on $flatten\soc_I.\bram_I.$procdff$23429 ($dff) from module top. Setting constant 1-bit at position 13 on $flatten\soc_I.\bram_I.$procdff$23429 ($dff) from module top. Setting constant 1-bit at position 14 on $flatten\soc_I.\bram_I.$procdff$23429 ($dff) from module top. Setting constant 1-bit at position 15 on $flatten\soc_I.\bram_I.$procdff$23429 ($dff) from module top. Setting constant 1-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$23426 ($dff) from module top. Setting constant 1-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$23426 ($dff) from module top. Setting constant 1-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$23426 ($dff) from module top. Setting constant 1-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$23426 ($dff) from module top. Setting constant 1-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$23426 ($dff) from module top. Setting constant 1-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$23426 ($dff) from module top. Setting constant 1-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$23426 ($dff) from module top. Setting constant 1-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$23426 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\i2c_I.$procdff$23480 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\i2c_I.$procdff$23480 ($dff) from module top. Setting constant 0-bit at position 2 on $flatten\i2c_I.$procdff$23480 ($dff) from module top. Setting constant 0-bit at position 3 on $flatten\i2c_I.$procdff$23480 ($dff) from module top. Setting constant 0-bit at position 4 on $flatten\i2c_I.$procdff$23480 ($dff) from module top. Setting constant 0-bit at position 5 on $flatten\i2c_I.$procdff$23480 ($dff) from module top. Setting constant 0-bit at position 6 on $flatten\i2c_I.$procdff$23480 ($dff) from module top. Setting constant 0-bit at position 7 on $flatten\i2c_I.$procdff$23480 ($dff) from module top. Setting constant 0-bit at position 8 on $flatten\i2c_I.$procdff$23480 ($dff) from module top. Setting constant 0-bit at position 9 on $flatten\i2c_I.$procdff$23480 ($dff) from module top. Setting constant 0-bit at position 10 on $flatten\i2c_I.$procdff$23480 ($dff) from module top. Setting constant 0-bit at position 11 on $flatten\i2c_I.$procdff$23480 ($dff) from module top. Setting constant 0-bit at position 12 on $flatten\i2c_I.$procdff$23480 ($dff) from module top. Setting constant 0-bit at position 13 on $flatten\i2c_I.$procdff$23480 ($dff) from module top. Setting constant 0-bit at position 14 on $flatten\i2c_I.$procdff$23480 ($dff) from module top. Setting constant 0-bit at position 15 on $flatten\i2c_I.$procdff$23480 ($dff) from module top. Setting constant 0-bit at position 16 on $flatten\i2c_I.$procdff$23480 ($dff) from module top. Setting constant 0-bit at position 17 on $flatten\i2c_I.$procdff$23480 ($dff) from module top. Setting constant 0-bit at position 18 on $flatten\i2c_I.$procdff$23480 ($dff) from module top. Setting constant 0-bit at position 19 on $flatten\i2c_I.$procdff$23480 ($dff) from module top. Setting constant 0-bit at position 20 on $flatten\i2c_I.$procdff$23480 ($dff) from module top. Setting constant 1-bit at position 9 on $auto$opt_dff.cc:764:run$24879 ($adffe) from module top. Adding SRST signal on $auto$opt_dff.cc:764:run$24579 ($dffe) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14969_Y, Q = \soc_I.cpu_I.mem_valid, rval = 1'0). Adding SRST signal on $auto$opt_dff.cc:764:run$24562 ($dffe) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14916_Y, Q = \soc_I.cpu_I.mem_state, rval = 2'00). Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 16 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 17 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 18 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 19 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 20 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 21 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 22 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 23 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$24331 ($sdff) from module top. Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$24331 ($sdff) from module top. Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$24331 ($sdff) from module top. Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$24331 ($sdff) from module top. Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$24331 ($sdff) from module top. Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$24331 ($sdff) from module top. Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$24331 ($sdff) from module top. Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$24331 ($sdff) from module top. Setting constant 0-bit at position 16 on $auto$opt_dff.cc:702:run$24331 ($sdff) from module top. Setting constant 0-bit at position 17 on $auto$opt_dff.cc:702:run$24331 ($sdff) from module top. Setting constant 0-bit at position 18 on $auto$opt_dff.cc:702:run$24331 ($sdff) from module top. Setting constant 0-bit at position 19 on $auto$opt_dff.cc:702:run$24331 ($sdff) from module top. Setting constant 0-bit at position 20 on $auto$opt_dff.cc:702:run$24331 ($sdff) from module top. Setting constant 0-bit at position 21 on $auto$opt_dff.cc:702:run$24331 ($sdff) from module top. Setting constant 0-bit at position 22 on $auto$opt_dff.cc:702:run$24331 ($sdff) from module top. Setting constant 0-bit at position 23 on $auto$opt_dff.cc:702:run$24331 ($sdff) from module top. 75.21.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 4 unused cells and 17 unused wires. <suppressed ~5 debug messages> 75.21.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.21.9. Rerunning OPT passes. (Maybe there is more to do..) 75.21.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~204 debug messages> 75.21.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 75.21.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.21.13. Executing OPT_DFF pass (perform DFF optimizations). 75.21.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.21.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.21.16. Finished OPT passes. (There is nothing left to do.) 75.22. Executing MEMORY pass. 75.22.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 75.22.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). Checking cell `$flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5467' in module `\top': merged $dff to cell. Checking cell `$flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5467' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3534' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3535' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3536' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3537' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5467' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5467' in module `\top': merged $dff to cell. Checking cell `$flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5466' in module `\top': merged data $dff to cell. Checking cell `$flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5466' in module `\top': merged data $dff to cell. Checking cell `$flatten\soc_I.\bram_I.$memrd$\mem$/build/gateware/common/rtl/soc_bram.v:32$3524' in module `\top': merged data $dff to cell. Checking cell `$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5466' in module `\top': merged data $dff to cell. Checking cell `$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5466' in module `\top': merged data $dff to cell. 75.22.3. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 25 unused cells and 30 unused wires. <suppressed ~26 debug messages> 75.22.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). Consolidating write ports of memory top.soc_I.bram_I.mem by address: New clock domain: posedge \blinker_I.clk Port 0 ($flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3534) has addr \soc_I.cpu_I.mem_addr [9:2]. Active bits: 00000000000000000000000011111111 Port 1 ($flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3535) has addr \soc_I.cpu_I.mem_addr [9:2]. Active bits: 00000000000000001111111100000000 Merging port 0 into this one. Active bits: 00000000000000001111111111111111 Port 2 ($flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3536) has addr \soc_I.cpu_I.mem_addr [9:2]. Active bits: 00000000111111110000000000000000 Merging port 1 into this one. Active bits: 00000000111111111111111111111111 Port 3 ($flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3537) has addr \soc_I.cpu_I.mem_addr [9:2]. Active bits: 11111111000000000000000000000000 Merging port 2 into this one. Active bits: 11111111111111111111111111111111 75.22.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.22.6. Executing MEMORY_COLLECT pass (generating $mem cells). Collecting $memrd, $memwr and $meminit for memory `\gps_uart_I.uart_rx_fifo_I.ram_I.ram' in module `\top': $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5467 ($memwr) $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5466 ($memrd) Collecting $memrd, $memwr and $meminit for memory `\gps_uart_I.uart_tx_fifo_I.ram_I.ram' in module `\top': $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5467 ($memwr) $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5466 ($memrd) Collecting $memrd, $memwr and $meminit for memory `\soc_I.bram_I.mem' in module `\top': $flatten\soc_I.\bram_I.$meminit$\mem$/build/gateware/common/rtl/soc_bram.v:0$3533 ($meminit) $flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3537 ($memwr) $flatten\soc_I.\bram_I.$memrd$\mem$/build/gateware/common/rtl/soc_bram.v:32$3524 ($memrd) Collecting $memrd, $memwr and $meminit for memory `\soc_I.uart_I.uart_rx_fifo_I.ram_I.ram' in module `\top': $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5467 ($memwr) $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5466 ($memrd) Collecting $memrd, $memwr and $meminit for memory `\soc_I.uart_I.uart_tx_fifo_I.ram_I.ram' in module `\top': $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5467 ($memwr) $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5466 ($memrd) 75.23. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.24. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). Processing top.gps_uart_I.uart_rx_fifo_I.ram_I.ram: Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512 Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #2 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=0 efficiency=100 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 2): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=3072 efficiency=25 Storing for later selection. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'max wports 0' not met. Selecting best of 4 rules: Efficiency for rule 4.3: efficiency=25, cells=4, acells=1 Efficiency for rule 4.2: efficiency=50, cells=2, acells=1 Efficiency for rule 4.1: efficiency=100, cells=1, acells=1 Efficiency for rule 1.1: efficiency=50, cells=2, acells=2 Selected rule 4.1 with efficiency 100. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Creating $__ICE40_RAM4K_M123 cell at grid position <0 0 0>: gps_uart_I.uart_rx_fifo_I.ram_I.ram.0.0.0 Processing top.gps_uart_I.uart_tx_fifo_I.ram_I.ram: Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512 Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #2 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=0 efficiency=100 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 2): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=3072 efficiency=25 Storing for later selection. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'max wports 0' not met. Selecting best of 4 rules: Efficiency for rule 4.3: efficiency=25, cells=4, acells=1 Efficiency for rule 4.2: efficiency=50, cells=2, acells=1 Efficiency for rule 4.1: efficiency=100, cells=1, acells=1 Efficiency for rule 1.1: efficiency=50, cells=2, acells=2 Selected rule 4.1 with efficiency 100. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Creating $__ICE40_RAM4K_M123 cell at grid position <0 0 0>: gps_uart_I.uart_tx_fifo_I.ram_I.ram.0.0.0 Processing top.soc_I.bram_I.mem: Properties: ports=2 bits=8192 rports=1 wports=1 dbits=32 abits=8 words=256 Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=0 efficiency=100 Storing for later selection. Checking rule #2 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=256 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=768 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 2): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=3072 efficiency=25 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1792 dwaste=0 bwaste=3584 waste=3584 efficiency=12 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=3584 efficiency=12 Storing for later selection. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=256 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=768 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1792 dwaste=0 bwaste=3584 waste=3584 efficiency=12 Rule for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=256 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=768 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1792 dwaste=0 bwaste=3584 waste=3584 efficiency=12 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'max wports 0' not met. Selecting best of 4 rules: Efficiency for rule 4.3: efficiency=12, cells=16, acells=1 Efficiency for rule 4.2: efficiency=25, cells=8, acells=1 Efficiency for rule 4.1: efficiency=50, cells=4, acells=1 Efficiency for rule 1.1: efficiency=100, cells=2, acells=1 Selected rule 1.1 with efficiency 100. Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Creating $__ICE40_RAM4K_M0 cell at grid position <0 0 0>: soc_I.bram_I.mem.0.0.0 Creating $__ICE40_RAM4K_M0 cell at grid position <1 0 0>: soc_I.bram_I.mem.1.0.0 Processing top.soc_I.uart_I.uart_rx_fifo_I.ram_I.ram: Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512 Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #2 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=0 efficiency=100 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 2): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=3072 efficiency=25 Storing for later selection. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'max wports 0' not met. Selecting best of 4 rules: Efficiency for rule 4.3: efficiency=25, cells=4, acells=1 Efficiency for rule 4.2: efficiency=50, cells=2, acells=1 Efficiency for rule 4.1: efficiency=100, cells=1, acells=1 Efficiency for rule 1.1: efficiency=50, cells=2, acells=2 Selected rule 4.1 with efficiency 100. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Creating $__ICE40_RAM4K_M123 cell at grid position <0 0 0>: soc_I.uart_I.uart_rx_fifo_I.ram_I.ram.0.0.0 Processing top.soc_I.uart_I.uart_tx_fifo_I.ram_I.ram: Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512 Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #2 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=0 efficiency=100 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 2): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=3072 efficiency=25 Storing for later selection. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'max wports 0' not met. Selecting best of 4 rules: Efficiency for rule 4.3: efficiency=25, cells=4, acells=1 Efficiency for rule 4.2: efficiency=50, cells=2, acells=1 Efficiency for rule 4.1: efficiency=100, cells=1, acells=1 Efficiency for rule 1.1: efficiency=50, cells=2, acells=2 Selected rule 4.1 with efficiency 100. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Creating $__ICE40_RAM4K_M123 cell at grid position <0 0 0>: soc_I.uart_I.uart_tx_fifo_I.ram_I.ram.0.0.0 75.25. Executing TECHMAP pass (map to technology primitives). 75.25.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/brams_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ICE40_RAM4K'. Generating RTLIL representation for module `\$__ICE40_RAM4K_M0'. Generating RTLIL representation for module `\$__ICE40_RAM4K_M123'. Successfully finished Verilog frontend. 75.25.2. Continuing TECHMAP pass. Using template $paramod\$__ICE40_RAM4K_M123\CFG_ABITS=9\CFG_DBITS=8\CLKPOL2=1\CLKPOL3=1 for cells of type $__ICE40_RAM4K_M123. Using template $paramod$b9e8582c288289ac723b215129f56c6fb55d152a\$__ICE40_RAM4K_M0 for cells of type $__ICE40_RAM4K_M0. Using template $paramod$4db28c01ad2f8fb3d28d8b45acd344e29c76a5e2\$__ICE40_RAM4K_M0 for cells of type $__ICE40_RAM4K_M0. Using template $paramod$7577afd8fd444532bbc3532c110d9d682708035f\$__ICE40_RAM4K for cells of type $__ICE40_RAM4K. Using template $paramod$604ec1e346c2dd44ad2f04f633da753d2abbf02c\$__ICE40_RAM4K for cells of type $__ICE40_RAM4K. Using template $paramod$66c3fa288a62dc560ce3ddd26d81551ab195105f\$__ICE40_RAM4K for cells of type $__ICE40_RAM4K. No more expansions possible. <suppressed ~211 debug messages> 75.26. Executing ICE40_BRAMINIT pass. Processing soc_I.usb_I.trans_I.mc_rom_I : usb_trans_mc.hex 75.27. Executing OPT pass (performing simple optimizations). 75.27.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~308 debug messages> 75.27.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.27.3. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23272 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$0\reg_sh[4:0] [1:0], Q = \soc_I.cpu_I.reg_sh [1:0]). 75.27.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 39 unused cells and 264 unused wires. <suppressed ~51 debug messages> 75.27.5. Rerunning OPT passes. (Removed registers in this run.) 75.27.6. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.27.7. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.27.8. Executing OPT_DFF pass (perform DFF optimizations). 75.27.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.27.10. Finished fast OPT passes. 75.28. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). 75.29. Executing OPT pass (performing simple optimizations). 75.29.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.29.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.29.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~185 debug messages> 75.29.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $techmap$techmap25300\soc_I.bram_I.mem.0.0.0.$reduce_or$/opt/fpga-toolchain/bin/../share/yosys/ice40/brams_map.v:222$25299: { $auto$wreduce.cc:454:run$24918 [7] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3508_EN[31:0]$3517 [15] } New input vector for $reduce_or cell $techmap$techmap25297\soc_I.bram_I.mem.1.0.0.$reduce_or$/opt/fpga-toolchain/bin/../share/yosys/ice40/brams_map.v:222$25296: { $auto$wreduce.cc:454:run$24921 [23] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3510_EN[31:0]$3523 [31] } Consolidated identical input bits for $mux cell $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1591: Old ports: A=16'1111111111111111, B=16'0000000000000000, Y=$flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1591_Y New ports: A=1'1, B=1'0, Y=$flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1591_Y [0] New connections: $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1591_Y [15:1] = { $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1591_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1591_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1591_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1591_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1591_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1591_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1591_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1591_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1591_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1591_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1591_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1591_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1591_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1591_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1591_Y [0] } Consolidated identical input bits for $mux cell $flatten\gps_uart_I.\uart_rx_I.\gf_I.$procmux$12302: Old ports: A=2'00, B=2'11, Y=$flatten\gps_uart_I.\uart_rx_I.\gf_I.$2\cnt_move[1:0] New ports: A=1'0, B=1'1, Y=$flatten\gps_uart_I.\uart_rx_I.\gf_I.$2\cnt_move[1:0] [0] New connections: $flatten\gps_uart_I.\uart_rx_I.\gf_I.$2\cnt_move[1:0] [1] = $flatten\gps_uart_I.\uart_rx_I.\gf_I.$2\cnt_move[1:0] [0] Consolidated identical input bits for $mux cell $flatten\i2c_I.\core_I.$procmux$15388: Old ports: A=4'1000, B=4'0000, Y=$flatten\i2c_I.\core_I.$procmux$15388_Y New ports: A=1'1, B=1'0, Y=$flatten\i2c_I.\core_I.$procmux$15388_Y [3] New connections: $flatten\i2c_I.\core_I.$procmux$15388_Y [2:0] = 3'000 Consolidated identical input bits for $mux cell $flatten\misc_I.\dfu_I.\btn_flt_I.$procmux$5641: Old ports: A=4'0000, B=4'1111, Y=$flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] New ports: A=1'0, B=1'1, Y=$flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] New connections: $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [3:1] = { $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] } Consolidated identical input bits for $mux cell $flatten\misc_I.\pps_flt_I.$procmux$12492: Old ports: A=2'00, B=2'11, Y=$flatten\misc_I.\pps_flt_I.$2\cnt_move[1:0] New ports: A=1'0, B=1'1, Y=$flatten\misc_I.\pps_flt_I.$2\cnt_move[1:0] [0] New connections: $flatten\misc_I.\pps_flt_I.$2\cnt_move[1:0] [1] = $flatten\misc_I.\pps_flt_I.$2\cnt_move[1:0] [0] Consolidated identical input bits for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13192: Old ports: A=\soc_I.cpu_I.mem_rdata_word, B={ \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15:0] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7:0] }, Y=$flatten\soc_I.\cpu_I.$procmux$13192_Y New ports: A=\soc_I.cpu_I.mem_rdata_word [31:8], B={ \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15:7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] }, Y=$flatten\soc_I.\cpu_I.$procmux$13192_Y [31:8] New connections: $flatten\soc_I.\cpu_I.$procmux$13192_Y [7:0] = \soc_I.cpu_I.mem_rdata_word [7:0] Consolidated identical input bits for $pmux cell $flatten\soc_I.\cpu_I.$procmux$15235: Old ports: A=\soc_I.cpu_I.reg_op2, B={ \soc_I.cpu_I.reg_op2 [15:0] \soc_I.cpu_I.reg_op2 [15:0] \soc_I.cpu_I.reg_op2 [7:0] \soc_I.cpu_I.reg_op2 [7:0] \soc_I.cpu_I.reg_op2 [7:0] \soc_I.cpu_I.reg_op2 [7:0] }, Y=\soc_I.cpu_I.mem_la_wdata New ports: A=\soc_I.cpu_I.reg_op2 [31:8], B={ \soc_I.cpu_I.reg_op2 [15:0] \soc_I.cpu_I.reg_op2 [15:0] \soc_I.cpu_I.reg_op2 [7:0] \soc_I.cpu_I.reg_op2 [7:0] }, Y=\soc_I.cpu_I.mem_la_wdata [31:8] New connections: \soc_I.cpu_I.mem_la_wdata [7:0] = \soc_I.cpu_I.reg_op2 [7:0] Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1192$4043: Old ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 2'00 }, B={ \soc_I.cpu_I.reg_out [31:1] 1'0 }, Y=\soc_I.cpu_I.next_pc New ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 1'0 }, B=\soc_I.cpu_I.reg_out [31:1], Y=\soc_I.cpu_I.next_pc [31:1] New connections: \soc_I.cpu_I.next_pc [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$4112: Old ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 2'00 }, B={ $auto$opt_expr.cc:205:group_cell_inputs$25366 1'0 }, Y=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$4112_Y New ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 1'0 }, B=$auto$opt_expr.cc:205:group_cell_inputs$25366, Y=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$4112_Y [31:1] New connections: $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$4112_Y [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1621$4165: Old ports: A={ \soc_I.cpu_I.reg_pc [31:2] 2'00 }, B=0, Y=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1621$4165_Y New ports: A=\soc_I.cpu_I.reg_pc [31:2], B=30'000000000000000000000000000000, Y=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1621$4165_Y [31:2] New connections: $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1621$4165_Y [1:0] = 2'00 Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:366$3686: Old ports: A={ \soc_I.cpu_I.reg_op1 [31:2] 2'00 }, B={ \soc_I.cpu_I.next_pc [31:2] 2'00 }, Y=\soc_I.cpu_I.mem_la_addr New ports: A=\soc_I.cpu_I.reg_op1 [31:2], B=\soc_I.cpu_I.next_pc [31:2], Y=\soc_I.cpu_I.mem_la_addr [31:2] New connections: \soc_I.cpu_I.mem_la_addr [1:0] = 2'00 Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3701: Old ports: A=4'0011, B=4'1100, Y=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3701_Y New ports: A=2'01, B=2'10, Y={ $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3701_Y [2] $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3701_Y [0] } New connections: { $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3701_Y [3] $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3701_Y [1] } = { $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3701_Y [2] $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3701_Y [0] } Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:601$3761: Old ports: A=2'11, B=2'00, Y=$flatten\soc_I.\cpu_I.$procmux$14922_Y New ports: A=1'1, B=1'0, Y=$flatten\soc_I.\cpu_I.$procmux$14922_Y [0] New connections: $flatten\soc_I.\cpu_I.$procmux$14922_Y [1] = $flatten\soc_I.\cpu_I.$procmux$14922_Y [0] Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$4631: Old ports: A={ 3'000 $auto$wreduce.cc:454:run$24939 [12] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_out_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_out_I.rd_empty $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_in_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_in_I.rd_empty 6'000000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.aligned $auto$wreduce.cc:454:run$24939 [0] }, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_out_I.stage[1].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_out_I.data[1] [8:7] 6'000000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_out_I.data[1] [6:0] }, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$4631_Y New ports: A={ 3'000 $auto$wreduce.cc:454:run$24939 [12] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_out_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_out_I.rd_empty $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_in_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_in_I.rd_empty 5'00000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.aligned $auto$wreduce.cc:454:run$24939 [0] }, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_out_I.stage[1].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_out_I.data[1] [8:7] 5'00000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_out_I.data[1] [6:0] }, Y={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$4631_Y [15:8] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$4631_Y [6:0] } New connections: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$4631_Y [7] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.\rx_I.\deframer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$12: Old ports: A=2'00, B=2'11, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [1:0] New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [0] New connections: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [1] = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [0] Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4591: Old ports: A={ 3'000 $auto$wreduce.cc:454:run$24945 [12] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bd_tx_out_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bd_tx_out_I.rd_empty $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bd_tx_in_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bd_tx_in_I.rd_empty 7'0000000 $auto$wreduce.cc:454:run$24945 [0] }, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bd_tx_out_I.stage[1].l_valid 8'00000000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bd_tx_out_I.data[1] }, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4591_Y New ports: A={ 1'0 $auto$wreduce.cc:454:run$24945 [12] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bd_tx_out_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bd_tx_out_I.rd_empty $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bd_tx_in_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bd_tx_in_I.rd_empty 6'000000 $auto$wreduce.cc:454:run$24945 [0] }, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bd_tx_out_I.stage[1].l_valid 5'00000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.bd_tx_out_I.data[1] }, Y={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4591_Y [15] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4591_Y [12:8] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4591_Y [6:0] } New connections: { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4591_Y [14:13] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4591_Y [7] } = 3'000 Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:167$4565: Old ports: A=5'00000, B=5'11001, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:167$4565_Y New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:167$4565_Y [0] New connections: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:167$4565_Y [4:1] = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:167$4565_Y [0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:167$4565_Y [0] 2'00 } Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:168$4566: Old ports: A=5'00000, B=5'11001, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:168$4566_Y New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:168$4566_Y [0] New connections: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:168$4566_Y [4:1] = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:168$4566_Y [0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:168$4566_Y [0] 2'00 } Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.\framer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$12: Old ports: A=2'00, B=2'11, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.framer_I.crc_I.state_upd_mux [1:0] New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.framer_I.crc_I.state_upd_mux [0] New connections: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.framer_I.crc_I.state_upd_mux [1] = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.framer_I.crc_I.state_upd_mux [0] Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_buf_I.$procmux$12447: Old ports: A=2'00, B=2'10, Y=\soc_I.e1_buf_I.t_nxt_chan New ports: A=1'0, B=1'1, Y=\soc_I.e1_buf_I.t_nxt_chan [1] New connections: \soc_I.e1_buf_I.t_nxt_chan [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:115$5020: Old ports: A=2'10, B=2'00, Y=$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5706_Y New ports: A=1'1, B=1'0, Y=$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5706_Y [1] New connections: $flatten\soc_I.\iobuf_I.\dma_I.$procmux$5706_Y [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:205$5070: Old ports: A=16'0000000000000000, B={ \soc_I.iobuf_I.dma_I.state [1] \soc_I.iobuf_I.dma_I.dir 1'0 \soc_I.iobuf_I.dma_I.len }, Y=\soc_I.iobuf_I.wb_rdata_dma [15:0] New ports: A=15'000000000000000, B={ \soc_I.iobuf_I.dma_I.state [1] \soc_I.iobuf_I.dma_I.dir \soc_I.iobuf_I.dma_I.len }, Y={ \soc_I.iobuf_I.wb_rdata_dma [15:14] \soc_I.iobuf_I.wb_rdata_dma [12:0] } New connections: \soc_I.iobuf_I.wb_rdata_dma [13] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$5138: Old ports: A=0, B={ \soc_I.e1_buf_I.wb_wdata_byte \soc_I.e1_buf_I.wb_wdata_byte \soc_I.e1_buf_I.wb_wdata_byte \soc_I.e1_buf_I.wb_wdata_byte }, Y=$flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$5138_Y New ports: A=8'00000000, B=\soc_I.e1_buf_I.wb_wdata_byte, Y=$flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$5138_Y [7:0] New connections: $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$5138_Y [31:8] = { $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$5138_Y [7:0] $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$5138_Y [7:0] $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$5138_Y [7:0] } Consolidated identical input bits for $mux cell $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procmux$12302: Old ports: A=2'00, B=2'11, Y=$flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$2\cnt_move[1:0] New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$2\cnt_move[1:0] [0] New connections: $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$2\cnt_move[1:0] [1] = $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$2\cnt_move[1:0] [0] Consolidated identical input bits for $mux cell $flatten\soc_I.\uart_I.\uart_tx_I.$procmux$12457: Old ports: A={ 1'1 \soc_I.uart_I.uart_tx_I.shift [9:1] }, B={ 1'1 \soc_I.uart_I.uart_tx_fifo_I.ram_I.rd_data 1'0 }, Y=$flatten\soc_I.\uart_I.\uart_tx_I.$0\shift[9:0] New ports: A=\soc_I.uart_I.uart_tx_I.shift [9:1], B={ \soc_I.uart_I.uart_tx_fifo_I.ram_I.rd_data 1'0 }, Y=$flatten\soc_I.\uart_I.\uart_tx_I.$0\shift[9:0] [8:0] New connections: $flatten\soc_I.\uart_I.\uart_tx_I.$0\shift[9:0] [9] = 1'1 Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\rx_pkt_I.\crc_16_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4957: Old ports: A=16'0000000000000000, B=16'1000000000000101, Y=\soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux New ports: A=1'0, B=1'1, Y=\soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux [0] New connections: \soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux [15:1] = { \soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux [0] 12'000000000000 \soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\rx_pkt_I.\crc_5_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4970: Old ports: A=3'000, B=3'101, Y=\soc_I.usb_I.rx_pkt_I.crc_5_I.state_upd_mux [2:0] New ports: A=1'0, B=1'1, Y=\soc_I.usb_I.rx_pkt_I.crc_5_I.state_upd_mux [0] New connections: \soc_I.usb_I.rx_pkt_I.crc_5_I.state_upd_mux [2:1] = { \soc_I.usb_I.rx_pkt_I.crc_5_I.state_upd_mux [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$procmux$11903: Old ports: A=3'000, B=3'110, Y=$auto$wreduce.cc:454:run$24970 [2:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:454:run$24970 [1] New connections: { $auto$wreduce.cc:454:run$24970 [2] $auto$wreduce.cc:454:run$24970 [0] } = { $auto$wreduce.cc:454:run$24970 [1] 1'0 } Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$procmux$11906: Old ports: A={ 1'0 $auto$wreduce.cc:454:run$24970 [2:0] }, B=4'0100, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11906_Y New ports: A=$auto$wreduce.cc:454:run$24970 [2:0], B=3'100, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11906_Y [2:0] New connections: $flatten\soc_I.\usb_I.\trans_I.$procmux$11906_Y [3] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_trans.v:340$1450: Old ports: A={ 8'00000000 \soc_I.usb_I.trans_I.ep_data_toggle \soc_I.usb_I.trans_I.ep_bd_idx_nxt \soc_I.usb_I.trans_I.ep_bd_ctrl \soc_I.usb_I.trans_I.ep_bd_dual 1'0 \soc_I.usb_I.trans_I.ep_type }, B={ \soc_I.usb_I.trans_I.bd_state \soc_I.usb_I.trans_I.trans_is_setup 2'00 \soc_I.usb_I.trans_I.xfer_length }, Y=\soc_I.usb_I.ep_status_I.p_din_0 New ports: A={ 6'000000 \soc_I.usb_I.trans_I.ep_data_toggle \soc_I.usb_I.trans_I.ep_bd_idx_nxt \soc_I.usb_I.trans_I.ep_bd_ctrl \soc_I.usb_I.trans_I.ep_bd_dual 1'0 \soc_I.usb_I.trans_I.ep_type }, B={ \soc_I.usb_I.trans_I.bd_state \soc_I.usb_I.trans_I.trans_is_setup \soc_I.usb_I.trans_I.xfer_length }, Y={ \soc_I.usb_I.ep_status_I.p_din_0 [15:12] \soc_I.usb_I.ep_status_I.p_din_0 [9:0] } New connections: \soc_I.usb_I.ep_status_I.p_din_0 [11:10] = 2'00 Consolidated identical input bits for $pmux cell $flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11854: Old ports: A=3'000, B=6'110111, Y=$flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11854_Y New ports: A=2'00, B=4'1011, Y=$flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11854_Y [1:0] New connections: $flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11854_Y [2] = $flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11854_Y [1] Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\tx_pkt_I.\crc_16_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4957: Old ports: A=16'0000000000000000, B=16'1000000000000101, Y=\soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux New ports: A=1'0, B=1'1, Y=\soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux [0] New connections: \soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux [15:1] = { \soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux [0] 12'000000000000 \soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\spi_mux_I.$ternary$/build/gateware/icE1usb/rtl/sr_btn_if.v:144$3210: Old ports: A=3'010, B=3'100, Y=$auto$wreduce.cc:454:run$24978 [2:0] New ports: A=2'01, B=2'10, Y=$auto$wreduce.cc:454:run$24978 [2:1] New connections: $auto$wreduce.cc:454:run$24978 [0] = 1'0 Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\misc_I.\dfu_I.\btn_flt_I.$procmux$5647: Old ports: A=$flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0], B=4'0001, Y=\misc_I.dfu_I.btn_flt_I.cnt_move New ports: A={ $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] }, B=2'01, Y=\misc_I.dfu_I.btn_flt_I.cnt_move [1:0] New connections: \misc_I.dfu_I.btn_flt_I.cnt_move [3:2] = { \misc_I.dfu_I.btn_flt_I.cnt_move [1] \misc_I.dfu_I.btn_flt_I.cnt_move [1] } Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$procmux$12926: Old ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 2'00 }, B=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$4112_Y, Y={ $flatten\soc_I.\cpu_I.$3\current_pc[31:0] [31:2] $auto$alumacc.cc:501:replace_alu$25077 [1:0] } New ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 1'0 }, B=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$4112_Y [31:1], Y={ $flatten\soc_I.\cpu_I.$3\current_pc[31:0] [31:2] $auto$alumacc.cc:501:replace_alu$25077 [1] } New connections: $auto$alumacc.cc:501:replace_alu$25077 [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$4632: Old ports: A=16'0000000000000000, B=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$4631_Y, Y=\soc_I.e1_I.bus_rdata_rx[0] New ports: A=15'000000000000000, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$4631_Y [15:8] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$4631_Y [6:0] }, Y={ \soc_I.e1_I.bus_rdata_rx[0] [15:8] \soc_I.e1_I.bus_rdata_rx[0] [6:0] } New connections: \soc_I.e1_I.bus_rdata_rx[0] [7] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4592: Old ports: A=16'0000000000000000, B=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4591_Y, Y=\soc_I.e1_I.bus_rdata_tx[0] New ports: A=13'0000000000000, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4591_Y [15] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4591_Y [12:8] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4591_Y [6:0] }, Y={ \soc_I.e1_I.bus_rdata_tx[0] [15] \soc_I.e1_I.bus_rdata_tx[0] [12:8] \soc_I.e1_I.bus_rdata_tx[0] [6:0] } New connections: { \soc_I.e1_I.bus_rdata_tx[0] [14:13] \soc_I.e1_I.bus_rdata_tx[0] [7] } = 3'000 Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$procmux$11906: Old ports: A=$auto$wreduce.cc:454:run$24970 [2:0], B=3'100, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11906_Y [2:0] New ports: A={ $auto$wreduce.cc:454:run$24970 [1] $auto$wreduce.cc:454:run$24970 [1] }, B=2'10, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11906_Y [2:1] New connections: $flatten\soc_I.\usb_I.\trans_I.$procmux$11906_Y [0] = 1'0 Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$procmux$11909: Old ports: A=$flatten\soc_I.\usb_I.\trans_I.$procmux$11906_Y, B=4'1000, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11909_Y New ports: A={ 1'0 $flatten\soc_I.\usb_I.\trans_I.$procmux$11906_Y [2:1] }, B=3'100, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11909_Y [3:1] New connections: $flatten\soc_I.\usb_I.\trans_I.$procmux$11909_Y [0] = 1'0 Optimizing cells in module \top. Performed a total of 41 changes. 75.29.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.29.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$23181 ($dff) from module top (D = \soc_I.cpu_I.mem_wdata [11:10], Q = \soc_I.usb_I.ep_status_I.din_1 [11:10], rval = 2'00). Adding SRST signal on $auto$opt_dff.cc:702:run$24411 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx.v:170$4567_Y [2:1], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.pg_hi [2:1], rval = 2'00). Adding SRST signal on $auto$opt_dff.cc:702:run$24410 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx.v:171$4568_Y [2:1], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.pg_lo [2:1], rval = 2'00). 75.29.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.29.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~37 debug messages> 75.29.9. Rerunning OPT passes. (Maybe there is more to do..) 75.29.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 1/2 on $mux $flatten\soc_I.\e1_buf_I.$procmux$12413. dead port 1/2 on $mux $flatten\soc_I.\e1_buf_I.$procmux$12428. Removed 2 multiplexer ports. <suppressed ~186 debug messages> 75.29.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 75.29.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~3 debug messages> Removed a total of 1 cells. 75.29.13. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$opt_dff.cc:764:run$24851 ($dffe) from module top (D = $auto$wreduce.cc:454:run$24917 [2:0], Q = \i2c_I.core_I.bit_cnt [2:0], rval = 3'000). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$24584 ($dffe) from module top. Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$24584 ($dffe) from module top. Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$24365 ($dffe) from module top. Setting constant 1-bit at position 9 on $auto$opt_dff.cc:764:run$24313 ($adffe) from module top. 75.29.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 20 unused wires. <suppressed ~2 debug messages> 75.29.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.29.16. Rerunning OPT passes. (Maybe there is more to do..) 75.29.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~186 debug messages> 75.29.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 75.29.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.29.20. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$24376 ($sdff) from module top. Adding SRST signal on $auto$opt_dff.cc:702:run$24376 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_out_I.data[1] [8:7], Q = \soc_I.e1_I.wb_rdata [14:13], rval = 2'00). Removing never-active SRST on $auto$opt_dff.cc:702:run$24371 ($sdffce) from module top. Removing never-active SRST on $auto$opt_dff.cc:702:run$24369 ($sdffce) from module top. Removing never-active SRST on $auto$opt_dff.cc:702:run$24367 ($sdffce) from module top. 75.29.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.29.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~5 debug messages> 75.29.23. Rerunning OPT passes. (Maybe there is more to do..) 75.29.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~186 debug messages> 75.29.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 75.29.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~3 debug messages> Removed a total of 1 cells. 75.29.27. Executing OPT_DFF pass (perform DFF optimizations). 75.29.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 3 unused wires. <suppressed ~1 debug messages> 75.29.29. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.29.30. Rerunning OPT passes. (Maybe there is more to do..) 75.29.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~186 debug messages> 75.29.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 75.29.33. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.29.34. Executing OPT_DFF pass (perform DFF optimizations). 75.29.35. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.29.36. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.29.37. Finished OPT passes. (There is nothing left to do.) 75.30. Executing ICE40_WRAPCARRY pass (wrap carries). 75.31. Executing TECHMAP pass (map to technology primitives). 75.31.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/techmap.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 75.31.2. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ice40_alu'. Successfully finished Verilog frontend. 75.31.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $sdffce. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $sdffe. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $ne. Using extmapper simplemap for cells of type $reduce_bool. Using extmapper simplemap for cells of type $sdff. Using extmapper simplemap for cells of type $dffe. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu. Using extmapper simplemap for cells of type $adffe. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $xor. Using extmapper simplemap for cells of type $adff. Using extmapper simplemap for cells of type $mux. Using template $paramod$constmap:37b3cc4e06391b7a7ef418215dc52e2abb59f048$paramod$71443bc33ec938a4dea8c4b4bbb3a548919fd2a5\_90_shift_shiftx for cells of type $shiftx. Using template $paramod$constmap:f131a727070ba63172385ab8bc15babdfc05a11a$paramod$4d8c31a57f918e2cd1d0bc24d8284efd6d83f4a8\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=3\Y_WIDTH=3 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=7\B_WIDTH=1\Y_WIDTH=7 for cells of type $alu. Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu. Using extmapper simplemap for cells of type $logic_and. Using extmapper simplemap for cells of type $logic_or. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=1\Y_WIDTH=5 for cells of type $alu. Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=1\Y_WIDTH=2 for cells of type $alu. Using template $paramod$constmap:98a2574d6790db88f29c592e698ccfc2583099ee$paramod$da4b7a069bab2d2cb126ab511d2c5f5d67aa4129\_90_shift_shiftx for cells of type $shiftx. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=1\Y_WIDTH=4 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=14\Y_WIDTH=14 for cells of type $alu. Using template $paramod$constmap:2a578b20caa92a5095129d48a2f94bbad08a990f$paramod$5c10e52cdc159999f3945c97d8a1bfa2ca0de2dc\_90_shift_shiftx for cells of type $shiftx. Using template $paramod\_90_pmux\WIDTH=2\S_WIDTH=3 for cells of type $pmux. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=11\B_WIDTH=1\Y_WIDTH=12 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=13\B_WIDTH=1\Y_WIDTH=13 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=9\Y_WIDTH=9 for cells of type $alu. Using extmapper simplemap for cells of type $reduce_xor. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=20\Y_WIDTH=20 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=1\Y_WIDTH=4 for cells of type $alu. Using template $paramod\_90_pmux\WIDTH=16\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=5 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=2\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=4 for cells of type $pmux. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=11\B_WIDTH=1\Y_WIDTH=11 for cells of type $alu. Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=6 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=3 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=8 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=6 for cells of type $pmux. Using extmapper simplemap for cells of type $reduce_xnor. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=8\Y_WIDTH=8 for cells of type $alu. Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=3 for cells of type $pmux. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=9\B_WIDTH=1\Y_WIDTH=9 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=2\Y_WIDTH=3 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=10\Y_WIDTH=10 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=11\Y_WIDTH=11 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=10\B_WIDTH=10\Y_WIDTH=10 for cells of type $alu. Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu. Using template $paramod$constmap:66d421c313e4e958be776b99540ac2de3b59fdbc$paramod$9b74a473ccd678a23e1df4cc12019cbbece20051\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=30\Y_WIDTH=30 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=31\B_WIDTH=31\Y_WIDTH=31 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=30\B_WIDTH=30\Y_WIDTH=30 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=16\Y_WIDTH=16 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=6\B_WIDTH=1\Y_WIDTH=6 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=1\B_SIGNED=1\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=1\Y_WIDTH=3 for cells of type $alu. Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=3 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=24\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=5 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=4 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=5 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=9\B_WIDTH=9\Y_WIDTH=9 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu. Using template $paramod$constmap:87e158a1e7f9a65bc3daafa14cddbc2f2a62b0f9$paramod$00673b792be9df78f478ac12e847ffbbf69ec54f\_90_shift_shiftx for cells of type $shiftx. Using template $paramod$constmap:97d3e8470f71c97b2a3f4cc7d3b643b1fee5fa20$paramod$46cd3b166c849b74a0d50b3191f97ef695044070\_90_shift_shiftx for cells of type $shiftx. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=26\Y_WIDTH=26 for cells of type $alu. Using template $paramod$constmap:684fca2758d270a6aba8ac07bc0dd26758fbc9a0$paramod$ce139bdae4db109c6875842b953e3d257bf611b7\_90_shift_shiftx for cells of type $shiftx. Analyzing pattern of constant bits for this cell: Constant input on bit 0 of port A: 1'0 Constant input on bit 1 of port A: 1'0 Constant input on bit 2 of port A: 1'0 Constant input on bit 3 of port A: 1'0 Constant input on bit 4 of port A: 1'1 Constant input on bit 5 of port A: 1'1 Constant input on bit 6 of port A: 1'1 Constant input on bit 7 of port A: 1'1 Constant input on bit 8 of port A: 1'0 Constant input on bit 9 of port A: 1'0 Constant input on bit 10 of port A: 1'0 Constant input on bit 11 of port A: 1'0 Constant input on bit 12 of port A: 1'1 Constant input on bit 13 of port A: 1'1 Constant input on bit 14 of port A: 1'1 Constant input on bit 15 of port A: 1'1 Creating constmapped module `$paramod$constmap:8b3644844662a5df890757b6e744f94687338ba9$paramod$ce139bdae4db109c6875842b953e3d257bf611b7\_90_shift_shiftx'. 75.31.151. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod$constmap:8b3644844662a5df890757b6e744f94687338ba9$paramod$ce139bdae4db109c6875842b953e3d257bf611b7\_90_shift_shiftx.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 2/2 on $mux $procmux$36256. dead port 2/2 on $mux $procmux$36250. dead port 2/2 on $mux $procmux$36244. dead port 2/2 on $mux $procmux$36238. Removed 4 multiplexer ports. <suppressed ~4260 debug messages> 75.31.152. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$constmap:8b3644844662a5df890757b6e744f94687338ba9$paramod$ce139bdae4db109c6875842b953e3d257bf611b7\_90_shift_shiftx. <suppressed ~3 debug messages> Removed 0 unused cells and 11 unused wires. Using template $paramod$constmap:8b3644844662a5df890757b6e744f94687338ba9$paramod$ce139bdae4db109c6875842b953e3d257bf611b7\_90_shift_shiftx for cells of type $shiftx. Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=7 for cells of type $pmux. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=13\B_WIDTH=13\Y_WIDTH=13 for cells of type $alu. Using extmapper simplemap for cells of type $pos. Using template $paramod\_90_lcu\WIDTH=2 for cells of type $lcu. No more expansions possible. <suppressed ~1296 debug messages> 75.32. Executing OPT pass (performing simple optimizations). 75.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~3427 debug messages> 75.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~3765 debug messages> Removed a total of 1255 cells. 75.32.3. Executing OPT_DFF pass (perform DFF optimizations). 75.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1003 unused cells and 4623 unused wires. <suppressed ~1016 debug messages> 75.32.5. Finished fast OPT passes. 75.33. Executing ICE40_OPT pass (performing simple optimizations). 75.33.1. Running ICE40 specific optimizations. Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24989.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24989.BB [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24998.slice[0].carry: CO=\blinker_I.tick_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25004.slice[0].carry: CO=\gps_uart_I.uart_div [1] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25004.slice[11].carry: CO=$auto$alumacc.cc:485:replace_alu$25004.C [11] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25007.slice[0].carry: CO=\gps_uart_I.uart_rx_I.div_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25010.slice[0].carry: CO=\gps_uart_I.uart_rx_I.bit_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25016.slice[0].carry: CO=\gps_uart_I.uart_rx_fifo_I.ram_rd_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25022.slice[0].carry: CO=\gps_uart_I.uart_rx_fifo_I.ram_wr_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25025.slice[0].carry: CO=\gps_uart_I.uart_tx_I.div_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25028.slice[0].carry: CO=\gps_uart_I.uart_tx_I.bit_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25031.slice[0].carry: CO=\gps_uart_I.uart_tx_fifo_I.ram_rd_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25037.slice[0].carry: CO=\gps_uart_I.uart_tx_fifo_I.ram_wr_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25040.slice[0].carry: CO=\i2c_I.core_I.cyc_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25043.slice[0].carry: CO=\i2c_I.core_I.bit_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25052.slice[0].carry: CO=\sys_mgr_I.rst_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25073.slice[0].carry: CO=\soc_I.cpu_I.reg_pc [2] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25076.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25076.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25105.slice[0].carry: CO=\soc_I.cpu_I.reg_sh [2] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25108.slice[0].carry: CO=\soc_I.cpu_I.reg_sh [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25111.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25111.A [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25114.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25114.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25117.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25117.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25120.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25120.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25135.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25135.A [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25159.slice[0].carry: CO=\soc_I.e1_buf_I.buf_tx_ts [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25162.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25162.A [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25165.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25165.A [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25171.slice[0].carry: CO=\soc_I.iobuf_I.dma_I.m0_addr_i [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25174.slice[0].carry: CO=\soc_I.iobuf_I.dma_I.m1_addr_i [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25177.slice[0].carry: CO=\soc_I.iobuf_I.dma_I.len [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25180.slice[0].carry: CO=\soc_I.uart_I.uart_div [1] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25180.slice[11].carry: CO=$auto$alumacc.cc:485:replace_alu$25180.C [11] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25183.slice[0].carry: CO=\soc_I.uart_I.uart_rx_I.div_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25186.slice[0].carry: CO=\soc_I.uart_I.uart_rx_I.bit_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25192.slice[0].carry: CO=\soc_I.uart_I.uart_rx_fifo_I.ram_rd_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25198.slice[0].carry: CO=\soc_I.uart_I.uart_rx_fifo_I.ram_wr_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25201.slice[0].carry: CO=\soc_I.uart_I.uart_tx_I.div_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25204.slice[0].carry: CO=\soc_I.uart_I.uart_tx_I.bit_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25207.slice[0].carry: CO=\soc_I.uart_I.uart_tx_fifo_I.ram_rd_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25213.slice[0].carry: CO=\soc_I.uart_I.uart_tx_fifo_I.ram_wr_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25225.slice[0].carry: CO=\soc_I.usb_I.rx_pkt_I.bit_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25225.slice[3].carry: CO=$auto$alumacc.cc:485:replace_alu$25225.C [3] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25228.slice[0].carry: CO=\soc_I.usb_I.trans_I.mc_pc [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25243.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25243.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25243.slice[2].carry: CO=1'0 Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25246.slice[0].carry: CO=\soc_I.usb_I.tx_ll_I.bs_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25249.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25249.A [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25252.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25252.A [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25255.slice[0].carry: CO=\spi_mux_I.tick_cnt [0] 75.33.2. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~41 debug messages> 75.33.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.33.4. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30618 ($_SDFFCE_PP0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12189.B_AND_S [3], Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [3], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30617 ($_SDFFCE_PP0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12189.Y_B [2], Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [2], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30616 ($_SDFFCE_PP0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12189.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [1], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30614 ($_SDFFCE_PN0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12206.B_AND_S [3], Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1 [3], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30613 ($_SDFFCE_PN0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12206.Y_B [2], Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1 [2], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30612 ($_SDFFCE_PN0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12206.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1 [1], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35192 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [31], Q = \misc_I.wb_rdata [31], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35191 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [30], Q = \misc_I.wb_rdata [30], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35190 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [29], Q = \misc_I.wb_rdata [29], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35189 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [28], Q = \misc_I.wb_rdata [28], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35188 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [27], Q = \misc_I.wb_rdata [27], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35187 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [26], Q = \misc_I.wb_rdata [26], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35186 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [25], Q = \misc_I.wb_rdata [25], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35185 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [24], Q = \misc_I.wb_rdata [24], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35184 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [23], Q = \misc_I.wb_rdata [23], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35183 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [22], Q = \misc_I.wb_rdata [22], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35182 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [21], Q = \misc_I.wb_rdata [21], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35181 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [20], Q = \misc_I.wb_rdata [20], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35176 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [15], Q = \misc_I.wb_rdata [15], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35175 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [14], Q = \misc_I.wb_rdata [14], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35174 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [13], Q = \misc_I.wb_rdata [13], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35173 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [12], Q = \misc_I.wb_rdata [12], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35168 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [7], Q = \misc_I.wb_rdata [7], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35167 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [6], Q = \misc_I.wb_rdata [6], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35166 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [5], Q = \misc_I.wb_rdata [5], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35165 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [4], Q = \misc_I.wb_rdata [4], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$31214 ($_SDFF_PP0_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12232.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.samp_cnt [1], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34791 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [31], Q = \soc_I.cpu_I.decoded_imm [31], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34790 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [30], Q = \soc_I.cpu_I.decoded_imm [30], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34789 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [29], Q = \soc_I.cpu_I.decoded_imm [29], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34788 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [28], Q = \soc_I.cpu_I.decoded_imm [28], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34787 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [27], Q = \soc_I.cpu_I.decoded_imm [27], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34786 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [26], Q = \soc_I.cpu_I.decoded_imm [26], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34785 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [25], Q = \soc_I.cpu_I.decoded_imm [25], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34784 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [24], Q = \soc_I.cpu_I.decoded_imm [24], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34783 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [23], Q = \soc_I.cpu_I.decoded_imm [23], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34782 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [22], Q = \soc_I.cpu_I.decoded_imm [22], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34781 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [21], Q = \soc_I.cpu_I.decoded_imm [21], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34780 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [20], Q = \soc_I.cpu_I.decoded_imm [20], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34779 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [19], Q = \soc_I.cpu_I.decoded_imm [19], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34778 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [18], Q = \soc_I.cpu_I.decoded_imm [18], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34777 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [17], Q = \soc_I.cpu_I.decoded_imm [17], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34776 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [16], Q = \soc_I.cpu_I.decoded_imm [16], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34775 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [15], Q = \soc_I.cpu_I.decoded_imm [15], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34774 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [14], Q = \soc_I.cpu_I.decoded_imm [14], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34773 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [13], Q = \soc_I.cpu_I.decoded_imm [13], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34772 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [12], Q = \soc_I.cpu_I.decoded_imm [12], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34771 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [11], Q = \soc_I.cpu_I.decoded_imm [11], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34770 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [10], Q = \soc_I.cpu_I.decoded_imm [10], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34769 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [9], Q = \soc_I.cpu_I.decoded_imm [9], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34768 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [8], Q = \soc_I.cpu_I.decoded_imm [8], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34767 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [7], Q = \soc_I.cpu_I.decoded_imm [7], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34766 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [6], Q = \soc_I.cpu_I.decoded_imm [6], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34765 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [5], Q = \soc_I.cpu_I.decoded_imm [5], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34764 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [4], Q = \soc_I.cpu_I.decoded_imm [4], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34763 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [3], Q = \soc_I.cpu_I.decoded_imm [3], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34762 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [2], Q = \soc_I.cpu_I.decoded_imm [2], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34761 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [1], Q = \soc_I.cpu_I.decoded_imm [1], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$30608 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12221.B_AND_S [2], Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [2], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$30607 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12221.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [1], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$30606 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12221.Y_B [0], Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [0], rval = 1'0). 75.33.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 62 unused cells and 32 unused wires. <suppressed ~63 debug messages> 75.33.6. Rerunning OPT passes. (Removed registers in this run.) 75.33.7. Running ICE40 specific optimizations. 75.33.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.33.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~132 debug messages> Removed a total of 44 cells. 75.33.10. Executing OPT_DFF pass (perform DFF optimizations). 75.33.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 44 unused wires. <suppressed ~1 debug messages> 75.33.12. Rerunning OPT passes. (Removed registers in this run.) 75.33.13. Running ICE40 specific optimizations. 75.33.14. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.33.15. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.33.16. Executing OPT_DFF pass (perform DFF optimizations). 75.33.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.33.18. Finished OPT passes. (There is nothing left to do.) 75.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 75.35. Executing TECHMAP pass (map to technology primitives). 75.35.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. Successfully finished Verilog frontend. 75.35.2. Continuing TECHMAP pass. Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_. Using template \$_SDFFCE_PP0P_ for cells of type $_SDFFCE_PP0P_. Using template \$_DFF_PP1_ for cells of type $_DFF_PP1_. Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template \$_DFF_P_ for cells of type $_DFF_P_. Using template \$_DFF_PP0_ for cells of type $_DFF_PP0_. Using template \$_DFFE_PP1P_ for cells of type $_DFFE_PP1P_. Using template \$_SDFFCE_PP1P_ for cells of type $_SDFFCE_PP1P_. Using template \$_DFFE_PP0P_ for cells of type $_DFFE_PP0P_. Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_. No more expansions possible. <suppressed ~2238 debug messages> 75.36. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). Mapping top.$auto$alumacc.cc:485:replace_alu$24998.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25004.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25004.slice[11].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25007.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25010.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25016.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25022.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25025.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25028.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25031.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25037.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25040.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25043.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25052.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25073.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25076.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25105.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25108.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25111.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25114.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25117.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25120.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25135.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25159.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25162.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25165.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25171.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25174.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25177.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25180.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25180.slice[11].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25183.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25186.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25192.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25198.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25201.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25204.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25207.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25213.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25225.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25225.slice[3].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25228.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25243.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25243.slice[2].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25246.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25249.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25252.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25255.slice[0].carry ($lut). 75.38. Executing ICE40_OPT pass (performing simple optimizations). 75.38.1. Running ICE40 specific optimizations. 75.38.2. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~1264 debug messages> 75.38.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~1350 debug messages> Removed a total of 450 cells. 75.38.4. Executing OPT_DFF pass (perform DFF optimizations). 75.38.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 12116 unused wires. <suppressed ~1 debug messages> 75.38.6. Rerunning OPT passes. (Removed registers in this run.) 75.38.7. Running ICE40 specific optimizations. 75.38.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.38.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.38.10. Executing OPT_DFF pass (perform DFF optimizations). 75.38.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.38.12. Finished OPT passes. (There is nothing left to do.) 75.39. Executing TECHMAP pass (map to technology primitives). 75.39.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/latches_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/latches_map.v' to AST representation. Generating RTLIL representation for module `\$_DLATCH_N_'. Generating RTLIL representation for module `\$_DLATCH_P_'. Successfully finished Verilog frontend. 75.39.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~4 debug messages> 75.40. Executing ABC pass (technology mapping using ABC). 75.40.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'.. Extracted 6464 gates and 8900 wires to a netlist network with 2434 inputs and 1805 outputs. 75.40.1.1. Executing ABC. Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1 ABC: ABC command line: "source <abc-temp-dir>/abc.script". ABC: ABC: + read_blif <abc-temp-dir>/input.blif ABC: + read_lut <abc-temp-dir>/lutdefs.txt ABC: + strash ABC: + ifraig ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + strash ABC: + dch -f ABC: + if ABC: + mfs2 ABC: + lutpack -S 1 ABC: + dress ABC: Total number of equiv classes = 2232. ABC: Participating nodes from both networks = 4725. ABC: Participating nodes from the first network = 2248. ( 79.66 % of nodes) ABC: Participating nodes from the second network = 2477. ( 87.77 % of nodes) ABC: Node pairs (any polarity) = 2248. ( 79.66 % of names can be moved) ABC: Node pairs (same polarity) = 1996. ( 70.73 % of names can be moved) ABC: Total runtime = 0.04 sec ABC: + write_blif <abc-temp-dir>/output.blif 75.40.1.2. Re-integrating ABC results. ABC RESULTS: $lut cells: 2821 ABC RESULTS: internal signals: 4661 ABC RESULTS: input signals: 2434 ABC RESULTS: output signals: 1805 Removing temp directory. 75.41. Executing ICE40_WRAPCARRY pass (wrap carries). 75.42. Executing TECHMAP pass (map to technology primitives). 75.42.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. Successfully finished Verilog frontend. 75.42.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~22 debug messages> Removed 107 unused cells and 5884 unused wires. 75.43. Executing OPT_LUT pass (optimize LUTs). Discovering LUTs. Number of LUTs: 3499 1-LUT 116 2-LUT 981 3-LUT 1269 4-LUT 1133 Eliminating LUTs. Number of LUTs: 3495 1-LUT 116 2-LUT 981 3-LUT 1265 4-LUT 1133 Combining LUTs. Number of LUTs: 3238 1-LUT 116 2-LUT 660 3-LUT 1146 4-LUT 1316 Eliminated 4 LUTs. Combined 257 LUTs. <suppressed ~18803 debug messages> 75.44. Executing TECHMAP pass (map to technology primitives). 75.44.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v' to AST representation. Generating RTLIL representation for module `\$lut'. Successfully finished Verilog frontend. 75.44.2. Continuing TECHMAP pass. Using template $paramod\$lut\WIDTH=3\LUT=8'01010011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101110011001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101001100110011 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'1000 for cells of type $lut. Using template $paramod\$lut\WIDTH=1\LUT=2'01 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0110000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'0100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000011101110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0110100110010110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000101110111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10101100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00110101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000110000001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'0001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000110000000101 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011101111 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'0111 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'1110 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100101011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000010111011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011010111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000011101110111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000011100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100101011 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'1011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'0110 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11101000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10110010 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11010100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001000111110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11101111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111111110 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00001011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100011101110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111100011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01001011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111011111110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000111111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000110011001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11000101 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100111110100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00000111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011100100001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011101110110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101110111011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111001111110101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111110000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00011111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100111110110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000010001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'1001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111100010001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101000001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100101000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100111101000100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00001110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100000000000010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111010000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110110000110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111000001110111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111010111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111110111011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111100000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011000010111011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010110011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00011000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001010111111100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000011111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11100111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11111110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100101111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100000011 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00010100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100001011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100010111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000001001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100000100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011110001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000010111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011101000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000111110001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000011111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010110011001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000100011110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1101000000110011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001010000101000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111011101110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000101010100010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100010011110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000001110111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111111110000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00111010 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11110001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011110011001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010110000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111010000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110101100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011101100001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00001101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101001111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0010001010001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110111111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011000000110011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101111111110011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001001100111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011010100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110101011110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100010100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101011111100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100111000001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010101111101010 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1001100100111100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1001011010010110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111010001000100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111111100110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111001100000101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111110000001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0010100000101000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000110100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111001011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000010001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010001111001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100000100010100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10111100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0110000000001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010101010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111110110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101010111000011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111010001001011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000100000001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111011101000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111000001011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010000000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100010100110101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101000000011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100001110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111011001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111110011111010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011101100110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001010000010100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010110010100011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101001101011100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101110001010011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100110101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101010100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010101011000011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110101110111110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010001000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100101110110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001000101000100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1001110010011100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110111111111110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000001100001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0010000100010010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100000000 for cells of type $lut. No more expansions possible. <suppressed ~6127 debug messages> Removed 0 unused cells and 6897 unused wires. 75.45. Executing AUTONAME pass. Renamed 194351 objects in module top (123 iterations). <suppressed ~8204 debug messages> 75.46. Executing HIERARCHY pass (managing design hierarchy). 75.46.1. Analyzing design hierarchy.. Top module: \top 75.46.2. Analyzing design hierarchy.. Top module: \top Removed 0 unused modules. 75.47. Printing statistics. === top === Number of wires: 3743 Number of wire bits: 18330 Number of public wires: 3743 Number of public wire bits: 18330 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 6241 SB_CARRY 688 SB_DFF 317 SB_DFFE 577 SB_DFFER 431 SB_DFFES 44 SB_DFFESR 219 SB_DFFESS 41 SB_DFFR 131 SB_DFFS 49 SB_DFFSR 375 SB_DFFSS 31 SB_GB 2 SB_GB_IO 1 SB_IO 25 SB_LEDDA_IP 1 SB_LUT4 3277 SB_MAC16 4 SB_PLL40_CORE 1 SB_RAM40_4K 16 SB_RAM40_4KNR 4 SB_RGBA_DRV 1 SB_SPI 1 SB_SPRAM256KA 4 SB_WARMBOOT 1 75.48. Executing CHECK pass (checking for obvious problems). checking module top.. found and reported 0 problems. 75.49. Executing JSON backend. Warnings: 10 unique messages, 18 total End of script. Logfile hash: 10d239cfe3, CPU: user 17.02s system 0.18s, MEM: 323.04 MB peak Yosys 0.9+3568 (open-tool-forge build) (git sha1 859e52af, gcc 9.3.0-10ubuntu2 -Os) Time spent: 22% 40x opt_expr (3 sec), 21% 31x opt_clean (3 sec), ... nextpnr-ice40 --pre-pack data/clocks.py --pre-pack data/opt.py --seed 15 --no-promote-globals --timing-allow-fail \ --up5k --package sg48 \ -l /build/gateware/icE1usb/build-tmp/icE1usb.pnr.rpt \ --json /build/gateware/icE1usb/build-tmp/icE1usb.json \ --pcf /build/gateware/icE1usb/data/top-ice1usb.pcf \ --asc /build/gateware/icE1usb/build-tmp/icE1usb.asc Info: constrained 'e1A_rx_hi_p' to bel 'X8/Y31/io0' Warning: unmatched constraint 'e1A_rx_hi_n' (on line 3) Info: constrained 'e1A_rx_lo_p' to bel 'X16/Y31/io0' Warning: unmatched constraint 'e1A_rx_lo_n' (on line 5) Info: constrained 'e1A_tx_hi' to bel 'X9/Y31/io0' Info: constrained 'e1A_tx_lo' to bel 'X9/Y31/io1' Info: constrained 'e1B_rx_hi_p' to bel 'X19/Y31/io0' Warning: unmatched constraint 'e1B_rx_hi_n' (on line 10) Info: constrained 'e1B_rx_lo_p' to bel 'X18/Y31/io0' Warning: unmatched constraint 'e1B_rx_lo_n' (on line 12) Info: constrained 'e1B_tx_hi' to bel 'X13/Y31/io1' Info: constrained 'e1B_tx_lo' to bel 'X13/Y31/io0' Info: constrained 'e1_rx_bias[0]' to bel 'X17/Y31/io0' Info: constrained 'e1_rx_bias[1]' to bel 'X12/Y31/io1' Info: constrained 'usb_dp' to bel 'X16/Y0/io0' Info: constrained 'usb_dn' to bel 'X15/Y0/io0' Info: constrained 'usb_pu' to bel 'X17/Y0/io0' Info: constrained 'flash_mosi' to bel 'X23/Y0/io0' Info: constrained 'flash_miso' to bel 'X23/Y0/io1' Info: constrained 'flash_clk' to bel 'X24/Y0/io0' Info: constrained 'flash_cs_n' to bel 'X24/Y0/io1' Info: constrained 'e1_led_rclk' to bel 'X22/Y0/io1' Info: constrained 'gps_reset_n' to bel 'X13/Y0/io1' Info: constrained 'gps_rx' to bel 'X6/Y0/io0' Info: constrained 'gps_tx' to bel 'X5/Y0/io0' Info: constrained 'gps_pps' to bel 'X8/Y0/io0' Info: constrained 'i2c_sda' to bel 'X9/Y0/io1' Info: constrained 'i2c_scl' to bel 'X9/Y0/io0' Info: constrained 'gpio[0]' to bel 'X19/Y0/io0' Info: constrained 'gpio[1]' to bel 'X19/Y0/io1' Info: constrained 'gpio[2]' to bel 'X21/Y0/io1' Info: constrained 'clk_in' to bel 'X6/Y0/io1' Info: constrained 'clk_tune_hi' to bel 'X7/Y0/io0' Info: constrained 'clk_tune_lo' to bel 'X7/Y0/io1' Info: constrained 'dbg_rx' to bel 'X18/Y0/io1' Info: constrained 'dbg_tx' to bel 'X18/Y0/io0' Info: constrained 'rgb[0]' to bel 'X4/Y31/io0' Info: constrained 'rgb[1]' to bel 'X5/Y31/io0' Info: constrained 'rgb[2]' to bel 'X6/Y31/io0' Info: constraining clock net 'clk_sys' to 30.72 MHz Info: constraining clock net 'clk_48m' to 48.00 MHz 1 251 ControlSet(rs=None, ena=None, clk='clk_sys') 5 ControlSet(rs='wb_ack[1]', ena=None, clk='clk_sys') -------------- 0 252 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='spi_mux_I.srio_dat_o_SB_DFFSR_Q_R', ena=None, clk='clk_sys') -------------- 1 257 ControlSet(rs=None, ena=None, clk='clk_sys') 5 ControlSet(rs='soc_I.wb_ack[1]', ena=None, clk='clk_sys') -------------- 0 72 ControlSet(rs=None, ena=None, clk='clk_48m') 1 ControlSet(rs='soc_I.usb_I.tx_ll_I.lvl_prev_SB_DFFSS_Q_S', ena=None, clk='clk_48m') -------------- 1 73 ControlSet(rs=None, ena=None, clk='clk_48m') 1 ControlSet(rs='soc_I.usb_I.tx_ll_I.ll_ack_SB_LUT4_I2_O_SB_LUT4_I2_O[3]', ena='soc_I.usb_I.tx_pkt_I.shift_now', clk='clk_48m') 1 12 ControlSet(rs=None, ena='soc_I.usb_I.tx_pkt_I.shift_now', clk='clk_48m') 1 ControlSet(rs='soc_I.usb_I.tx_ll_I.ll_ack_SB_LUT4_I2_O_SB_LUT4_I2_O[3]', ena='soc_I.usb_I.tx_pkt_I.shift_now', clk='clk_48m') -------------- 2 75 ControlSet(rs=None, ena=None, clk='clk_48m') 2 ControlSet(rs='soc_I.usb_I.rx_pkt_I.state[0]', ena='soc_I.usb_I.rx_pkt_I.crc5_ok_SB_DFFESR_Q_E', clk='clk_48m') -------------- 3 80 ControlSet(rs=None, ena=None, clk='clk_48m') 5 ControlSet(rs='soc_I.usb_I.rx_pkt_I.state[0]', ena='soc_I.usb_I.rx_pkt_I.bit_cnt_SB_DFFESR_Q_E', clk='clk_48m') -------------- 0 82 ControlSet(rs=None, ena=None, clk='clk_48m') 2 ControlSet(rs='soc_I.usb_I.rx_ll_I.samp_sync', ena=None, clk='clk_48m') -------------- 0 83 ControlSet(rs=None, ena=None, clk='clk_48m') 1 ControlSet(rs='soc_I.usb_I.rx_ll_I.samp_cnt_SB_DFFSR_Q_R', ena=None, clk='clk_48m') -------------- 0 84 ControlSet(rs=None, ena=None, clk='clk_48m') 1 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_sync_1_SB_LUT4_I2_O[1]', ena='soc_I.usb_I.rx_pkt_I.crc_in_first_SB_DFFESS_Q_E', clk='clk_48m') -------------- 5 15 ControlSet(rs=None, ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m') 3 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_sync_1_SB_DFFESR_Q_R', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m') 3 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_eop_1_SB_DFFESR_Q_R', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m') 1 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_rep_state_1_SB_DFFESR_Q_R', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m') 3 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_sym_same_0_SB_LUT4_I3_1_O', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m') 1 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_sym_se_0', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m') 3 87 ControlSet(rs=None, ena=None, clk='clk_48m') 3 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_sync_1_SB_DFFESR_Q_R', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m') -------------- 0 86 ControlSet(rs=None, ena=None, clk='clk_48m') 2 ControlSet(rs='soc_I.usb_I.eps_write_0', ena=None, clk='clk_48m') -------------- 0 89 ControlSet(rs=None, ena=None, clk='clk_48m') 3 ControlSet(rs='soc_I.usb_I.eps_bus_clear', ena=None, clk='clk_48m') -------------- 0 94 ControlSet(rs=None, ena=None, clk='clk_48m') 5 ControlSet(rs='soc_I.usb_I.csr_bus_clear', ena=None, clk='clk_48m') -------------- 0 264 ControlSet(rs=None, ena=None, clk='clk_sys') 7 ControlSet(rs='soc_I.uart_I.ub_rdata_SB_DFFSR_Q_9_R', ena=None, clk='clk_sys') -------------- 0 265 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.uart_I.uart_tx_I.ce_SB_LUT4_I2_O[2]', ena=None, clk='clk_sys') -------------- 4 270 ControlSet(rs=None, ena=None, clk='clk_sys') 5 ControlSet(rs='soc_I.uart_I.uart_tx_I.bit_cnt_SB_DFFESS_Q_S', ena='soc_I.uart_I.uart_tx_I.ce_SB_LUT4_I2_O[2]', clk='clk_sys') -------------- 4 275 ControlSet(rs=None, ena=None, clk='clk_sys') 5 ControlSet(rs='soc_I.uart_I.uart_rx_I.bit_cnt_SB_DFFESS_Q_S', ena='soc_I.uart_I.uart_rx_I.bit_cnt_SB_DFFESS_Q_E', clk='clk_sys') -------------- 1 276 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.latched_store_SB_DFFESS_Q_E', clk='clk_sys') -------------- 5 281 ControlSet(rs=None, ena=None, clk='clk_sys') 5 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.latched_stalu_SB_DFFESR_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O', clk='clk_sys') -------------- 0 282 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.latched_stalu_SB_DFFESR_Q_E', clk='clk_sys') -------------- 2 284 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.latched_is_lh_SB_DFFESR_Q_E', clk='clk_sys') -------------- 1 285 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.latched_branch_SB_DFFESR_Q_E', clk='clk_sys') -------------- 1 286 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu_SB_DFFESR_Q_E', clk='clk_sys') -------------- 0 13 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.len_ce', clk='clk_sys') 1 ControlSet(rs='soc_I.iobuf_I.dma_I.len_ld', ena='soc_I.iobuf_I.dma_I.len_ce', clk='clk_sys') 1 287 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.iobuf_I.dma_I.len_ld', ena='soc_I.iobuf_I.dma_I.len_ce', clk='clk_sys') -------------- 0 288 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs='soc_I.e1_I.wb_rdata_SB_DFFSR_Q_14_R', ena=None, clk='clk_sys') -------------- 0 292 ControlSet(rs=None, ena=None, clk='clk_sys') 4 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I1_I0_SB_LUT4_I0_O_SB_DFFR_D_Q_SB_DFF_D_Q_SB_LUT4_I3_2_O', ena=None, clk='clk_sys') -------------- 0 295 ControlSet(rs=None, ena=None, clk='clk_sys') 3 ControlSet(rs='soc_I.e1_I.lb_bit_SB_DFFESR_Q_E_SB_LUT4_I2_O', ena=None, clk='clk_sys') -------------- 0 299 ControlSet(rs=None, ena=None, clk='clk_sys') 4 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_1_I0_SB_LUT4_I2_I1_SB_DFFSR_Q_R', ena=None, clk='clk_sys') -------------- 3 19 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_buf_I.buf_tx_re_SB_LUT4_O_I3', clk='clk_sys') 1 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_1_I3_SB_DFFR_Q_D_SB_LUT4_O_I3_SB_DFF_Q_D_SB_LUT4_O_I3[1]', clk='clk_sys') 4 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_LUT4_I2_O', clk='clk_sys') -------------- 1 300 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I0_SB_LUT4_I0_O_SB_DFFR_D_Q_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_DFFESR_Q_E', clk='clk_sys') -------------- 0 301 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I0_SB_LUT4_I0_O_SB_DFFR_D_Q_SB_LUT4_I2_O', clk='clk_sys') -------------- 0 303 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I3_O_SB_DFFSR_R_3_Q_SB_LUT4_I2_O', ena=None, clk='clk_sys') -------------- 0 305 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I3_O_SB_DFFSR_R_1_Q_SB_LUT4_I2_O', ena=None, clk='clk_sys') -------------- 0 309 ControlSet(rs=None, ena=None, clk='clk_sys') 4 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I3_O', ena=None, clk='clk_sys') -------------- 0 311 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I3_I2_SB_LUT4_I3_O_SB_DFFSR_R_3_Q_SB_LUT4_I2_O', ena=None, clk='clk_sys') -------------- 0 313 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I3_I2_SB_LUT4_I3_O_SB_DFFSR_R_1_Q_SB_LUT4_I2_O', ena=None, clk='clk_sys') -------------- 0 317 ControlSet(rs=None, ena=None, clk='clk_sys') 4 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I3_I2_SB_LUT4_I3_O', ena=None, clk='clk_sys') -------------- 6 324 ControlSet(rs=None, ena=None, clk='clk_sys') 7 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O_SB_LUT4_I0_O_SB_DFF_D_Q[0]', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_1_I0_SB_LUT4_I2_I3_SB_DFF_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_DFFSS_Q_D_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O', clk='clk_sys') -------------- 5 331 ControlSet(rs=None, ena=None, clk='clk_sys') 7 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O_SB_LUT4_I0_O_SB_DFF_D_Q[0]', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_1_I0_SB_LUT4_I2_I3_SB_DFF_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_DFFSS_Q_D_SB_LUT4_O_I2_SB_DFFESR_Q_E', clk='clk_sys') -------------- 4 336 ControlSet(rs=None, ena=None, clk='clk_sys') 5 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O_SB_LUT4_I0_O_SB_DFF_D_Q[0]', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I3_O_SB_DFFSR_R_1_D_SB_LUT4_O_I3_SB_DFFESS_D_Q_SB_LUT4_I2_I3_SB_DFFESS_Q_E', clk='clk_sys') -------------- 0 337 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O_SB_LUT4_I0_O_SB_DFF_D_Q[0]', ena=None, clk='clk_sys') -------------- 0 338 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.cpu_I.mem_state_SB_DFFESR_Q_R', ena='soc_I.cpu_I.mem_valid_SB_DFFESR_Q_E', clk='clk_sys') -------------- 2 340 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs='soc_I.cpu_I.mem_state_SB_DFFESR_Q_R', ena='soc_I.cpu_I.mem_state_SB_DFFESR_Q_E', clk='clk_sys') -------------- 0 341 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.cpu_I.mem_do_wdata_SB_DFFESS_Q_S[1]', ena='soc_I.cpu_I.mem_do_wdata_SB_DFFESS_Q_E', clk='clk_sys') -------------- 1 342 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.cpu_I.instr_sra_SB_LUT4_I2_1_I3_SB_LUT4_I1_O[0]', ena='soc_I.cpu_I.mem_do_rinst_SB_DFFESS_Q_E', clk='clk_sys') -------------- 0 343 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.cpu_I.instr_sb_SB_LUT4_I1_I3[0]', ena='soc_I.cpu_I.mem_do_prefetch_SB_DFFESR_Q_E', clk='clk_sys') -------------- 0 344 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.cpu_I.instr_or_SB_DFFESR_Q_E', ena=None, clk='clk_sys') -------------- 0 345 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.cpu_I.instr_lbu_SB_LUT4_I3_O[3]', ena='soc_I.cpu_I.mem_do_rdata_SB_DFFESS_Q_E', clk='clk_sys') -------------- 0 346 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.cpu_I.decoder_pseudo_trigger_SB_DFFSR_Q_R', ena=None, clk='clk_sys') -------------- 0 347 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.cpu_I.alu_wait_SB_DFFSR_Q_R', ena=None, clk='clk_sys') -------------- 1 192 ControlSet(rs='rst_sys', ena=None, clk='clk_sys') 1 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_tx_fifo_I.rd_valid_SB_DFFER_Q_E[1]', clk='clk_sys') 1 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_rx_fifo_I.rd_valid_SB_DFFER_Q_E[1]', clk='clk_sys') 1 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_tx_fifo_I.rd_valid_SB_DFFER_Q_E[1]', clk='clk_sys') 3 ControlSet(rs='rst_sys', ena='misc_I.bus_we_boot', clk='clk_sys') 3 ControlSet(rs='rst_sys', ena='misc_I.dfu_I.wb_sel_SB_DFFER_Q_E', clk='clk_sys') 2 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E', clk='clk_sys') 7 ControlSet(rs='rst_sys', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I3_SB_DFFER_Q_E', clk='clk_sys') 2 ControlSet(rs='rst_sys', ena='soc_I.iobuf_I.dma_I.state_SB_DFFER_Q_E', clk='clk_sys') 3 ControlSet(rs='rst_sys', ena='soc_I.rgb_I.led_ctrl_SB_DFFER_Q_E', clk='clk_sys') 1 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_rx_fifo_I.rd_valid_SB_DFFER_Q_E[1]', clk='clk_sys') -------------- 0 348 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_rx_I.gf_I.state_SB_DFFESS_Q_E', clk='clk_sys') -------------- 1 349 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='rst_sys', ena='i2c_I.core_I.sda_oe_SB_DFFESR_Q_E', clk='clk_sys') -------------- 0 350 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='rst_sys', ena='i2c_I.core_I.scl_oe_SB_DFFESR_Q_E', clk='clk_sys') -------------- 0 351 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_rx_I.gf_I.state_SB_DFFESS_Q_E', clk='clk_sys') -------------- 5 67 ControlSet(rs='rst_48m', ena=None, clk='clk_48m') 3 ControlSet(rs='rst_48m', ena='soc_I.usb_I.tx_ll_I.state_SB_DFFER_Q_E', clk='clk_48m') 2 ControlSet(rs='rst_48m', ena='soc_I.usb_I.tx_ll_I.br_cnt[2]', clk='clk_48m') -------------- 0 352 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='misc_I.tick_e1_SB_DFFSS_Q_S[2]', ena='misc_I.tick_e1_SB_DFFSS_Q_S_SB_LUT4_I3_O', clk='clk_sys') -------------- 0 353 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='misc_I.tick_e1_SB_DFFSS_Q_S[2]', ena=None, clk='clk_sys') -------------- 0 354 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='misc_I.tick_e1_SB_DFFSS_Q_D[2]', ena='misc_I.tick_e1_SB_DFFSS_Q_D_SB_LUT4_I3_O', clk='clk_sys') -------------- 0 355 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='misc_I.pps_flt_I.state_SB_LUT4_I1_O[1]', ena='misc_I.pps_flt_I.state_SB_DFFESR_Q_E', clk='clk_sys') -------------- 0 356 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='misc_I.dfu_I.btn_flt_I.fall_SB_DFF_Q_D', ena='misc_I.dfu_I.btn_flt_I.state_SB_DFFESR_Q_E', clk='clk_sys') -------------- 0 361 ControlSet(rs=None, ena=None, clk='clk_sys') 5 ControlSet(rs='i2c_I.core_I.cyc_cnt_SB_DFFSR_Q_R', ena=None, clk='clk_sys') -------------- 2 364 ControlSet(rs=None, ena=None, clk='clk_sys') 3 ControlSet(rs='i2c_I.core_I.bit_cnt_SB_DFFESR_Q_R[1]', ena='i2c_I.core_I.bit_last_SB_DFFE_Q_E', clk='clk_sys') -------------- 0 371 ControlSet(rs=None, ena=None, clk='clk_sys') 7 ControlSet(rs='gps_uart_I.ub_rdata_SB_DFFSR_Q_9_R', ena=None, clk='clk_sys') -------------- 0 372 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='gps_uart_I.uart_tx_I.ce_SB_LUT4_I2_O[2]', ena=None, clk='clk_sys') -------------- 4 377 ControlSet(rs=None, ena=None, clk='clk_sys') 5 ControlSet(rs='gps_uart_I.uart_tx_I.bit_cnt_SB_DFFESS_Q_S', ena='gps_uart_I.uart_tx_I.ce_SB_LUT4_I2_O[2]', clk='clk_sys') -------------- 4 382 ControlSet(rs=None, ena=None, clk='clk_sys') 5 ControlSet(rs='gps_uart_I.uart_rx_I.bit_cnt_SB_DFFESS_Q_S', ena='gps_uart_I.uart_rx_I.bit_cnt_SB_DFFESS_Q_E', clk='clk_sys') -------------- 3 386 ControlSet(rs=None, ena=None, clk='clk_sys') 4 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena='soc_I.e1_I.lb_bit_SB_DFFESR_Q_E[0]', clk='clk_sys') -------------- 0 387 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_DFFESR_Q_E', clk='clk_sys') -------------- 1 389 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena='e1A_rx_lo_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O_SB_LUT4_I2_O', clk='clk_sys') -------------- 1 391 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O_SB_LUT4_I2_O', clk='clk_sys') -------------- 1 395 ControlSet(rs=None, ena=None, clk='clk_sys') 4 ControlSet(rs=None, ena='tick_e1[0]', clk='clk_sys') -------------- 0 96 ControlSet(rs=None, ena=None, clk='clk_48m') 2 ControlSet(rs=None, ena='soc_I.usb_I.tx_pkt_I.shift_data_crc_SB_DFFE_Q_E', clk='clk_48m') -------------- 1 100 ControlSet(rs=None, ena=None, clk='clk_48m') 4 ControlSet(rs=None, ena='soc_I.usb_I.trans_I.mc_op_tx', clk='clk_48m') -------------- 4 104 ControlSet(rs=None, ena=None, clk='clk_48m') 4 ControlSet(rs=None, ena='soc_I.usb_I.trans_I.mc_op_ld', clk='clk_48m') -------------- 2 111 ControlSet(rs=None, ena=None, clk='clk_48m') 7 ControlSet(rs=None, ena='soc_I.usb_I.trans_I.epfw_issue_wb_SB_LUT4_I1_O[0]', clk='clk_48m') -------------- 1 117 ControlSet(rs=None, ena=None, clk='clk_48m') 6 ControlSet(rs=None, ena='soc_I.usb_I.trans_I.ep_bd_dual_SB_LUT4_I2_O[2]', clk='clk_48m') -------------- 3 120 ControlSet(rs=None, ena=None, clk='clk_48m') 3 ControlSet(rs=None, ena='soc_I.usb_I.trans_I.bd_state_SB_DFFE_Q_E', clk='clk_48m') -------------- 0 124 ControlSet(rs=None, ena=None, clk='clk_48m') 4 ControlSet(rs=None, ena='soc_I.usb_I.rxpkt_done_ok', clk='clk_48m') -------------- 0 127 ControlSet(rs=None, ena=None, clk='clk_48m') 3 ControlSet(rs=None, ena='soc_I.usb_I.rx_pkt_I.token_data_SB_DFFE_Q_E[1]', clk='clk_48m') -------------- 0 396 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.len_ld', clk='clk_sys') -------------- 1 400 ControlSet(rs=None, ena=None, clk='clk_sys') 4 ControlSet(rs=None, ena='soc_I.e1_buf_I.buf_rx_we_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I1', clk='clk_sys') -------------- 0 404 ControlSet(rs=None, ena=None, clk='clk_sys') 4 ControlSet(rs=None, ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I3_O_SB_DFFSR_R_1_D_SB_LUT4_O_I3_SB_DFFESS_D_Q_SB_LUT4_I2_I3_SB_LUT4_I0_O[0]', clk='clk_sys') -------------- 1 405 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs=None, ena='soc_I.cpu_I.reg_op1_SB_DFFE_Q_31_E', clk='clk_sys') -------------- 2 407 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs=None, ena='soc_I.cpu_I.instr_sra_SB_LUT4_I2_O[3]', clk='clk_sys') -------------- 4 411 ControlSet(rs=None, ena=None, clk='clk_sys') 4 ControlSet(rs=None, ena='soc_I.bridge_I.ram_rdy_SB_LUT4_I0_O[1]', clk='clk_sys') -------------- 0 413 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs=None, ena='misc_I.bus_we_tick_sel', clk='clk_sys') -------------- 0 415 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs=None, ena='i2c_I.stb', clk='clk_sys') -------------- 1 416 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs=None, ena='i2c_I.core_I.bit_last_SB_DFFE_Q_E', clk='clk_sys') -------------- Control Set Optimizer: cost 96 to reduce control sets from 206 to 100 Total control sets: 100 1 2 3 1 4 1 6 1 8 14 9 21 10 12 11 3 12 3 13 5 14 2 15 2 16 5 17 2 18 1 19 1 20 4 24 1 25 1 28 1 29 1 31 2 32 5 33 2 45 1 55 1 60 1 67 1 127 1 192 1 416 1 1 ControlSet(rs='sys_mgr_I.pll_lock_SB_LUT4_I3_O', ena=None, clk='clk_sys') 1 ControlSet(rs='sys_mgr_I.rst_30m72_i', ena=None, clk='clk_48m') 3 ControlSet(rs='sys_mgr_I.pll_lock_SB_LUT4_I3_O', ena='sys_mgr_I.rst_30m72_i', clk='clk_sys') 4 ControlSet(rs='soc_I.usb_I.txll_start', ena='soc_I.usb_I.tx_ll_I.br_cnt[2]', clk='clk_48m') 6 ControlSet(rs='rst_sys', ena=None, clk='clk_48m') 8 ControlSet(rs=None, ena='spi_mux_I.shift_ce', clk='clk_sys') 8 ControlSet(rs=None, ena='soc_I.usb_I.rx_pkt_I.llu_byte_stb_SB_LUT4_I2_O[1]', clk='clk_48m') 8 ControlSet(rs='rst_sys', ena='misc_I.bus_we_gpio', clk='clk_sys') 8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I0_SB_LUT4_I1_O[1]', clk='clk_sys') 8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I0_SB_LUT4_I1_O[4]', clk='clk_sys') 8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I1_SB_LUT4_I1_O[4]', clk='clk_sys') 8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I1_SB_LUT4_I1_O[3]', clk='clk_sys') 8 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I3_I1', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_1_I0_SB_LUT4_I2_I3_SB_DFF_Q_D_SB_LUT4_O_I3_SB_LUT4_I2_I0_SB_LUT4_I1_I3_SB_DFFSR_Q_D_SB_LUT4_O_I2_SB_LUT4_I2_O', clk='clk_sys') 8 ControlSet(rs='misc_I.wb_ack_SB_LUT4_I2_O_SB_LUT4_I2_O', ena=None, clk='clk_sys') 8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I0_SB_LUT4_I1_O[3]', clk='clk_sys') 8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I1_SB_LUT4_I1_O[1]', clk='clk_sys') 8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I0_SB_LUT4_I1_O[2]', clk='clk_sys') 8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I1_SB_LUT4_I1_O[2]', clk='clk_sys') 8 ControlSet(rs=None, ena='soc_I.e1_buf_I.t_done[2]', clk='clk_sys') 9 ControlSet(rs=None, ena='soc_I.usb_I.rx_pkt_I.pid_cap', clk='clk_48m') 9 ControlSet(rs='soc_I.uart_I.ub_rdata_rst', ena=None, clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='soc_I.uart_I.ub_wr_data', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_tx_fifo_I.ram_rd_ena', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_tx_I.ce_SB_LUT4_I3_O', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='soc_I.uart_I.urf_wren', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_rx_fifo_I.ram_rd_ena', clk='clk_sys') 9 ControlSet(rs=None, ena='soc_I.uart_I.uart_rx_I.ce', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='misc_I.bus_we_pdm_e1[0]', clk='clk_sys') 9 ControlSet(rs=None, ena='tick_e1[2]', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='gps_uart_I.ub_wr_data', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_tx_fifo_I.ram_rd_ena', clk='clk_sys') 9 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.m1_addr_ce', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_rx_fifo_I.ram_rd_ena', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_tx_I.ce_SB_LUT4_I3_O', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='misc_I.bus_we_pdm_e1[1]', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='gps_uart_I.urf_wren', clk='clk_sys') 9 ControlSet(rs=None, ena='gps_uart_I.uart_rx_I.ce', clk='clk_sys') 9 ControlSet(rs='gps_uart_I.ub_rdata_rst', ena=None, clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='misc_I.bus_we_led', clk='clk_sys') 9 ControlSet(rs=None, ena='i2c_I.core_I.stb_SB_LUT4_I2_O', clk='clk_sys') 10 ControlSet(rs='soc_I.usb_I.trans_I.len_ld', ena=None, clk='clk_48m') 10 ControlSet(rs='rst_48m', ena='soc_I.usb_I.cr_bus_we', clk='clk_48m') 10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I2_SB_LUT4_I1_O[3]', clk='clk_sys') 10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I2_SB_LUT4_I1_O[2]', clk='clk_sys') 10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I2_SB_LUT4_I1_O[1]', clk='clk_sys') 10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I3_SB_LUT4_I1_O[3]', clk='clk_sys') 10 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I0_SB_LUT4_I0_O_SB_DFFR_D_Q_SB_LUT4_I3_O[2]', clk='clk_sys') 10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I2_SB_LUT4_I1_O[4]', clk='clk_sys') 10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I3_SB_LUT4_I1_O[4]', clk='clk_sys') 10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I3_SB_LUT4_I1_O[1]', clk='clk_sys') 10 ControlSet(rs='i2c_I.bus_clr', ena=None, clk='clk_sys') 10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I3_SB_LUT4_I1_O[2]', clk='clk_sys') 11 ControlSet(rs=None, ena='soc_I.usb_I.tx_pkt_I.shift_now', clk='clk_48m') 11 ControlSet(rs=None, ena='soc_I.usb_I.tx_pkt_I.len_dec', clk='clk_48m') 11 ControlSet(rs='soc_I.usb_I.trans_I.mc_op_zlen', ena=None, clk='clk_48m') 12 ControlSet(rs=None, ena='soc_I.uart_I.ub_wr_div', clk='clk_sys') 12 ControlSet(rs='misc_I.bus_clr', ena=None, clk='clk_sys') 12 ControlSet(rs=None, ena='gps_uart_I.ub_wr_div', clk='clk_sys') 13 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.len_ce', clk='clk_sys') Info: Packing constants.. 13 ControlSet(rs=None, ena='soc_I.cpu_I.decoder_pseudo_trigger_SB_LUT4_I2_O[0]', clk='clk_sys') 13 ControlSet(rs='rst_sys', ena='misc_I.bus_we_pdm_clk[1]', clk='clk_sys') 13 ControlSet(rs='rst_sys', ena='misc_I.bus_we_pdm_clk[0]', clk='clk_sys') 13 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_buf_I.buf_tx_ts_SB_DFFES_Q_E', clk='clk_sys') 14 ControlSet(rs=None, ena='soc_I.usb_I.ep_status_I.p_read_2', clk='clk_48m') 14 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.m0_addr_ce', clk='clk_sys') 15 ControlSet(rs=None, ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m') 15 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='tick_e1[0]', clk='clk_sys') 16 ControlSet(rs='soc_I.wb_48m_xclk_I.s_cyc_SB_LUT4_I3_O', ena=None, clk='clk_sys') 16 ControlSet(rs=None, ena='soc_I.ub_ack', clk='clk_48m') 16 ControlSet(rs=None, ena='soc_I.usb_I.tx_pkt_I.crc_in_valid', clk='clk_48m') 16 ControlSet(rs='soc_I.usb_I.ep_status_I.s_zero_2', ena='soc_I.usb_I.ep_status_I.s_read_2', clk='clk_48m') 16 ControlSet(rs=None, ena='soc_I.e1_buf_tx_re[0]', clk='clk_sys') 17 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O_SB_LUT4_I0_O_SB_DFF_D_Q[0]', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I3_O_SB_DFFSR_R_1_D_SB_LUT4_O_I3_SB_DFFESS_D_Q_SB_LUT4_I2_I3_SB_LUT4_I0_1_O', clk='clk_sys') 17 ControlSet(rs='soc_I.e1_I.bus_clr', ena=None, clk='clk_sys') 18 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.instr_or_SB_DFFESR_Q_E', clk='clk_sys') 19 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena=None, clk='clk_sys') 20 ControlSet(rs='soc_I.usb_I.oob_sof_SB_LUT4_I2_O', ena=None, clk='clk_48m') 20 ControlSet(rs='soc_I.usb_I.phy_I.rx_dn_SB_LUT4_I3_O', ena=None, clk='clk_48m') 20 ControlSet(rs='misc_I.wb_ack_SB_LUT4_I2_O_SB_LUT4_I3_O', ena=None, clk='clk_sys') 20 ControlSet(rs=None, ena='soc_I.cpu_I.trap_SB_LUT4_I3_O', clk='clk_sys') 24 ControlSet(rs=None, ena='soc_I.e1_buf_rx_we[0]', clk='clk_sys') 25 ControlSet(rs=None, ena='soc_I.e1_buf_I.t_busy_SB_LUT4_I3_O', clk='clk_sys') 28 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena=None, clk='clk_sys') 29 ControlSet(rs=None, ena='soc_I.usb_I.rx_pkt_I.crc_in_valid', clk='clk_48m') 31 ControlSet(rs='soc_I.cpu_I.is_lui_auipc_jal_SB_DFF_Q_D_SB_LUT4_I2_O', ena='soc_I.cpu_I.decoder_pseudo_trigger_SB_LUT4_I2_O[0]', clk='clk_sys') 31 ControlSet(rs=None, ena='soc_I.cpu_I.instr_sra_SB_LUT4_I2_1_O_SB_LUT4_I2_O', clk='clk_sys') 32 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.ack_rd', clk='clk_sys') 32 ControlSet(rs=None, ena='soc_I.pb_rst_n_SB_LUT4_I2_O', clk='clk_sys') 32 ControlSet(rs='soc_I.bridge_I.wb_cyc_rst', ena=None, clk='clk_sys') 32 ControlSet(rs=None, ena='soc_I.cpu_I.trap_SB_LUT4_I2_O', clk='clk_sys') 32 ControlSet(rs=None, ena='soc_I.cpu_I.instr_ecall_ebreak_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I0[3]', clk='clk_sys') 33 ControlSet(rs=None, ena='soc_I.cpu_I.cpu_state_SB_DFF_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I2_O', clk='clk_sys') 33 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena=None, clk='clk_sys') 45 ControlSet(rs='rst_sys', ena='soc_I.iobuf_I.epbam_arb_I.reselect', clk='clk_sys') 55 ControlSet(rs='rst_sys', ena='soc_I.iobuf_I.spram_arb_I.reselect', clk='clk_sys') 60 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.pb_rst_n_SB_LUT4_I3_1_O', clk='clk_sys') 67 ControlSet(rs='rst_48m', ena=None, clk='clk_48m') 127 ControlSet(rs=None, ena=None, clk='clk_48m') 192 ControlSet(rs='rst_sys', ena=None, clk='clk_sys') 416 ControlSet(rs=None, ena=None, clk='clk_sys') LUT replication: 0 new LUTs in 0 groups Info: Packing IOs.. Info: clk_in feeds SB_IO sys_mgr_I.gb_in, removing $nextpnr_ibuf clk_in. Info: clk_tune_hi feeds SB_IO misc_I.pdm_clk_I[1].io_reg_I, removing $nextpnr_obuf clk_tune_hi. Info: clk_tune_lo feeds SB_IO misc_I.pdm_clk_I[0].io_reg_I, removing $nextpnr_obuf clk_tune_lo. Info: e1A_rx_hi_p feeds SB_IO e1A_rx_hi_p_SB_IO_PACKAGE_PIN, removing $nextpnr_ibuf e1A_rx_hi_p. Info: e1A_rx_lo_p feeds SB_IO e1A_rx_lo_p_SB_IO_PACKAGE_PIN, removing $nextpnr_ibuf e1A_rx_lo_p. Info: e1A_tx_hi feeds SB_IO e1A_tx_hi_SB_IO_PACKAGE_PIN, removing $nextpnr_obuf e1A_tx_hi. Info: e1A_tx_lo feeds SB_IO e1A_tx_lo_SB_IO_PACKAGE_PIN, removing $nextpnr_obuf e1A_tx_lo. Info: e1B_rx_hi_p feeds SB_IO e1_dummy_rx_I[1], removing $nextpnr_ibuf e1B_rx_hi_p. Info: e1B_rx_lo_p feeds SB_IO e1_dummy_rx_I[0], removing $nextpnr_ibuf e1B_rx_lo_p. Info: e1B_tx_hi feeds SB_IO e1_dummy_tx_I[1], removing $nextpnr_obuf e1B_tx_hi. Info: e1B_tx_lo feeds SB_IO e1_dummy_tx_I[0], removing $nextpnr_obuf e1B_tx_lo. Info: e1_led_rclk feeds SB_IO spi_mux_I.iob_I[0], removing $nextpnr_iobuf e1_led_rclk. Info: flash_clk feeds SB_IO spi_mux_I.iob_I[1], removing $nextpnr_iobuf flash_clk. Info: flash_miso feeds SB_IO spi_mux_I.iob_I[2], removing $nextpnr_iobuf flash_miso. Info: flash_mosi feeds SB_IO spi_mux_I.iob_I[3], removing $nextpnr_iobuf flash_mosi. Info: gps_pps feeds SB_IO misc_I.pps_iob_I, removing $nextpnr_ibuf gps_pps. Info: gps_reset_n feeds SB_IO misc_I.gpio_iob_I[3], removing $nextpnr_obuf gps_reset_n. Info: i2c_scl feeds SB_IO i2c_iob_I[1], removing $nextpnr_iobuf i2c_scl. Info: i2c_sda feeds SB_IO i2c_iob_I[0], removing $nextpnr_iobuf i2c_sda. Info: usb_dn feeds SB_IO soc_I.usb_I.phy_I.io_dn_I, removing $nextpnr_iobuf usb_dn. Info: usb_dp feeds SB_IO soc_I.usb_I.phy_I.io_dp_I, removing $nextpnr_iobuf usb_dp. Info: gpio[0] feeds SB_IO misc_I.gpio_iob_I[0], removing $nextpnr_iobuf gpio[0]. Info: gpio[1] feeds SB_IO misc_I.gpio_iob_I[1], removing $nextpnr_iobuf gpio[1]. Info: gpio[2] feeds SB_IO misc_I.gpio_iob_I[2], removing $nextpnr_iobuf gpio[2]. Info: e1_rx_bias[0] feeds SB_IO misc_I.pdm_e1_I[0].io_reg_I, removing $nextpnr_obuf e1_rx_bias[0]. Info: e1_rx_bias[1] feeds SB_IO misc_I.pdm_e1_I[1].io_reg_I, removing $nextpnr_obuf e1_rx_bias[1]. Info: rgb[0] use by SB_RGBA_DRV/SB_RGB_DRV soc_I.rgb_I.rgb_drv_I, not creating SB_IO Info: rgb[1] use by SB_RGBA_DRV/SB_RGB_DRV soc_I.rgb_I.rgb_drv_I, not creating SB_IO Info: rgb[2] use by SB_RGBA_DRV/SB_RGB_DRV soc_I.rgb_I.rgb_drv_I, not creating SB_IO Info: Packing LUT-FFs.. Info: 1756 LCs used as LUT4 only Info: 1706 LCs used as LUT4 and DFF Info: Packing non-LUT FFs.. Info: 509 LCs used as DFF only Info: Packing carries.. Info: 233 LCs used as CARRY only Info: Packing RAMs.. Info: Placing PLLs.. Info: constrained PLL 'sys_mgr_I.pll_I' to X12/Y31/pll_3 Info: Packing special functions.. Info: constrained SB_LEDDA_IP 'soc_I.rgb_I.led_I' to X0/Y31/ledda_ip_2 Info: constrained SB_RGBA_DRV 'soc_I.rgb_I.rgb_drv_I' to X0/Y30/rgba_drv_0 Info: constrained SB_SPI 'soc_I.spi_I.spi_I' to X0/Y0/spi_0 Info: PLL 'sys_mgr_I.pll_I' has LOCK output, need to pass all outputs via LUT Info: constrained 'sys_mgr_I.pll_lock_SB_LUT4_I3_LC' to X1/Y30/lc0 Info: Constraining chains... Info: 210 LCs used to legalise carry chains. Info: Checksum: 0x47526ac2 Info: Annotating ports with timing budgets for target frequency 12.00 MHz Info: Checksum: 0x392b22fa Info: Device utilisation: Info: ICESTORM_LC: 4419/ 5280 83% Info: ICESTORM_RAM: 20/ 30 66% Info: SB_IO: 32/ 96 33% Info: SB_GB: 4/ 8 50% Info: ICESTORM_PLL: 1/ 1 100% Info: SB_WARMBOOT: 1/ 1 100% Info: ICESTORM_DSP: 4/ 8 50% Info: ICESTORM_HFOSC: 0/ 1 0% Info: ICESTORM_LFOSC: 0/ 1 0% Info: SB_I2C: 0/ 2 0% Info: SB_SPI: 1/ 2 50% Info: IO_I3C: 0/ 2 0% Info: SB_LEDDA_IP: 1/ 1 100% Info: SB_RGBA_DRV: 1/ 1 100% Info: ICESTORM_SPRAM: 4/ 4 100% Info: Placed 39 cells based on constraints. Info: Creating initial analytic placement for 3559 cells, random placement wirelen = 109349. Info: at initial placer iter 0, wirelen = 3562 Info: at initial placer iter 1, wirelen = 3171 Info: at initial placer iter 2, wirelen = 3221 Info: at initial placer iter 3, wirelen = 3155 Info: Running main analytical placer. Info: at iteration #1, type ALL: wirelen solved = 3214, spread = 36851, legal = 43640; time = 0.16s Info: at iteration #2, type ALL: wirelen solved = 4655, spread = 30351, legal = 47344; time = 0.24s Info: at iteration #3, type ALL: wirelen solved = 5595, spread = 29638, legal = 39407; time = 0.13s Info: at iteration #4, type ALL: wirelen solved = 6873, spread = 27841, legal = 47585; time = 0.24s Info: at iteration #5, type ALL: wirelen solved = 7402, spread = 27591, legal = 42966; time = 0.18s Info: at iteration #6, type ALL: wirelen solved = 8154, spread = 27297, legal = 44649; time = 0.23s Info: at iteration #7, type ALL: wirelen solved = 8722, spread = 26816, legal = 36263; time = 0.12s Info: at iteration #8, type ALL: wirelen solved = 9401, spread = 26705, legal = 37586; time = 0.11s Info: at iteration #9, type ALL: wirelen solved = 9929, spread = 26096, legal = 37681; time = 0.14s Info: at iteration #10, type ALL: wirelen solved = 10313, spread = 25726, legal = 40378; time = 0.16s Info: at iteration #11, type ALL: wirelen solved = 10611, spread = 25823, legal = 38935; time = 0.16s Info: at iteration #12, type ALL: wirelen solved = 10904, spread = 25713, legal = 37783; time = 0.11s Info: HeAP Placer Time: 2.29s Info: of which solving equations: 0.53s Info: of which spreading cells: 0.08s Info: of which strict legalisation: 1.44s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 852, wirelen = 36263 Info: at iteration #5: temp = 0.000000, timing cost = 726, wirelen = 29959 Info: at iteration #10: temp = 0.000000, timing cost = 839, wirelen = 28487 Info: at iteration #15: temp = 0.000000, timing cost = 830, wirelen = 27680 Info: at iteration #20: temp = 0.000000, timing cost = 805, wirelen = 27167 Info: at iteration #25: temp = 0.000000, timing cost = 801, wirelen = 27035 Info: at iteration #30: temp = 0.000000, timing cost = 794, wirelen = 26965 Info: at iteration #30: temp = 0.000000, timing cost = 793, wirelen = 26968 Info: SA placement time 3.25s Info: Max frequency for clock 'clk_sys': 35.99 MHz (PASS at 30.72 MHz) Info: Max frequency for clock 'clk_48m': 52.63 MHz (PASS at 48.00 MHz) Info: Max delay <async> -> posedge clk_sys: 7.02 ns Info: Max delay posedge clk_48m -> <async> : 3.15 ns Info: Max delay posedge clk_48m -> posedge clk_sys: 6.19 ns Info: Max delay posedge clk_sys -> <async> : 12.59 ns Info: Max delay posedge clk_sys -> posedge clk_48m: 15.84 ns Info: Slack histogram: Info: legend: * represents 52 endpoint(s) Info: + represents [1,52) endpoint(s) Info: [ 1833, 5751) |+ Info: [ 5751, 9669) |*****+ Info: [ 9669, 13587) |***********+ Info: [ 13587, 17505) |*********************************+ Info: [ 17505, 21423) |*************************+ Info: [ 21423, 25341) |*********************************+ Info: [ 25341, 29259) |************************************************************ Info: [ 29259, 33177) |*+ Info: [ 33177, 37095) | Info: [ 37095, 41013) | Info: [ 41013, 44931) | Info: [ 44931, 48849) | Info: [ 48849, 52767) | Info: [ 52767, 56685) | Info: [ 56685, 60603) | Info: [ 60603, 64521) | Info: [ 64521, 68439) | Info: [ 68439, 72357) |+ Info: [ 72357, 76275) |+ Info: [ 76275, 80193) |+ Info: Checksum: 0x77765b40 Info: Routing.. Info: Setting up routing queue. Info: Routing 15254 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 1000 | 15 984 | 15 984 | 14277| 0.07 0.07| Info: 2000 | 21 1978 | 6 994 | 13285| 0.05 0.12| Info: 3000 | 101 2898 | 80 920 | 12387| 0.15 0.27| Info: 4000 | 205 3794 | 104 896 | 11514| 0.13 0.40| Info: 5000 | 340 4659 | 135 865 | 10679| 0.14 0.54| Info: 6000 | 543 5456 | 203 797 | 9939| 0.22 0.76| Info: 7000 | 829 6170 | 286 714 | 9356| 0.22 0.98| Info: 8000 | 1137 6862 | 308 692 | 8781| 0.19 1.17| Info: 9000 | 1425 7574 | 288 712 | 8178| 0.20 1.37| Info: 10000 | 1734 8265 | 309 691 | 7622| 0.30 1.67| Info: 11000 | 2218 8781 | 484 516 | 7384| 0.40 2.07| Info: 12000 | 2702 9297 | 484 516 | 7135| 0.43 2.50| Info: 13000 | 3183 9816 | 481 519 | 6841| 0.44 2.94| Info: 14000 | 3683 10316 | 500 500 | 6653| 0.42 3.36| Info: 15000 | 4148 10851 | 465 535 | 6394| 0.36 3.71| Info: 16000 | 4672 11327 | 524 476 | 6264| 0.37 4.08| Info: 17000 | 5246 11753 | 574 426 | 6174| 0.38 4.47| Info: 18000 | 5562 12437 | 316 684 | 5679| 0.25 4.72| Info: 19000 | 5980 13019 | 418 582 | 5281| 0.45 5.17| Info: 20000 | 6263 13736 | 283 717 | 4666| 0.27 5.44| Info: 21000 | 6740 14259 | 477 523 | 4424| 0.86 6.30| Info: 22000 | 7335 14664 | 595 405 | 4279| 1.15 7.46| Info: 23000 | 7844 15155 | 509 491 | 4162| 0.56 8.02| Info: 24000 | 8474 15525 | 630 370 | 4103| 0.59 8.61| Info: 25000 | 9031 15968 | 557 443 | 4009| 0.83 9.44| Info: 26000 | 9582 16417 | 551 449 | 3951| 0.61 10.05| Info: 27000 | 10180 16819 | 598 402 | 3933| 0.70 10.75| Info: 28000 | 10740 17259 | 560 440 | 3781| 0.54 11.29| Info: 29000 | 11327 17672 | 587 413 | 3744| 0.74 12.03| Info: 30000 | 11910 18089 | 583 417 | 3665| 0.60 12.63| Info: 31000 | 12488 18511 | 578 422 | 3615| 0.71 13.35| Info: 32000 | 13061 18938 | 573 427 | 3521| 0.62 13.97| Info: 33000 | 13658 19341 | 597 403 | 3466| 0.58 14.55| Info: 34000 | 14203 19796 | 545 455 | 3394| 0.51 15.06| Info: 35000 | 14824 20175 | 621 379 | 3341| 0.57 15.63| Info: 36000 | 15402 20597 | 578 422 | 3255| 0.53 16.17| Info: 37000 | 15969 21030 | 567 433 | 3158| 0.99 17.16| Info: 38000 | 16556 21443 | 587 413 | 3076| 0.68 17.83| Info: 39000 | 17131 21868 | 575 425 | 3018| 0.59 18.43| Info: 40000 | 17772 22227 | 641 359 | 2985| 0.76 19.19| Info: 41000 | 18339 22660 | 567 433 | 2899| 0.51 19.70| Info: 42000 | 18926 23073 | 587 413 | 2810| 0.64 20.34| Info: 43000 | 19456 23543 | 530 470 | 2659| 0.80 21.15| Info: 44000 | 20065 23934 | 609 391 | 2606| 0.62 21.76| Info: 45000 | 20667 24332 | 602 398 | 2592| 0.69 22.45| Info: 46000 | 21170 24829 | 503 497 | 2297| 0.53 22.99| Info: 47000 | 21577 25422 | 407 593 | 1869| 0.34 23.32| Info: 48000 | 21988 26011 | 411 589 | 1417| 0.37 23.70| Info: 49000 | 22323 26676 | 335 665 | 958| 0.95 24.64| Info: 50000 | 22838 27161 | 515 485 | 809| 1.36 26.00| Info: 51000 | 23452 27547 | 614 386 | 711| 0.80 26.80| Info: 52000 | 24008 27991 | 556 444 | 512| 1.11 27.91| Info: 53000 | 24486 28513 | 478 522 | 241| 0.62 28.53| Info: 53274 | 24514 28760 | 28 247 | 0| 0.09 28.62| Info: Routing complete. Info: Router1 time 28.62s Info: Checksum: 0x9234d1bf Info: Critical path report for clock 'clk_sys' (posedge -> posedge): Info: curr total Info: 1.4 1.4 Source soc_I.cpu_I.alu_out_SB_LUT4_O_27_LC.O Info: 3.6 5.0 Net soc_I.cpu_I.alu_out_q[4] budget 0.000000 ns (8,20) -> (5,14) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_7_I0_SB_LUT4_O_LC.I1 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/common/rtl/picorv32.v:1200.22-1200.31 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: 1.2 6.2 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_7_I0_SB_LUT4_O_LC.O Info: 1.8 8.0 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_7_I0[0] budget 0.000000 ns (5,14) -> (4,15) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_7_I0_SB_LUT4_I0_LC.I0 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/common/rtl/picorv32.v:1296.23-1296.55 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:62.5-70.4 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 1.3 9.3 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_7_I0_SB_LUT4_I0_LC.O Info: 1.8 11.0 Net soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_27_D_SB_LUT4_O_I1[1] budget 1.816000 ns (4,15) -> (4,16) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_6_LC.I1 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.7 11.7 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_6_LC.COUT Info: 0.0 11.7 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[4] budget 0.000000 ns (4,16) -> (4,16) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_5_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 12.0 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_5_LC.COUT Info: 0.0 12.0 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[5] budget 0.000000 ns (4,16) -> (4,16) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_4_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 12.3 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_4_LC.COUT Info: 0.0 12.3 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[6] budget 0.000000 ns (4,16) -> (4,16) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_3_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 12.5 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_3_LC.COUT Info: 0.0 12.5 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[7] budget 0.000000 ns (4,16) -> (4,16) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_2_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 12.8 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_2_LC.COUT Info: 0.6 13.4 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[8] budget 0.560000 ns (4,16) -> (4,17) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_1_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 13.6 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_1_LC.COUT Info: 0.0 13.6 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[9] budget 0.000000 ns (4,17) -> (4,17) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 13.9 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_LC.COUT Info: 0.0 13.9 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[10] budget 0.000000 ns (4,17) -> (4,17) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_29_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 14.2 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_29_LC.COUT Info: 0.0 14.2 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[11] budget 0.000000 ns (4,17) -> (4,17) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_28_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 14.5 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_28_LC.COUT Info: 0.0 14.5 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[12] budget 0.000000 ns (4,17) -> (4,17) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_27_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 14.8 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_27_LC.COUT Info: 0.0 14.8 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[13] budget 0.000000 ns (4,17) -> (4,17) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_26_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 15.0 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_26_LC.COUT Info: 0.0 15.0 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[14] budget 0.000000 ns (4,17) -> (4,17) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_25_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 15.3 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_25_LC.COUT Info: 0.0 15.3 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[15] budget 0.000000 ns (4,17) -> (4,17) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_24_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 15.6 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_24_LC.COUT Info: 0.6 16.1 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[16] budget 0.560000 ns (4,17) -> (4,18) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_23_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 16.4 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_23_LC.COUT Info: 0.0 16.4 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[17] budget 0.000000 ns (4,18) -> (4,18) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_22_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 16.7 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_22_LC.COUT Info: 0.0 16.7 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[18] budget 0.000000 ns (4,18) -> (4,18) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_21_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 17.0 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_21_LC.COUT Info: 0.0 17.0 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[19] budget 0.000000 ns (4,18) -> (4,18) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_20_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 17.3 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_20_LC.COUT Info: 0.0 17.3 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[20] budget 0.000000 ns (4,18) -> (4,18) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_18_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 17.5 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_18_LC.COUT Info: 0.0 17.5 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[21] budget 0.000000 ns (4,18) -> (4,18) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_17_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 17.8 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_17_LC.COUT Info: 0.0 17.8 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[22] budget 0.000000 ns (4,18) -> (4,18) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_16_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 18.1 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_16_LC.COUT Info: 0.0 18.1 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[23] budget 0.000000 ns (4,18) -> (4,18) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_15_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 18.4 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_15_LC.COUT Info: 0.6 18.9 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[24] budget 0.560000 ns (4,18) -> (4,19) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_14_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 19.2 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_14_LC.COUT Info: 0.0 19.2 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[25] budget 0.000000 ns (4,19) -> (4,19) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_13_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 19.5 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_13_LC.COUT Info: 0.0 19.5 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[26] budget 0.000000 ns (4,19) -> (4,19) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_12_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 19.8 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_12_LC.COUT Info: 0.0 19.8 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[27] budget 0.000000 ns (4,19) -> (4,19) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_11_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 20.0 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_11_LC.COUT Info: 0.0 20.0 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[28] budget 0.000000 ns (4,19) -> (4,19) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_10_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 20.3 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_10_LC.COUT Info: 0.0 20.3 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[29] budget 0.000000 ns (4,19) -> (4,19) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_9_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 20.6 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_9_LC.COUT Info: 0.7 21.3 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[30] budget 0.660000 ns (4,19) -> (4,19) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_7_LC.I3 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.9 22.1 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_7_LC.O Info: 3.0 25.1 Net soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_29_D_SB_LUT4_O_I0[30] budget 2.522000 ns (4,19) -> (3,23) Info: Sink soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_LC.I0 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:33.26-33.27 Info: 1.3 26.4 Source soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_LC.O Info: 1.8 28.1 Net soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_D_SB_LUT4_O_I1[0] budget 2.373000 ns (3,23) -> (3,23) Info: Sink soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_D_SB_LUT4_O_LC.I1 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 1.2 29.3 Setup soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_D_SB_LUT4_O_LC.I1 Info: 15.1 ns logic, 14.2 ns routing Info: Critical path report for clock 'clk_48m' (posedge -> posedge): Info: curr total Info: 1.4 1.4 Source soc_I.usb_I.trans_I.mc_a_reg_SB_DFFE_Q_1_conv_LC.O Info: 1.8 3.2 Net soc_I.usb_I.trans_I.mc_a_reg[2] budget 0.910000 ns (18,8) -> (18,9) Info: Sink soc_I.usb_I.trans_I.mc_match_bits_SB_LUT4_O_1_LC.I2 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:82.14-82.22 Info: /build/gateware/common/rtl/soc_base.v:373.4-393.3 Info: 1.2 4.4 Source soc_I.usb_I.trans_I.mc_match_bits_SB_LUT4_O_1_LC.O Info: 2.3 6.7 Net soc_I.usb_I.trans_I.mc_match_bits[2] budget 0.911000 ns (18,9) -> (18,9) Info: Sink soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_I0_SB_LUT4_O_LC.I2 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:85.32-85.45 Info: /build/gateware/common/rtl/soc_base.v:373.4-393.3 Info: 1.2 7.9 Source soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_I0_SB_LUT4_O_LC.O Info: 1.8 9.6 Net soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_I0[0] budget 1.219000 ns (18,9) -> (18,9) Info: Sink soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_LC.I0 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 1.3 10.9 Source soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_LC.O Info: 1.8 12.7 Net soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_O[0] budget 1.143000 ns (18,9) -> (18,10) Info: Sink soc_I.usb_I.trans_I.mc_pc_SB_LUT4_O_7_LC.I2 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 1.2 13.9 Source soc_I.usb_I.trans_I.mc_pc_SB_LUT4_O_7_LC.O Info: 1.8 15.6 Net soc_I.usb_I.trans_I.mc_pc[0] budget 1.361000 ns (18,10) -> (17,10) Info: Sink $nextpnr_ICESTORM_LC_196.I1 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:373.4-393.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.7 16.3 Source $nextpnr_ICESTORM_LC_196.COUT Info: 0.0 16.3 Net $nextpnr_ICESTORM_LC_196$O budget 0.000000 ns (17,10) -> (17,10) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_6_LC.CIN Info: 0.3 16.6 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_6_LC.COUT Info: 0.0 16.6 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[2] budget 0.000000 ns (17,10) -> (17,10) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_5_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:373.4-393.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 16.9 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_5_LC.COUT Info: 0.0 16.9 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[3] budget 0.000000 ns (17,10) -> (17,10) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_4_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:373.4-393.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 17.1 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_4_LC.COUT Info: 0.0 17.1 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[4] budget 0.000000 ns (17,10) -> (17,10) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_3_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:373.4-393.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 17.4 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_3_LC.COUT Info: 0.0 17.4 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[5] budget 0.000000 ns (17,10) -> (17,10) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_2_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:373.4-393.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 17.7 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_2_LC.COUT Info: 0.0 17.7 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[6] budget 0.000000 ns (17,10) -> (17,10) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_1_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:373.4-393.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 18.0 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_1_LC.COUT Info: 0.7 18.6 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[7] budget 0.660000 ns (17,10) -> (17,10) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_LC.I3 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:373.4-393.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.8 19.5 Setup soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_LC.I3 Info: 9.5 ns logic, 10.0 ns routing Info: Critical path report for cross-domain path '<async>' -> 'posedge clk_sys': Info: curr total Info: 0.0 0.0 Source spi_mux_I.iob_I[2].D_IN_0 Info: 8.2 8.2 Net flash_miso_i budget 31.052000 ns (23,0) -> (0,0) Info: Sink soc_I.spi_I.spi_I.MI Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:371.4-397.3 Info: /build/gateware/icE1usb/rtl/sr_btn_if.v:32.14-32.24 Info: 1.5 9.7 Setup soc_I.spi_I.spi_I.MI Info: 1.5 ns logic, 8.2 ns routing Info: Critical path report for cross-domain path 'posedge clk_48m' -> '<async>': Info: curr total Info: 1.4 1.4 Source soc_I.usb_I.pad_pu_SB_DFFSR_Q_DFFLC.O Info: 1.8 3.2 Net usb_pu$SB_IO_OUT budget 81.943001 ns (17,1) -> (17,0) Info: Sink usb_pu$sb_io.D_OUT_0 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:39.14-39.20 Info: 1.4 ns logic, 1.8 ns routing Info: Critical path report for cross-domain path 'posedge clk_48m' -> 'posedge clk_sys': Info: curr total Info: 1.4 1.4 Source soc_I.wb_48m_xclk_I.m_rdata_SB_LUT4_O_3_LC.O Info: 3.6 5.0 Net soc_I.wb_48m_xclk_I.m_rdata_i[12] budget 29.927999 ns (13,5) -> (15,12) Info: Sink soc_I.wb_48m_xclk_I.s_rdata_SB_DFFSR_Q_3_DFFLC.I0 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3 Info: /build/gateware/cores/no2misc//rtl/xclk_wb.v:53.15-53.24 Info: /build/gateware/common/rtl/soc_base.v:399.4-415.3 Info: 1.2 6.2 Setup soc_I.wb_48m_xclk_I.s_rdata_SB_DFFSR_Q_3_DFFLC.I0 Info: 2.6 ns logic, 3.6 ns routing Info: Critical path report for cross-domain path 'posedge clk_sys' -> '<async>': Info: curr total Info: 1.5 1.5 Source soc_I.spi_I.spi_I.MCSNO0 Info: 5.7 7.2 Net flash_csn_o budget 36.775002 ns (0,0) -> (3,1) Info: Sink flash_cs_n_SB_LUT4_O_LC.I2 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:371.4-397.3 Info: /build/gateware/icE1usb/rtl/sr_btn_if.v:40.14-40.23 Info: 1.2 8.4 Source flash_cs_n_SB_LUT4_O_LC.O Info: 5.8 14.2 Net flash_cs_n$SB_IO_OUT budget 40.313999 ns (3,1) -> (24,0) Info: Sink flash_cs_n$sb_io.D_OUT_0 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:371.4-397.3 Info: /build/gateware/icE1usb/rtl/sr_btn_if.v:90.7-90.16 Info: 2.7 ns logic, 11.5 ns routing Info: Critical path report for cross-domain path 'posedge clk_sys' -> 'posedge clk_48m': Info: curr total Info: 1.4 1.4 Source soc_I.cpu_I.mem_la_addr_SB_LUT4_O_19_LC.O Info: 4.1 5.5 Net wb_addr[0] budget 3.965000 ns (5,8) -> (13,7) Info: Sink soc_I.iobuf_I.dma_I.len_ld_SB_LUT4_O_I2_SB_LUT4_O_LC.I2 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:91.18-91.25 Info: 1.2 6.7 Source soc_I.iobuf_I.dma_I.len_ld_SB_LUT4_O_I2_SB_LUT4_O_LC.O Info: 1.8 8.5 Net soc_I.wb_48m_xclk_I.m_rdata_SB_LUT4_O_1_I1_SB_LUT4_O_I1[1] budget 4.126000 ns (13,7) -> (14,7) Info: Sink soc_I.wb_48m_xclk_I.m_rdata_SB_LUT4_O_1_I1_SB_LUT4_O_LC.I2 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 1.2 9.7 Source soc_I.wb_48m_xclk_I.m_rdata_SB_LUT4_O_1_I1_SB_LUT4_O_LC.O Info: 2.4 12.1 Net soc_I.wb_48m_xclk_I.m_rdata_SB_LUT4_O_1_I1[1] budget 3.587000 ns (14,7) -> (13,9) Info: Sink soc_I.wb_48m_xclk_I.m_rdata_SB_LUT4_O_1_LC.I1 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 1.2 13.3 Setup soc_I.wb_48m_xclk_I.m_rdata_SB_LUT4_O_1_LC.I1 Info: 5.0 ns logic, 8.3 ns routing Info: Max frequency for clock 'clk_sys': 34.12 MHz (PASS at 30.72 MHz) Info: Max frequency for clock 'clk_48m': 51.38 MHz (PASS at 48.00 MHz) Info: Max delay <async> -> posedge clk_sys: 9.74 ns Info: Max delay posedge clk_48m -> <async> : 3.15 ns Info: Max delay posedge clk_48m -> posedge clk_sys: 6.22 ns Info: Max delay posedge clk_sys -> <async> : 14.19 ns Info: Max delay posedge clk_sys -> posedge clk_48m: 13.29 ns Info: Slack histogram: Info: legend: * represents 54 endpoint(s) Info: + represents [1,54) endpoint(s) Info: [ 1369, 5310) |+ Info: [ 5310, 9251) |***+ Info: [ 9251, 13192) |**********+ Info: [ 13192, 17133) |******************************+ Info: [ 17133, 21074) |*****************+ Info: [ 21074, 25015) |*****************************************+ Info: [ 25015, 28956) |************************************************************ Info: [ 28956, 32897) |*+ Info: [ 32897, 36838) | Info: [ 36838, 40779) | Info: [ 40779, 44720) | Info: [ 44720, 48661) | Info: [ 48661, 52602) | Info: [ 52602, 56543) | Info: [ 56543, 60484) | Info: [ 60484, 64425) | Info: [ 64425, 68366) | Info: [ 68366, 72307) |+ Info: [ 72307, 76248) |+ Info: [ 76248, 80189) |+ 4 warnings, 0 errors icepack -s /build/gateware/icE1usb/build-tmp/icE1usb.asc /build/gateware/icE1usb/build-tmp/icE1usb.bin make: Leaving directory '/build/gateware/icE1usb' Finished: SUCCESS