/* * top.v * * vim: ts=4 sw=4 * * Copyright (C) 2022 Sylvain Munaut * SPDX-License-Identifier: CERN-OHL-P-2.0 */ `default_nettype none module top ( // USP tap input wire tap_dp, input wire tap_dn, // USB inout wire usb_dp, inout wire usb_dn, output wire usb_pu, // Flash & PSRAM output wire spi_sck, inout wire [3:0] spi_io, output wire [1:0] spi_cs_n, // UART input wire uart_rx, output wire uart_tx, // Clock input wire clk_in, // Button input wire btn, // RGB LEDs output wire [2:0] rgb ); localparam integer WN = 7; genvar i; // Signals // ------- // Wishbone wire [15:0] wb_addr; wire [31:0] wb_rdata [0:WN-1]; wire [31:0] wb_wdata; wire [3:0] wb_wmsk; wire [WN-1:0] wb_cyc; wire wb_we; wire [WN-1:0] wb_ack; wire [(32*WN)-1:0] wb_rdata_flat; // Misc/Platform reg misc_bus_ack; reg misc_bus_we_csr; reg misc_boot_now; reg [1:0] misc_boot_sel; // Memory interface wire [23:0] mi_addr; wire [ 6:0] mi_len; wire mi_rw; wire mi_valid; wire mi_ready; wire [7:0] mi_wdata; wire mi_wack; wire mi_wlast; wire [7:0] mi_rdata; wire mi_rstb; wire mi_rlast; // QPI PHY wire [7:0] qpi_phy_io_i; wire [7:0] qpi_phy_io_o; wire [3:0] qpi_phy_io_oe; wire [1:0] qpi_phy_clk_o; wire [1:0] qpi_phy_cs_o; // DMA wire dma_req; wire dma_gnt; wire [15:0] dma_addr; wire [31:0] dma_data; wire dma_we; // USB Core // Wishbone in 48 MHz domain wire [11:0] ub_addr; wire [15:0] ub_wdata; wire [15:0] ub_rdata; wire ub_cyc; wire ub_we; wire ub_ack; // EP Buffer wire [ 8:0] ep_tx_addr_0; wire [31:0] ep_tx_data_0; wire ep_tx_we_0; wire [ 8:0] ep_rx_addr_0; wire [31:0] ep_rx_data_1; wire ep_rx_re_0; // Clock / Reset wire clk_1x; wire clk_2x; wire rst; // SoC // --- soc_picorv32_base #( .WB_N (WN), .WB_DW (32), .WB_AW (16), .BRAM_AW (8), // 1k BRAM .SPRAM_AW (14) // 64k SPRAM ) base_I ( .wb_addr (wb_addr), .wb_rdata (wb_rdata_flat), .wb_wdata (wb_wdata), .wb_wmsk (wb_wmsk), .wb_we (wb_we), .wb_cyc (wb_cyc), .wb_ack (wb_ack), .clk (clk_1x), .rst (rst) ); for (i=0; i