Started by upstream project "master-osmo-e1-hardware" build number 1296 originally caused by: Started by timer Running as SYSTEM Building remotely on host2-deb11build-ansible (ttcn3 obs osmocom-gerrit osmocom-master) in workspace /home/osmocom-build/jenkins/workspace/master-osmo-e1-hardware/JOB_TYPE/gateware/a1/default/a3/default/a4/default/label/osmocom-master [ssh-agent] Looking for ssh-agent implementation... [ssh-agent] Exec ssh-agent (binary ssh-agent on a remote machine) $ ssh-agent SSH_AUTH_SOCK=/tmp/ssh-IOqceCAwdo0A/agent.3816450 SSH_AGENT_PID=3816452 [ssh-agent] Started. Running ssh-add (command line suppressed) Identity added: /home/osmocom-build/jenkins/workspace/master-osmo-e1-hardware/JOB_TYPE/gateware/a1/default/a3/default/a4/default/label/osmocom-master@tmp/private_key_7472415933548406230.key (osmocom-jenkins) [ssh-agent] Using credentials binaries (OS#5798) Running ssh-add (command line suppressed) Identity added: /home/osmocom-build/jenkins/workspace/master-osmo-e1-hardware/JOB_TYPE/gateware/a1/default/a3/default/a4/default/label/osmocom-master@tmp/private_key_3516670337451214442.key (osmocom-jenkins) [ssh-agent] Using credentials docs (OS#5798) The recommended git tool is: NONE No credentials specified > git rev-parse --resolve-git-dir /home/osmocom-build/jenkins/workspace/master-osmo-e1-hardware/JOB_TYPE/gateware/a1/default/a3/default/a4/default/label/osmocom-master/.git # timeout=10 Fetching changes from the remote Git repository > git config remote.origin.url https://gerrit.osmocom.org/osmo-e1-hardware # timeout=10 Fetching upstream changes from https://gerrit.osmocom.org/osmo-e1-hardware > git --version # timeout=10 > git --version # 'git version 2.30.2' > git fetch --tags --force --progress -- https://gerrit.osmocom.org/osmo-e1-hardware +refs/heads/*:refs/remotes/origin/* # timeout=10 Checking out Revision b936e3af89559f68870a278f1b0e25ea7449655d (origin/master) > git config core.sparsecheckout # timeout=10 > git checkout -f b936e3af89559f68870a278f1b0e25ea7449655d # timeout=10 Commit message: "icE1usb fw: Ensure alignement of the structure for the usb_data_write" > git rev-list --no-walk b936e3af89559f68870a278f1b0e25ea7449655d # timeout=10 > git remote # timeout=10 > git submodule init # timeout=10 > git submodule sync # timeout=10 > git config --get remote.origin.url # timeout=10 > git submodule init # timeout=10 > git config -f .gitmodules --get-regexp ^submodule\.(.+)\.url # timeout=10 > git config --get submodule.gateware/build.url # timeout=10 > git config -f .gitmodules --get submodule.gateware/build.path # timeout=10 > git config --get submodule.gateware/cores/no2e1.url # timeout=10 > git config -f .gitmodules --get submodule.gateware/cores/no2e1.path # timeout=10 > git config --get submodule.gateware/cores/no2ice40.url # timeout=10 > git config -f .gitmodules --get submodule.gateware/cores/no2ice40.path # timeout=10 > git config --get submodule.gateware/cores/no2misc.url # timeout=10 > git config -f .gitmodules --get submodule.gateware/cores/no2misc.path # timeout=10 > git config --get submodule.gateware/cores/no2usb.url # timeout=10 > git config -f .gitmodules --get submodule.gateware/cores/no2usb.path # timeout=10 > git submodule update --init --recursive gateware/build # timeout=10 > git submodule update --init --recursive gateware/cores/no2e1 # timeout=10 > git submodule update --init --recursive gateware/cores/no2ice40 # timeout=10 > git submodule update --init --recursive gateware/cores/no2misc # timeout=10 > git submodule update --init --recursive gateware/cores/no2usb # timeout=10 [osmocom-master] $ /bin/sh -xe /tmp/jenkins13170300867714408843.sh + DOCKER_IMG=osmocom-build/debian-bookworm-build + DOCKER_IMG=registry.osmocom.org/osmocom-build/fpga-build + docker pull registry.osmocom.org/osmocom-build/fpga-build Using default tag: latest latest: Pulling from osmocom-build/fpga-build 609c73876867: Already exists 380eb531264a: Already exists 3d59ad2386a6: Already exists 0411f100e518: Already exists 705989f1d362: Already exists d58e2f685c2b: Already exists 5c4e78d99f74: Already exists 70583fada898: Already exists 293dd14fd9d5: Already exists c1f60399e306: Already exists b50ce5e41c0f: Pulling fs layer 3e61ffbc57c2: Pulling fs layer 626b7ad105dd: Pulling fs layer 8bd8dcdd1c96: Pulling fs layer def111821763: Pulling fs layer 1f23c531c3f9: Pulling fs layer 7ef0301f70a1: Pulling fs layer 032441e680d8: Pulling fs layer 8bd8dcdd1c96: Waiting def111821763: Waiting 1f23c531c3f9: Waiting 032441e680d8: Waiting 7ef0301f70a1: Waiting b50ce5e41c0f: Download complete 626b7ad105dd: Download complete 3e61ffbc57c2: Download complete def111821763: Verifying Checksum def111821763: Download complete 8bd8dcdd1c96: Download complete b50ce5e41c0f: Pull complete 3e61ffbc57c2: Pull complete 1f23c531c3f9: Verifying Checksum 1f23c531c3f9: Download complete 626b7ad105dd: Pull complete 8bd8dcdd1c96: Pull complete def111821763: Pull complete 1f23c531c3f9: Pull complete 7ef0301f70a1: Verifying Checksum 7ef0301f70a1: Download complete 032441e680d8: Verifying Checksum 032441e680d8: Download complete 7ef0301f70a1: Pull complete 032441e680d8: Pull complete Digest: sha256:1489a10fdaaafb7012d9f2d412fe09e9050870a1f7e59feb64d0808b9010ecb2 Status: Downloaded newer image for registry.osmocom.org/osmocom-build/fpga-build:latest registry.osmocom.org/osmocom-build/fpga-build:latest + readlink -f /tmp/ssh-IOqceCAwdo0A/agent.3816450 + docker run --rm=true --cap-add SYS_PTRACE -e ASCIIDOC_WARNINGS_CHECK=1 -e HOME=/build -e IS_MASTER_BUILD=1 -e JOB_NAME=master-osmo-e1-hardware/JOB_TYPE=gateware,a1=default,a3=default,a4=default,label=osmocom-master -e MAKE=make -e OSMOPY_DEBUG_TCP_SOCKETS=1 -e OSMO_GSM_MANUALS_DIR=/opt/osmo-gsm-manuals -e PARALLEL_MAKE=-j 4 -e PUBLISH=1 -e SSH_AUTH_SOCK=/ssh-agent -e WITH_MANUALS=1 -w /build -i -u build -v /tmp/ssh-IOqceCAwdo0A/agent.3816450:/ssh-agent -v /home/osmocom-build/jenkins/workspace/master-osmo-e1-hardware/JOB_TYPE/gateware/a1/default/a3/default/a4/default/label/osmocom-master:/build -v /home/osmocom-build/.ssh:/home/build/.ssh:ro -e JOB_TYPE=gateware registry.osmocom.org/osmocom-build/fpga-build /usr/bin/timeout 30m /build/contrib/jenkins.sh --publish =============== gateware/e1-tracer GATEWARE ============== make: Entering directory '/build/gateware/e1-tracer' make: Leaving directory '/build/gateware/e1-tracer' make: Entering directory '/build/gateware/e1-tracer' /build/gateware/cores/no2usb//utils/microcode.py > /build/gateware/e1-tracer/build-tmp/usb_trans_mc.hex cp -a /build/gateware/cores/no2usb//data/usb_ep_status.hex /build/gateware/e1-tracer/build-tmp/usb_ep_status.hex cp ../common/fw/boot.hex /build/gateware/e1-tracer/build-tmp/boot.hex cd /build/gateware/e1-tracer/build-tmp && \ yosys -s /build/gateware/e1-tracer/build-tmp/e1-tracer.ys \ -l /build/gateware/e1-tracer/build-tmp/e1-tracer.synth.rpt /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9+3568 (open-tool-forge build) (git sha1 859e52af, gcc 9.3.0-10ubuntu2 -Os) -- Executing script file `/build/gateware/e1-tracer/build-tmp/e1-tracer.ys' -- 1. Executing Verilog-2005 frontend: /build/gateware/e1-tracer/rtl/top.v Parsing Verilog input from `/build/gateware/e1-tracer/rtl/top.v' to AST representation. Generating RTLIL representation for module `\top'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_crc4.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_crc4.v' to AST representation. Generating RTLIL representation for module `\e1_crc4'. Successfully finished Verilog frontend. 3. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v' to AST representation. Generating RTLIL representation for module `\e1_rx_clock_recovery'. Successfully finished Verilog frontend. 4. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v' to AST representation. Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:65) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:204) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:208) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:208) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:209) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:210) is not recognized unless read_verilog is called with -sv! Generating RTLIL representation for module `\e1_rx_deframer'. Successfully finished Verilog frontend. 5. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx_filter.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx_filter.v' to AST representation. Generating RTLIL representation for module `\e1_rx_filter'. Successfully finished Verilog frontend. 6. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx_phy.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx_phy.v' to AST representation. Generating RTLIL representation for module `\e1_rx_phy'. Successfully finished Verilog frontend. 7. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx_liu.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx_liu.v' to AST representation. Generating RTLIL representation for module `\e1_rx_liu'. Successfully finished Verilog frontend. 8. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx.v' to AST representation. Generating RTLIL representation for module `\e1_rx'. Successfully finished Verilog frontend. 9. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_tx_framer.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_tx_framer.v' to AST representation. Generating RTLIL representation for module `\e1_tx_framer'. Successfully finished Verilog frontend. 10. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_tx_phy.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_tx_phy.v' to AST representation. Generating RTLIL representation for module `\e1_tx_phy'. Successfully finished Verilog frontend. 11. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_tx_liu.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_tx_liu.v' to AST representation. Generating RTLIL representation for module `\e1_tx_liu'. Successfully finished Verilog frontend. 12. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_tx.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_tx.v' to AST representation. Generating RTLIL representation for module `\e1_tx'. Successfully finished Verilog frontend. 13. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v' to AST representation. Generating RTLIL representation for module `\e1_buf_if_wb'. Warning: Replacing memory \tx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:165 Warning: Replacing memory \tx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:145 Warning: Replacing memory \rx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:103 Warning: Replacing memory \rx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:102 Successfully finished Verilog frontend. 14. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_wb_rx.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_wb_rx.v' to AST representation. Generating RTLIL representation for module `\e1_wb_rx'. Successfully finished Verilog frontend. 15. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_wb_tx.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_wb_tx.v' to AST representation. Generating RTLIL representation for module `\e1_wb_tx'. Successfully finished Verilog frontend. 16. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_wb.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_wb.v' to AST representation. Generating RTLIL representation for module `\e1_wb'. Successfully finished Verilog frontend. 17. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/hdb3_dec.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/hdb3_dec.v' to AST representation. Generating RTLIL representation for module `\hdb3_dec'. Successfully finished Verilog frontend. 18. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/hdb3_enc.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/hdb3_enc.v' to AST representation. Generating RTLIL representation for module `\hdb3_enc'. Successfully finished Verilog frontend. 19. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_ebr.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_ebr.v' to AST representation. Generating RTLIL representation for module `\ice40_ebr'. Successfully finished Verilog frontend. 20. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_i2c_wb.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_i2c_wb.v' to AST representation. Generating RTLIL representation for module `\ice40_i2c_wb'. Successfully finished Verilog frontend. 21. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v' to AST representation. Generating RTLIL representation for module `\ice40_rgb_wb'. Successfully finished Verilog frontend. 22. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_spi_wb.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_spi_wb.v' to AST representation. Generating RTLIL representation for module `\ice40_spi_wb'. Successfully finished Verilog frontend. 23. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v' to AST representation. Generating RTLIL representation for module `\ice40_spram_gen'. ice40_spram_gen: (32768x32) -> 2x2 array of SPRAM Successfully finished Verilog frontend. 24. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v' to AST representation. Generating RTLIL representation for module `\ice40_spram_wb'. Successfully finished Verilog frontend. 25. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_iserdes.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_iserdes.v' to AST representation. Generating RTLIL representation for module `\ice40_iserdes'. Successfully finished Verilog frontend. 26. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_oserdes.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_oserdes.v' to AST representation. Generating RTLIL representation for module `\ice40_oserdes'. Successfully finished Verilog frontend. 27. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_serdes_crg.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_serdes_crg.v' to AST representation. Generating RTLIL representation for module `\ice40_serdes_crg'. Successfully finished Verilog frontend. 28. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_serdes_dff.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_serdes_dff.v' to AST representation. Generating RTLIL representation for module `\ice40_serdes_dff'. Successfully finished Verilog frontend. 29. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_serdes_sync.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_serdes_sync.v' to AST representation. Generating RTLIL representation for module `\ice40_serdes_sync'. Successfully finished Verilog frontend. 30. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/delay.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/delay.v' to AST representation. Generating RTLIL representation for module `\delay_bit'. Generating RTLIL representation for module `\delay_bus'. Warning: Replacing memory \dl with list of registers. See /build/gateware/cores/no2misc//rtl/delay.v:59 Generating RTLIL representation for module `\delay_toggle'. Successfully finished Verilog frontend. 31. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/fifo_sync_ram.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v' to AST representation. Generating RTLIL representation for module `\fifo_sync_ram'. Successfully finished Verilog frontend. 32. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/fifo_sync_shift.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v' to AST representation. Generating RTLIL representation for module `\fifo_sync_shift'. Successfully finished Verilog frontend. 33. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/glitch_filter.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/glitch_filter.v' to AST representation. Generating RTLIL representation for module `\glitch_filter'. Successfully finished Verilog frontend. 34. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/i2c_master.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/i2c_master.v' to AST representation. Generating RTLIL representation for module `\i2c_master'. Successfully finished Verilog frontend. 35. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/i2c_master_wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/i2c_master_wb.v' to AST representation. Generating RTLIL representation for module `\i2c_master_wb'. Successfully finished Verilog frontend. 36. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/muacm2wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/muacm2wb.v' to AST representation. Generating RTLIL representation for module `\muacm2wb'. Successfully finished Verilog frontend. 37. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/prims.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/prims.v' to AST representation. Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:31) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:75) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:117) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:150) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:186) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:237) is not recognized unless read_verilog is called with -sv! Generating RTLIL representation for module `\lut4_n'. Generating RTLIL representation for module `\lut4_carry_n'. Generating RTLIL representation for module `\dff_n'. Generating RTLIL representation for module `\dffe_n'. Generating RTLIL representation for module `\dffer_n'. Generating RTLIL representation for module `\dffesr_n'. Successfully finished Verilog frontend. 38. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/pdm.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/pdm.v' to AST representation. Warning: Yosys has only limited support for tri-state logic at the moment. (/build/gateware/cores/no2misc//rtl/pdm.v:91) Generating RTLIL representation for module `\pdm'. Generating RTLIL representation for module `\pdm_lfsr'. Successfully finished Verilog frontend. 39. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/pwm.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/pwm.v' to AST representation. Warning: Yosys has only limited support for tri-state logic at the moment. (/build/gateware/cores/no2misc//rtl/pwm.v:69) Generating RTLIL representation for module `\pwm'. Successfully finished Verilog frontend. 40. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/ram_sdp.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/ram_sdp.v' to AST representation. Generating RTLIL representation for module `\ram_sdp'. Successfully finished Verilog frontend. 41. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/stream2wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/stream2wb.v' to AST representation. Generating RTLIL representation for module `\stream2wb'. Successfully finished Verilog frontend. 42. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/uart2wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/uart2wb.v' to AST representation. Generating RTLIL representation for module `\uart2wb'. Successfully finished Verilog frontend. 43. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/uart_rx.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/uart_rx.v' to AST representation. Generating RTLIL representation for module `\uart_rx'. Successfully finished Verilog frontend. 44. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/uart_tx.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/uart_tx.v' to AST representation. Generating RTLIL representation for module `\uart_tx'. Successfully finished Verilog frontend. 45. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/uart_wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/uart_wb.v' to AST representation. Generating RTLIL representation for module `\uart_wb'. Successfully finished Verilog frontend. 46. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/xclk_strobe.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/xclk_strobe.v' to AST representation. Generating RTLIL representation for module `\xclk_strobe'. Successfully finished Verilog frontend. 47. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/xclk_wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/xclk_wb.v' to AST representation. Generating RTLIL representation for module `\xclk_wb'. Successfully finished Verilog frontend. 48. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb.v' to AST representation. Generating RTLIL representation for module `\usb'. Successfully finished Verilog frontend. 49. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_crc.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_crc.v' to AST representation. Generating RTLIL representation for module `\usb_crc'. Successfully finished Verilog frontend. 50. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_ep_buf.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_ep_buf.v' to AST representation. Generating RTLIL representation for module `\usb_ep_buf'. READ_MODE : 3 WRITE_MODE : 3 Successfully finished Verilog frontend. 51. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_ep_status.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_ep_status.v' to AST representation. Generating RTLIL representation for module `\usb_ep_status'. Successfully finished Verilog frontend. 52. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_phy.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_phy.v' to AST representation. Generating RTLIL representation for module `\usb_phy'. Successfully finished Verilog frontend. 53. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_rx_ll.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_rx_ll.v' to AST representation. Generating RTLIL representation for module `\usb_rx_ll'. Successfully finished Verilog frontend. 54. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_rx_pkt.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v' to AST representation. Generating RTLIL representation for module `\usb_rx_pkt'. Successfully finished Verilog frontend. 55. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_trans.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_trans.v' to AST representation. Generating RTLIL representation for module `\usb_trans'. Successfully finished Verilog frontend. 56. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_tx_ll.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_tx_ll.v' to AST representation. Generating RTLIL representation for module `\usb_tx_ll'. Successfully finished Verilog frontend. 57. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_tx_pkt.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v' to AST representation. Generating RTLIL representation for module `\usb_tx_pkt'. Successfully finished Verilog frontend. 58. Executing Verilog-2005 frontend: /build/gateware/e1-tracer/rtl/misc.v Parsing Verilog input from `/build/gateware/e1-tracer/rtl/misc.v' to AST representation. Generating RTLIL representation for module `\misc'. Successfully finished Verilog frontend. 59. Executing Verilog-2005 frontend: /build/gateware/e1-tracer/rtl/sysmgr.v Parsing Verilog input from `/build/gateware/e1-tracer/rtl/sysmgr.v' to AST representation. Generating RTLIL representation for module `\sysmgr'. Successfully finished Verilog frontend. 60. Executing Verilog-2005 frontend: /build/gateware/common/rtl/capcnt.v Parsing Verilog input from `/build/gateware/common/rtl/capcnt.v' to AST representation. Generating RTLIL representation for module `\capcnt'. Successfully finished Verilog frontend. 61. Executing Verilog-2005 frontend: /build/gateware/common/rtl/capcnt_sb_mac16.v Parsing Verilog input from `/build/gateware/common/rtl/capcnt_sb_mac16.v' to AST representation. Generating RTLIL representation for module `\capcnt16_sb_mac16'. Generating RTLIL representation for module `\capcnt32_sb_mac16'. Successfully finished Verilog frontend. 62. Executing Verilog-2005 frontend: /build/gateware/common/rtl/dfu_helper.v Parsing Verilog input from `/build/gateware/common/rtl/dfu_helper.v' to AST representation. Generating RTLIL representation for module `\dfu_helper'. Successfully finished Verilog frontend. 63. Executing Verilog-2005 frontend: /build/gateware/common/rtl/picorv32.v Parsing Verilog input from `/build/gateware/common/rtl/picorv32.v' to AST representation. Generating RTLIL representation for module `\picorv32'. Generating RTLIL representation for module `\picorv32_regs'. Generating RTLIL representation for module `\picorv32_pcpi_mul'. Generating RTLIL representation for module `\picorv32_pcpi_fast_mul'. Generating RTLIL representation for module `\picorv32_pcpi_div'. Generating RTLIL representation for module `\picorv32_axi'. Generating RTLIL representation for module `\picorv32_axi_adapter'. Generating RTLIL representation for module `\picorv32_wb'. Successfully finished Verilog frontend. 64. Executing Verilog-2005 frontend: /build/gateware/common/rtl/picorv32_ice40_regs.v Parsing Verilog input from `/build/gateware/common/rtl/picorv32_ice40_regs.v' to AST representation. Generating RTLIL representation for module `\picorv32_ice40_regs'. Successfully finished Verilog frontend. 65. Executing Verilog-2005 frontend: /build/gateware/common/rtl/soc_base.v Parsing Verilog input from `/build/gateware/common/rtl/soc_base.v' to AST representation. Generating RTLIL representation for module `\soc_base'. Successfully finished Verilog frontend. 66. Executing Verilog-2005 frontend: /build/gateware/common/rtl/soc_bram.v Parsing Verilog input from `/build/gateware/common/rtl/soc_bram.v' to AST representation. Generating RTLIL representation for module `\soc_bram'. Successfully finished Verilog frontend. 67. Executing Verilog-2005 frontend: /build/gateware/common/rtl/soc_iobuf.v Parsing Verilog input from `/build/gateware/common/rtl/soc_iobuf.v' to AST representation. Generating RTLIL representation for module `\soc_iobuf'. Successfully finished Verilog frontend. 68. Executing Verilog-2005 frontend: /build/gateware/common/rtl/soc_picorv32_bridge.v Parsing Verilog input from `/build/gateware/common/rtl/soc_picorv32_bridge.v' to AST representation. Generating RTLIL representation for module `\soc_picorv32_bridge'. Successfully finished Verilog frontend. 69. Executing Verilog-2005 frontend: /build/gateware/common/rtl/soc_spram.v Parsing Verilog input from `/build/gateware/common/rtl/soc_spram.v' to AST representation. Generating RTLIL representation for module `\soc_spram'. Successfully finished Verilog frontend. 70. Executing Verilog-2005 frontend: /build/gateware/common/rtl/wb_arbiter.v Parsing Verilog input from `/build/gateware/common/rtl/wb_arbiter.v' to AST representation. Generating RTLIL representation for module `\wb_arbiter'. Successfully finished Verilog frontend. 71. Executing Verilog-2005 frontend: /build/gateware/common/rtl/wb_dma.v Parsing Verilog input from `/build/gateware/common/rtl/wb_dma.v' to AST representation. Generating RTLIL representation for module `\wb_dma'. Successfully finished Verilog frontend. 72. Executing Verilog-2005 frontend: /build/gateware/common/rtl/wb_epbuf.v Parsing Verilog input from `/build/gateware/common/rtl/wb_epbuf.v' to AST representation. Generating RTLIL representation for module `\wb_epbuf'. Successfully finished Verilog frontend. 73. Executing SYNTH_ICE40 pass. 73.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v' to AST representation. Generating RTLIL representation for module `\SB_IO'. Generating RTLIL representation for module `\SB_GB_IO'. Generating RTLIL representation for module `\SB_GB'. Generating RTLIL representation for module `\SB_LUT4'. Generating RTLIL representation for module `\SB_CARRY'. Generating RTLIL representation for module `\SB_DFF'. Generating RTLIL representation for module `\SB_DFFE'. Generating RTLIL representation for module `\SB_DFFSR'. Generating RTLIL representation for module `\SB_DFFR'. Generating RTLIL representation for module `\SB_DFFSS'. Generating RTLIL representation for module `\SB_DFFS'. Generating RTLIL representation for module `\SB_DFFESR'. Generating RTLIL representation for module `\SB_DFFER'. Generating RTLIL representation for module `\SB_DFFESS'. Generating RTLIL representation for module `\SB_DFFES'. Generating RTLIL representation for module `\SB_DFFN'. Generating RTLIL representation for module `\SB_DFFNE'. Generating RTLIL representation for module `\SB_DFFNSR'. Generating RTLIL representation for module `\SB_DFFNR'. Generating RTLIL representation for module `\SB_DFFNSS'. Generating RTLIL representation for module `\SB_DFFNS'. Generating RTLIL representation for module `\SB_DFFNESR'. Generating RTLIL representation for module `\SB_DFFNER'. Generating RTLIL representation for module `\SB_DFFNESS'. Generating RTLIL representation for module `\SB_DFFNES'. Generating RTLIL representation for module `\SB_RAM40_4K'. Generating RTLIL representation for module `\SB_RAM40_4KNR'. Generating RTLIL representation for module `\SB_RAM40_4KNW'. Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. Generating RTLIL representation for module `\ICESTORM_LC'. Generating RTLIL representation for module `\SB_PLL40_CORE'. Generating RTLIL representation for module `\SB_PLL40_PAD'. Generating RTLIL representation for module `\SB_PLL40_2_PAD'. Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. Generating RTLIL representation for module `\SB_WARMBOOT'. Generating RTLIL representation for module `\SB_SPRAM256KA'. Generating RTLIL representation for module `\SB_HFOSC'. Generating RTLIL representation for module `\SB_LFOSC'. Generating RTLIL representation for module `\SB_RGBA_DRV'. Generating RTLIL representation for module `\SB_LED_DRV_CUR'. Generating RTLIL representation for module `\SB_RGB_DRV'. Generating RTLIL representation for module `\SB_I2C'. Generating RTLIL representation for module `\SB_SPI'. Generating RTLIL representation for module `\SB_LEDDA_IP'. Generating RTLIL representation for module `\SB_FILTER_50NS'. Generating RTLIL representation for module `\SB_IO_I3C'. Generating RTLIL representation for module `\SB_IO_OD'. Generating RTLIL representation for module `\SB_MAC16'. Generating RTLIL representation for module `\ICESTORM_RAM'. Successfully finished Verilog frontend. 73.2. Executing HIERARCHY pass (managing design hierarchy). 73.2.1. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: \ice40_spi_wb Used module: \misc Used module: \capcnt Used module: \capcnt16_sb_mac16 Used module: \dfu_helper Used module: \glitch_filter Used module: \soc_base Used module: \e1_buf_if_wb Used module: \e1_wb Used module: \e1_wb_tx Used module: \e1_tx Used module: \e1_tx_phy Used module: \hdb3_enc Used module: \e1_tx_framer Used module: \e1_crc4 Used module: \fifo_sync_shift Used module: \e1_wb_rx Used module: \e1_rx Used module: \hdb3_dec Used module: \e1_rx_clock_recovery Used module: \e1_rx_filter Used module: \e1_rx_phy Used module: \e1_rx_deframer Used module: \soc_iobuf Used module: \wb_dma Used module: \wb_arbiter Used module: \wb_epbuf Used module: \ice40_spram_wb Used module: \ice40_spram_gen Used module: \xclk_strobe Used module: \xclk_wb Used module: \usb Used module: \usb_ep_status Used module: \usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: \usb_crc Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: \usb_phy Used module: \ice40_rgb_wb Used module: \uart_wb Used module: \fifo_sync_ram Used module: \ram_sdp Used module: \uart_rx Used module: \uart_tx Used module: \soc_spram Used module: \soc_bram Used module: \soc_picorv32_bridge Used module: \picorv32 Used module: \picorv32_ice40_regs Used module: \ice40_ebr Parameter \N_CS = 2 Parameter \WITH_IOB = 1 Parameter \UNIT = 1 73.2.2. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_spi_wb'. Parameter \N_CS = 2 Parameter \WITH_IOB = 1 Parameter \UNIT = 1 Generating RTLIL representation for module `$paramod\ice40_spi_wb\N_CS=2\WITH_IOB=1\UNIT=1'. Parameter \WB_N = 2 Parameter \E1_N = 2 Parameter \E1_UNIT_HAS_RX = 2'11 Parameter \E1_UNIT_HAS_TX = 2'00 Parameter \E1_LIU = 1 73.2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_base'. Parameter \WB_N = 2 Parameter \E1_N = 2 Parameter \E1_UNIT_HAS_RX = 2'11 Parameter \E1_UNIT_HAS_TX = 2'00 Parameter \E1_LIU = 1 Generating RTLIL representation for module `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base'. Parameter \N = 1 Parameter \UNIT_HAS_RX = 1'1 Parameter \UNIT_HAS_TX = 1'1 Parameter \MFW = 7 Parameter \DW = 32 73.2.4. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_buf_if_wb'. Parameter \N = 1 Parameter \UNIT_HAS_RX = 1'1 Parameter \UNIT_HAS_TX = 1'1 Parameter \MFW = 7 Parameter \DW = 32 Generating RTLIL representation for module `$paramod\e1_buf_if_wb\N=1\UNIT_HAS_RX=1'1\UNIT_HAS_TX=1'1\MFW=7\DW=32'. Warning: Replacing memory \tx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:165 Warning: Replacing memory \tx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:145 Warning: Replacing memory \rx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:103 Warning: Replacing memory \rx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:102 Parameter \N = 1 Parameter \UNIT_HAS_RX = 1'1 Parameter \UNIT_HAS_TX = 1'1 Parameter \LIU = 0 Parameter \MFW = 7 73.2.5. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_wb'. Parameter \N = 1 Parameter \UNIT_HAS_RX = 1'1 Parameter \UNIT_HAS_TX = 1'1 Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_wb\N=1\UNIT_HAS_RX=1'1\UNIT_HAS_TX=1'1\LIU=0\MFW=7'. Parameter \DW = 16 Parameter \AW = 12 73.2.6. Executing AST frontend in derive mode using pre-parsed AST for module `\xclk_wb'. Parameter \DW = 16 Parameter \AW = 12 Generating RTLIL representation for module `$paramod\xclk_wb\DW=16\AW=12'. Parameter \EPDW = 32 73.2.7. Executing AST frontend in derive mode using pre-parsed AST for module `\usb'. Parameter \EPDW = 32 Generating RTLIL representation for module `$paramod\usb\EPDW=32'. Parameter \CURRENT_MODE = 24'001100000110001000110001 Parameter \RGB0_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB1_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB2_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 73.2.8. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_rgb_wb'. Parameter \CURRENT_MODE = 24'001100000110001000110001 Parameter \RGB0_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB1_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB2_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Generating RTLIL representation for module `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb'. Parameter \DIV_WIDTH = 12 Parameter \DW = 32 73.2.9. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_wb'. Parameter \DIV_WIDTH = 12 Parameter \DW = 32 Generating RTLIL representation for module `$paramod\uart_wb\DIV_WIDTH=12\DW=32'. Parameter \N_CS = 1 Parameter \WITH_IOB = 0 Parameter \UNIT = 0 73.2.10. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_spi_wb'. Parameter \N_CS = 1 Parameter \WITH_IOB = 0 Parameter \UNIT = 0 Generating RTLIL representation for module `$paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0'. Parameter \AW = 14 73.2.11. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_spram'. Parameter \AW = 14 Generating RTLIL representation for module `$paramod\soc_spram\AW=14'. Parameter \AW = 8 Parameter \INIT_FILE = 64'0110001001101111011011110111010000101110011010000110010101111000 73.2.12. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_bram'. Parameter \AW = 8 Parameter \INIT_FILE = 64'0110001001101111011011110111010000101110011010000110010101111000 Generating RTLIL representation for module `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram'. Parameter \WB_N = 9 Parameter \WB_DW = 32 Parameter \WB_AW = 16 Parameter \WB_AI = 2 Parameter \WB_REG = 4 73.2.13. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_picorv32_bridge'. Parameter \WB_N = 9 Parameter \WB_DW = 32 Parameter \WB_AW = 16 Parameter \WB_AI = 2 Parameter \WB_REG = 4 Generating RTLIL representation for module `$paramod\soc_picorv32_bridge\WB_N=9\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4'. Parameter \ENABLE_COUNTERS = 0 Parameter \BARREL_SHIFTER = 0 Parameter \TWO_CYCLE_COMPARE = 0 Parameter \TWO_CYCLE_ALU = 0 Parameter \COMPRESSED_ISA = 0 Parameter \CATCH_MISALIGN = 0 Parameter \CATCH_ILLINSN = 0 Parameter \ENABLE_MUL = 0 Parameter \ENABLE_DIV = 0 Parameter \ENABLE_IRQ = 0 Parameter \ENABLE_IRQ_QREGS = 0 Parameter \PROGADDR_RESET = 0 Parameter \STACKADDR = 1024 73.2.14. Executing AST frontend in derive mode using pre-parsed AST for module `\picorv32'. Parameter \ENABLE_COUNTERS = 0 Parameter \BARREL_SHIFTER = 0 Parameter \TWO_CYCLE_COMPARE = 0 Parameter \TWO_CYCLE_ALU = 0 Parameter \COMPRESSED_ISA = 0 Parameter \CATCH_MISALIGN = 0 Parameter \CATCH_ILLINSN = 0 Parameter \ENABLE_MUL = 0 Parameter \ENABLE_DIV = 0 Parameter \ENABLE_IRQ = 0 Parameter \ENABLE_IRQ_QREGS = 0 Parameter \PROGADDR_RESET = 0 Parameter \STACKADDR = 1024 Generating RTLIL representation for module `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32'. Parameter \W = 16 73.2.15. Executing AST frontend in derive mode using pre-parsed AST for module `\capcnt'. Parameter \W = 16 Generating RTLIL representation for module `$paramod\capcnt\W=16'. Parameter \W = 16 Found cached RTLIL representation for module `$paramod\capcnt\W=16'. Parameter \TIMER_WIDTH = 26 Parameter \BTN_MODE = 3 Parameter \DFU_MODE = 0 73.2.16. Executing AST frontend in derive mode using pre-parsed AST for module `\dfu_helper'. Parameter \TIMER_WIDTH = 26 Parameter \BTN_MODE = 3 Parameter \DFU_MODE = 0 Generating RTLIL representation for module `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0'. Parameter \W = 32 73.2.17. Executing AST frontend in derive mode using pre-parsed AST for module `\capcnt'. Parameter \W = 32 Generating RTLIL representation for module `$paramod\capcnt\W=32'. Parameter \LIU = 0 Parameter \MFW = 7 73.2.18. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_rx'. Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_rx\LIU=0\MFW=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 73.2.19. Executing AST frontend in derive mode using pre-parsed AST for module `\fifo_sync_shift'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 Generating RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 73.2.20. Executing AST frontend in derive mode using pre-parsed AST for module `\fifo_sync_shift'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 Generating RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7'. Parameter \LIU = 0 Parameter \MFW = 7 73.2.21. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_tx'. Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_tx\LIU=0\MFW=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9'. Parameter \LIU = 0 Parameter \MFW = 7 73.2.22. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_wb_tx'. Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_wb_tx\LIU=0\MFW=7'. Parameter \LIU = 0 Parameter \MFW = 7 73.2.23. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_wb_rx'. Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_wb_rx\LIU=0\MFW=7'. Parameter \ADDR_WIDTH = 14 Parameter \DATA_WIDTH = 32 73.2.24. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_spram_gen'. Parameter \ADDR_WIDTH = 14 Parameter \DATA_WIDTH = 32 Generating RTLIL representation for module `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32'. ice40_spram_gen: (16384x32) -> 1x2 array of SPRAM Parameter \AWIDTH = 8 Parameter \DWIDTH = 16 73.2.25. Executing AST frontend in derive mode using pre-parsed AST for module `\ram_sdp'. Parameter \AWIDTH = 8 Parameter \DWIDTH = 16 Generating RTLIL representation for module `$paramod\ram_sdp\AWIDTH=8\DWIDTH=16'. Parameter \L = 2 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 73.2.26. Executing AST frontend in derive mode using pre-parsed AST for module `\glitch_filter'. Parameter \L = 2 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Generating RTLIL representation for module `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1'. Parameter \DEPTH = 512 Parameter \WIDTH = 8 73.2.27. Executing AST frontend in derive mode using pre-parsed AST for module `\fifo_sync_ram'. Parameter \DEPTH = 512 Parameter \WIDTH = 8 Generating RTLIL representation for module `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8'. Parameter \DIV_WIDTH = 8 Parameter \GLITCH_FILTER = 2 73.2.28. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'. Parameter \DIV_WIDTH = 8 Parameter \GLITCH_FILTER = 2 Generating RTLIL representation for module `$paramod\uart_rx\DIV_WIDTH=8\GLITCH_FILTER=2'. Parameter \DEPTH = 512 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8'. Parameter \DIV_WIDTH = 8 73.2.29. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'. Parameter \DIV_WIDTH = 8 Generating RTLIL representation for module `$paramod\uart_tx\DIV_WIDTH=8'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 16 Parameter \WWIDTH = 8 73.2.30. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_ep_buf'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 16 Parameter \WWIDTH = 8 Generating RTLIL representation for module `$paramod$7d82212fad3e4929db14b64ca83adffce21ba555\usb_ep_buf'. READ_MODE : 2 WRITE_MODE : 3 Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 8 Parameter \WWIDTH = 16 73.2.31. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_ep_buf'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 8 Parameter \WWIDTH = 16 Generating RTLIL representation for module `$paramod$e9a8417cc0e9fc03e370009e77135e9e1e2b5499\usb_ep_buf'. READ_MODE : 3 WRITE_MODE : 2 Parameter \TARGET = 40'0100100101000011010001010011010000110000 73.2.32. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_phy'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Generating RTLIL representation for module `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000'. Parameter \WIDTH = 16 Parameter \POLY = 16'1000000000000101 Parameter \MATCH = 16'1000000000001101 73.2.33. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_crc'. Parameter \WIDTH = 16 Parameter \POLY = 16'1000000000000101 Parameter \MATCH = 16'1000000000001101 Generating RTLIL representation for module `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101'. Parameter \WIDTH = 16 Parameter \POLY = 16'1000000000000101 Parameter \MATCH = 16'1000000000001101 Found cached RTLIL representation for module `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101'. Parameter \WIDTH = 5 Parameter \POLY = 5'00101 Parameter \MATCH = 5'01100 73.2.34. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_crc'. Parameter \WIDTH = 5 Parameter \POLY = 5'00101 Parameter \MATCH = 5'01100 Generating RTLIL representation for module `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100'. Parameter \L = 4 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Parameter \WITH_SAMP_COND = 1'0 73.2.35. Executing AST frontend in derive mode using pre-parsed AST for module `\glitch_filter'. Parameter \L = 4 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Parameter \WITH_SAMP_COND = 1'0 Generating RTLIL representation for module `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0'. Parameter \READ_MODE = 0 Parameter \WRITE_MODE = 0 Parameter \MASK_WORKAROUND = 0 Parameter \NEG_WR_CLK = 0 Parameter \NEG_RD_CLK = 1 73.2.36. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_ebr'. Parameter \READ_MODE = 0 Parameter \WRITE_MODE = 0 Parameter \MASK_WORKAROUND = 0 Parameter \NEG_WR_CLK = 0 Parameter \NEG_RD_CLK = 1 Generating RTLIL representation for module `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr'. Parameter \READ_MODE = 0 Parameter \WRITE_MODE = 0 Parameter \MASK_WORKAROUND = 0 Parameter \NEG_WR_CLK = 0 Parameter \NEG_RD_CLK = 1 Found cached RTLIL representation for module `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr'. Parameter \READ_MODE = 0 Parameter \WRITE_MODE = 0 Parameter \MASK_WORKAROUND = 0 Parameter \NEG_WR_CLK = 0 Parameter \NEG_RD_CLK = 1 Found cached RTLIL representation for module `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr'. Parameter \READ_MODE = 0 Parameter \WRITE_MODE = 0 Parameter \MASK_WORKAROUND = 0 Parameter \NEG_WR_CLK = 0 Parameter \NEG_RD_CLK = 1 Found cached RTLIL representation for module `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr'. Parameter \ADDR_WIDTH = 14 Parameter \DATA_WIDTH = 32 Found cached RTLIL representation for module `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32'. Parameter \A0W = 14 Parameter \A1W = 9 Parameter \DW = 32 73.2.37. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_dma'. Parameter \A0W = 14 Parameter \A1W = 9 Parameter \DW = 32 Generating RTLIL representation for module `$paramod\wb_dma\A0W=14\A1W=9\DW=32'. Parameter \N = 2 Parameter \DW = 32 Parameter \AW = 9 73.2.38. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_arbiter'. Parameter \N = 2 Parameter \DW = 32 Parameter \AW = 9 Generating RTLIL representation for module `$paramod\wb_arbiter\N=2\DW=32\AW=9'. Parameter \AW = 9 Parameter \DW = 32 73.2.39. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_epbuf'. Parameter \AW = 9 Parameter \DW = 32 Generating RTLIL representation for module `$paramod\wb_epbuf\AW=9\DW=32'. Parameter \N = 3 Parameter \DW = 32 Parameter \AW = 14 73.2.40. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_arbiter'. Parameter \N = 3 Parameter \DW = 32 Parameter \AW = 14 Generating RTLIL representation for module `$paramod\wb_arbiter\N=3\DW=32\AW=14'. Parameter \AW = 14 Parameter \DW = 32 Parameter \ZERO_RDATA = 0 73.2.41. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_spram_wb'. Parameter \AW = 14 Parameter \DW = 32 Parameter \ZERO_RDATA = 0 Generating RTLIL representation for module `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0'. 73.2.42. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: $paramod\ice40_spi_wb\N_CS=2\WITH_IOB=1\UNIT=1 Used module: \misc Used module: $paramod\capcnt\W=16 Used module: \capcnt16_sb_mac16 Used module: $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0 Used module: \glitch_filter Used module: $paramod\capcnt\W=32 Used module: \capcnt32_sb_mac16 Used module: $paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base Used module: \e1_buf_if_wb Used module: \e1_wb Used module: $paramod\e1_wb_tx\LIU=0\MFW=7 Used module: \e1_tx Used module: \e1_tx_phy Used module: \hdb3_enc Used module: \e1_tx_framer Used module: \e1_crc4 Used module: \fifo_sync_shift Used module: $paramod\e1_wb_rx\LIU=0\MFW=7 Used module: \e1_rx Used module: \hdb3_dec Used module: \e1_rx_clock_recovery Used module: \e1_rx_filter Used module: \e1_rx_phy Used module: \e1_rx_deframer Used module: \soc_iobuf Used module: $paramod\wb_dma\A0W=14\A1W=9\DW=32 Used module: $paramod\wb_arbiter\N=2\DW=32\AW=9 Used module: $paramod\wb_epbuf\AW=9\DW=32 Used module: $paramod\wb_arbiter\N=3\DW=32\AW=14 Used module: $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0 Used module: \ice40_spram_gen Used module: \xclk_strobe Used module: \xclk_wb Used module: \usb Used module: \usb_ep_status Used module: $paramod$7d82212fad3e4929db14b64ca83adffce21ba555\usb_ep_buf Used module: $paramod$e9a8417cc0e9fc03e370009e77135e9e1e2b5499\usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101 Used module: $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100 Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000 Used module: \ice40_rgb_wb Used module: \uart_wb Used module: $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8 Used module: \ram_sdp Used module: $paramod\uart_rx\DIV_WIDTH=8\GLITCH_FILTER=2 Used module: $paramod\uart_tx\DIV_WIDTH=8 Used module: \ice40_spi_wb Used module: \soc_spram Used module: $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32 Used module: \soc_bram Used module: \soc_picorv32_bridge Used module: \picorv32 Used module: \picorv32_ice40_regs Used module: $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr Parameter \L = 4 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Parameter \WITH_SAMP_COND = 1'0 Found cached RTLIL representation for module `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0'. Parameter \N = 2 Parameter \UNIT_HAS_RX = 2'11 Parameter \UNIT_HAS_TX = 2'00 Parameter \MFW = 7 Parameter \DW = 32 73.2.43. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_buf_if_wb'. Parameter \N = 2 Parameter \UNIT_HAS_RX = 2'11 Parameter \UNIT_HAS_TX = 2'00 Parameter \MFW = 7 Parameter \DW = 32 Generating RTLIL representation for module `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32'. Warning: Replacing memory \tx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:176 Warning: Replacing memory \tx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:175 Warning: Replacing memory \rx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:103 Warning: Replacing memory \rx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:102 Parameter \N = 2 Parameter \UNIT_HAS_RX = 2'11 Parameter \UNIT_HAS_TX = 2'00 Parameter \LIU = 1 Parameter \MFW = 7 73.2.44. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_wb'. Parameter \N = 2 Parameter \UNIT_HAS_RX = 2'11 Parameter \UNIT_HAS_TX = 2'00 Parameter \LIU = 1 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7'. Parameter \DW = 16 Parameter \AW = 12 Found cached RTLIL representation for module `$paramod\xclk_wb\DW=16\AW=12'. Parameter \EPDW = 32 Found cached RTLIL representation for module `$paramod\usb\EPDW=32'. Parameter \CURRENT_MODE = 24'001100000110001000110001 Parameter \RGB0_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB1_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB2_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Found cached RTLIL representation for module `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb'. Parameter \DIV_WIDTH = 12 Parameter \DW = 32 Found cached RTLIL representation for module `$paramod\uart_wb\DIV_WIDTH=12\DW=32'. Parameter \N_CS = 1 Parameter \WITH_IOB = 0 Parameter \UNIT = 0 Found cached RTLIL representation for module `$paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0'. Parameter \AW = 14 Found cached RTLIL representation for module `$paramod\soc_spram\AW=14'. Parameter \AW = 8 Parameter \INIT_FILE = 64'0110001001101111011011110111010000101110011010000110010101111000 Found cached RTLIL representation for module `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram'. Parameter \WB_N = 10 Parameter \WB_DW = 32 Parameter \WB_AW = 16 Parameter \WB_AI = 2 Parameter \WB_REG = 4 73.2.45. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_picorv32_bridge'. Parameter \WB_N = 10 Parameter \WB_DW = 32 Parameter \WB_AW = 16 Parameter \WB_AI = 2 Parameter \WB_REG = 4 Generating RTLIL representation for module `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4'. Parameter \ENABLE_COUNTERS = 0 Parameter \BARREL_SHIFTER = 0 Parameter \TWO_CYCLE_COMPARE = 0 Parameter \TWO_CYCLE_ALU = 0 Parameter \COMPRESSED_ISA = 0 Parameter \CATCH_MISALIGN = 0 Parameter \CATCH_ILLINSN = 0 Parameter \ENABLE_MUL = 0 Parameter \ENABLE_DIV = 0 Parameter \ENABLE_IRQ = 0 Parameter \ENABLE_IRQ_QREGS = 0 Parameter \PROGADDR_RESET = 0 Parameter \STACKADDR = 1024 Found cached RTLIL representation for module `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32'. Parameter \LIU = 0 Parameter \MFW = 7 Found cached RTLIL representation for module `$paramod\e1_tx\LIU=0\MFW=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9'. Parameter \LIU = 0 Parameter \MFW = 7 Found cached RTLIL representation for module `$paramod\e1_rx\LIU=0\MFW=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7'. Parameter \AWIDTH = 9 Parameter \DWIDTH = 8 73.2.46. Executing AST frontend in derive mode using pre-parsed AST for module `\ram_sdp'. Parameter \AWIDTH = 9 Parameter \DWIDTH = 8 Generating RTLIL representation for module `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8'. Parameter \L = 2 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Found cached RTLIL representation for module `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1'. Parameter \ADDR_WIDTH = 14 Parameter \DATA_WIDTH = 32 Found cached RTLIL representation for module `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32'. 73.2.47. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: $paramod\ice40_spi_wb\N_CS=2\WITH_IOB=1\UNIT=1 Used module: \misc Used module: $paramod\capcnt\W=16 Used module: \capcnt16_sb_mac16 Used module: $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0 Used module: $paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0 Used module: $paramod\capcnt\W=32 Used module: \capcnt32_sb_mac16 Used module: $paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base Used module: $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32 Used module: $paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7 Used module: \e1_wb_rx Used module: $paramod\e1_rx\LIU=0\MFW=7 Used module: \hdb3_dec Used module: \e1_rx_clock_recovery Used module: \e1_rx_filter Used module: \e1_rx_phy Used module: \e1_rx_deframer Used module: \e1_crc4 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7 Used module: \soc_iobuf Used module: $paramod\wb_dma\A0W=14\A1W=9\DW=32 Used module: $paramod\wb_arbiter\N=2\DW=32\AW=9 Used module: $paramod\wb_epbuf\AW=9\DW=32 Used module: $paramod\wb_arbiter\N=3\DW=32\AW=14 Used module: $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0 Used module: $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32 Used module: \xclk_strobe Used module: $paramod\xclk_wb\DW=16\AW=12 Used module: $paramod\usb\EPDW=32 Used module: \usb_ep_status Used module: \usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101 Used module: $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100 Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: \usb_phy Used module: $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb Used module: $paramod\uart_wb\DIV_WIDTH=12\DW=32 Used module: \fifo_sync_ram Used module: $paramod\ram_sdp\AWIDTH=8\DWIDTH=16 Used module: \uart_rx Used module: $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1 Used module: \uart_tx Used module: $paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0 Used module: $paramod\soc_spram\AW=14 Used module: \ice40_spram_gen Used module: $paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram Used module: $paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4 Used module: $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32 Used module: \picorv32_ice40_regs Used module: $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 32 Parameter \WWIDTH = 8 73.2.48. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_ep_buf'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 32 Parameter \WWIDTH = 8 Generating RTLIL representation for module `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf'. READ_MODE : 1 WRITE_MODE : 3 Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 8 Parameter \WWIDTH = 32 73.2.49. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_ep_buf'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 8 Parameter \WWIDTH = 32 Generating RTLIL representation for module `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf'. READ_MODE : 3 WRITE_MODE : 1 Parameter \TARGET = 40'0100100101000011010001010011010000110000 Found cached RTLIL representation for module `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000'. Parameter \DEPTH = 512 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8'. Parameter \DIV_WIDTH = 12 Parameter \GLITCH_FILTER = 2 73.2.50. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'. Parameter \DIV_WIDTH = 12 Parameter \GLITCH_FILTER = 2 Generating RTLIL representation for module `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2'. Parameter \DEPTH = 512 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8'. Parameter \DIV_WIDTH = 12 73.2.51. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'. Parameter \DIV_WIDTH = 12 Generating RTLIL representation for module `$paramod\uart_tx\DIV_WIDTH=12'. Parameter \ADDR_WIDTH = 14 Parameter \DATA_WIDTH = 32 Found cached RTLIL representation for module `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32'. Parameter \LIU = 1 Parameter \MFW = 7 73.2.52. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_wb_rx'. Parameter \LIU = 1 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_wb_rx\LIU=1\MFW=7'. Parameter \LIU = 1 Parameter \MFW = 7 Found cached RTLIL representation for module `$paramod\e1_wb_rx\LIU=1\MFW=7'. 73.2.53. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: $paramod\ice40_spi_wb\N_CS=2\WITH_IOB=1\UNIT=1 Used module: \misc Used module: $paramod\capcnt\W=16 Used module: \capcnt16_sb_mac16 Used module: $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0 Used module: $paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0 Used module: $paramod\capcnt\W=32 Used module: \capcnt32_sb_mac16 Used module: $paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base Used module: $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32 Used module: $paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7 Used module: $paramod\e1_wb_rx\LIU=1\MFW=7 Used module: \e1_rx Used module: \hdb3_dec Used module: \e1_rx_clock_recovery Used module: \e1_rx_filter Used module: \e1_rx_phy Used module: \e1_rx_deframer Used module: \e1_crc4 Used module: \fifo_sync_shift Used module: \soc_iobuf Used module: $paramod\wb_dma\A0W=14\A1W=9\DW=32 Used module: $paramod\wb_arbiter\N=2\DW=32\AW=9 Used module: $paramod\wb_epbuf\AW=9\DW=32 Used module: $paramod\wb_arbiter\N=3\DW=32\AW=14 Used module: $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0 Used module: $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32 Used module: \xclk_strobe Used module: $paramod\xclk_wb\DW=16\AW=12 Used module: $paramod\usb\EPDW=32 Used module: \usb_ep_status Used module: $paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf Used module: $paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101 Used module: $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100 Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000 Used module: $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb Used module: $paramod\uart_wb\DIV_WIDTH=12\DW=32 Used module: $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8 Used module: $paramod\ram_sdp\AWIDTH=9\DWIDTH=8 Used module: $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2 Used module: \glitch_filter Used module: $paramod\uart_tx\DIV_WIDTH=12 Used module: $paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0 Used module: $paramod\soc_spram\AW=14 Used module: $paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram Used module: $paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4 Used module: $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32 Used module: \picorv32_ice40_regs Used module: $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr Parameter \L = 2 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Found cached RTLIL representation for module `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1'. Parameter \LIU = 1 Parameter \MFW = 7 73.2.54. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_rx'. Parameter \LIU = 1 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_rx\LIU=1\MFW=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7'. 73.2.55. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: $paramod\ice40_spi_wb\N_CS=2\WITH_IOB=1\UNIT=1 Used module: \misc Used module: $paramod\capcnt\W=16 Used module: \capcnt16_sb_mac16 Used module: $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0 Used module: $paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0 Used module: $paramod\capcnt\W=32 Used module: \capcnt32_sb_mac16 Used module: $paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base Used module: $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32 Used module: $paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7 Used module: $paramod\e1_wb_rx\LIU=1\MFW=7 Used module: $paramod\e1_rx\LIU=1\MFW=7 Used module: \e1_rx_liu Used module: \e1_rx_deframer Used module: \e1_crc4 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7 Used module: \soc_iobuf Used module: $paramod\wb_dma\A0W=14\A1W=9\DW=32 Used module: $paramod\wb_arbiter\N=2\DW=32\AW=9 Used module: $paramod\wb_epbuf\AW=9\DW=32 Used module: $paramod\wb_arbiter\N=3\DW=32\AW=14 Used module: $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0 Used module: $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32 Used module: \xclk_strobe Used module: $paramod\xclk_wb\DW=16\AW=12 Used module: $paramod\usb\EPDW=32 Used module: \usb_ep_status Used module: $paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf Used module: $paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101 Used module: $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100 Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000 Used module: $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb Used module: $paramod\uart_wb\DIV_WIDTH=12\DW=32 Used module: $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8 Used module: $paramod\ram_sdp\AWIDTH=9\DWIDTH=8 Used module: $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2 Used module: $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1 Used module: $paramod\uart_tx\DIV_WIDTH=12 Used module: $paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0 Used module: $paramod\soc_spram\AW=14 Used module: $paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram Used module: $paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4 Used module: $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32 Used module: \picorv32_ice40_regs Used module: $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr 73.2.56. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: $paramod\ice40_spi_wb\N_CS=2\WITH_IOB=1\UNIT=1 Used module: \misc Used module: $paramod\capcnt\W=16 Used module: \capcnt16_sb_mac16 Used module: $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0 Used module: $paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0 Used module: $paramod\capcnt\W=32 Used module: \capcnt32_sb_mac16 Used module: $paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base Used module: $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32 Used module: $paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7 Used module: $paramod\e1_wb_rx\LIU=1\MFW=7 Used module: $paramod\e1_rx\LIU=1\MFW=7 Used module: \e1_rx_liu Used module: \e1_rx_deframer Used module: \e1_crc4 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7 Used module: \soc_iobuf Used module: $paramod\wb_dma\A0W=14\A1W=9\DW=32 Used module: $paramod\wb_arbiter\N=2\DW=32\AW=9 Used module: $paramod\wb_epbuf\AW=9\DW=32 Used module: $paramod\wb_arbiter\N=3\DW=32\AW=14 Used module: $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0 Used module: $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32 Used module: \xclk_strobe Used module: $paramod\xclk_wb\DW=16\AW=12 Used module: $paramod\usb\EPDW=32 Used module: \usb_ep_status Used module: $paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf Used module: $paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101 Used module: $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100 Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000 Used module: $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb Used module: $paramod\uart_wb\DIV_WIDTH=12\DW=32 Used module: $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8 Used module: $paramod\ram_sdp\AWIDTH=9\DWIDTH=8 Used module: $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2 Used module: $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1 Used module: $paramod\uart_tx\DIV_WIDTH=12 Used module: $paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0 Used module: $paramod\soc_spram\AW=14 Used module: $paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram Used module: $paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4 Used module: $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32 Used module: \picorv32_ice40_regs Used module: $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr Removing unused module `$paramod$e9a8417cc0e9fc03e370009e77135e9e1e2b5499\usb_ep_buf'. Removing unused module `$paramod$7d82212fad3e4929db14b64ca83adffce21ba555\usb_ep_buf'. Removing unused module `$paramod\uart_tx\DIV_WIDTH=8'. Removing unused module `$paramod\uart_rx\DIV_WIDTH=8\GLITCH_FILTER=2'. Removing unused module `$paramod\ram_sdp\AWIDTH=8\DWIDTH=16'. Removing unused module `$paramod\e1_wb_rx\LIU=0\MFW=7'. Removing unused module `$paramod\e1_wb_tx\LIU=0\MFW=7'. Removing unused module `$paramod\e1_tx\LIU=0\MFW=7'. Removing unused module `$paramod\e1_rx\LIU=0\MFW=7'. Removing unused module `$paramod\soc_picorv32_bridge\WB_N=9\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4'. Removing unused module `$paramod\e1_wb\N=1\UNIT_HAS_RX=1'1\UNIT_HAS_TX=1'1\LIU=0\MFW=7'. Removing unused module `$paramod\e1_buf_if_wb\N=1\UNIT_HAS_RX=1'1\UNIT_HAS_TX=1'1\MFW=7\DW=32'. Removing unused module `\wb_epbuf'. Removing unused module `\wb_dma'. Removing unused module `\wb_arbiter'. Removing unused module `\soc_spram'. Removing unused module `\soc_picorv32_bridge'. Removing unused module `\soc_bram'. Removing unused module `\soc_base'. Removing unused module `\picorv32_wb'. Removing unused module `\picorv32_axi_adapter'. Removing unused module `\picorv32_axi'. Removing unused module `\picorv32_pcpi_div'. Removing unused module `\picorv32_pcpi_fast_mul'. Removing unused module `\picorv32_pcpi_mul'. Removing unused module `\picorv32_regs'. Removing unused module `\picorv32'. Removing unused module `\dfu_helper'. Removing unused module `\capcnt'. Removing unused module `\usb_phy'. Removing unused module `\usb_ep_buf'. Removing unused module `\usb_crc'. Removing unused module `\usb'. Removing unused module `\xclk_wb'. Removing unused module `\uart_wb'. Removing unused module `\uart_tx'. Removing unused module `\uart_rx'. Removing unused module `\uart2wb'. Removing unused module `\stream2wb'. Removing unused module `\ram_sdp'. Removing unused module `\pwm'. Removing unused module `\pdm_lfsr'. Removing unused module `\pdm'. Removing unused module `\dffesr_n'. Removing unused module `\dffer_n'. Removing unused module `\dffe_n'. Removing unused module `\dff_n'. Removing unused module `\lut4_carry_n'. Removing unused module `\lut4_n'. Removing unused module `\muacm2wb'. Removing unused module `\i2c_master_wb'. Removing unused module `\i2c_master'. Removing unused module `\glitch_filter'. Removing unused module `\fifo_sync_shift'. Removing unused module `\fifo_sync_ram'. Removing unused module `\delay_bus'. Removing unused module `\delay_bit'. Removing unused module `\ice40_serdes_sync'. Removing unused module `\ice40_serdes_dff'. Removing unused module `\ice40_serdes_crg'. Removing unused module `\ice40_oserdes'. Removing unused module `\ice40_iserdes'. Removing unused module `\ice40_spram_wb'. Removing unused module `\ice40_spram_gen'. Removing unused module `\ice40_spi_wb'. Removing unused module `\ice40_rgb_wb'. Removing unused module `\ice40_i2c_wb'. Removing unused module `\ice40_ebr'. Removing unused module `\hdb3_enc'. Removing unused module `\hdb3_dec'. Removing unused module `\e1_wb'. Removing unused module `\e1_wb_tx'. Removing unused module `\e1_wb_rx'. Removing unused module `\e1_buf_if_wb'. Removing unused module `\e1_tx'. Removing unused module `\e1_tx_liu'. Removing unused module `\e1_tx_phy'. Removing unused module `\e1_tx_framer'. Removing unused module `\e1_rx'. Removing unused module `\e1_rx_phy'. Removing unused module `\e1_rx_filter'. Removing unused module `\e1_rx_clock_recovery'. Removed 82 unused modules. 73.3. Executing PROC pass (convert processes to netlists). 73.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5222'. Removing empty process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4474'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5167'. Found and cleaned up 1 empty switch in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4089'. Found and cleaned up 15 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. Found and cleaned up 1 empty switch in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$3891'. Found and cleaned up 6 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:530$3537'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:530$3537'. Found and cleaned up 1 empty switch in `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:0$3343'. Removing empty process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:0$3343'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:471$3212'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:471$3212'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:360$132'. Cleaned up 26 empty switches. 73.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:909$2908 in module SB_DFFNSR. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$2900 in module SB_DFFES. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:697$2893 in module SB_DFFESS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$2889 in module SB_DFFER. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:566$2882 in module SB_DFFESR. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:497$2879 in module SB_DFFS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:449$2876 in module SB_DFFSS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:380$2873 in module SB_DFFR. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:332$2870 in module SB_DFFSR. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_epbuf.v:51$4852 in module $paramod\wb_epbuf\AW=9\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_arbiter.v:116$4841 in module $paramod\wb_arbiter\N=2\DW=32\AW=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_arbiter.v:80$4831 in module $paramod\wb_arbiter\N=2\DW=32\AW=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_dma.v:190$4799 in module $paramod\wb_dma\A0W=14\A1W=9\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_dma.v:98$4760 in module $paramod\wb_dma\A0W=14\A1W=9\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_dma.v:92$4759 in module $paramod\wb_dma\A0W=14\A1W=9\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_dma.v:86$4755 in module $paramod\wb_dma\A0W=14\A1W=9\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4731 in module $paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4727 in module $paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4723 in module $paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4715 in module $paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0. Removed 2 dead cases from process $proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4676 in module $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4676 in module $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:199$5306 in module $paramod\e1_rx\LIU=1\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:184$5296 in module $paramod\e1_rx\LIU=1\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:246$5286 in module $paramod\e1_wb_rx\LIU=1\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:239$5284 in module $paramod\e1_wb_rx\LIU=1\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$5266 in module $paramod\e1_wb_rx\LIU=1\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$5265 in module $paramod\e1_wb_rx\LIU=1\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$5257 in module $paramod\e1_wb_rx\LIU=1\MFW=7. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5255 in module $paramod\uart_tx\DIV_WIDTH=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:51$5252 in module $paramod\uart_tx\DIV_WIDTH=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:42$5248 in module $paramod\uart_tx\DIV_WIDTH=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:35$5244 in module $paramod\uart_tx\DIV_WIDTH=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:88$5234 in module $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:77$5230 in module $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:70$5226 in module $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4527 in module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4521 in module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4519 in module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:83$4510 in module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:67$4504 in module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4498 in module $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4494 in module $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4490 in module $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4482 in module $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1. Marked 16 switch rules as full_case in process $proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317 in module $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/e1-tracer/rtl/sysmgr.v:81$1589 in module sysmgr. Marked 1 switch rules as full_case in process $proc$/build/gateware/e1-tracer/rtl/misc.v:116$1587 in module misc. Marked 2 switch rules as full_case in process $proc$/build/gateware/e1-tracer/rtl/misc.v:73$1586 in module misc. Marked 1 switch rules as full_case in process $proc$/build/gateware/e1-tracer/rtl/misc.v:66$1582 in module misc. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:159$1541 in module usb_tx_pkt. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:126$1525 in module usb_tx_pkt. Marked 8 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:86$1523 in module usb_tx_pkt. Removed 1 dead cases from process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1520 in module usb_tx_ll. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1520 in module usb_tx_ll. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1498 in module usb_tx_ll. Marked 4 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1492 in module usb_tx_ll. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:236$1488 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:421$1477 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:387$1461 in module usb_trans. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1446 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:345$1443 in module usb_trans. Marked 5 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1438 in module usb_trans. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1427 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:225$1422 in module usb_trans. Removed 1 dead cases from process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1419 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1419 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:175$1410 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:162$1401 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1338 in module usb_rx_pkt. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:244$1335 in module usb_rx_pkt. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:230$1332 in module usb_rx_pkt. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:220$1329 in module usb_rx_pkt. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:188$1319 in module usb_rx_pkt. Marked 18 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:117$1303 in module usb_rx_pkt. Removed 1 dead cases from process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1298 in module usb_rx_ll. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1298 in module usb_rx_ll. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:137$1297 in module usb_rx_ll. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:124$1296 in module usb_rx_ll. Removed 1 dead cases from process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1280 in module usb_rx_ll. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1280 in module usb_rx_ll. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:67$1270 in module usb_rx_ll. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:163$5101 in module $paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4201 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4199 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4190 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4188 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4179 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4177 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4168 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4166 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4155 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4153 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4144 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4142 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4133 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4131 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4122 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4120 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:125$5027 in module $paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:40$1098 in module xclk_strobe. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:34$1097 in module xclk_strobe. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:28$1095 in module xclk_strobe. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/dfu_helper.v:149$4098 in module $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0. Marked 2 switch rules as full_case in process $proc$/build/gateware/common/rtl/dfu_helper.v:120$4089 in module $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/dfu_helper.v:109$4085 in module $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/dfu_helper.v:103$4083 in module $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0. Marked 37 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:1375$3905 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 2 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:1288$3877 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 2 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:1274$3872 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 8 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:1165$3837 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 3 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:840$3577 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 3 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:791$3575 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 2 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:760$3571 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 47 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:684$3570 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 4 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:549$3546 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:414$3508 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Removed 2 dead cases from process $proc$/build/gateware/common/rtl/picorv32.v:385$3505 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 2 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:385$3505 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:374$3500 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:309$3426 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5002 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$4996 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$4985 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32. Marked 5 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4952 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:206$4947 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32. Marked 4 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$4945 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:185$3305 in module $paramod\uart_wb\DIV_WIDTH=12\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:177$3295 in module $paramod\uart_wb\DIV_WIDTH=12\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3278 in module $paramod\uart_wb\DIV_WIDTH=12\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:154$3273 in module $paramod\uart_wb\DIV_WIDTH=12\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3266 in module $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:536$3260 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:643$3252 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:636$3248 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:628$3244 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:619$3240 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:514$3226 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3213 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3211 in module $paramod\usb\EPDW=32. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:442$3207 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3189 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:99$3185 in module $paramod\xclk_wb\DW=16\AW=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:73$3178 in module $paramod\xclk_wb\DW=16\AW=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v:50$4916 in module $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_arbiter.v:116$4895 in module $paramod\wb_arbiter\N=3\DW=32\AW=14. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_arbiter.v:80$4883 in module $paramod\wb_arbiter\N=3\DW=32\AW=14. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/soc_base.v:185$3089 in module $paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$2938 in module SB_DFFNES. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1274$2931 in module SB_DFFNESS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$2927 in module SB_DFFNER. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1143$2920 in module SB_DFFNESR. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1074$2917 in module SB_DFFNS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1026$2914 in module SB_DFFNSS. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:395$138 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:360$132 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:339$106 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:324$88 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:310$66 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:269$54 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:261$50 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:253$46 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:226$38 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:214$34 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:202$30 in module e1_rx_deframer. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:146$23 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:139$21 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:118$16 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:957$2911 in module SB_DFFNR. Removed a total of 8 dead cases. 73.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 121 redundant assignments. Promoted 277 assignments to connections. 73.3.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2910'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2907'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2905'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2903'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2899'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2892'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2888'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2881'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2878'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2875'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2872'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2869'. Set init value: \Q = 1'0 Found init rule in `\SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2867'. Set init value: \Q = 1'0 Found init rule in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:49$1302'. Set init value: \dec_sym_1 = 2'00 Found init rule in `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2941'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2937'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2930'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2926'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2919'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2916'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2913'. Set init value: \Q = 1'0 73.3.5. Executing PROC_ARST pass (detect async resets in processes). Found async reset \S in `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$2900'. Found async reset \R in `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$2889'. Found async reset \S in `\SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:497$2879'. Found async reset \R in `\SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:380$2873'. Found async reset \rst in `$paramod\wb_epbuf\AW=9\DW=32.$proc$/build/gateware/common/rtl/wb_epbuf.v:51$4852'. Found async reset \rst in `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4841'. Found async reset \rst in `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4831'. Found async reset \rst in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$4799'. Found async reset \rst in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:92$4759'. Found async reset \rst in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:86$4755'. Found async reset \rst in `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4676'. Found async reset \rst in `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:199$5306'. Found async reset \rst in `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:184$5296'. Found async reset \rst in `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:246$5286'. Found async reset \rst in `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:239$5284'. Found async reset \rst in `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$5265'. Found async reset \rst in `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5255'. Found async reset \rst in `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:35$5244'. Found async reset \rst in `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:70$5226'. Found async reset \rst in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4527'. Found async reset \rst in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4521'. Found async reset \rst in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4519'. Found async reset \rst in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:83$4510'. Found async reset \rst in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:67$4504'. Found async reset \pll_lock in `\sysmgr.$proc$/build/gateware/e1-tracer/rtl/sysmgr.v:81$1589'. Found async reset \rst in `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:116$1587'. Found async reset \rst in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:126$1525'. Found async reset \rst in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1520'. Found async reset \ll_start in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1498'. Found async reset \rst in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1492'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:387$1461'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:345$1443'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1438'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1427'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:225$1422'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:175$1410'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:162$1401'. Found async reset \rst in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:188$1319'. Found async reset \rst in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:67$1270'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4201'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4199'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4190'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4188'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4179'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4177'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4168'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4166'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4155'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4153'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4144'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4142'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4133'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4131'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4122'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4120'. Found async reset \rst in `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:40$1098'. Found async reset \rst in `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:34$1097'. Found async reset \rst in `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:28$1095'. Found async reset \rst in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:149$4098'. Found async reset \rst in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4089'. Found async reset \rst in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:109$4085'. Found async reset \rst in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:103$4083'. Found async reset \rst in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5002'. Found async reset \rst in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$4996'. Found async reset \rst in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:206$4947'. Found async reset \rst in `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:154$3273'. Found async reset \rst in `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.$proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3266'. Found async reset \rst in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:536$3260'. Found async reset \rst in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:636$3248'. Found async reset \rst in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:514$3226'. Found async reset \rst in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3211'. Found async reset \rst in `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:99$3185'. Found async reset \rst in `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v:50$4916'. Found async reset \rst in `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4895'. Found async reset \rst in `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4883'. Found async reset \rst_sys in `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:185$3089'. Found async reset \S in `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$2938'. Found async reset \R in `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$2927'. Found async reset \S in `\SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1074$2917'. Found async reset \R in `\SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:957$2911'. 73.3.6. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2910'. Creating decoders for process `\SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:909$2908'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2907'. Creating decoders for process `\SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:866$2906'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2905'. Creating decoders for process `\SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:830$2904'. Creating decoders for process `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2903'. Creating decoders for process `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$2900'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2899'. Creating decoders for process `\SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:697$2893'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2892'. Creating decoders for process `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$2889'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2888'. Creating decoders for process `\SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:566$2882'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2881'. Creating decoders for process `\SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:497$2879'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2878'. Creating decoders for process `\SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:449$2876'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2875'. Creating decoders for process `\SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:380$2873'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2872'. Creating decoders for process `\SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:332$2870'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2869'. Creating decoders for process `\SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:289$2868'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2867'. Creating decoders for process `\SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:253$2866'. Creating decoders for process `$paramod\wb_epbuf\AW=9\DW=32.$proc$/build/gateware/common/rtl/wb_epbuf.v:51$4852'. 1/1: $0\ack_i[0:0] Creating decoders for process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4841'. 1/2: $0\busy[0:0] 2/2: $0\sel[1:0] Creating decoders for process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$4834'. 1/2: $0\sel_nxt[1:0] [1] 2/2: $0\sel_nxt[1:0] [0] Creating decoders for process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4831'. 1/4: $0\m_wmsk[3:0] 2/4: $0\m_we[0:0] 3/4: $0\m_wdata[31:0] 4/4: $0\m_addr[8:0] Creating decoders for process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4818'. Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$4799'. 1/3: $0\ctl_ack_i[0:0] 2/3: $0\ctl_do_read[0:0] 3/3: $0\ctl_do_write[0:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:178$4795'. 1/1: $0\dir[0:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:174$4792'. 1/1: $0\len[12:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:157$4782'. 1/1: $0\m1_addr_i[8:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:153$4778'. 1/1: $0\m0_addr_i[13:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:142$4776'. 1/1: $0\data_reg[31:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:98$4760'. 1/1: $0\state_nxt[1:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:92$4759'. 1/1: $0\state[1:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:86$4755'. 1/1: $0\go[0:0] Creating decoders for process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4751'. Creating decoders for process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4747'. Creating decoders for process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4743'. Creating decoders for process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4736'. Creating decoders for process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4731'. 1/2: $0\fall[0:0] 2/2: $0\rise[0:0] Creating decoders for process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4727'. 1/1: $0\state[0:0] Creating decoders for process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4723'. 1/1: $0\cnt[3:0] Creating decoders for process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4715'. 1/2: $2\cnt_move[3:0] 2/2: $1\cnt_move[3:0] Creating decoders for process `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4713'. 1/1: $0\state[4:0] Creating decoders for process `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4700'. 1/1: $0\state[15:0] Creating decoders for process `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4676'. 1/2: $0\dn_state[2:0] 2/2: $0\dp_state[2:0] Creating decoders for process `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:199$5306'. 1/1: $0\bd_crc_e[1:0] Creating decoders for process `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:192$5300'. Creating decoders for process `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:184$5296'. 1/1: $0\mf_valid[0:0] Creating decoders for process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:253$5290'. Creating decoders for process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:246$5286'. 1/1: $0\rx_overflow[0:0] Creating decoders for process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:239$5284'. 1/1: $0\rx_rst[0:0] Creating decoders for process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$5266'. 1/2: $0\bro_rden[0:0] 2/2: $0\bri_wren[0:0] Creating decoders for process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$5265'. 1/2: $0\rx_mode[1:0] 2/2: $0\rx_enabled[0:0] Creating decoders for process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$5257'. 1/2: $0\crx_clear[0:0] 2/2: $0\crx_wren[0:0] Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:67$5256'. Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5255'. 1/1: $0\shift[9:0] Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:51$5252'. 1/1: $0\bit_cnt[4:0] Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:42$5248'. 1/1: $0\div_cnt[12:0] Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:35$5244'. 1/1: $0\active[0:0] Creating decoders for process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:102$5238'. Creating decoders for process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:95$5237'. 1/1: $0\shift[8:0] Creating decoders for process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:88$5234'. 1/1: $0\bit_cnt[4:0] Creating decoders for process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:77$5230'. 1/1: $0\div_cnt[12:0] Creating decoders for process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:70$5226'. 1/1: $0\active[0:0] Creating decoders for process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4527'. 1/1: $0\rd_valid[0:0] Creating decoders for process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4521'. 1/1: $0\ram_rd_addr[8:0] Creating decoders for process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4519'. 1/1: $0\ram_wr_addr[8:0] Creating decoders for process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:83$4510'. 1/1: $0\full[0:0] Creating decoders for process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:67$4504'. 1/1: $0\level[9:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4503'. Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4498'. 1/2: $0\fall[0:0] 2/2: $0\rise[0:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4494'. 1/1: $0\state[0:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4490'. 1/1: $0\cnt[1:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4482'. 1/2: $2\cnt_move[1:0] 2/2: $1\cnt_move[1:0] Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5218'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5214'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5210'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5206'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5202'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5198'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5194'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5190'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5186'. Creating decoders for process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4473'. Creating decoders for process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317'. 1/320: $8\mem_dm_w[7:0] [7] 2/320: $8\mem_dm_w[7:0] [4] 3/320: $8\mem_dm_w[7:0] [2] 4/320: $8\mem_dm_w[7:0] [0] 5/320: $8\mem_dm_w[7:0] [6] 6/320: $8\mem_dm_w[7:0] [1] 7/320: $8\mem_dm_w[7:0] [3] 8/320: $8\mem_dm_w[7:0] [5] 9/320: $8\mem_di_w[31:0] [31] 10/320: $8\mem_di_w[31:0] [24] 11/320: $8\mem_di_w[31:0] [22] 12/320: $8\mem_di_w[31:0] [20] 13/320: $8\mem_di_w[31:0] [18] 14/320: $8\mem_di_w[31:0] [16] 15/320: $8\mem_di_w[31:0] [14] 16/320: $8\mem_di_w[31:0] [12] 17/320: $8\mem_di_w[31:0] [10] 18/320: $8\mem_di_w[31:0] [8] 19/320: $8\mem_di_w[31:0] [6] 20/320: $8\mem_di_w[31:0] [4] 21/320: $8\mem_di_w[31:0] [2] 22/320: $8\mem_di_w[31:0] [0] 23/320: $8\mem_di_w[31:0] [30] 24/320: $8\mem_di_w[31:0] [27] 25/320: $8\mem_di_w[31:0] [23] 26/320: $8\mem_di_w[31:0] [21] 27/320: $8\mem_di_w[31:0] [17] 28/320: $8\mem_di_w[31:0] [13] 29/320: $8\mem_di_w[31:0] [9] 30/320: $8\mem_di_w[31:0] [5] 31/320: $8\mem_di_w[31:0] [1] 32/320: $8\mem_di_w[31:0] [28] 33/320: $8\mem_di_w[31:0] [26] 34/320: $8\mem_di_w[31:0] [15] 35/320: $8\mem_di_w[31:0] [3] 36/320: $8\mem_di_w[31:0] [7] 37/320: $8\mem_di_w[31:0] [25] 38/320: $8\mem_di_w[31:0] [19] 39/320: $8\mem_di_w[31:0] [29] 40/320: $8\mem_di_w[31:0] [11] 41/320: $7\mem_dm_w[7:0] [7] 42/320: $7\mem_dm_w[7:0] [4] 43/320: $7\mem_dm_w[7:0] [2] 44/320: $7\mem_dm_w[7:0] [0] 45/320: $7\mem_dm_w[7:0] [6] 46/320: $7\mem_dm_w[7:0] [1] 47/320: $7\mem_dm_w[7:0] [3] 48/320: $7\mem_dm_w[7:0] [5] 49/320: $7\mem_di_w[31:0] [31] 50/320: $7\mem_di_w[31:0] [24] 51/320: $7\mem_di_w[31:0] [22] 52/320: $7\mem_di_w[31:0] [20] 53/320: $7\mem_di_w[31:0] [18] 54/320: $7\mem_di_w[31:0] [16] 55/320: $7\mem_di_w[31:0] [14] 56/320: $7\mem_di_w[31:0] [12] 57/320: $7\mem_di_w[31:0] [10] 58/320: $7\mem_di_w[31:0] [8] 59/320: $7\mem_di_w[31:0] [6] 60/320: $7\mem_di_w[31:0] [4] 61/320: $7\mem_di_w[31:0] [2] 62/320: $7\mem_di_w[31:0] [0] 63/320: $7\mem_di_w[31:0] [30] 64/320: $7\mem_di_w[31:0] [27] 65/320: $7\mem_di_w[31:0] [23] 66/320: $7\mem_di_w[31:0] [21] 67/320: $7\mem_di_w[31:0] [17] 68/320: $7\mem_di_w[31:0] [13] 69/320: $7\mem_di_w[31:0] [9] 70/320: $7\mem_di_w[31:0] [5] 71/320: $7\mem_di_w[31:0] [1] 72/320: $7\mem_di_w[31:0] [28] 73/320: $7\mem_di_w[31:0] [26] 74/320: $7\mem_di_w[31:0] [15] 75/320: $7\mem_di_w[31:0] [3] 76/320: $7\mem_di_w[31:0] [7] 77/320: $7\mem_di_w[31:0] [25] 78/320: $7\mem_di_w[31:0] [19] 79/320: $7\mem_di_w[31:0] [29] 80/320: $7\mem_di_w[31:0] [11] 81/320: $6\mem_dm_w[7:0] [7] 82/320: $6\mem_dm_w[7:0] [4] 83/320: $6\mem_dm_w[7:0] [2] 84/320: $6\mem_dm_w[7:0] [0] 85/320: $6\mem_dm_w[7:0] [6] 86/320: $6\mem_dm_w[7:0] [1] 87/320: $6\mem_dm_w[7:0] [3] 88/320: $6\mem_dm_w[7:0] [5] 89/320: $6\mem_di_w[31:0] [31] 90/320: $6\mem_di_w[31:0] [24] 91/320: $6\mem_di_w[31:0] [22] 92/320: $6\mem_di_w[31:0] [20] 93/320: $6\mem_di_w[31:0] [18] 94/320: $6\mem_di_w[31:0] [16] 95/320: $6\mem_di_w[31:0] [14] 96/320: $6\mem_di_w[31:0] [12] 97/320: $6\mem_di_w[31:0] [10] 98/320: $6\mem_di_w[31:0] [8] 99/320: $6\mem_di_w[31:0] [6] 100/320: $6\mem_di_w[31:0] [4] 101/320: $6\mem_di_w[31:0] [2] 102/320: $6\mem_di_w[31:0] [0] 103/320: $6\mem_di_w[31:0] [30] 104/320: $6\mem_di_w[31:0] [27] 105/320: $6\mem_di_w[31:0] [23] 106/320: $6\mem_di_w[31:0] [21] 107/320: $6\mem_di_w[31:0] [17] 108/320: $6\mem_di_w[31:0] [13] 109/320: $6\mem_di_w[31:0] [9] 110/320: $6\mem_di_w[31:0] [5] 111/320: $6\mem_di_w[31:0] [1] 112/320: $6\mem_di_w[31:0] [28] 113/320: $6\mem_di_w[31:0] [26] 114/320: $6\mem_di_w[31:0] [15] 115/320: $6\mem_di_w[31:0] [3] 116/320: $6\mem_di_w[31:0] [7] 117/320: $6\mem_di_w[31:0] [25] 118/320: $6\mem_di_w[31:0] [19] 119/320: $6\mem_di_w[31:0] [29] 120/320: $6\mem_di_w[31:0] [11] 121/320: $5\mem_dm_w[7:0] [7] 122/320: $5\mem_dm_w[7:0] [4] 123/320: $5\mem_dm_w[7:0] [2] 124/320: $5\mem_dm_w[7:0] [0] 125/320: $5\mem_dm_w[7:0] [6] 126/320: $5\mem_dm_w[7:0] [1] 127/320: $5\mem_dm_w[7:0] [3] 128/320: $5\mem_dm_w[7:0] [5] 129/320: $5\mem_di_w[31:0] [31] 130/320: $5\mem_di_w[31:0] [24] 131/320: $5\mem_di_w[31:0] [22] 132/320: $5\mem_di_w[31:0] [20] 133/320: $5\mem_di_w[31:0] [18] 134/320: $5\mem_di_w[31:0] [16] 135/320: $5\mem_di_w[31:0] [14] 136/320: $5\mem_di_w[31:0] [12] 137/320: $5\mem_di_w[31:0] [10] 138/320: $5\mem_di_w[31:0] [8] 139/320: $5\mem_di_w[31:0] [6] 140/320: $5\mem_di_w[31:0] [4] 141/320: $5\mem_di_w[31:0] [2] 142/320: $5\mem_di_w[31:0] [0] 143/320: $5\mem_di_w[31:0] [30] 144/320: $5\mem_di_w[31:0] [27] 145/320: $5\mem_di_w[31:0] [23] 146/320: $5\mem_di_w[31:0] [21] 147/320: $5\mem_di_w[31:0] [17] 148/320: $5\mem_di_w[31:0] [13] 149/320: $5\mem_di_w[31:0] [9] 150/320: $5\mem_di_w[31:0] [5] 151/320: $5\mem_di_w[31:0] [1] 152/320: $5\mem_di_w[31:0] [28] 153/320: $5\mem_di_w[31:0] [26] 154/320: $5\mem_di_w[31:0] [15] 155/320: $5\mem_di_w[31:0] [3] 156/320: $5\mem_di_w[31:0] [7] 157/320: $5\mem_di_w[31:0] [25] 158/320: $5\mem_di_w[31:0] [19] 159/320: $5\mem_di_w[31:0] [29] 160/320: $5\mem_di_w[31:0] [11] 161/320: $4\mem_dm_w[7:0] [7] 162/320: $4\mem_dm_w[7:0] [4] 163/320: $4\mem_dm_w[7:0] [2] 164/320: $4\mem_dm_w[7:0] [0] 165/320: $4\mem_dm_w[7:0] [6] 166/320: $4\mem_dm_w[7:0] [1] 167/320: $4\mem_dm_w[7:0] [3] 168/320: $4\mem_dm_w[7:0] [5] 169/320: $4\mem_di_w[31:0] [31] 170/320: $4\mem_di_w[31:0] [24] 171/320: $4\mem_di_w[31:0] [22] 172/320: $4\mem_di_w[31:0] [20] 173/320: $4\mem_di_w[31:0] [18] 174/320: $4\mem_di_w[31:0] [16] 175/320: $4\mem_di_w[31:0] [14] 176/320: $4\mem_di_w[31:0] [12] 177/320: $4\mem_di_w[31:0] [10] 178/320: $4\mem_di_w[31:0] [8] 179/320: $4\mem_di_w[31:0] [6] 180/320: $4\mem_di_w[31:0] [4] 181/320: $4\mem_di_w[31:0] [2] 182/320: $4\mem_di_w[31:0] [0] 183/320: $4\mem_di_w[31:0] [30] 184/320: $4\mem_di_w[31:0] [27] 185/320: $4\mem_di_w[31:0] [23] 186/320: $4\mem_di_w[31:0] [21] 187/320: $4\mem_di_w[31:0] [17] 188/320: $4\mem_di_w[31:0] [13] 189/320: $4\mem_di_w[31:0] [9] 190/320: $4\mem_di_w[31:0] [5] 191/320: $4\mem_di_w[31:0] [1] 192/320: $4\mem_di_w[31:0] [28] 193/320: $4\mem_di_w[31:0] [26] 194/320: $4\mem_di_w[31:0] [15] 195/320: $4\mem_di_w[31:0] [3] 196/320: $4\mem_di_w[31:0] [7] 197/320: $4\mem_di_w[31:0] [25] 198/320: $4\mem_di_w[31:0] [19] 199/320: $4\mem_di_w[31:0] [29] 200/320: $4\mem_di_w[31:0] [11] 201/320: $3\mem_dm_w[7:0] [7] 202/320: $3\mem_dm_w[7:0] [4] 203/320: $3\mem_dm_w[7:0] [2] 204/320: $3\mem_dm_w[7:0] [0] 205/320: $3\mem_dm_w[7:0] [6] 206/320: $3\mem_dm_w[7:0] [1] 207/320: $3\mem_dm_w[7:0] [3] 208/320: $3\mem_dm_w[7:0] [5] 209/320: $3\mem_di_w[31:0] [31] 210/320: $3\mem_di_w[31:0] [24] 211/320: $3\mem_di_w[31:0] [22] 212/320: $3\mem_di_w[31:0] [20] 213/320: $3\mem_di_w[31:0] [18] 214/320: $3\mem_di_w[31:0] [16] 215/320: $3\mem_di_w[31:0] [14] 216/320: $3\mem_di_w[31:0] [12] 217/320: $3\mem_di_w[31:0] [10] 218/320: $3\mem_di_w[31:0] [8] 219/320: $3\mem_di_w[31:0] [6] 220/320: $3\mem_di_w[31:0] [4] 221/320: $3\mem_di_w[31:0] [2] 222/320: $3\mem_di_w[31:0] [0] 223/320: $3\mem_di_w[31:0] [30] 224/320: $3\mem_di_w[31:0] [27] 225/320: $3\mem_di_w[31:0] [23] 226/320: $3\mem_di_w[31:0] [21] 227/320: $3\mem_di_w[31:0] [17] 228/320: $3\mem_di_w[31:0] [13] 229/320: $3\mem_di_w[31:0] [9] 230/320: $3\mem_di_w[31:0] [5] 231/320: $3\mem_di_w[31:0] [1] 232/320: $3\mem_di_w[31:0] [28] 233/320: $3\mem_di_w[31:0] [26] 234/320: $3\mem_di_w[31:0] [15] 235/320: $3\mem_di_w[31:0] [3] 236/320: $3\mem_di_w[31:0] [7] 237/320: $3\mem_di_w[31:0] [25] 238/320: $3\mem_di_w[31:0] [19] 239/320: $3\mem_di_w[31:0] [29] 240/320: $3\mem_di_w[31:0] [11] 241/320: $2\mem_dm_w[7:0] [7] 242/320: $2\mem_dm_w[7:0] [4] 243/320: $2\mem_dm_w[7:0] [2] 244/320: $2\mem_dm_w[7:0] [0] 245/320: $2\mem_dm_w[7:0] [6] 246/320: $2\mem_dm_w[7:0] [1] 247/320: $2\mem_dm_w[7:0] [3] 248/320: $2\mem_dm_w[7:0] [5] 249/320: $2\mem_di_w[31:0] [31] 250/320: $2\mem_di_w[31:0] [24] 251/320: $2\mem_di_w[31:0] [22] 252/320: $2\mem_di_w[31:0] [20] 253/320: $2\mem_di_w[31:0] [18] 254/320: $2\mem_di_w[31:0] [16] 255/320: $2\mem_di_w[31:0] [14] 256/320: $2\mem_di_w[31:0] [12] 257/320: $2\mem_di_w[31:0] [10] 258/320: $2\mem_di_w[31:0] [8] 259/320: $2\mem_di_w[31:0] [6] 260/320: $2\mem_di_w[31:0] [4] 261/320: $2\mem_di_w[31:0] [2] 262/320: $2\mem_di_w[31:0] [0] 263/320: $2\mem_di_w[31:0] [30] 264/320: $2\mem_di_w[31:0] [27] 265/320: $2\mem_di_w[31:0] [23] 266/320: $2\mem_di_w[31:0] [21] 267/320: $2\mem_di_w[31:0] [17] 268/320: $2\mem_di_w[31:0] [13] 269/320: $2\mem_di_w[31:0] [9] 270/320: $2\mem_di_w[31:0] [5] 271/320: $2\mem_di_w[31:0] [1] 272/320: $2\mem_di_w[31:0] [28] 273/320: $2\mem_di_w[31:0] [26] 274/320: $2\mem_di_w[31:0] [15] 275/320: $2\mem_di_w[31:0] [3] 276/320: $2\mem_di_w[31:0] [7] 277/320: $2\mem_di_w[31:0] [25] 278/320: $2\mem_di_w[31:0] [19] 279/320: $2\mem_di_w[31:0] [29] 280/320: $2\mem_di_w[31:0] [11] 281/320: $1\mem_dm_w[7:0] [7] 282/320: $1\mem_dm_w[7:0] [4] 283/320: $1\mem_dm_w[7:0] [2] 284/320: $1\mem_dm_w[7:0] [0] 285/320: $1\mem_dm_w[7:0] [6] 286/320: $1\mem_dm_w[7:0] [1] 287/320: $1\mem_dm_w[7:0] [3] 288/320: $1\mem_dm_w[7:0] [5] 289/320: $1\mem_di_w[31:0] [31] 290/320: $1\mem_di_w[31:0] [24] 291/320: $1\mem_di_w[31:0] [22] 292/320: $1\mem_di_w[31:0] [20] 293/320: $1\mem_di_w[31:0] [18] 294/320: $1\mem_di_w[31:0] [16] 295/320: $1\mem_di_w[31:0] [14] 296/320: $1\mem_di_w[31:0] [12] 297/320: $1\mem_di_w[31:0] [10] 298/320: $1\mem_di_w[31:0] [8] 299/320: $1\mem_di_w[31:0] [6] 300/320: $1\mem_di_w[31:0] [4] 301/320: $1\mem_di_w[31:0] [2] 302/320: $1\mem_di_w[31:0] [0] 303/320: $1\mem_di_w[31:0] [30] 304/320: $1\mem_di_w[31:0] [27] 305/320: $1\mem_di_w[31:0] [23] 306/320: $1\mem_di_w[31:0] [21] 307/320: $1\mem_di_w[31:0] [17] 308/320: $1\mem_di_w[31:0] [13] 309/320: $1\mem_di_w[31:0] [9] 310/320: $1\mem_di_w[31:0] [5] 311/320: $1\mem_di_w[31:0] [1] 312/320: $1\mem_di_w[31:0] [28] 313/320: $1\mem_di_w[31:0] [26] 314/320: $1\mem_di_w[31:0] [15] 315/320: $1\mem_di_w[31:0] [3] 316/320: $1\mem_di_w[31:0] [7] 317/320: $1\mem_di_w[31:0] [25] 318/320: $1\mem_di_w[31:0] [19] 319/320: $1\mem_di_w[31:0] [29] 320/320: $1\mem_di_w[31:0] [11] Creating decoders for process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:73$4316'. 1/1: $0\addr_r[13:0] Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5163'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5159'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5155'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5151'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5147'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5143'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5139'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5135'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5131'. Creating decoders for process `\sysmgr.$proc$/build/gateware/e1-tracer/rtl/sysmgr.v:81$1589'. 1/1: $0\rst_cnt[3:0] Creating decoders for process `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:116$1587'. 1/2: $0\boot_now[0:0] 2/2: $0\boot_sel[1:0] Creating decoders for process `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:73$1586'. 1/1: $0\wb_rdata[31:0] Creating decoders for process `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:66$1582'. 1/1: $0\bus_we_boot[0:0] Creating decoders for process `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:60$1577'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:241$1573'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:229$1570'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:202$1564'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:191$1560'. 1/1: $0\len[10:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:182$1554'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:175$1547'. 1/2: $0\shift_last_byte[0:0] 2/2: $0\shift_data_crc[0:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:170$1545'. 1/1: $0\shift_data[7:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:159$1541'. 1/1: $0\shift_load[7:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:152$1538'. 1/1: $0\shift_bit[3:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:136$1526'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:126$1525'. 1/1: $0\state[3:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:86$1523'. 1/8: $8\state_nxt[3:0] 2/8: $7\state_nxt[3:0] 3/8: $6\state_nxt[3:0] 4/8: $5\state_nxt[3:0] 5/8: $4\state_nxt[3:0] 6/8: $3\state_nxt[3:0] 7/8: $2\state_nxt[3:0] 8/8: $1\state_nxt[3:0] Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:134$1522'. Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1520'. 1/1: $0\out_sym[1:0] Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:110$1513'. Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:102$1508'. Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1498'. 1/2: $0\bs_now[0:0] 2/2: $0\bs_cnt[2:0] Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:79$1495'. Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1492'. 1/1: $0\state[2:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:236$1488'. 1/1: $0\pkt_pid[3:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:428$1480'. Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:421$1477'. 1/1: $0\bd_length[10:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:414$1471'. Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:403$1470'. Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:399$1467'. 1/1: $0\txpkt_pid[3:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:387$1461'. 1/1: $0\cel_state_i[0:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:380$1459'. Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1446'. 1/7: $0\bd_state[2:0] 2/7: $0\ep_data_toggle[0:0] 3/7: $0\ep_bd_idx_nxt[0:0] 4/7: $0\ep_bd_idx_cur[0:0] 5/7: $0\ep_bd_ctrl[0:0] 6/7: $0\ep_bd_dual[0:0] 7/7: $0\ep_type[2:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:345$1443'. 1/1: $0\epfw_cap_dl[5:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1438'. 1/1: $0\epfw_state[3:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1434'. 1/4: $0\trans_cel[0:0] 2/4: $0\trans_dir[0:0] 3/4: $0\trans_endp[3:0] 4/4: $0\trans_is_setup[0:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1427'. 1/1: $0\rto_cnt[9:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:225$1422'. 1/1: $0\evt[3:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1419'. 1/1: $0\mc_a_reg[3:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:175$1410'. 1/1: $0\mc_pc_nxt[7:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:162$1401'. 1/1: $0\mc_rst_n[0:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:374$1398'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:353$1389'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:349$1387'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:340$1384'. 1/1: $0\token_data[10:8] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:336$1381'. 1/1: $0\token_data[7:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1364'. 1/5: $0\pid_is_handshake[0:0] 2/5: $0\pid_is_data[0:0] 3/5: $0\pid_is_token[0:0] 4/5: $0\pid_is_sof[0:0] 5/5: $0\pid[3:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:318$1363'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:304$1342'. 1/1: $0\pid_valid[0:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1338'. 1/2: $0\crc16_ok[0:0] 2/2: $0\crc5_ok[0:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:284$1337'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:244$1335'. 1/1: $0\crc_in_first[0:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:230$1332'. 1/1: $0\bit_eop_ok[0:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:220$1329'. 1/1: $0\bit_cnt[3:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:215$1328'. 1/1: $0\data[7:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:198$1320'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:188$1319'. 1/1: $0\state[3:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:117$1303'. 1/18: $18\state_nxt[3:0] 2/18: $17\state_nxt[3:0] 3/18: $16\state_nxt[3:0] 4/18: $15\state_nxt[3:0] 5/18: $14\state_nxt[3:0] 6/18: $13\state_nxt[3:0] 7/18: $12\state_nxt[3:0] 8/18: $11\state_nxt[3:0] 9/18: $10\state_nxt[3:0] 10/18: $9\state_nxt[3:0] 11/18: $8\state_nxt[3:0] 12/18: $7\state_nxt[3:0] 13/18: $6\state_nxt[3:0] 14/18: $5\state_nxt[3:0] 15/18: $4\state_nxt[3:0] 16/18: $3\state_nxt[3:0] 17/18: $2\state_nxt[3:0] 18/18: $1\state_nxt[3:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:49$1302'. Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:181$1300'. 1/1: $0\dec_bs_skip_1[0:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1298'. 1/1: $0\dec_rep_state_1[3:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:137$1297'. 1/1: $0\dec_sync_state_1[3:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:124$1296'. 1/1: $0\dec_eop_state_1[2:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:120$1295'. Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:111$1288'. 1/2: $0\dec_bit_1[0:0] 2/2: $0\dec_sym_1[1:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:97$1281'. Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1280'. 1/1: $0\samp_cnt[2:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:67$1270'. 1/1: $0\samp_active[0:0] Creating decoders for process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5107'. 1/4: $0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5106_EN[7:0]$5110 2/4: $0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5106_DATA[7:0]$5109 3/4: $0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5106_ADDR[8:0]$5108 4/4: $0\rd_data[7:0] Creating decoders for process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:80$1266'. 1/1: $0\s_dout_3[15:0] Creating decoders for process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:76$1264'. 1/1: $0\p_dout_3[15:0] Creating decoders for process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1261'. Creating decoders for process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1253'. Creating decoders for process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:163$5101'. 1/1: $0\wb_rdata_reg[31:0] Creating decoders for process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:160$5099'. Creating decoders for process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:147$5074'. Creating decoders for process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:91$5071'. Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4210'. Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4201'. 1/1: $0\stage[4].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4199'. 1/1: $0\stage[4].l_data[6:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4190'. 1/1: $0\stage[3].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4188'. 1/1: $0\stage[3].l_data[6:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4179'. 1/1: $0\stage[2].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4177'. 1/1: $0\stage[2].l_data[6:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4168'. 1/1: $0\stage[1].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4166'. 1/1: $0\stage[1].l_data[6:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4164'. Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4155'. 1/1: $0\stage[4].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4153'. 1/1: $0\stage[4].l_data[8:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4144'. 1/1: $0\stage[3].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4142'. 1/1: $0\stage[3].l_data[8:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4133'. 1/1: $0\stage[2].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4131'. 1/1: $0\stage[2].l_data[8:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4122'. 1/1: $0\stage[1].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4120'. 1/1: $0\stage[1].l_data[8:0] Creating decoders for process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:0$5032'. Creating decoders for process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:125$5027'. 1/1: $0\wb_rdata[15:0] Creating decoders for process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:117$5022'. Creating decoders for process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:106$5017'. Creating decoders for process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:40$1098'. 1/1: $0\out_stb[0:0] Creating decoders for process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:34$1097'. 1/1: $0\dst[1:0] Creating decoders for process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:28$1095'. 1/1: $0\src[0:0] Creating decoders for process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:149$4098'. 1/1: $0\wb_now[0:0] Creating decoders for process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4089'. 1/3: $0\wb_req[0:0] 2/3: $0\wb_sel[1:0] 3/3: $0\rst_req[0:0] Creating decoders for process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:109$4085'. 1/1: $0\timer[25:0] Creating decoders for process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:103$4083'. 1/1: $0\armed[0:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. 1/82: $0\reg_next_pc[31:0] [31:2] 2/82: $0\reg_next_pc[31:0] [1:0] 3/82: $0\reg_pc[31:0] [1:0] 4/82: $18\next_irq_pending[2:2] 5/82: $17\next_irq_pending[2:2] 6/82: $16\next_irq_pending[2:2] 7/82: $15\next_irq_pending[2:2] 8/82: $14\next_irq_pending[2:2] 9/82: $13\next_irq_pending[2:2] 10/82: $4\next_irq_pending[31:0] [31:2] 11/82: $3\set_mem_do_rdata[0:0] 12/82: $4\next_irq_pending[31:0] [1] 13/82: $3\set_mem_do_wdata[0:0] 14/82: $4\next_irq_pending[31:0] [0] 15/82: $4\set_mem_do_rinst[0:0] 16/82: $3\set_mem_do_rinst[0:0] 17/82: $4\set_mem_do_wdata[0:0] 18/82: $11\next_irq_pending[1:1] 19/82: $10\next_irq_pending[1:1] 20/82: $9\next_irq_pending[1:1] 21/82: $4\set_mem_do_rdata[0:0] 22/82: $7\next_irq_pending[1:1] 23/82: $6\next_irq_pending[1:1] 24/82: $12\next_irq_pending[1:1] 25/82: $5\set_mem_do_rinst[0:0] 26/82: $8\next_irq_pending[1:1] 27/82: $5\next_irq_pending[31:0] 28/82: $3\current_pc[31:0] 29/82: $2\current_pc[31:0] 30/82: $2\set_mem_do_wdata[0:0] 31/82: $2\set_mem_do_rdata[0:0] 32/82: $2\set_mem_do_rinst[0:0] 33/82: $3\next_irq_pending[31:0] 34/82: $1\current_pc[31:0] 35/82: $1\set_mem_do_wdata[0:0] 36/82: $1\set_mem_do_rdata[0:0] 37/82: $1\set_mem_do_rinst[0:0] 38/82: $0\trace_data[35:0] 39/82: $2\next_irq_pending[0:0] 40/82: $1\next_irq_pending[0:0] 41/82: $0\count_instr[63:0] 42/82: $0\count_cycle[63:0] 43/82: $0\trace_valid[0:0] 44/82: $0\do_waitirq[0:0] 45/82: $0\decoder_pseudo_trigger[0:0] 46/82: $0\decoder_trigger[0:0] 47/82: $0\alu_wait_2[0:0] 48/82: $0\alu_wait[0:0] 49/82: $0\reg_out[31:0] 50/82: $0\reg_sh[4:0] 51/82: $0\trap[0:0] 52/82: $0\pcpi_timeout[0:0] 53/82: $0\latched_rd[4:0] 54/82: $0\latched_is_lb[0:0] 55/82: $0\latched_is_lh[0:0] 56/82: $0\latched_is_lu[0:0] 57/82: $0\latched_trace[0:0] 58/82: $0\latched_compr[0:0] 59/82: $0\latched_branch[0:0] 60/82: $0\latched_stalu[0:0] 61/82: $0\latched_store[0:0] 62/82: $0\irq_state[1:0] 63/82: $0\cpu_state[7:0] 64/82: $0\dbg_rs2val_valid[0:0] 65/82: $0\dbg_rs1val_valid[0:0] 66/82: $0\dbg_rs2val[31:0] 67/82: $0\dbg_rs1val[31:0] 68/82: $0\mem_do_wdata[0:0] 69/82: $0\mem_do_rdata[0:0] 70/82: $0\mem_do_rinst[0:0] 71/82: $0\mem_do_prefetch[0:0] 72/82: $0\mem_wordsize[1:0] 73/82: $0\irq_mask[31:0] 74/82: $0\irq_active[0:0] 75/82: $0\irq_delay[0:0] 76/82: $0\reg_op2[31:0] 77/82: $0\reg_op1[31:0] 78/82: $0\reg_pc[31:0] [31:2] 79/82: $19\next_irq_pending[2:2] 80/82: $0\eoi[31:0] 81/82: $0\pcpi_valid[0:0] 82/82: $0\timer[31:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$3891'. Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1288$3877'. 1/4: $2\cpuregs_write[0:0] 2/4: $2\cpuregs_wrdata[31:0] 3/4: $1\cpuregs_wrdata[31:0] 4/4: $1\cpuregs_write[0:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1274$3872'. 1/2: $2\clear_prefetched_high_word[0:0] 2/2: $1\clear_prefetched_high_word[0:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1272$3871'. Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1228$3849'. 1/2: $1\alu_out[31:0] 2/2: $1\alu_out_0[0:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1165$3837'. 1/8: $8\dbg_ascii_state[127:0] 2/8: $7\dbg_ascii_state[127:0] 3/8: $6\dbg_ascii_state[127:0] 4/8: $5\dbg_ascii_state[127:0] 5/8: $4\dbg_ascii_state[127:0] 6/8: $3\dbg_ascii_state[127:0] 7/8: $2\dbg_ascii_state[127:0] 8/8: $1\dbg_ascii_state[127:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. 1/76: $0\decoded_rs1[4:0] [4] 2/76: $0\decoded_imm_uj[31:0] [10] 3/76: $0\decoded_imm_uj[31:0] [7] 4/76: $0\decoded_imm_uj[31:0] [6] 5/76: $0\decoded_imm_uj[31:0] [3:1] 6/76: $0\decoded_imm_uj[31:0] [5] 7/76: $0\decoded_imm_uj[31:0] [9:8] 8/76: $0\decoded_imm_uj[31:0] [31:20] 9/76: $0\decoded_imm_uj[31:0] [4] 10/76: $0\decoded_imm_uj[31:0] [11] 11/76: $0\decoded_imm_uj[31:0] [0] 12/76: $0\decoded_rs1[4:0] [3:0] 13/76: $0\is_lui_auipc_jal_jalr_addi_add_sub[0:0] 14/76: $0\is_alu_reg_reg[0:0] 15/76: $0\is_alu_reg_imm[0:0] 16/76: $0\is_beq_bne_blt_bge_bltu_bgeu[0:0] 17/76: $0\is_sll_srl_sra[0:0] 18/76: $0\is_sb_sh_sw[0:0] 19/76: $0\is_jalr_addi_slti_sltiu_xori_ori_andi[0:0] 20/76: $0\is_slli_srli_srai[0:0] 21/76: $0\is_lb_lh_lw_lbu_lhu[0:0] 22/76: $0\compressed_instr[0:0] 23/76: $0\is_compare[0:0] 24/76: $0\decoded_imm[31:0] 25/76: $0\decoded_rs2[4:0] 26/76: $0\decoded_imm_uj[31:0] [19:12] 27/76: $0\decoded_rd[4:0] 28/76: $0\instr_timer[0:0] 29/76: $0\instr_waitirq[0:0] 30/76: $0\instr_maskirq[0:0] 31/76: $0\instr_retirq[0:0] 32/76: $0\instr_setq[0:0] 33/76: $0\instr_getq[0:0] 34/76: $0\instr_ecall_ebreak[0:0] 35/76: $0\instr_rdinstrh[0:0] 36/76: $0\instr_rdinstr[0:0] 37/76: $0\instr_rdcycleh[0:0] 38/76: $0\instr_rdcycle[0:0] 39/76: $0\instr_and[0:0] 40/76: $0\instr_or[0:0] 41/76: $0\instr_sra[0:0] 42/76: $0\instr_srl[0:0] 43/76: $0\instr_xor[0:0] 44/76: $0\instr_sltu[0:0] 45/76: $0\instr_slt[0:0] 46/76: $0\instr_sll[0:0] 47/76: $0\instr_sub[0:0] 48/76: $0\instr_add[0:0] 49/76: $0\instr_srai[0:0] 50/76: $0\instr_srli[0:0] 51/76: $0\instr_slli[0:0] 52/76: $0\instr_andi[0:0] 53/76: $0\instr_ori[0:0] 54/76: $0\instr_xori[0:0] 55/76: $0\instr_sltiu[0:0] 56/76: $0\instr_slti[0:0] 57/76: $0\instr_addi[0:0] 58/76: $0\instr_sw[0:0] 59/76: $0\instr_sh[0:0] 60/76: $0\instr_sb[0:0] 61/76: $0\instr_lhu[0:0] 62/76: $0\instr_lbu[0:0] 63/76: $0\instr_lw[0:0] 64/76: $0\instr_lh[0:0] 65/76: $0\instr_lb[0:0] 66/76: $0\instr_bgeu[0:0] 67/76: $0\instr_bltu[0:0] 68/76: $0\instr_bge[0:0] 69/76: $0\instr_blt[0:0] 70/76: $0\instr_bne[0:0] 71/76: $0\instr_beq[0:0] 72/76: $0\instr_jalr[0:0] 73/76: $0\instr_jal[0:0] 74/76: $0\instr_auipc[0:0] 75/76: $0\instr_lui[0:0] 76/76: $0\pcpi_insn[31:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3575'. 1/13: $3\dbg_insn_opcode[31:0] 2/13: $2\dbg_insn_rd[4:0] 3/13: $2\dbg_insn_rs2[4:0] 4/13: $2\dbg_insn_rs1[4:0] 5/13: $2\dbg_insn_opcode[31:0] 6/13: $2\dbg_insn_imm[31:0] 7/13: $2\dbg_ascii_instr[63:0] 8/13: $1\dbg_insn_rd[4:0] 9/13: $1\dbg_insn_rs2[4:0] 10/13: $1\dbg_insn_rs1[4:0] 11/13: $1\dbg_insn_imm[31:0] 12/13: $1\dbg_ascii_instr[63:0] 13/13: $1\dbg_insn_opcode[31:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3571'. 1/8: $0\cached_insn_rd[4:0] 2/8: $0\cached_insn_rs2[4:0] 3/8: $0\cached_insn_rs1[4:0] 4/8: $0\cached_insn_opcode[31:0] 5/8: $0\cached_insn_imm[31:0] 6/8: $0\cached_ascii_instr[63:0] 7/8: $0\dbg_valid_insn[0:0] 8/8: $0\dbg_insn_addr[31:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:684$3570'. 1/47: $47\new_ascii_instr[63:0] 2/47: $46\new_ascii_instr[63:0] 3/47: $45\new_ascii_instr[63:0] 4/47: $44\new_ascii_instr[63:0] 5/47: $43\new_ascii_instr[63:0] 6/47: $42\new_ascii_instr[63:0] 7/47: $41\new_ascii_instr[63:0] 8/47: $40\new_ascii_instr[63:0] 9/47: $39\new_ascii_instr[63:0] 10/47: $38\new_ascii_instr[63:0] 11/47: $37\new_ascii_instr[63:0] 12/47: $36\new_ascii_instr[63:0] 13/47: $35\new_ascii_instr[63:0] 14/47: $34\new_ascii_instr[63:0] 15/47: $33\new_ascii_instr[63:0] 16/47: $32\new_ascii_instr[63:0] 17/47: $31\new_ascii_instr[63:0] 18/47: $30\new_ascii_instr[63:0] 19/47: $29\new_ascii_instr[63:0] 20/47: $28\new_ascii_instr[63:0] 21/47: $27\new_ascii_instr[63:0] 22/47: $26\new_ascii_instr[63:0] 23/47: $25\new_ascii_instr[63:0] 24/47: $24\new_ascii_instr[63:0] 25/47: $23\new_ascii_instr[63:0] 26/47: $22\new_ascii_instr[63:0] 27/47: $21\new_ascii_instr[63:0] 28/47: $20\new_ascii_instr[63:0] 29/47: $19\new_ascii_instr[63:0] 30/47: $18\new_ascii_instr[63:0] 31/47: $17\new_ascii_instr[63:0] 32/47: $16\new_ascii_instr[63:0] 33/47: $15\new_ascii_instr[63:0] 34/47: $14\new_ascii_instr[63:0] 35/47: $13\new_ascii_instr[63:0] 36/47: $12\new_ascii_instr[63:0] 37/47: $11\new_ascii_instr[63:0] 38/47: $10\new_ascii_instr[63:0] 39/47: $9\new_ascii_instr[63:0] 40/47: $8\new_ascii_instr[63:0] 41/47: $7\new_ascii_instr[63:0] 42/47: $6\new_ascii_instr[63:0] 43/47: $5\new_ascii_instr[63:0] 44/47: $4\new_ascii_instr[63:0] 45/47: $3\new_ascii_instr[63:0] 46/47: $2\new_ascii_instr[63:0] 47/47: $1\new_ascii_instr[63:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3546'. 1/9: $0\mem_16bit_buffer[15:0] 2/9: $0\prefetched_high_word[0:0] 3/9: $0\mem_la_secondword[0:0] 4/9: $0\mem_state[1:0] 5/9: $0\mem_wstrb[3:0] 6/9: $0\mem_wdata[31:0] 7/9: $0\mem_instr[0:0] 8/9: $0\mem_valid[0:0] 9/9: $0\mem_addr[31:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1218$4070'. Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:414$3508'. 1/9: $0\mem_rdata_q[31:0] [31] 2/9: $0\mem_rdata_q[31:0] [7] 3/9: $0\mem_rdata_q[31:0] [24:20] 4/9: $0\mem_rdata_q[31:0] [19:15] 5/9: $0\mem_rdata_q[31:0] [6:0] 6/9: $0\mem_rdata_q[31:0] [14:12] 7/9: $0\mem_rdata_q[31:0] [11:8] 8/9: $0\mem_rdata_q[31:0] [30:25] 9/9: $0\next_insn_opcode[31:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3505'. 1/5: $3\mem_rdata_word[31:0] 2/5: $2\mem_rdata_word[31:0] 3/5: $1\mem_rdata_word[31:0] 4/5: $1\mem_la_wstrb[3:0] 5/5: $1\mem_la_wdata[31:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:374$3500'. 1/2: $0\last_mem_valid[0:0] 2/2: $0\mem_la_firstword_reg[0:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3426'. 1/2: $1\pcpi_int_rd[31:0] 2/2: $1\pcpi_int_wr[0:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5008'. Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5007'. Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5002'. 1/1: $0\rx_pending[1:1] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5001'. 1/2: $0\rx_addr_reg[1][15:0] 2/2: $0\rx_data_reg[1][7:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$4996'. 1/1: $0\rx_pending[0:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$4995'. 1/2: $0\rx_addr_reg[0][15:0] 2/2: $0\rx_data_reg[0][7:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$4985'. 1/3: $1\t_done[3:0] 2/3: $1$bitselwrite$data$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:268$4944[3:0]$4989 3/3: $1$bitselwrite$mask$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:268$4943[3:0]$4988 Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4952'. 1/20: $2$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$4938[15:0]$4981 2/20: $2$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$4937[15:0]$4980 3/20: $2$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$4936[15:0]$4978 4/20: $2$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$4935[15:0]$4977 5/20: $2$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$4932[15:0]$4975 6/20: $2$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$4931[15:0]$4974 7/20: $2$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$4930[15:0]$4972 8/20: $2$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$4929[15:0]$4971 9/20: $1\mux.j[31:0] 10/20: $1$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$4938[15:0]$4969 11/20: $1$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$4937[15:0]$4968 12/20: $1$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$4936[15:0]$4967 13/20: $1$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$4935[15:0]$4966 14/20: $1$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$4932[15:0]$4965 15/20: $1$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$4931[15:0]$4964 16/20: $1$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$4930[15:0]$4963 17/20: $1$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$4929[15:0]$4962 18/20: $0\wb_wdata_byte[7:0] 19/20: $0\wb_addr_lsb[1:0] 20/20: $0\wb_addr[13:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:212$4949'. 1/1: $0\t_chan[1:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:206$4947'. 1/1: $0\t_busy[0:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$4945'. 1/4: $4\t_nxt_chan[1:0] 2/4: $3\t_nxt_chan[1:0] 3/4: $2\t_nxt_chan[1:0] 4/4: $1\t_nxt_chan[1:0] Creating decoders for process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3316'. 1/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3312_EN[31:0]$3319 2/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3312_DATA[31:0]$3318 3/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3312_ADDR[7:0]$3317 4/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3313_EN[31:0]$3322 5/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3313_DATA[31:0]$3321 6/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3313_ADDR[7:0]$3320 7/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3314_EN[31:0]$3325 8/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3314_DATA[31:0]$3324 9/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3314_ADDR[7:0]$3323 10/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3315_EN[31:0]$3328 11/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3315_DATA[31:0]$3327 12/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3315_ADDR[7:0]$3326 Creating decoders for process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:193$3307'. 1/1: $0\uart_div[11:0] Creating decoders for process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:185$3305'. 1/1: $0\ub_rdata[31:0] Creating decoders for process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:177$3295'. 1/1: $0\ub_ack[0:0] Creating decoders for process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3278'. 1/4: $0\ub_wr_div[0:0] 2/4: $0\ub_wr_data[0:0] 3/4: $0\ub_rd_ctrl[0:0] 4/4: $0\ub_rd_data[0:0] Creating decoders for process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:154$3273'. 1/1: $0\urf_overflow[0:0] Creating decoders for process `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.$proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3266'. 1/1: $0\led_ctrl[4:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:536$3260'. 1/1: $0\evt_cnt[3:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:656$3255'. Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:653$3253'. Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:643$3252'. 1/1: $0\pad_pu[0:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:636$3248'. 1/1: $0\rst_pending[0:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:628$3244'. 1/1: $0\timeout_reset[19:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:619$3240'. 1/1: $0\timeout_suspend[19:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:514$3226'. 1/1: $0\eps_bus_ack_wait[0:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:510$3223'. Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3213'. 1/3: $0\eps_bus_req[0:0] 2/3: $0\eps_bus_write[0:0] 3/3: $0\eps_bus_read[0:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:697$3264'. Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3211'. 1/4: $0\cr_addr[6:0] 2/4: $0\cr_addr_chk[0:0] 3/4: $0\cr_cel_ena[0:0] 4/4: $0\cr_pu_ena[0:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:442$3207'. 1/2: $2\csr_bus_dout[15:0] 2/2: $1\csr_bus_dout[15:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3189'. 1/7: $0\ir_bus_we[0:0] 2/7: $0\evt_rd_ack[0:0] 3/7: $0\sof_clear[0:0] 4/7: $0\rst_clear[0:0] 5/7: $0\cel_rel[0:0] 6/7: $0\cr_bus_we[0:0] 7/7: $0\csr_bus_req[0:0] Creating decoders for process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:99$3185'. 1/1: $0\m_cyc_i[0:0] Creating decoders for process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:83$3181'. Creating decoders for process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:73$3178'. 1/1: $0\s_rdata[15:0] Creating decoders for process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:68$3177'. 1/1: $0\m_rdata_i[15:0] Creating decoders for process `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v:50$4916'. 1/1: $0\ack_i[0:0] Creating decoders for process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4895'. 1/2: $0\busy[0:0] 2/2: $0\sel[2:0] Creating decoders for process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$4886'. 1/3: $0\sel_nxt[2:0] [2] 2/3: $0\sel_nxt[2:0] [0] 3/3: $0\sel_nxt[2:0] [1] Creating decoders for process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4883'. 1/4: $0\m_wmsk[3:0] 2/4: $0\m_we[0:0] 3/4: $0\m_wdata[31:0] 4/4: $0\m_addr[13:0] Creating decoders for process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4864'. Creating decoders for process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3094'. Creating decoders for process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3092'. Creating decoders for process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3090'. Creating decoders for process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:185$3089'. 1/1: $0\pb_rst_n[0:0] Creating decoders for process `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2941'. Creating decoders for process `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$2938'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2937'. Creating decoders for process `\SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1274$2931'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2930'. Creating decoders for process `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$2927'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2926'. Creating decoders for process `\SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1143$2920'. 1/1: $0\Q[0:0] Creating decoders for process `\e1_rx_liu.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_liu.v:60$174'. Creating decoders for process `\e1_rx_liu.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_liu.v:53$173'. Creating decoders for process `\SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2919'. Creating decoders for process `\SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1074$2917'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2916'. Creating decoders for process `\SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1026$2914'. 1/1: $0\Q[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:395$138'. 1/1: $0\aligned[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:360$132'. 1/7: $0\out_last[0:0] 2/7: $0\out_first[0:0] 3/7: $0\out_ts_is0[0:0] 4/7: $0\out_ts[4:0] 5/7: $0\out_frame[3:0] 6/7: $0\out_data[7:0] 7/7: $0\out_valid[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$124'. Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:339$106'. 1/4: $0\ec_mfa[1:0] 2/4: $0\ec_crc[1:0] 3/4: $0\ec_nfas[1:0] 4/4: $0\ec_fas[1:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:324$88'. 1/4: $0\ed_mfa[0:0] 2/4: $0\ep_mfa[0:0] 3/4: $0\ed_crc[0:0] 4/4: $0\ep_crc[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:310$66'. 1/4: $0\ed_nfas[0:0] 2/4: $0\ep_nfas[0:0] 3/4: $0\ed_fas[0:0] 4/4: $0\ep_fas[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:301$65'. 1/1: $0\crc_smf[3:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:269$54'. 1/3: $0\ts0_msbs_match_crc[0:0] 2/3: $0\ts0_msbs_match_mf[0:0] 3/3: $0\ts0_msbs[15:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:261$50'. 1/1: $0\mfa_timeout[6:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:253$46'. 1/1: $0\fas_pos[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:226$38'. 1/5: $0\frame_mf_last[0:0] 2/5: $0\frame_mf_first[0:0] 3/5: $0\frame_smf_last[0:0] 4/5: $0\frame_smf_first[0:0] 5/5: $0\frame[3:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:214$34'. 1/3: $0\ts_is_ts31[0:0] 2/3: $0\ts_is_ts0[0:0] 3/3: $0\ts[4:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:202$30'. 1/3: $0\bit_last[0:0] 2/3: $0\bit_first[0:0] 3/3: $0\bit[2:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:146$23'. 1/1: $0\fsm_state_nxt[2:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:139$21'. 1/1: $0\fsm_state[2:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:130$18'. 1/1: $0\data_match_fas[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:125$17'. 1/1: $0\data[7:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:118$16'. 1/1: $0\strobe[0:0] Creating decoders for process `\SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2913'. Creating decoders for process `\SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:957$2911'. 1/1: $0\Q[0:0] Creating decoders for process `\e1_crc4.$proc$/build/gateware/cores/no2e1//rtl/e1_crc4.v:38$10'. 1/1: $0\state[3:0] 73.3.7. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\sel_nxt' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$4834'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\prio.i' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$4834'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\mux_addr' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4818'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\mux_wdata' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4818'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\mux_wmsk' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4818'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\mux.i' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4818'. No latch inferred for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\state_nxt' from process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:98$4760'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:92$4739$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4751'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:92$4742$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4751'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:92$4742$\sig' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4751'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:91$4738$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4747'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:91$4741$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4747'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:91$4741$\sig' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4747'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:81$4737$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4743'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:81$4740$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4743'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:81$4740$\sig' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4743'. No latch inferred for signal `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\cnt_move' from process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4715'. No latch inferred for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\cnt_move' from process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4482'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5176$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5218'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5185$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5218'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5185$\wdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5218'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5175$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5214'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5184$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5214'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5184$\rdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5214'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5174$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5210'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5183$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5210'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5183$\wdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5210'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5173$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5206'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5182$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5206'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5182$\rdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5206'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5172$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5202'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5181$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5202'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5181$\wdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5202'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5171$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5198'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5180$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5198'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5180$\rdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5198'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5170$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5194'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5179$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5194'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5179$\wdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5194'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5169$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5190'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5178$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5190'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5178$\rdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5190'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:220$5168$\ram_wr_shuffle_32' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5186'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:220$5177$\ram_wr_shuffle_32' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5186'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:220$5177$\src' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5186'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_do_m[0]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4473'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di[0]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4473'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di[1]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4473'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm[0]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4473'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm[1]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4473'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\rd_data' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\map.n' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\map.x' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\map.o' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317'. Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [0]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$15252 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [1]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$15367 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [2]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$15530 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [3]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$15741 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [4]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$15952 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [5]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$16163 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [6]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$16374 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [7]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$16585 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [8]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$16796 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [9]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$17007 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [10]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$17218 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [11]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$17429 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [12]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$17640 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [13]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$17851 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [14]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$18062 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [15]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$18273 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [16]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$18484 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [17]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$18695 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [18]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$18906 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [19]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$19117 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [20]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$19328 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [21]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$19539 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [22]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$19750 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [23]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$19961 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [24]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$20172 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [25]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$20383 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [26]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$20594 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [27]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$20805 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [28]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$21016 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [29]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$21227 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [30]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$21438 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [31]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$21649 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [0]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$21716 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [1]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$21783 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [2]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$21850 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [3]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$21917 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [4]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$21984 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [5]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$22051 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [6]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$22118 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [7]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317': $auto$proc_dlatch.cc:430:proc_dlatch$22185 No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5121$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5163'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5130$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5163'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5130$\wdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5163'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5120$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5159'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5129$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5159'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5129$\rdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5159'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5119$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5155'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5128$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5155'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5128$\wdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5155'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5118$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5151'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5127$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5151'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5127$\rdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5151'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5117$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5147'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5126$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5147'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5126$\wdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5147'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5116$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5143'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5125$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5143'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5125$\rdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5143'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5115$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5139'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5124$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5139'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5124$\wdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5139'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5114$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5135'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5123$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5135'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5123$\rdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5135'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:211$5113$\ram_rd_shuffle_32' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5131'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:211$5122$\ram_rd_shuffle_32' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5131'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:211$5122$\src' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5131'. No latch inferred for signal `\usb_tx_pkt.\shift_load' from process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:159$1541'. No latch inferred for signal `\usb_tx_pkt.\state_nxt' from process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:86$1523'. No latch inferred for signal `\usb_rx_pkt.\state_nxt' from process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:117$1303'. No latch inferred for signal `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.\wb_rdata_or' from process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:147$5074'. No latch inferred for signal `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.\wb_or.i' from process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:147$5074'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[0]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4210'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[1]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4210'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[2]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4210'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[3]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4210'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[4]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4210'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[5]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4210'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[0]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4164'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[1]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4164'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[2]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4164'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[3]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4164'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[4]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4164'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[5]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4164'. No latch inferred for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.\bus_rdata_tx[0]' from process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:0$5032'. No latch inferred for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.\bus_rdata_tx[1]' from process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:0$5032'. No latch inferred for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.\bus_rdata' from process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:117$5022'. No latch inferred for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.\rdata_or.j' from process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:117$5022'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cpuregs_rs1' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$3891'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cpuregs_rs2' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$3891'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\decoded_rs' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$3891'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cpuregs_write' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1288$3877'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cpuregs_wrdata' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1288$3877'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\clear_prefetched_high_word' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1274$3872'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_out' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1228$3849'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_out_0' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1228$3849'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_ascii_state' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1165$3837'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_insn_opcode' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3575'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_ascii_instr' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3575'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_insn_imm' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3575'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_insn_rs1' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3575'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_insn_rs2' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3575'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_insn_rd' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3575'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\new_ascii_instr' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:684$3570'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_add_sub' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1218$4070'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_shl' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1218$4070'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_shr' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1218$4070'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_eq' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1218$4070'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_ltu' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1218$4070'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_lts' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1218$4070'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_la_wdata' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3505'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_la_wstrb' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3505'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_rdata_word' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3505'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\pcpi_int_wr' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3426'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\pcpi_int_rd' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3426'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\pcpi_int_wait' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3426'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\pcpi_int_ready' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3426'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\t_done' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$4985'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$bitselwrite$mask$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:268$4943' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$4985'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$bitselwrite$data$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:268$4944' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$4985'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\t_nxt_busy' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$4945'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\t_nxt_chan' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$4945'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\next_sel.j' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$4945'. No latch inferred for signal `$paramod\usb\EPDW=32.\irq' from process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:697$3264'. No latch inferred for signal `$paramod\usb\EPDW=32.\csr_bus_dout' from process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:442$3207'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\sel_nxt' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$4886'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\prio.i' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$4886'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\mux_addr' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4864'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\mux_wdata' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4864'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\mux_wmsk' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4864'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\mux.i' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4864'. No latch inferred for signal `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.\wb_rdata[3] [31:16]' from process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3094'. No latch inferred for signal `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.\wb_rdata[5]' from process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3094'. No latch inferred for signal `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.\wb_rdata[6]' from process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3094'. No latch inferred for signal `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.\wb_rdata[7] [31:16]' from process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3094'. No latch inferred for signal `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$mem2bits$\wb_rdata$/build/gateware/common/rtl/soc_base.v:499$3088' from process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3092'. No latch inferred for signal `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$mem2bits$\wb_rdata$/build/gateware/common/rtl/soc_base.v:402$3087' from process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3090'. No latch inferred for signal `\e1_rx_deframer.\fsm_state_nxt' from process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:146$23'. 73.3.8. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:909$2908'. created $dff cell `$procdff$22186' with negative edge clock. Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:866$2906'. created $dff cell `$procdff$22187' with negative edge clock. Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:830$2904'. created $dff cell `$procdff$22188' with negative edge clock. Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$2900'. created $adff cell `$procdff$22189' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:697$2893'. created $dff cell `$procdff$22190' with positive edge clock. Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$2889'. created $adff cell `$procdff$22191' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:566$2882'. created $dff cell `$procdff$22192' with positive edge clock. Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:497$2879'. created $adff cell `$procdff$22193' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:449$2876'. created $dff cell `$procdff$22194' with positive edge clock. Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:380$2873'. created $adff cell `$procdff$22195' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:332$2870'. created $dff cell `$procdff$22196' with positive edge clock. Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:289$2868'. created $dff cell `$procdff$22197' with positive edge clock. Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:253$2866'. created $dff cell `$procdff$22198' with positive edge clock. Creating register for signal `$paramod\wb_epbuf\AW=9\DW=32.\ack_i' using process `$paramod\wb_epbuf\AW=9\DW=32.$proc$/build/gateware/common/rtl/wb_epbuf.v:51$4852'. created $adff cell `$procdff$22199' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\sel' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4841'. created $adff cell `$procdff$22200' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\busy' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4841'. created $adff cell `$procdff$22201' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\m_addr' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4831'. created $adff cell `$procdff$22202' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\m_wdata' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4831'. created $adff cell `$procdff$22203' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\m_we' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4831'. created $adff cell `$procdff$22204' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\m_wmsk' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4831'. created $adff cell `$procdff$22205' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\ctl_do_write' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$4799'. created $adff cell `$procdff$22206' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\ctl_do_read' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$4799'. created $adff cell `$procdff$22207' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\ctl_ack_i' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$4799'. created $adff cell `$procdff$22208' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\dir' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:178$4795'. created $dff cell `$procdff$22209' with positive edge clock. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\len' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:174$4792'. created $dff cell `$procdff$22210' with positive edge clock. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\m1_addr_i' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:157$4782'. created $dff cell `$procdff$22211' with positive edge clock. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\m0_addr_i' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:153$4778'. created $dff cell `$procdff$22212' with positive edge clock. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\data_reg' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:142$4776'. created $dff cell `$procdff$22213' with positive edge clock. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\state' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:92$4759'. created $adff cell `$procdff$22214' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\go' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:86$4755'. created $adff cell `$procdff$22215' with positive edge clock and positive level reset. Creating register for signal `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\sync' using process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4736'. created $dff cell `$procdff$22216' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\rise' using process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4731'. created $dff cell `$procdff$22217' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\fall' using process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4731'. created $dff cell `$procdff$22218' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\state' using process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4727'. created $dff cell `$procdff$22219' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\cnt' using process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4723'. created $dff cell `$procdff$22220' with positive edge clock. Creating register for signal `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100.\state' using process `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4713'. created $dff cell `$procdff$22221' with positive edge clock. Creating register for signal `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101.\state' using process `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4700'. created $dff cell `$procdff$22222' with positive edge clock. Creating register for signal `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.\dp_state' using process `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4676'. created $adff cell `$procdff$22223' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.\dn_state' using process `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4676'. created $adff cell `$procdff$22224' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_rx\LIU=1\MFW=7.\bd_crc_e' using process `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:199$5306'. created $adff cell `$procdff$22225' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_rx\LIU=1\MFW=7.\bd_done' using process `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:192$5300'. created $dff cell `$procdff$22226' with positive edge clock. Creating register for signal `$paramod\e1_rx\LIU=1\MFW=7.\bd_miss' using process `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:192$5300'. created $dff cell `$procdff$22227' with positive edge clock. Creating register for signal `$paramod\e1_rx\LIU=1\MFW=7.\mf_valid' using process `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:184$5296'. created $adff cell `$procdff$22228' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_rx\LIU=1\MFW=7.\tx_crc_e_auto' using process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:253$5290'. created $dff cell `$procdff$22229' with positive edge clock. Creating register for signal `$paramod\e1_wb_rx\LIU=1\MFW=7.\rx_overflow' using process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:246$5286'. created $adff cell `$procdff$22230' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_rx\LIU=1\MFW=7.\rx_rst' using process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:239$5284'. created $adff cell `$procdff$22231' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_rx\LIU=1\MFW=7.\bri_wren' using process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$5266'. created $dff cell `$procdff$22232' with positive edge clock. Creating register for signal `$paramod\e1_wb_rx\LIU=1\MFW=7.\bro_rden' using process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$5266'. created $dff cell `$procdff$22233' with positive edge clock. Creating register for signal `$paramod\e1_wb_rx\LIU=1\MFW=7.\rx_enabled' using process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$5265'. created $adff cell `$procdff$22234' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_rx\LIU=1\MFW=7.\rx_mode' using process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$5265'. created $adff cell `$procdff$22235' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_rx\LIU=1\MFW=7.\crx_wren' using process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$5257'. created $dff cell `$procdff$22236' with positive edge clock. Creating register for signal `$paramod\e1_wb_rx\LIU=1\MFW=7.\crx_clear' using process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$5257'. created $dff cell `$procdff$22237' with positive edge clock. Creating register for signal `$paramod\uart_tx\DIV_WIDTH=12.\ack' using process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:67$5256'. created $dff cell `$procdff$22238' with positive edge clock. Creating register for signal `$paramod\uart_tx\DIV_WIDTH=12.\shift' using process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5255'. created $adff cell `$procdff$22239' with positive edge clock and positive level reset. Creating register for signal `$paramod\uart_tx\DIV_WIDTH=12.\bit_cnt' using process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:51$5252'. created $dff cell `$procdff$22240' with positive edge clock. Creating register for signal `$paramod\uart_tx\DIV_WIDTH=12.\div_cnt' using process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:42$5248'. created $dff cell `$procdff$22241' with positive edge clock. Creating register for signal `$paramod\uart_tx\DIV_WIDTH=12.\active' using process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:35$5244'. created $adff cell `$procdff$22242' with positive edge clock and positive level reset. Creating register for signal `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.\stb' using process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:102$5238'. created $dff cell `$procdff$22243' with positive edge clock. Creating register for signal `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.\shift' using process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:95$5237'. created $dff cell `$procdff$22244' with positive edge clock. Creating register for signal `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.\bit_cnt' using process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:88$5234'. created $dff cell `$procdff$22245' with positive edge clock. Creating register for signal `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.\div_cnt' using process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:77$5230'. created $dff cell `$procdff$22246' with positive edge clock. Creating register for signal `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.\active' using process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:70$5226'. created $adff cell `$procdff$22247' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.\rd_valid' using process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4527'. created $adff cell `$procdff$22248' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.\ram_rd_addr' using process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4521'. created $adff cell `$procdff$22249' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.\ram_wr_addr' using process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4519'. created $adff cell `$procdff$22250' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.\full' using process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:83$4510'. created $adff cell `$procdff$22251' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.\level' using process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:67$4504'. created $adff cell `$procdff$22252' with positive edge clock and positive level reset. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\sync' using process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4503'. created $dff cell `$procdff$22253' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\rise' using process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4498'. created $dff cell `$procdff$22254' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\fall' using process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4498'. created $dff cell `$procdff$22255' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\state' using process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4494'. created $dff cell `$procdff$22256' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\cnt' using process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4490'. created $dff cell `$procdff$22257' with positive edge clock. Creating register for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\addr_r' using process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:73$4316'. created $dff cell `$procdff$22258' with positive edge clock. Creating register for signal `\sysmgr.\rst_cnt' using process `\sysmgr.$proc$/build/gateware/e1-tracer/rtl/sysmgr.v:81$1589'. created $adff cell `$procdff$22259' with positive edge clock and negative level reset. Creating register for signal `\misc.\boot_sel' using process `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:116$1587'. created $adff cell `$procdff$22260' with positive edge clock and positive level reset. Creating register for signal `\misc.\boot_now' using process `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:116$1587'. created $adff cell `$procdff$22261' with positive edge clock and positive level reset. Creating register for signal `\misc.\wb_rdata' using process `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:73$1586'. created $dff cell `$procdff$22262' with positive edge clock. Creating register for signal `\misc.\bus_we_boot' using process `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:66$1582'. created $dff cell `$procdff$22263' with positive edge clock. Creating register for signal `\misc.\wb_ack' using process `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:60$1577'. created $dff cell `$procdff$22264' with positive edge clock. Creating register for signal `\usb_tx_pkt.\pkt_done' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:241$1573'. created $dff cell `$procdff$22265' with positive edge clock. Creating register for signal `\usb_tx_pkt.\pkt_data_ack' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:241$1573'. created $dff cell `$procdff$22266' with positive edge clock. Creating register for signal `\usb_tx_pkt.\ll_start' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:229$1570'. created $dff cell `$procdff$22267' with positive edge clock. Creating register for signal `\usb_tx_pkt.\crc_in_first' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:202$1564'. created $dff cell `$procdff$22268' with positive edge clock. Creating register for signal `\usb_tx_pkt.\len' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:191$1560'. created $dff cell `$procdff$22269' with positive edge clock. Creating register for signal `\usb_tx_pkt.\shift_new_bit' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:182$1554'. created $dff cell `$procdff$22270' with positive edge clock. Creating register for signal `\usb_tx_pkt.\shift_data_crc' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:175$1547'. created $dff cell `$procdff$22271' with positive edge clock. Creating register for signal `\usb_tx_pkt.\shift_last_byte' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:175$1547'. created $dff cell `$procdff$22272' with positive edge clock. Creating register for signal `\usb_tx_pkt.\shift_data' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:170$1545'. created $dff cell `$procdff$22273' with positive edge clock. Creating register for signal `\usb_tx_pkt.\shift_bit' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:152$1538'. created $dff cell `$procdff$22274' with positive edge clock. Creating register for signal `\usb_tx_pkt.\pid_is_handshake' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:136$1526'. created $dff cell `$procdff$22275' with positive edge clock. Creating register for signal `\usb_tx_pkt.\state' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:126$1525'. created $adff cell `$procdff$22276' with positive edge clock and positive level reset. Creating register for signal `\usb_tx_ll.\out_active' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:134$1522'. created $dff cell `$procdff$22277' with positive edge clock. Creating register for signal `\usb_tx_ll.\out_sym' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1520'. created $adff cell `$procdff$22278' with positive edge clock and positive level reset. Creating register for signal `\usb_tx_ll.\ll_ack' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:110$1513'. created $dff cell `$procdff$22279' with positive edge clock. Creating register for signal `\usb_tx_ll.\lvl_prev' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:102$1508'. created $dff cell `$procdff$22280' with positive edge clock. Creating register for signal `\usb_tx_ll.\bs_cnt' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1498'. created $adff cell `$procdff$22281' with positive edge clock and positive level reset. Creating register for signal `\usb_tx_ll.\bs_now' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1498'. created $adff cell `$procdff$22282' with positive edge clock and positive level reset. Creating register for signal `\usb_tx_ll.\br_cnt' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:79$1495'. created $dff cell `$procdff$22283' with positive edge clock. Creating register for signal `\usb_tx_ll.\state' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1492'. created $adff cell `$procdff$22284' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\pkt_pid' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:236$1488'. created $dff cell `$procdff$22285' with positive edge clock. Creating register for signal `\usb_trans.\xfer_length' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:428$1480'. created $dff cell `$procdff$22286' with positive edge clock. Creating register for signal `\usb_trans.\bd_length' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:421$1477'. created $dff cell `$procdff$22287' with positive edge clock. Creating register for signal `\usb_trans.\addr' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:414$1471'. created $dff cell `$procdff$22288' with positive edge clock. Creating register for signal `\usb_trans.\txpkt_start_i' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:403$1470'. created $dff cell `$procdff$22289' with positive edge clock. Creating register for signal `\usb_trans.\txpkt_pid' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:399$1467'. created $dff cell `$procdff$22290' with positive edge clock. Creating register for signal `\usb_trans.\cel_state_i' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:387$1461'. created $adff cell `$procdff$22291' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\epfw_issue_wb' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:380$1459'. created $dff cell `$procdff$22292' with positive edge clock. Creating register for signal `\usb_trans.\ep_type' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1446'. created $dff cell `$procdff$22293' with positive edge clock. Creating register for signal `\usb_trans.\ep_bd_dual' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1446'. created $dff cell `$procdff$22294' with positive edge clock. Creating register for signal `\usb_trans.\ep_bd_ctrl' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1446'. created $dff cell `$procdff$22295' with positive edge clock. Creating register for signal `\usb_trans.\ep_bd_idx_cur' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1446'. created $dff cell `$procdff$22296' with positive edge clock. Creating register for signal `\usb_trans.\ep_bd_idx_nxt' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1446'. created $dff cell `$procdff$22297' with positive edge clock. Creating register for signal `\usb_trans.\ep_data_toggle' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1446'. created $dff cell `$procdff$22298' with positive edge clock. Creating register for signal `\usb_trans.\bd_state' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1446'. created $dff cell `$procdff$22299' with positive edge clock. Creating register for signal `\usb_trans.\epfw_cap_dl' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:345$1443'. created $adff cell `$procdff$22300' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\epfw_state' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1438'. created $adff cell `$procdff$22301' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\trans_is_setup' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1434'. created $dff cell `$procdff$22302' with positive edge clock. Creating register for signal `\usb_trans.\trans_endp' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1434'. created $dff cell `$procdff$22303' with positive edge clock. Creating register for signal `\usb_trans.\trans_dir' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1434'. created $dff cell `$procdff$22304' with positive edge clock. Creating register for signal `\usb_trans.\trans_cel' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1434'. created $dff cell `$procdff$22305' with positive edge clock. Creating register for signal `\usb_trans.\rto_cnt' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1427'. created $adff cell `$procdff$22306' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\evt' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:225$1422'. created $adff cell `$procdff$22307' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\mc_a_reg' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1419'. created $dff cell `$procdff$22308' with positive edge clock. Creating register for signal `\usb_trans.\mc_pc_nxt' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:175$1410'. created $adff cell `$procdff$22309' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\mc_rst_n' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:162$1401'. created $adff cell `$procdff$22310' with positive edge clock and positive level reset. Creating register for signal `\usb_rx_pkt.\pkt_data_stb' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:374$1398'. created $dff cell `$procdff$22311' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pkt_done_ok' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:353$1389'. created $dff cell `$procdff$22312' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pkt_done_err' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:353$1389'. created $dff cell `$procdff$22313' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pkt_start' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:349$1387'. created $dff cell `$procdff$22314' with positive edge clock. Creating register for signal `\usb_rx_pkt.\token_data [10:8]' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:340$1384'. created $dff cell `$procdff$22315' with positive edge clock. Creating register for signal `\usb_rx_pkt.\token_data [7:0]' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:336$1381'. created $dff cell `$procdff$22316' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1364'. created $dff cell `$procdff$22317' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_is_sof' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1364'. created $dff cell `$procdff$22318' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_is_token' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1364'. created $dff cell `$procdff$22319' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_is_data' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1364'. created $dff cell `$procdff$22320' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_is_handshake' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1364'. created $dff cell `$procdff$22321' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_cap_r' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:318$1363'. created $dff cell `$procdff$22322' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_valid' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:304$1342'. created $dff cell `$procdff$22323' with positive edge clock. Creating register for signal `\usb_rx_pkt.\crc5_ok' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1338'. created $dff cell `$procdff$22324' with positive edge clock. Creating register for signal `\usb_rx_pkt.\crc16_ok' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1338'. created $dff cell `$procdff$22325' with positive edge clock. Creating register for signal `\usb_rx_pkt.\crc_cap' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:284$1337'. created $dff cell `$procdff$22326' with positive edge clock. Creating register for signal `\usb_rx_pkt.\crc_in_first' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:244$1335'. created $dff cell `$procdff$22327' with positive edge clock. Creating register for signal `\usb_rx_pkt.\bit_eop_ok' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:230$1332'. created $dff cell `$procdff$22328' with positive edge clock. Creating register for signal `\usb_rx_pkt.\bit_cnt' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:220$1329'. created $dff cell `$procdff$22329' with positive edge clock. Creating register for signal `\usb_rx_pkt.\data' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:215$1328'. created $dff cell `$procdff$22330' with positive edge clock. Creating register for signal `\usb_rx_pkt.\state_prev_idle' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:198$1320'. created $dff cell `$procdff$22331' with positive edge clock. Creating register for signal `\usb_rx_pkt.\state_prev_error' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:198$1320'. created $dff cell `$procdff$22332' with positive edge clock. Creating register for signal `\usb_rx_pkt.\state' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:188$1319'. created $adff cell `$procdff$22333' with positive edge clock and positive level reset. Creating register for signal `\usb_rx_ll.\dec_bs_skip_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:181$1300'. created $dff cell `$procdff$22334' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_rep_state_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1298'. created $dff cell `$procdff$22335' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_sync_state_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:137$1297'. created $dff cell `$procdff$22336' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_eop_state_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:124$1296'. created $dff cell `$procdff$22337' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_valid_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:120$1295'. created $dff cell `$procdff$22338' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_sym_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:111$1288'. created $dff cell `$procdff$22339' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_bit_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:111$1288'. created $dff cell `$procdff$22340' with positive edge clock. Creating register for signal `\usb_rx_ll.\samp_valid_0' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:97$1281'. created $dff cell `$procdff$22341' with positive edge clock. Creating register for signal `\usb_rx_ll.\samp_cnt' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1280'. created $dff cell `$procdff$22342' with positive edge clock. Creating register for signal `\usb_rx_ll.\samp_active' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:67$1270'. created $adff cell `$procdff$22343' with positive edge clock and positive level reset. Creating register for signal `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.\rd_data' using process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5107'. created $dff cell `$procdff$22344' with positive edge clock. Creating register for signal `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5106_ADDR' using process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5107'. created $dff cell `$procdff$22345' with positive edge clock. Creating register for signal `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5106_DATA' using process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5107'. created $dff cell `$procdff$22346' with positive edge clock. Creating register for signal `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5106_EN' using process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5107'. created $dff cell `$procdff$22347' with positive edge clock. Creating register for signal `\usb_ep_status.\s_dout_3' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:80$1266'. created $dff cell `$procdff$22348' with positive edge clock. Creating register for signal `\usb_ep_status.\p_dout_3' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:76$1264'. created $dff cell `$procdff$22349' with positive edge clock. Creating register for signal `\usb_ep_status.\p_read_2' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1261'. created $dff cell `$procdff$22350' with positive edge clock. Creating register for signal `\usb_ep_status.\p_zero_2' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1261'. created $dff cell `$procdff$22351' with positive edge clock. Creating register for signal `\usb_ep_status.\s_read_2' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1261'. created $dff cell `$procdff$22352' with positive edge clock. Creating register for signal `\usb_ep_status.\s_zero_2' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1261'. created $dff cell `$procdff$22353' with positive edge clock. Creating register for signal `\usb_ep_status.\addr_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1253'. created $dff cell `$procdff$22354' with positive edge clock. Creating register for signal `\usb_ep_status.\din_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1253'. created $dff cell `$procdff$22355' with positive edge clock. Creating register for signal `\usb_ep_status.\we_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1253'. created $dff cell `$procdff$22356' with positive edge clock. Creating register for signal `\usb_ep_status.\p_read_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1253'. created $dff cell `$procdff$22357' with positive edge clock. Creating register for signal `\usb_ep_status.\p_zero_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1253'. created $dff cell `$procdff$22358' with positive edge clock. Creating register for signal `\usb_ep_status.\s_read_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1253'. created $dff cell `$procdff$22359' with positive edge clock. Creating register for signal `\usb_ep_status.\s_zero_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1253'. created $dff cell `$procdff$22360' with positive edge clock. Creating register for signal `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.\wb_rdata_reg' using process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:163$5101'. created $dff cell `$procdff$22361' with positive edge clock. Creating register for signal `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.\wb_rdy_reg' using process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:160$5099'. created $dff cell `$procdff$22362' with positive edge clock. Creating register for signal `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.\ram_rdy' using process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:91$5071'. created $dff cell `$procdff$22363' with positive edge clock. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[4].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4201'. created $adff cell `$procdff$22364' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[4].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4199'. created $adff cell `$procdff$22365' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[3].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4190'. created $adff cell `$procdff$22366' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[3].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4188'. created $adff cell `$procdff$22367' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[2].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4179'. created $adff cell `$procdff$22368' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[2].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4177'. created $adff cell `$procdff$22369' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[1].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4168'. created $adff cell `$procdff$22370' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[1].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4166'. created $adff cell `$procdff$22371' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[4].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4155'. created $adff cell `$procdff$22372' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[4].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4153'. created $adff cell `$procdff$22373' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[3].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4144'. created $adff cell `$procdff$22374' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[3].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4142'. created $adff cell `$procdff$22375' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[2].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4133'. created $adff cell `$procdff$22376' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[2].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4131'. created $adff cell `$procdff$22377' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[1].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4122'. created $adff cell `$procdff$22378' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[1].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4120'. created $adff cell `$procdff$22379' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.\wb_rdata' using process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:125$5027'. created $dff cell `$procdff$22380' with positive edge clock. Creating register for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.\wb_ack' using process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:106$5017'. created $dff cell `$procdff$22381' with positive edge clock. Creating register for signal `\xclk_strobe.\out_stb' using process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:40$1098'. created $adff cell `$procdff$22382' with positive edge clock and positive level reset. Creating register for signal `\xclk_strobe.\dst' using process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:34$1097'. created $adff cell `$procdff$22383' with positive edge clock and positive level reset. Creating register for signal `\xclk_strobe.\src' using process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:28$1095'. created $adff cell `$procdff$22384' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.\wb_now' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:149$4098'. created $adff cell `$procdff$22385' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.\rst_req' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4089'. created $adff cell `$procdff$22386' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.\wb_sel' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4089'. created $adff cell `$procdff$22387' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.\wb_req' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4089'. created $adff cell `$procdff$22388' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.\timer' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:109$4085'. created $adff cell `$procdff$22389' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.\armed' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:103$4083'. created $adff cell `$procdff$22390' with positive edge clock and positive level reset. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\timer' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22391' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\trap' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22392' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\pcpi_valid' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22393' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\eoi' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22394' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\trace_valid' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22395' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\trace_data' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22396' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\count_cycle' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22397' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\count_instr' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22398' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\reg_pc' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22399' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\reg_next_pc' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22400' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\reg_op1' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22401' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\reg_op2' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22402' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\reg_out' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22403' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\reg_sh' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22404' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\irq_delay' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22405' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\irq_active' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22406' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\irq_mask' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22407' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\irq_pending' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22408' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_wordsize' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22409' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_do_prefetch' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22410' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_do_rinst' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22411' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_do_rdata' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22412' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_do_wdata' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22413' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\decoder_trigger' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22414' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\decoder_trigger_q' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22415' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\decoder_pseudo_trigger' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22416' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\decoder_pseudo_trigger_q' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22417' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_rs1val' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22418' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_rs2val' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22419' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_rs1val_valid' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22420' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_rs2val_valid' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22421' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cpu_state' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22422' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\irq_state' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22423' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\set_mem_do_rinst' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22424' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\set_mem_do_rdata' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22425' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\set_mem_do_wdata' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22426' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\latched_store' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22427' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\latched_stalu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22428' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\latched_branch' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22429' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\latched_compr' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22430' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\latched_trace' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22431' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\latched_is_lu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22432' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\latched_is_lh' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22433' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\latched_is_lb' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22434' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\latched_rd' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22435' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\current_pc' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22436' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\pcpi_timeout' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22437' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\next_irq_pending' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22438' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\do_waitirq' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22439' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_out_q' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22440' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_out_0_q' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22441' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_wait' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22442' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_wait_2' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. created $dff cell `$procdff$22443' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\clear_prefetched_high_word_q' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1272$3871'. created $dff cell `$procdff$22444' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\pcpi_insn' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22445' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_lui' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22446' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_auipc' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22447' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_jal' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22448' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_jalr' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22449' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_beq' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22450' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_bne' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22451' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_blt' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22452' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_bge' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22453' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_bltu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22454' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_bgeu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22455' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_lb' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22456' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_lh' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22457' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_lw' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22458' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_lbu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22459' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_lhu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22460' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_sb' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22461' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_sh' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22462' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_sw' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22463' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_addi' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22464' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_slti' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22465' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_sltiu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22466' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_xori' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22467' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_ori' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22468' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_andi' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22469' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_slli' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22470' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_srli' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22471' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_srai' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22472' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_add' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22473' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_sub' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22474' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_sll' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22475' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_slt' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22476' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_sltu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22477' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_xor' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22478' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_srl' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22479' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_sra' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22480' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_or' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22481' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_and' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22482' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_rdcycle' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22483' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_rdcycleh' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22484' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_rdinstr' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22485' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_rdinstrh' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22486' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_ecall_ebreak' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22487' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_getq' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22488' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_setq' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22489' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_retirq' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22490' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_maskirq' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22491' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_waitirq' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22492' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_timer' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22493' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\decoded_rd' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22494' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\decoded_rs1' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22495' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\decoded_rs2' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22496' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\decoded_imm' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22497' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\decoded_imm_uj' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22498' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\compressed_instr' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22499' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_lui_auipc_jal' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22500' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_lb_lh_lw_lbu_lhu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22501' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_slli_srli_srai' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22502' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_jalr_addi_slti_sltiu_xori_ori_andi' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22503' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_sb_sh_sw' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22504' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_sll_srl_sra' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22505' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_lui_auipc_jal_jalr_addi_add_sub' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22506' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_slti_blt_slt' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22507' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_sltiu_bltu_sltu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22508' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_beq_bne_blt_bge_bltu_bgeu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22509' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_lbu_lhu_lw' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22510' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_alu_reg_imm' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22511' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_alu_reg_reg' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22512' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_compare' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. created $dff cell `$procdff$22513' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_insn_addr' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3571'. created $dff cell `$procdff$22514' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\q_ascii_instr' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3571'. created $dff cell `$procdff$22515' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\q_insn_imm' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3571'. created $dff cell `$procdff$22516' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\q_insn_opcode' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3571'. created $dff cell `$procdff$22517' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\q_insn_rs1' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3571'. created $dff cell `$procdff$22518' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\q_insn_rs2' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3571'. created $dff cell `$procdff$22519' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\q_insn_rd' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3571'. created $dff cell `$procdff$22520' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_next' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3571'. created $dff cell `$procdff$22521' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_valid_insn' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3571'. created $dff cell `$procdff$22522' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cached_ascii_instr' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3571'. created $dff cell `$procdff$22523' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cached_insn_imm' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3571'. created $dff cell `$procdff$22524' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cached_insn_opcode' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3571'. created $dff cell `$procdff$22525' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cached_insn_rs1' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3571'. created $dff cell `$procdff$22526' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cached_insn_rs2' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3571'. created $dff cell `$procdff$22527' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cached_insn_rd' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3571'. created $dff cell `$procdff$22528' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_addr' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3546'. created $dff cell `$procdff$22529' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_valid' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3546'. created $dff cell `$procdff$22530' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_instr' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3546'. created $dff cell `$procdff$22531' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_wdata' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3546'. created $dff cell `$procdff$22532' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_wstrb' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3546'. created $dff cell `$procdff$22533' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_state' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3546'. created $dff cell `$procdff$22534' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_la_secondword' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3546'. created $dff cell `$procdff$22535' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\prefetched_high_word' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3546'. created $dff cell `$procdff$22536' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_16bit_buffer' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3546'. created $dff cell `$procdff$22537' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\next_insn_opcode' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:414$3508'. created $dff cell `$procdff$22538' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_rdata_q' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:414$3508'. created $dff cell `$procdff$22539' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_la_firstword_reg' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:374$3500'. created $dff cell `$procdff$22540' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\last_mem_valid' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:374$3500'. created $dff cell `$procdff$22541' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\tx_pending [1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5008'. created $dff cell `$procdff$22542' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\tx_data_reg[1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5008'. created $dff cell `$procdff$22543' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\tx_addr_reg[1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5008'. created $dff cell `$procdff$22544' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\tx_pending [0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5007'. created $dff cell `$procdff$22545' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\tx_addr_reg[0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5007'. created $dff cell `$procdff$22546' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\tx_data_reg[0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5007'. created $dff cell `$procdff$22547' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\rx_pending [1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5002'. created $adff cell `$procdff$22548' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\rx_data_reg[1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5001'. created $dff cell `$procdff$22549' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\rx_addr_reg[1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5001'. created $dff cell `$procdff$22550' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\rx_pending [0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$4996'. created $adff cell `$procdff$22551' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\rx_data_reg[0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$4995'. created $dff cell `$procdff$22552' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\rx_addr_reg[0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$4995'. created $dff cell `$procdff$22553' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\wb_addr' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4952'. created $dff cell `$procdff$22554' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$4929' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4952'. created $dff cell `$procdff$22555' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$4930' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4952'. created $dff cell `$procdff$22556' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\wb_addr_lsb' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4952'. created $dff cell `$procdff$22557' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\wb_wdata_byte' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4952'. created $dff cell `$procdff$22558' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\mux.j' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4952'. created $dff cell `$procdff$22559' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$4931' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4952'. created $dff cell `$procdff$22560' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$4932' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4952'. created $dff cell `$procdff$22561' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$4935' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4952'. created $dff cell `$procdff$22562' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$4936' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4952'. created $dff cell `$procdff$22563' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$4937' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4952'. created $dff cell `$procdff$22564' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$4938' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4952'. created $dff cell `$procdff$22565' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\t_chan' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:212$4949'. created $dff cell `$procdff$22566' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\t_busy' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:206$4947'. created $adff cell `$procdff$22567' with positive edge clock and positive level reset. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.\rdata' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3316'. created $dff cell `$procdff$22568' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3312_ADDR' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3316'. created $dff cell `$procdff$22569' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3312_DATA' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3316'. created $dff cell `$procdff$22570' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3312_EN' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3316'. created $dff cell `$procdff$22571' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3313_ADDR' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3316'. created $dff cell `$procdff$22572' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3313_DATA' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3316'. created $dff cell `$procdff$22573' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3313_EN' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3316'. created $dff cell `$procdff$22574' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3314_ADDR' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3316'. created $dff cell `$procdff$22575' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3314_DATA' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3316'. created $dff cell `$procdff$22576' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3314_EN' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3316'. created $dff cell `$procdff$22577' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3315_ADDR' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3316'. created $dff cell `$procdff$22578' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3315_DATA' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3316'. created $dff cell `$procdff$22579' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3315_EN' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3316'. created $dff cell `$procdff$22580' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\uart_div' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:193$3307'. created $dff cell `$procdff$22581' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_rdata' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:185$3305'. created $dff cell `$procdff$22582' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_ack' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:177$3295'. created $dff cell `$procdff$22583' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_rd_data' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3278'. created $dff cell `$procdff$22584' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_rd_ctrl' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3278'. created $dff cell `$procdff$22585' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_wr_data' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3278'. created $dff cell `$procdff$22586' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_wr_div' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3278'. created $dff cell `$procdff$22587' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\urf_overflow' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:154$3273'. created $adff cell `$procdff$22588' with positive edge clock and positive level reset. Creating register for signal `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.\led_ctrl' using process `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.$proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3266'. created $adff cell `$procdff$22589' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\evt_cnt' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:536$3260'. created $adff cell `$procdff$22590' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\sof_pending' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:656$3255'. created $dff cell `$procdff$22591' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\sof_ind' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:653$3253'. created $dff cell `$procdff$22592' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\pad_pu' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:643$3252'. created $dff cell `$procdff$22593' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\rst_pending' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:636$3248'. created $adff cell `$procdff$22594' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\timeout_reset' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:628$3244'. created $dff cell `$procdff$22595' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\timeout_suspend' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:619$3240'. created $dff cell `$procdff$22596' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\eps_bus_ack_wait' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:514$3226'. created $adff cell `$procdff$22597' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\eps_bus_req_ok_dly' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:510$3223'. created $dff cell `$procdff$22598' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\eps_bus_read' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3213'. created $dff cell `$procdff$22599' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\eps_bus_write' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3213'. created $dff cell `$procdff$22600' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\eps_bus_req' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3213'. created $dff cell `$procdff$22601' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\cr_pu_ena' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3211'. created $adff cell `$procdff$22602' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\cr_cel_ena' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3211'. created $adff cell `$procdff$22603' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\cr_addr_chk' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3211'. created $adff cell `$procdff$22604' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\cr_addr' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3211'. created $adff cell `$procdff$22605' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\cel_rel' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3189'. created $dff cell `$procdff$22606' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\csr_bus_req' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3189'. created $dff cell `$procdff$22607' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\cr_bus_we' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3189'. created $dff cell `$procdff$22608' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\ir_bus_we' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3189'. created $dff cell `$procdff$22609' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\evt_rd_ack' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3189'. created $dff cell `$procdff$22610' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\rst_clear' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3189'. created $dff cell `$procdff$22611' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\sof_clear' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3189'. created $dff cell `$procdff$22612' with positive edge clock. Creating register for signal `$paramod\xclk_wb\DW=16\AW=12.\m_cyc_i' using process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:99$3185'. created $adff cell `$procdff$22613' with positive edge clock and positive level reset. Creating register for signal `$paramod\xclk_wb\DW=16\AW=12.\s_cyc_d' using process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:83$3181'. created $dff cell `$procdff$22614' with positive edge clock. Creating register for signal `$paramod\xclk_wb\DW=16\AW=12.\s_ack_d' using process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:83$3181'. created $dff cell `$procdff$22615' with positive edge clock. Creating register for signal `$paramod\xclk_wb\DW=16\AW=12.\s_rdata' using process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:73$3178'. created $dff cell `$procdff$22616' with positive edge clock. Creating register for signal `$paramod\xclk_wb\DW=16\AW=12.\m_rdata_i' using process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:68$3177'. created $dff cell `$procdff$22617' with positive edge clock. Creating register for signal `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0.\ack_i' using process `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v:50$4916'. created $adff cell `$procdff$22618' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\sel' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4895'. created $adff cell `$procdff$22619' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\busy' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4895'. created $adff cell `$procdff$22620' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\m_addr' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4883'. created $adff cell `$procdff$22621' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\m_wdata' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4883'. created $adff cell `$procdff$22622' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\m_we' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4883'. created $adff cell `$procdff$22623' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\m_wmsk' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4883'. created $adff cell `$procdff$22624' with positive edge clock and positive level reset. Creating register for signal `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.\pb_rst_n' using process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:185$3089'. created $adff cell `$procdff$22625' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$2938'. created $adff cell `$procdff$22626' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1274$2931'. created $dff cell `$procdff$22627' with negative edge clock. Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$2927'. created $adff cell `$procdff$22628' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1143$2920'. created $dff cell `$procdff$22629' with negative edge clock. Creating register for signal `\e1_rx_liu.\out_data' using process `\e1_rx_liu.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_liu.v:60$174'. created $dff cell `$procdff$22630' with positive edge clock. Creating register for signal `\e1_rx_liu.\out_valid' using process `\e1_rx_liu.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_liu.v:60$174'. created $dff cell `$procdff$22631' with positive edge clock. Creating register for signal `\e1_rx_liu.\rx_data_r' using process `\e1_rx_liu.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_liu.v:53$173'. created $dff cell `$procdff$22632' with positive edge clock. Creating register for signal `\e1_rx_liu.\rx_clk_r' using process `\e1_rx_liu.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_liu.v:53$173'. created $dff cell `$procdff$22633' with positive edge clock. Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1074$2917'. created $adff cell `$procdff$22634' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1026$2914'. created $dff cell `$procdff$22635' with negative edge clock. Creating register for signal `\e1_rx_deframer.\aligned' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:395$138'. created $dff cell `$procdff$22636' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_data' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:360$132'. created $dff cell `$procdff$22637' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_frame' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:360$132'. created $dff cell `$procdff$22638' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_ts' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:360$132'. created $dff cell `$procdff$22639' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_ts_is0' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:360$132'. created $dff cell `$procdff$22640' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_first' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:360$132'. created $dff cell `$procdff$22641' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_last' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:360$132'. created $dff cell `$procdff$22642' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_valid' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:360$132'. created $dff cell `$procdff$22643' with positive edge clock. Creating register for signal `\e1_rx_deframer.\error' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$124'. created $dff cell `$procdff$22644' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ec_fas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:339$106'. created $dff cell `$procdff$22645' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ec_nfas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:339$106'. created $dff cell `$procdff$22646' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ec_crc' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:339$106'. created $dff cell `$procdff$22647' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ec_mfa' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:339$106'. created $dff cell `$procdff$22648' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ed_crc' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:324$88'. created $dff cell `$procdff$22649' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ep_crc' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:324$88'. created $dff cell `$procdff$22650' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ed_mfa' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:324$88'. created $dff cell `$procdff$22651' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ep_mfa' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:324$88'. created $dff cell `$procdff$22652' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ed_fas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:310$66'. created $dff cell `$procdff$22653' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ep_fas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:310$66'. created $dff cell `$procdff$22654' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ed_nfas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:310$66'. created $dff cell `$procdff$22655' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ep_nfas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:310$66'. created $dff cell `$procdff$22656' with positive edge clock. Creating register for signal `\e1_rx_deframer.\crc_smf' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:301$65'. created $dff cell `$procdff$22657' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts0_msbs' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:269$54'. created $dff cell `$procdff$22658' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts0_msbs_match_mf' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:269$54'. created $dff cell `$procdff$22659' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts0_msbs_match_crc' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:269$54'. created $dff cell `$procdff$22660' with positive edge clock. Creating register for signal `\e1_rx_deframer.\mfa_timeout' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:261$50'. created $dff cell `$procdff$22661' with positive edge clock. Creating register for signal `\e1_rx_deframer.\fas_pos' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:253$46'. created $dff cell `$procdff$22662' with positive edge clock. Creating register for signal `\e1_rx_deframer.\frame' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:226$38'. created $dff cell `$procdff$22663' with positive edge clock. Creating register for signal `\e1_rx_deframer.\frame_smf_first' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:226$38'. created $dff cell `$procdff$22664' with positive edge clock. Creating register for signal `\e1_rx_deframer.\frame_smf_last' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:226$38'. created $dff cell `$procdff$22665' with positive edge clock. Creating register for signal `\e1_rx_deframer.\frame_mf_first' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:226$38'. created $dff cell `$procdff$22666' with positive edge clock. Creating register for signal `\e1_rx_deframer.\frame_mf_last' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:226$38'. created $dff cell `$procdff$22667' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:214$34'. created $dff cell `$procdff$22668' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts_is_ts0' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:214$34'. created $dff cell `$procdff$22669' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts_is_ts31' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:214$34'. created $dff cell `$procdff$22670' with positive edge clock. Creating register for signal `\e1_rx_deframer.\bit' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:202$30'. created $dff cell `$procdff$22671' with positive edge clock. Creating register for signal `\e1_rx_deframer.\bit_first' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:202$30'. created $dff cell `$procdff$22672' with positive edge clock. Creating register for signal `\e1_rx_deframer.\bit_last' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:202$30'. created $dff cell `$procdff$22673' with positive edge clock. Creating register for signal `\e1_rx_deframer.\fsm_state' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:139$21'. created $dff cell `$procdff$22674' with positive edge clock. Creating register for signal `\e1_rx_deframer.\data_match_fas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:130$18'. created $dff cell `$procdff$22675' with positive edge clock. Creating register for signal `\e1_rx_deframer.\data' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:125$17'. created $dff cell `$procdff$22676' with positive edge clock. Creating register for signal `\e1_rx_deframer.\strobe' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:118$16'. created $dff cell `$procdff$22677' with positive edge clock. Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:957$2911'. created $adff cell `$procdff$22678' with negative edge clock and positive level reset. Creating register for signal `\e1_crc4.\state' using process `\e1_crc4.$proc$/build/gateware/cores/no2e1//rtl/e1_crc4.v:38$10'. created $dff cell `$procdff$22679' with positive edge clock. 73.3.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2910'. Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:909$2908'. Removing empty process `SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:909$2908'. Removing empty process `SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2907'. Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:866$2906'. Removing empty process `SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:866$2906'. Removing empty process `SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2905'. Removing empty process `SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:830$2904'. Removing empty process `SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2903'. Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$2900'. Removing empty process `SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$2900'. Removing empty process `SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2899'. Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:697$2893'. Removing empty process `SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:697$2893'. Removing empty process `SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2892'. Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$2889'. Removing empty process `SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$2889'. Removing empty process `SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2888'. Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:566$2882'. Removing empty process `SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:566$2882'. Removing empty process `SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2881'. Removing empty process `SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:497$2879'. Removing empty process `SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2878'. Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:449$2876'. Removing empty process `SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:449$2876'. Removing empty process `SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2875'. Removing empty process `SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:380$2873'. Removing empty process `SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2872'. Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:332$2870'. Removing empty process `SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:332$2870'. Removing empty process `SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2869'. Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:289$2868'. Removing empty process `SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:289$2868'. Removing empty process `SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2867'. Removing empty process `SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:253$2866'. Removing empty process `$paramod\wb_epbuf\AW=9\DW=32.$proc$/build/gateware/common/rtl/wb_epbuf.v:51$4852'. Found and cleaned up 1 empty switch in `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4841'. Removing empty process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4841'. Found and cleaned up 2 empty switches in `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$4834'. Removing empty process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$4834'. Found and cleaned up 1 empty switch in `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4831'. Removing empty process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4831'. Removing empty process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4818'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$4799'. Found and cleaned up 1 empty switch in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:178$4795'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:178$4795'. Found and cleaned up 1 empty switch in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:174$4792'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:174$4792'. Found and cleaned up 1 empty switch in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:157$4782'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:157$4782'. Found and cleaned up 1 empty switch in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:153$4778'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:153$4778'. Found and cleaned up 1 empty switch in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:142$4776'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:142$4776'. Found and cleaned up 4 empty switches in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:98$4760'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:98$4760'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:92$4759'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:86$4755'. Removing empty process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4751'. Removing empty process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4747'. Removing empty process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4743'. Removing empty process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4736'. Found and cleaned up 1 empty switch in `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4731'. Removing empty process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4731'. Found and cleaned up 3 empty switches in `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4727'. Removing empty process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4727'. Found and cleaned up 1 empty switch in `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4723'. Removing empty process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4723'. Found and cleaned up 2 empty switches in `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4715'. Removing empty process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4715'. Found and cleaned up 1 empty switch in `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4713'. Removing empty process `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4713'. Found and cleaned up 1 empty switch in `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4700'. Removing empty process `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4700'. Found and cleaned up 2 empty switches in `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4676'. Removing empty process `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4676'. Removing empty process `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:199$5306'. Removing empty process `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:192$5300'. Removing empty process `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:184$5296'. Removing empty process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:253$5290'. Removing empty process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:246$5286'. Removing empty process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:239$5284'. Found and cleaned up 1 empty switch in `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$5266'. Removing empty process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$5266'. Found and cleaned up 1 empty switch in `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$5265'. Removing empty process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$5265'. Found and cleaned up 1 empty switch in `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$5257'. Removing empty process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$5257'. Removing empty process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:67$5256'. Found and cleaned up 2 empty switches in `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5255'. Removing empty process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5255'. Found and cleaned up 2 empty switches in `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:51$5252'. Removing empty process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:51$5252'. Found and cleaned up 1 empty switch in `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:42$5248'. Removing empty process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:42$5248'. Removing empty process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:35$5244'. Removing empty process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:102$5238'. Found and cleaned up 1 empty switch in `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:95$5237'. Removing empty process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:95$5237'. Found and cleaned up 2 empty switches in `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:88$5234'. Removing empty process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:88$5234'. Found and cleaned up 2 empty switches in `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:77$5230'. Removing empty process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:77$5230'. Removing empty process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:70$5226'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4527'. Removing empty process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4527'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4521'. Removing empty process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4521'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4519'. Removing empty process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4519'. Removing empty process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:83$4510'. Removing empty process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:67$4504'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4503'. Found and cleaned up 1 empty switch in `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4498'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4498'. Found and cleaned up 3 empty switches in `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4494'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4494'. Found and cleaned up 1 empty switch in `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4490'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4490'. Found and cleaned up 2 empty switches in `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4482'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4482'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5218'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5214'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5210'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5206'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5202'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5198'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5194'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5190'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5186'. Removing empty process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4473'. Found and cleaned up 16 empty switches in `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317'. Removing empty process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4317'. Found and cleaned up 1 empty switch in `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:73$4316'. Removing empty process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:73$4316'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5163'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5159'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5155'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5151'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5147'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5143'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5139'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5135'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5131'. Found and cleaned up 1 empty switch in `\sysmgr.$proc$/build/gateware/e1-tracer/rtl/sysmgr.v:81$1589'. Removing empty process `sysmgr.$proc$/build/gateware/e1-tracer/rtl/sysmgr.v:81$1589'. Found and cleaned up 1 empty switch in `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:116$1587'. Removing empty process `misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:116$1587'. Found and cleaned up 2 empty switches in `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:73$1586'. Removing empty process `misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:73$1586'. Found and cleaned up 1 empty switch in `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:66$1582'. Removing empty process `misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:66$1582'. Removing empty process `misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:60$1577'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:241$1573'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:229$1570'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:202$1564'. Found and cleaned up 1 empty switch in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:191$1560'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:191$1560'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:182$1554'. Found and cleaned up 1 empty switch in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:175$1547'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:175$1547'. Found and cleaned up 1 empty switch in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:170$1545'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:170$1545'. Found and cleaned up 1 empty switch in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:159$1541'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:159$1541'. Found and cleaned up 1 empty switch in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:152$1538'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:152$1538'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:136$1526'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:126$1525'. Found and cleaned up 8 empty switches in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:86$1523'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:86$1523'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:134$1522'. Found and cleaned up 2 empty switches in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1520'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1520'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:110$1513'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:102$1508'. Found and cleaned up 1 empty switch in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1498'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1498'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:79$1495'. Found and cleaned up 4 empty switches in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1492'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1492'. Found and cleaned up 2 empty switches in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:236$1488'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:236$1488'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:428$1480'. Found and cleaned up 1 empty switch in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:421$1477'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:421$1477'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:414$1471'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:403$1470'. Found and cleaned up 1 empty switch in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:399$1467'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:399$1467'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:387$1461'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:380$1459'. Found and cleaned up 2 empty switches in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1446'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1446'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:345$1443'. Found and cleaned up 4 empty switches in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1438'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1438'. Found and cleaned up 1 empty switch in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1434'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1434'. Found and cleaned up 1 empty switch in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1427'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1427'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:225$1422'. Found and cleaned up 2 empty switches in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1419'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1419'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:175$1410'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:162$1401'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:374$1398'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:353$1389'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:349$1387'. Found and cleaned up 1 empty switch in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:340$1384'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:340$1384'. Found and cleaned up 1 empty switch in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:336$1381'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:336$1381'. Found and cleaned up 1 empty switch in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1364'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1364'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:318$1363'. Found and cleaned up 1 empty switch in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:304$1342'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:304$1342'. Found and cleaned up 2 empty switches in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1338'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1338'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:284$1337'. Found and cleaned up 2 empty switches in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:244$1335'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:244$1335'. Found and cleaned up 2 empty switches in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:230$1332'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:230$1332'. Found and cleaned up 2 empty switches in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:220$1329'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:220$1329'. Found and cleaned up 1 empty switch in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:215$1328'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:215$1328'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:198$1320'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:188$1319'. Found and cleaned up 18 empty switches in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:117$1303'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:117$1303'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:49$1302'. Found and cleaned up 1 empty switch in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:181$1300'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:181$1300'. Found and cleaned up 3 empty switches in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1298'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1298'. Found and cleaned up 3 empty switches in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:137$1297'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:137$1297'. Found and cleaned up 2 empty switches in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:124$1296'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:124$1296'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:120$1295'. Found and cleaned up 1 empty switch in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:111$1288'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:111$1288'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:97$1281'. Found and cleaned up 2 empty switches in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1280'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1280'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:67$1270'. Found and cleaned up 2 empty switches in `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5107'. Removing empty process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5107'. Found and cleaned up 1 empty switch in `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:80$1266'. Removing empty process `usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:80$1266'. Found and cleaned up 1 empty switch in `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:76$1264'. Removing empty process `usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:76$1264'. Removing empty process `usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1261'. Removing empty process `usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1253'. Found and cleaned up 1 empty switch in `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:163$5101'. Removing empty process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:163$5101'. Removing empty process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:160$5099'. Removing empty process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:147$5074'. Removing empty process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:91$5071'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4210'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4201'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4201'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4199'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4199'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4190'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4190'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4188'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4188'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4179'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4179'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4177'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4177'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4168'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4168'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4166'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4166'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4164'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4155'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4155'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4153'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4153'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4144'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4144'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4142'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4142'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4133'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4133'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4131'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4131'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4122'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4122'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4120'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4120'. Removing empty process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:0$5032'. Found and cleaned up 1 empty switch in `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:125$5027'. Removing empty process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:125$5027'. Removing empty process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:117$5022'. Removing empty process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:106$5017'. Removing empty process `xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:40$1098'. Removing empty process `xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:34$1097'. Removing empty process `xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:28$1095'. Removing empty process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:149$4098'. Found and cleaned up 2 empty switches in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4089'. Removing empty process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4089'. Removing empty process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:109$4085'. Removing empty process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:103$4083'. Found and cleaned up 55 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3905'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$3891'. Found and cleaned up 2 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1288$3877'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1288$3877'. Found and cleaned up 2 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1274$3872'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1274$3872'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1272$3871'. Found and cleaned up 2 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1228$3849'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1228$3849'. Found and cleaned up 8 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1165$3837'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1165$3837'. Found and cleaned up 22 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3577'. Found and cleaned up 3 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3575'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3575'. Found and cleaned up 5 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3571'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3571'. Found and cleaned up 47 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:684$3570'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:684$3570'. Found and cleaned up 16 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3546'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3546'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1218$4070'. Found and cleaned up 19 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:414$3508'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:414$3508'. Found and cleaned up 3 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3505'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3505'. Found and cleaned up 2 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:374$3500'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:374$3500'. Found and cleaned up 1 empty switch in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3426'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3426'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5008'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5007'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5002'. Found and cleaned up 1 empty switch in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5001'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5001'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$4996'. Found and cleaned up 1 empty switch in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$4995'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$4995'. Found and cleaned up 1 empty switch in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$4985'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$4985'. Found and cleaned up 5 empty switches in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4952'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4952'. Found and cleaned up 1 empty switch in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:212$4949'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:212$4949'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:206$4947'. Found and cleaned up 4 empty switches in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$4945'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$4945'. Found and cleaned up 4 empty switches in `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3316'. Removing empty process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3316'. Found and cleaned up 1 empty switch in `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:193$3307'. Removing empty process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:193$3307'. Found and cleaned up 1 empty switch in `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:185$3305'. Removing empty process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:185$3305'. Found and cleaned up 1 empty switch in `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:177$3295'. Removing empty process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:177$3295'. Found and cleaned up 1 empty switch in `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3278'. Removing empty process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3278'. Removing empty process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:154$3273'. Found and cleaned up 1 empty switch in `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.$proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3266'. Removing empty process `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.$proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3266'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:536$3260'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:656$3255'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:653$3253'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:643$3252'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:643$3252'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:636$3248'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:628$3244'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:628$3244'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:619$3240'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:619$3240'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:514$3226'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:510$3223'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3213'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3213'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:697$3264'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3211'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3211'. Found and cleaned up 2 empty switches in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:442$3207'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:442$3207'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3189'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3189'. Removing empty process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:99$3185'. Removing empty process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:83$3181'. Found and cleaned up 1 empty switch in `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:73$3178'. Removing empty process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:73$3178'. Found and cleaned up 1 empty switch in `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:68$3177'. Removing empty process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:68$3177'. Removing empty process `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v:50$4916'. Found and cleaned up 1 empty switch in `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4895'. Removing empty process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4895'. Found and cleaned up 3 empty switches in `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$4886'. Removing empty process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$4886'. Found and cleaned up 1 empty switch in `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4883'. Removing empty process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4883'. Removing empty process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4864'. Removing empty process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3094'. Removing empty process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3092'. Removing empty process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3090'. Removing empty process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:185$3089'. Removing empty process `SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2941'. Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$2938'. Removing empty process `SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$2938'. Removing empty process `SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2937'. Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1274$2931'. Removing empty process `SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1274$2931'. Removing empty process `SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2930'. Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$2927'. Removing empty process `SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$2927'. Removing empty process `SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2926'. Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1143$2920'. Removing empty process `SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1143$2920'. Removing empty process `e1_rx_liu.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_liu.v:60$174'. Removing empty process `e1_rx_liu.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_liu.v:53$173'. Removing empty process `SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2919'. Removing empty process `SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1074$2917'. Removing empty process `SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2916'. Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1026$2914'. Removing empty process `SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1026$2914'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:395$138'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:395$138'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:360$132'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:360$132'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$124'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:339$106'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:339$106'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:324$88'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:324$88'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:310$66'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:310$66'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:301$65'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:301$65'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:269$54'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:269$54'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:261$50'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:261$50'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:253$46'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:253$46'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:226$38'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:226$38'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:214$34'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:214$34'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:202$30'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:202$30'. Found and cleaned up 10 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:146$23'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:146$23'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:139$21'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:139$21'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:130$18'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:130$18'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:125$17'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:125$17'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:118$16'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:118$16'. Removing empty process `SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2913'. Removing empty process `SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:957$2911'. Found and cleaned up 1 empty switch in `\e1_crc4.$proc$/build/gateware/cores/no2e1//rtl/e1_crc4.v:38$10'. Removing empty process `e1_crc4.$proc$/build/gateware/cores/no2e1//rtl/e1_crc4.v:38$10'. Cleaned up 445 empty switches. 73.4. Executing FLATTEN pass (flatten design). Deleting now unused module $paramod\wb_epbuf\AW=9\DW=32. Deleting now unused module $paramod\wb_arbiter\N=2\DW=32\AW=9. Deleting now unused module $paramod\wb_dma\A0W=14\A1W=9\DW=32. Deleting now unused module $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr. Deleting now unused module $paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0. Deleting now unused module soc_iobuf. Deleting now unused module $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100. Deleting now unused module $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101. Deleting now unused module picorv32_ice40_regs. Deleting now unused module $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000. Deleting now unused module $paramod\e1_rx\LIU=1\MFW=7. Deleting now unused module $paramod\e1_wb_rx\LIU=1\MFW=7. Deleting now unused module $paramod\uart_tx\DIV_WIDTH=12. Deleting now unused module $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2. Deleting now unused module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Deleting now unused module $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1. Deleting now unused module $paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf. Deleting now unused module $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32. Deleting now unused module capcnt32_sb_mac16. Deleting now unused module capcnt16_sb_mac16. Deleting now unused module $paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf. Deleting now unused module sysmgr. Deleting now unused module misc. Deleting now unused module usb_tx_pkt. Deleting now unused module usb_tx_ll. Deleting now unused module usb_trans. Deleting now unused module usb_rx_pkt. Deleting now unused module usb_rx_ll. Deleting now unused module $paramod\ram_sdp\AWIDTH=9\DWIDTH=8. Deleting now unused module usb_ep_status. Deleting now unused module $paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4. Deleting now unused module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Deleting now unused module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Deleting now unused module $paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7. Deleting now unused module xclk_strobe. Deleting now unused module $paramod\capcnt\W=32. Deleting now unused module $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0. Deleting now unused module $paramod\capcnt\W=16. Deleting now unused module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Deleting now unused module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32. Deleting now unused module $paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram. Deleting now unused module $paramod\soc_spram\AW=14. Deleting now unused module $paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0. Deleting now unused module $paramod\uart_wb\DIV_WIDTH=12\DW=32. Deleting now unused module $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb. Deleting now unused module $paramod\usb\EPDW=32. Deleting now unused module $paramod\xclk_wb\DW=16\AW=12. Deleting now unused module $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0. Deleting now unused module $paramod\wb_arbiter\N=3\DW=32\AW=14. Deleting now unused module $paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base. Deleting now unused module $paramod\ice40_spi_wb\N_CS=2\WITH_IOB=1\UNIT=1. Deleting now unused module e1_rx_liu. Deleting now unused module e1_rx_deframer. Deleting now unused module e1_crc4. 73.5. Executing TRIBUF pass. 73.6. Executing DEMINOUT pass (demote inout ports to input or output). Demoting inout port top.flash_cs_n to output. Demoting inout port top.liu_cs_n to output. 73.7. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.8. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 990 unused cells and 14157 unused wires. 73.9. Executing CHECK pass (checking for obvious problems). checking module top.. found and reported 0 problems. 73.10. Executing OPT pass (performing simple optimizations). 73.10.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.10.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 469 cells. 73.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port B of cell $flatten\misc_I.\dfu_I.$procmux$11962: \misc_I.dfu_I.wb_req -> 1'1 Replacing known input bits on port B of cell $flatten\sys_mgr_I.$procmux$11397: \sys_mgr_I.rst_cnt -> { 1'1 \sys_mgr_I.rst_cnt [2:0] } Analyzing evaluation results. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12086. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12092. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12095. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12107. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12114. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12117. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12130. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12142. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12145. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12154. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12157. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12165. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12167. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12170. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12231. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12233. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12236. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12318. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12323. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12326. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12365. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12368. dead port 1/3 on $pmux $flatten\soc_I.\cpu_I.$procmux$12379. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12411. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12424. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12437. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12476. dead port 1/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12673. dead port 2/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12673. dead port 3/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12673. dead port 4/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12673. dead port 5/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12673. dead port 6/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12673. dead port 1/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$12679. dead port 2/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$12679. dead port 3/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$12679. dead port 4/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$12679. dead port 5/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$12679. dead port 4/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$12712. dead port 5/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$12712. dead port 6/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$12712. dead port 7/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$12712. dead port 8/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$12712. dead port 10/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$12712. dead port 11/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$12712. dead port 1/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12917. dead port 2/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12917. dead port 3/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12917. dead port 4/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12917. dead port 5/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12917. dead port 6/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12917. dead port 3/4 on $pmux $flatten\soc_I.\cpu_I.$procmux$12981. dead port 4/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13000. dead port 5/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13000. dead port 6/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13000. dead port 7/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13000. dead port 8/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13000. dead port 10/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13000. dead port 11/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13000. dead port 3/4 on $pmux $flatten\soc_I.\cpu_I.$procmux$13182. dead port 4/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13198. dead port 5/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13198. dead port 6/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13198. dead port 7/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13198. dead port 8/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13198. dead port 10/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13198. dead port 11/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13198. dead port 4/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13360. dead port 5/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13360. dead port 6/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13360. dead port 7/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13360. dead port 8/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13360. dead port 10/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13360. dead port 11/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13360. dead port 1/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13411. dead port 2/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13411. dead port 3/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13411. dead port 4/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13411. dead port 5/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13411. dead port 7/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13411. dead port 8/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13411. dead port 1/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$13508. dead port 2/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$13508. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$13513. dead port 1/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$13517. dead port 2/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$13517. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$13522. dead port 1/8 on $pmux $flatten\soc_I.\cpu_I.$procmux$13537. dead port 2/8 on $pmux $flatten\soc_I.\cpu_I.$procmux$13537. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$14668. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$14675. dead port 1/2 on $mux $flatten\misc_I.\dfu_I.\btn_flt_I.$procmux$5405. dead port 1/2 on $mux $flatten\soc_I.\e1_buf_I.$procmux$14846. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10008. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10008. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10008. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10008. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10008. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10025. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10025. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10025. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10025. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10025. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10044. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10044. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10044. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10044. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10065. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10065. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10065. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10065. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10088. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10088. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10088. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10088. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10088. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10113. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10113. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10113. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10113. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10113. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10140. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10140. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10140. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10140. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10140. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10169. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10169. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10169. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10169. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10169. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10200. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10200. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10200. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10200. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10200. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10233. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10233. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10233. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10233. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10233. dead port 1/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10268. dead port 2/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10268. dead port 3/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10268. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10308. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10308. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10308. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10308. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10308. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10318. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10318. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10318. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10318. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10318. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10332. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10332. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10332. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10332. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10332. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10348. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10348. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10348. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10348. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10348. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10368. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10368. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10368. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10368. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10392. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10392. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10392. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10392. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10392. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10420. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10420. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10420. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10420. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10420. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10452. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10452. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10452. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10452. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10452. dead port 1/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10488. dead port 2/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10488. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10495. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10495. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10495. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10495. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10495. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10506. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10506. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10506. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10506. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10506. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10528. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10528. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10528. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10528. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10528. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10562. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10562. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10562. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10562. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10592. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10592. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10592. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10592. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10592. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10604. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10604. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10604. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10604. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10604. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10622. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10622. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10622. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10622. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10630. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10630. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10630. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10630. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10630. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10656. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10656. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10656. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10656. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10656. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10714. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10714. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10714. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10714. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10714. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10727. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10727. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10727. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10727. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10727. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10742. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10742. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10742. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10742. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10742. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10759. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10759. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10759. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10759. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10759. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10778. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10778. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10778. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10778. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10778. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10799. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10799. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10799. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10799. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10799. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10822. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10822. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10822. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10822. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10822. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10847. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10847. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10847. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10847. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10847. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10874. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10874. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10874. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10874. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10874. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10903. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10903. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10903. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10903. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10903. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10934. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10934. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10934. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10934. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10934. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10967. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10967. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10967. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10967. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10967. dead port 1/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11002. dead port 2/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11002. dead port 4/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11002. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11042. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11042. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11042. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11042. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11042. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11052. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11052. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11052. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11052. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11052. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11066. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11066. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11066. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11066. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11066. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11082. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11082. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11082. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11082. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11082. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11102. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11102. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11102. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11102. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11102. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11126. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11126. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11126. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11126. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11126. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11154. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11154. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11154. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11154. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11154. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11186. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11186. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11186. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11186. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11186. dead port 1/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11222. dead port 3/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11222. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11229. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11229. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11229. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11229. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11229. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11240. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11240. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11240. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11240. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11240. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11262. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11262. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11262. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11262. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11262. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11296. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11296. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11296. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11296. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11326. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11326. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11326. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11326. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11326. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11338. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11338. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11338. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11338. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11338. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11356. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11356. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11356. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11356. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11356. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11364. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11364. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11364. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11364. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11364. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11390. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11390. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11390. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11390. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11390. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5576. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5576. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5576. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5576. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5589. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5589. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5589. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5589. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5604. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5604. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5604. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5604. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5621. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5621. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5621. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5621. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5640. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5640. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5640. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5640. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5661. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5661. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5661. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5661. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5684. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5684. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5684. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5684. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5709. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5709. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5709. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5709. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5736. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5736. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5736. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5736. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5765. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5765. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5765. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5765. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5796. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5796. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5796. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5796. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5829. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5829. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5829. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5829. dead port 1/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5864. dead port 2/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5864. dead port 3/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5864. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5904. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5904. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5904. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5904. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5914. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5914. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5914. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5914. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5928. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5928. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5928. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5928. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5944. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5944. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5944. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5944. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5964. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5964. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5964. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5964. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5988. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5988. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5988. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5988. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6016. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6016. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6016. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6016. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6048. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6048. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6048. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6048. dead port 1/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6084. dead port 2/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6084. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6091. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6091. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6091. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6091. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6102. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6102. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6102. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6102. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6124. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6124. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6124. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6124. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6158. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6158. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6158. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6158. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6188. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6188. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6188. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6188. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6200. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6200. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6200. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6200. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6218. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6218. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6218. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6218. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6226. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6226. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6226. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6226. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6252. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6252. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6252. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6252. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6310. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6310. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6310. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6310. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6310. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6323. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6323. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6323. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6323. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6338. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6338. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6338. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6338. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6355. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6355. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6355. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6355. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6374. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6374. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6374. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6374. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6395. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6395. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6395. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6395. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6418. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6418. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6418. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6418. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6443. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6443. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6443. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6443. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6470. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6470. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6470. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6470. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6499. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6499. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6499. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6499. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6530. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6530. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6530. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6530. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6563. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6563. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6563. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6563. dead port 1/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6598. dead port 2/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6598. dead port 3/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6598. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6638. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6638. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6638. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6638. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6638. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6648. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6648. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6648. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6648. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6662. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6662. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6662. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6662. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6678. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6678. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6678. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6678. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6698. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6698. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6698. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6698. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6722. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6722. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6722. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6722. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6750. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6750. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6750. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6750. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6782. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6782. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6782. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6782. dead port 1/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6818. dead port 2/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6818. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6825. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6825. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6825. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6825. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6825. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6836. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6836. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6836. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6836. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6858. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6858. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6858. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6858. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6892. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6892. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6892. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6892. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6922. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6922. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6922. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6922. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6934. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6934. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6934. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6934. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6952. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6952. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6952. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6952. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6960. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6960. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6960. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6960. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6960. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6986. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6986. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6986. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6986. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7044. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7044. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7044. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7044. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7044. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7057. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7057. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7057. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7057. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7072. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7072. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7072. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7072. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7089. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7089. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7089. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7089. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7108. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7108. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7108. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7108. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7129. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7129. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7129. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7129. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7152. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7152. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7152. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7152. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7152. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7177. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7177. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7177. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7177. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7177. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7204. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7204. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7204. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7204. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7233. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7233. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7233. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7233. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7264. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7264. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7264. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7264. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7297. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7297. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7297. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7297. dead port 1/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7332. dead port 2/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7332. dead port 3/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7332. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7372. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7372. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7372. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7372. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7372. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7382. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7382. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7382. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7382. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7396. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7396. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7396. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7396. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7412. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7412. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7412. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7412. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7432. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7432. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7432. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7432. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7456. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7456. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7456. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7456. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7456. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7484. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7484. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7484. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7484. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7516. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7516. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7516. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7516. dead port 1/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7552. dead port 2/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7552. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7559. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7559. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7559. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7559. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7559. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7570. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7570. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7570. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7570. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7592. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7592. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7592. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7592. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7592. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7626. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7626. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7626. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7626. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7656. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7656. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7656. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7656. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7668. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7668. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7668. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7668. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7686. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7686. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7686. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7686. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7694. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7694. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7694. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7694. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7694. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7720. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7720. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7720. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7720. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7778. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7778. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7778. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7778. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7778. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7791. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7791. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7791. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7791. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7791. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7806. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7806. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7806. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7806. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7823. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7823. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7823. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7823. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7842. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7842. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7842. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7842. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7863. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7863. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7863. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7863. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7886. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7886. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7886. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7886. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7886. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7911. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7911. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7911. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7911. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7911. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7938. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7938. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7938. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7938. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7967. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7967. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7967. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7967. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7998. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7998. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7998. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7998. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8031. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8031. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8031. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8031. dead port 1/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8066. dead port 2/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8066. dead port 3/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8066. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8106. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8106. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8106. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8106. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8106. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8116. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8116. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8116. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8116. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8116. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8130. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8130. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8130. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8130. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8146. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8146. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8146. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8146. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8166. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8166. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8166. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8166. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8190. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8190. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8190. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8190. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8190. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8218. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8218. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8218. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8218. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8250. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8250. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8250. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8250. dead port 1/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8286. dead port 2/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8286. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8293. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8293. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8293. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8293. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8293. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8304. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8304. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8304. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8304. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8304. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8326. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8326. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8326. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8326. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8326. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8360. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8360. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8360. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8360. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8390. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8390. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8390. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8390. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8402. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8402. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8402. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8402. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8402. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8420. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8420. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8420. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8420. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8428. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8428. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8428. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8428. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8428. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8454. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8454. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8454. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8454. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8512. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8512. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8512. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8512. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8512. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8525. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8525. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8525. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8525. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8525. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8540. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8540. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8540. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8540. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8557. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8557. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8557. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8557. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8576. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8576. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8576. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8576. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8597. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8597. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8597. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8597. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8620. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8620. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8620. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8620. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8620. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8645. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8645. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8645. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8645. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8645. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8672. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8672. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8672. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8672. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8672. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8701. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8701. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8701. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8701. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8701. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8732. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8732. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8732. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8732. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8765. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8765. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8765. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8765. dead port 1/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8800. dead port 2/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8800. dead port 3/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8800. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8840. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8840. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8840. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8840. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8840. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8850. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8850. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8850. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8850. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8850. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8864. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8864. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8864. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8864. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8880. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8880. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8880. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8880. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8900. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8900. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8900. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8900. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8924. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8924. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8924. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8924. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8924. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8952. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8952. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8952. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8952. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8952. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8984. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8984. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8984. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8984. dead port 1/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9020. dead port 2/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9020. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9027. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9027. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9027. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9027. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9027. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9038. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9038. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9038. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9038. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9038. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9060. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9060. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9060. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9060. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9060. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9094. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9094. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9094. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9094. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9124. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9124. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9124. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9124. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9136. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9136. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9136. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9136. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9136. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9154. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9154. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9154. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9154. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9162. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9162. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9162. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9162. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9162. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9188. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9188. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9188. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9188. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9188. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9246. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9246. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9246. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9246. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9246. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9259. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9259. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9259. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9259. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9259. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9274. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9274. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9274. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9274. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9274. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9291. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9291. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9291. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9291. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9291. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9310. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9310. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9310. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9310. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9331. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9331. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9331. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9331. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9354. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9354. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9354. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9354. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9354. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9379. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9379. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9379. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9379. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9379. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9406. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9406. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9406. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9406. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9406. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9435. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9435. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9435. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9435. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9435. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9466. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9466. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9466. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9466. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9499. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9499. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9499. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9499. dead port 1/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9534. dead port 2/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9534. dead port 3/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9534. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9574. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9574. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9574. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9574. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9574. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9584. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9584. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9584. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9584. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9584. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9598. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9598. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9598. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9598. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9598. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9614. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9614. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9614. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9614. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9614. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9634. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9634. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9634. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9634. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9658. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9658. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9658. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9658. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9658. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9686. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9686. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9686. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9686. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9686. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9718. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9718. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9718. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9718. dead port 1/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9754. dead port 2/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9754. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9761. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9761. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9761. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9761. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9761. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9772. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9772. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9772. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9772. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9772. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9794. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9794. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9794. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9794. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9794. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9828. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9828. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9828. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9828. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9858. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9858. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9858. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9858. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9870. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9870. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9870. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9870. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9870. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9888. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9888. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9888. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9888. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9896. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9896. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9896. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9896. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9896. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9922. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9922. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9922. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9922. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9922. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9980. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9980. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9980. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9980. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9980. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9993. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9993. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9993. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9993. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9993. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10008. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10008. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10008. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10008. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10008. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10025. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10025. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10025. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10025. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10025. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10044. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10044. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10044. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10044. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10065. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10065. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10065. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10065. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10088. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10088. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10088. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10088. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10088. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10113. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10113. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10113. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10113. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10113. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10140. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10140. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10140. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10140. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10140. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10169. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10169. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10169. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10169. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10169. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10200. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10200. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10200. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10200. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10200. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10233. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10233. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10233. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10233. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10233. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10268. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10268. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10268. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10308. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10308. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10308. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10308. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10308. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10318. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10318. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10318. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10318. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10318. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10332. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10332. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10332. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10332. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10332. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10348. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10348. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10348. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10348. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10348. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10368. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10368. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10368. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10368. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10392. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10392. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10392. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10392. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10392. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10420. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10420. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10420. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10420. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10420. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10452. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10452. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10452. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10452. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10452. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10488. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10488. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10495. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10495. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10495. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10495. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10495. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10506. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10506. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10506. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10506. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10506. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10528. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10528. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10528. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10528. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10528. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10562. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10562. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10562. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10562. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10592. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10592. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10592. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10592. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10592. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10604. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10604. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10604. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10604. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10604. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10622. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10622. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10622. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10622. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10630. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10630. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10630. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10630. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10630. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10656. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10656. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10656. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10656. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10656. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10714. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10714. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10714. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10714. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10714. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10727. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10727. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10727. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10727. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10727. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10742. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10742. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10742. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10742. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10742. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10759. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10759. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10759. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10759. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10759. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10778. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10778. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10778. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10778. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10778. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10799. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10799. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10799. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10799. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10799. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10822. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10822. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10822. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10822. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10822. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10847. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10847. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10847. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10847. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10847. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10874. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10874. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10874. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10874. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10874. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10903. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10903. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10903. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10903. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10903. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10934. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10934. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10934. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10934. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10934. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10967. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10967. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10967. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10967. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10967. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11002. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11002. dead port 4/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11002. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11042. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11042. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11042. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11042. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11042. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11052. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11052. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11052. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11052. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11052. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11066. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11066. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11066. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11066. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11066. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11082. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11082. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11082. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11082. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11082. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11102. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11102. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11102. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11102. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11102. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11126. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11126. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11126. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11126. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11126. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11154. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11154. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11154. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11154. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11154. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11186. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11186. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11186. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11186. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11186. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11222. dead port 3/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11222. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11229. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11229. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11229. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11229. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11229. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11240. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11240. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11240. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11240. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11240. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11262. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11262. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11262. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11262. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11262. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11296. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11296. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11296. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11296. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11326. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11326. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11326. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11326. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11326. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11338. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11338. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11338. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11338. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11338. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11356. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11356. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11356. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11356. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11356. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11364. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11364. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11364. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11364. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11364. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11390. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11390. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11390. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11390. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11390. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5576. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5576. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5576. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5576. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5589. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5589. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5589. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5589. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5604. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5604. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5604. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5604. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5621. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5621. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5621. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5621. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5640. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5640. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5640. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5640. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5661. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5661. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5661. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5661. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5684. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5684. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5684. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5684. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5709. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5709. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5709. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5709. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5736. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5736. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5736. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5736. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5765. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5765. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5765. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5765. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5796. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5796. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5796. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5796. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5829. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5829. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5829. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5829. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5864. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5864. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5864. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5904. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5904. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5904. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5904. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5914. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5914. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5914. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5914. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5928. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5928. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5928. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5928. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5944. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5944. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5944. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5944. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5964. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5964. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5964. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5964. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5988. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5988. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5988. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5988. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6016. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6016. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6016. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6016. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6048. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6048. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6048. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6048. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6084. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6084. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6091. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6091. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6091. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6091. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6102. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6102. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6102. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6102. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6124. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6124. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6124. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6124. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6158. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6158. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6158. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6158. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6188. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6188. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6188. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6188. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6200. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6200. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6200. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6200. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6218. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6218. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6218. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6218. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6226. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6226. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6226. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6226. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6252. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6252. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6252. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6252. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6310. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6310. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6310. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6310. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6310. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6323. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6323. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6323. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6323. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6338. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6338. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6338. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6338. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6355. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6355. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6355. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6355. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6374. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6374. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6374. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6374. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6395. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6395. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6395. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6395. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6418. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6418. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6418. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6418. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6443. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6443. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6443. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6443. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6470. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6470. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6470. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6470. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6499. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6499. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6499. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6499. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6530. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6530. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6530. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6530. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6563. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6563. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6563. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6563. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6598. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6598. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6598. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6638. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6638. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6638. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6638. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6638. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6648. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6648. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6648. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6648. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6662. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6662. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6662. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6662. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6678. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6678. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6678. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6678. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6698. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6698. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6698. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6698. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6722. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6722. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6722. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6722. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6750. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6750. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6750. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6750. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6782. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6782. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6782. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6782. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6818. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6818. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6825. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6825. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6825. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6825. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6825. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6836. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6836. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6836. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6836. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6858. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6858. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6858. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6858. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6892. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6892. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6892. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6892. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6922. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6922. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6922. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6922. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6934. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6934. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6934. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6934. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6952. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6952. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6952. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6952. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6960. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6960. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6960. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6960. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6960. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6986. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6986. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6986. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6986. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7044. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7044. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7044. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7044. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7044. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7057. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7057. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7057. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7057. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7072. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7072. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7072. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7072. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7089. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7089. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7089. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7089. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7108. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7108. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7108. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7108. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7129. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7129. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7129. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7129. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7152. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7152. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7152. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7152. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7152. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7177. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7177. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7177. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7177. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7177. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7204. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7204. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7204. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7204. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7233. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7233. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7233. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7233. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7264. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7264. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7264. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7264. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7297. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7297. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7297. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7297. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7332. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7332. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7332. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7372. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7372. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7372. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7372. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7372. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7382. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7382. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7382. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7382. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7396. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7396. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7396. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7396. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7412. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7412. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7412. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7412. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7432. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7432. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7432. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7432. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7456. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7456. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7456. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7456. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7456. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7484. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7484. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7484. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7484. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7516. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7516. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7516. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7516. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7552. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7552. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7559. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7559. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7559. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7559. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7559. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7570. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7570. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7570. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7570. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7592. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7592. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7592. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7592. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7592. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7626. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7626. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7626. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7626. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7656. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7656. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7656. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7656. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7668. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7668. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7668. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7668. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7686. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7686. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7686. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7686. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7694. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7694. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7694. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7694. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7694. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7720. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7720. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7720. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7720. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7778. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7778. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7778. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7778. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7778. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7791. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7791. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7791. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7791. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7791. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7806. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7806. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7806. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7806. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7823. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7823. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7823. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7823. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7842. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7842. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7842. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7842. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7863. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7863. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7863. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7863. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7886. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7886. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7886. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7886. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7886. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7911. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7911. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7911. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7911. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7911. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7938. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7938. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7938. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7938. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7967. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7967. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7967. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7967. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7998. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7998. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7998. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7998. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8031. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8031. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8031. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8031. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8066. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8066. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8066. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8106. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8106. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8106. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8106. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8106. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8116. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8116. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8116. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8116. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8116. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8130. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8130. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8130. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8130. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8146. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8146. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8146. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8146. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8166. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8166. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8166. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8166. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8190. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8190. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8190. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8190. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8190. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8218. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8218. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8218. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8218. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8250. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8250. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8250. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8250. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8286. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8286. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8293. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8293. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8293. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8293. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8293. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8304. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8304. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8304. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8304. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8304. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8326. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8326. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8326. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8326. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8326. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8360. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8360. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8360. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8360. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8390. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8390. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8390. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8390. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8402. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8402. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8402. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8402. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8402. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8420. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8420. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8420. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8420. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8428. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8428. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8428. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8428. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8428. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8454. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8454. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8454. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8454. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8512. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8512. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8512. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8512. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8512. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8525. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8525. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8525. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8525. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8525. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8540. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8540. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8540. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8540. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8557. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8557. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8557. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8557. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8576. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8576. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8576. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8576. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8597. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8597. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8597. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8597. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8620. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8620. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8620. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8620. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8620. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8645. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8645. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8645. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8645. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8645. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8672. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8672. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8672. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8672. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8672. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8701. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8701. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8701. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8701. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8701. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8732. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8732. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8732. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8732. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8765. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8765. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8765. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8765. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8800. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8800. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8800. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8840. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8840. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8840. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8840. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8840. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8850. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8850. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8850. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8850. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8850. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8864. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8864. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8864. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8864. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8880. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8880. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8880. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8880. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8900. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8900. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8900. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8900. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8924. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8924. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8924. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8924. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8924. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8952. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8952. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8952. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8952. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8952. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8984. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8984. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8984. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8984. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9020. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9020. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9027. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9027. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9027. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9027. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9027. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9038. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9038. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9038. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9038. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9038. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9060. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9060. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9060. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9060. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9060. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9094. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9094. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9094. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9094. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9124. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9124. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9124. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9124. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9136. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9136. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9136. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9136. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9136. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9154. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9154. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9154. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9154. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9162. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9162. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9162. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9162. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9162. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9188. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9188. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9188. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9188. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9188. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9246. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9246. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9246. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9246. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9246. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9259. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9259. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9259. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9259. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9259. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9274. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9274. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9274. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9274. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9274. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9291. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9291. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9291. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9291. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9291. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9310. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9310. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9310. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9310. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9331. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9331. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9331. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9331. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9354. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9354. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9354. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9354. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9354. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9379. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9379. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9379. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9379. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9379. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9406. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9406. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9406. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9406. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9406. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9435. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9435. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9435. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9435. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9435. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9466. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9466. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9466. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9466. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9499. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9499. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9499. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9499. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9534. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9534. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9534. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9574. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9574. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9574. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9574. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9574. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9584. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9584. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9584. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9584. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9584. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9598. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9598. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9598. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9598. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9598. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9614. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9614. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9614. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9614. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9614. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9634. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9634. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9634. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9634. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9658. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9658. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9658. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9658. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9658. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9686. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9686. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9686. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9686. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9686. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9718. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9718. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9718. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9718. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9754. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9754. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9761. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9761. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9761. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9761. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9761. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9772. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9772. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9772. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9772. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9772. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9794. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9794. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9794. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9794. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9794. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9828. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9828. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9828. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9828. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9858. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9858. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9858. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9858. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9870. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9870. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9870. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9870. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9870. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9888. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9888. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9888. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9888. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9896. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9896. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9896. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9896. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9896. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9922. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9922. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9922. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9922. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9922. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9980. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9980. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9980. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9980. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9980. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9993. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9993. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9993. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9993. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9993. dead port 1/2 on $mux $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procmux$5518. dead port 2/2 on $mux $flatten\soc_I.\usb_I.$procmux$14931. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11644. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11646. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11648. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11655. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11657. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11663. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11671. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11673. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11680. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11689. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11691. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11699. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11709. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11711. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11720. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11730. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11743. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11746. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11749. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11751. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11753. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11766. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11769. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11771. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11773. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11786. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11788. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11790. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11802. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11804. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11815. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11827. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11840. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11435. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11442. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11450. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11461. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11463. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11465. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11475. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11477. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11486. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11497. Removed 2298 multiplexer ports. 73.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $flatten\soc_I.\e1_buf_I.$reduce_or$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:195$4946: { \soc_I.cpu_I.do_waitirq \soc_I.e1_buf_I.rx_pending } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12120: $auto$opt_reduce.cc:134:opt_mux$22683 Consolidated identical input bits for $mux cell $flatten\soc_I.\bram_I.$procmux$14853: Old ports: A=0, B=255, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3312_EN[31:0]$3319 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3312_EN[31:0]$3319 [0] New connections: $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3312_EN[31:0]$3319 [31:1] = { 24'000000000000000000000000 $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3312_EN[31:0]$3319 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3312_EN[31:0]$3319 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3312_EN[31:0]$3319 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3312_EN[31:0]$3319 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3312_EN[31:0]$3319 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3312_EN[31:0]$3319 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3312_EN[31:0]$3319 [0] } Consolidated identical input bits for $mux cell $flatten\soc_I.\bram_I.$procmux$14859: Old ports: A=0, B=65280, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3313_EN[31:0]$3322 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3313_EN[31:0]$3322 [8] New connections: { $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3313_EN[31:0]$3322 [31:9] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3313_EN[31:0]$3322 [7:0] } = { 16'0000000000000000 $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3313_EN[31:0]$3322 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3313_EN[31:0]$3322 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3313_EN[31:0]$3322 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3313_EN[31:0]$3322 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3313_EN[31:0]$3322 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3313_EN[31:0]$3322 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3313_EN[31:0]$3322 [8] 8'00000000 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12401: { $flatten\soc_I.\cpu_I.$procmux$12115_CMP $auto$opt_reduce.cc:134:opt_mux$22685 } Consolidated identical input bits for $mux cell $flatten\soc_I.\bram_I.$procmux$14865: Old ports: A=0, B=16711680, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3314_EN[31:0]$3325 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3314_EN[31:0]$3325 [16] New connections: { $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3314_EN[31:0]$3325 [31:17] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3314_EN[31:0]$3325 [15:0] } = { 8'00000000 $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3314_EN[31:0]$3325 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3314_EN[31:0]$3325 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3314_EN[31:0]$3325 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3314_EN[31:0]$3325 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3314_EN[31:0]$3325 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3314_EN[31:0]$3325 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3314_EN[31:0]$3325 [16] 16'0000000000000000 } Consolidated identical input bits for $mux cell $flatten\soc_I.\bram_I.$procmux$14871: Old ports: A=0, B=32'11111111000000000000000000000000, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3315_EN[31:0]$3328 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3315_EN[31:0]$3328 [24] New connections: { $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3315_EN[31:0]$3328 [31:25] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3315_EN[31:0]$3328 [23:0] } = { $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3315_EN[31:0]$3328 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3315_EN[31:0]$3328 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3315_EN[31:0]$3328 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3315_EN[31:0]$3328 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3315_EN[31:0]$3328 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3315_EN[31:0]$3328 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3315_EN[31:0]$3328 [24] 24'000000000000000000000000 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12414: { $auto$opt_reduce.cc:134:opt_mux$22687 $flatten\soc_I.\cpu_I.$procmux$12093_CMP } New ctrl vector for $mux cell $flatten\soc_I.\cpu_I.$procmux$12083: { } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12427: { $flatten\soc_I.\cpu_I.$procmux$12124_CMP $auto$opt_reduce.cc:134:opt_mux$22689 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12653: { $flatten\soc_I.\cpu_I.$procmux$12124_CMP $flatten\soc_I.\cpu_I.$procmux$12123_CMP $flatten\soc_I.\cpu_I.$procmux$12093_CMP } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12712: { \soc_I.cpu_I.is_slli_srli_srai $auto$opt_reduce.cc:134:opt_mux$22691 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12754: { $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3878_Y $flatten\soc_I.\cpu_I.$procmux$12124_CMP } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12851: { $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3878_Y $flatten\soc_I.\cpu_I.$procmux$12124_CMP } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12894: { $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3878_Y $flatten\soc_I.\cpu_I.$procmux$12124_CMP $auto$opt_reduce.cc:134:opt_mux$22693 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13000: { \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu \soc_I.cpu_I.is_slli_srli_srai $auto$opt_reduce.cc:134:opt_mux$22695 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13172: { $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3878_Y $flatten\soc_I.\cpu_I.$procmux$12104_CMP $flatten\soc_I.\cpu_I.$procmux$12103_CMP $flatten\soc_I.\cpu_I.$procmux$12123_CMP } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13198: { \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu \soc_I.cpu_I.is_slli_srli_srai $auto$opt_reduce.cc:134:opt_mux$22697 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13360: { $auto$opt_reduce.cc:134:opt_mux$22701 $auto$opt_reduce.cc:134:opt_mux$22699 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13508: $auto$opt_reduce.cc:134:opt_mux$22703 New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12102: { } Consolidated identical input bits for $mux cell $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$procmux$11909: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5106_EN[7:0]$5110 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5106_EN[7:0]$5110 [0] New connections: $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5106_EN[7:0]$5110 [7:1] = { $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5106_EN[7:0]$5110 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5106_EN[7:0]$5110 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5106_EN[7:0]$5110 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5106_EN[7:0]$5110 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5106_EN[7:0]$5110 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5106_EN[7:0]$5110 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5106_EN[7:0]$5110 [0] } Consolidated identical input bits for $mux cell $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$procmux$11909: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5106_EN[7:0]$5110 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5106_EN[7:0]$5110 [0] New connections: $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5106_EN[7:0]$5110 [7:1] = { $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5106_EN[7:0]$5110 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5106_EN[7:0]$5110 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5106_EN[7:0]$5110 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5106_EN[7:0]$5110 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5106_EN[7:0]$5110 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5106_EN[7:0]$5110 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5106_EN[7:0]$5110 [0] } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.$procmux$14927: { $flatten\soc_I.\iobuf_I.\dma_I.$eq$/build/gateware/common/rtl/wb_dma.v:183$4797_Y $flatten\soc_I.\iobuf_I.\dma_I.$eq$/build/gateware/common/rtl/wb_dma.v:164$4788_Y } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.\phy_I.$procmux$5414: { $auto$opt_reduce.cc:134:opt_mux$22711 $auto$opt_reduce.cc:134:opt_mux$22709 $flatten\soc_I.\usb_I.\phy_I.$procmux$5423_CMP $flatten\soc_I.\usb_I.\phy_I.$procmux$5422_CMP $auto$opt_reduce.cc:134:opt_mux$22707 $auto$opt_reduce.cc:134:opt_mux$22705 } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.\phy_I.$procmux$5431: { $auto$opt_reduce.cc:134:opt_mux$22719 $auto$opt_reduce.cc:134:opt_mux$22717 $flatten\soc_I.\usb_I.\phy_I.$procmux$5440_CMP $flatten\soc_I.\usb_I.\phy_I.$procmux$5439_CMP $auto$opt_reduce.cc:134:opt_mux$22715 $auto$opt_reduce.cc:134:opt_mux$22713 } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11854: { $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11862_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11861_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11860_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11859_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11858_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11857_CMP $auto$opt_reduce.cc:134:opt_mux$22721 } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11886: { $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11890_CMP $auto$opt_reduce.cc:134:opt_mux$22723 $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11887_CMP } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11897: { $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11904_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11903_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11902_CMP $auto$opt_reduce.cc:134:opt_mux$22725 $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11900_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11899_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11898_CMP } Optimizing cells in module \top. Performed a total of 29 changes. 73.10.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 13 cells. 73.10.6. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $flatten\soc_I.\cpu_I.$procdff$22439 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\cpu_I.$procdff$22400 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\cpu_I.$procdff$22400 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\cpu_I.$procdff$22399 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\cpu_I.$procdff$22399 ($dff) from module top. Setting constant 1-bit at position 0 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 1 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 2 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 3 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 4 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 5 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 6 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 7 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 8 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 9 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 10 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 11 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 12 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 13 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 14 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 15 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 16 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 17 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 18 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 19 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 20 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 21 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 22 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 23 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 24 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 25 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 26 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 27 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 28 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 29 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 30 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 31 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 32 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 33 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 34 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 35 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 36 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 37 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 38 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 39 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 40 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 41 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 42 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 43 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 44 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 45 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 46 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 47 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 48 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 49 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 50 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 51 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 52 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 53 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 54 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 55 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 56 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 57 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 58 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 59 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 60 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 61 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 62 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 1-bit at position 63 on $flatten\soc_I.\cpu_I.$procdff$22397 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$22358 ($dff) from module top. Setting constant 1-bit at position 0 on $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procdff$22253 ($dff) from module top. Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21917 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21850 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21783 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21716 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21649 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21438 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21227 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21016 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20805 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20594 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20383 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20172 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19961 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19750 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19539 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19328 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19117 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18906 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18695 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18484 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18273 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18062 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17851 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17640 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17429 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17218 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17007 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16796 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16585 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16374 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16163 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$15952 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$15741 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$15530 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$15367 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$15252 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21984 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21917 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21850 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21783 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21716 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21649 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21438 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21227 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21016 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20805 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20594 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20383 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20172 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19961 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19750 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19539 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19328 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19117 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18906 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18695 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18484 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18273 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18062 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17851 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17640 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17429 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17218 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17007 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16796 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16585 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16374 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16163 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$15952 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$15741 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$15530 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$15367 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$15252 ($dlatch) from module top (changing to combinatorial circuit). Setting constant 0-bit at position 0 on $flatten\soc_I.\e1_buf_I.$procdff$22544 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\e1_buf_I.$procdff$22544 ($dff) from module top. Setting constant 0-bit at position 2 on $flatten\soc_I.\e1_buf_I.$procdff$22544 ($dff) from module top. Setting constant 0-bit at position 3 on $flatten\soc_I.\e1_buf_I.$procdff$22544 ($dff) from module top. Setting constant 0-bit at position 4 on $flatten\soc_I.\e1_buf_I.$procdff$22544 ($dff) from module top. Setting constant 0-bit at position 5 on $flatten\soc_I.\e1_buf_I.$procdff$22544 ($dff) from module top. Setting constant 0-bit at position 6 on $flatten\soc_I.\e1_buf_I.$procdff$22544 ($dff) from module top. Setting constant 0-bit at position 7 on $flatten\soc_I.\e1_buf_I.$procdff$22544 ($dff) from module top. Setting constant 0-bit at position 8 on $flatten\soc_I.\e1_buf_I.$procdff$22544 ($dff) from module top. Setting constant 0-bit at position 9 on $flatten\soc_I.\e1_buf_I.$procdff$22544 ($dff) from module top. Setting constant 0-bit at position 10 on $flatten\soc_I.\e1_buf_I.$procdff$22544 ($dff) from module top. Setting constant 0-bit at position 11 on $flatten\soc_I.\e1_buf_I.$procdff$22544 ($dff) from module top. Setting constant 0-bit at position 12 on $flatten\soc_I.\e1_buf_I.$procdff$22544 ($dff) from module top. Setting constant 0-bit at position 13 on $flatten\soc_I.\e1_buf_I.$procdff$22544 ($dff) from module top. Setting constant 0-bit at position 14 on $flatten\soc_I.\e1_buf_I.$procdff$22544 ($dff) from module top. Setting constant 0-bit at position 15 on $flatten\soc_I.\e1_buf_I.$procdff$22544 ($dff) from module top. 73.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 29 unused cells and 634 unused wires. 73.10.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.10.9. Rerunning OPT passes. (Maybe there is more to do..) 73.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 73.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $flatten\soc_I.\e1_buf_I.$reduce_or$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:195$4946: \soc_I.e1_buf_I.rx_pending New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12524: $auto$opt_reduce.cc:134:opt_mux$22727 New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12541: { $flatten\soc_I.\cpu_I.$procmux$12124_CMP $auto$opt_reduce.cc:134:opt_mux$22729 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12959: { $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3878_Y $flatten\soc_I.\cpu_I.$procmux$12104_CMP $flatten\soc_I.\cpu_I.$procmux$12103_CMP $flatten\soc_I.\cpu_I.$procmux$12124_CMP $flatten\soc_I.\cpu_I.$procmux$12123_CMP $auto$opt_reduce.cc:134:opt_mux$22731 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$14422: { $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:364$3475_Y $auto$opt_reduce.cc:134:opt_mux$22733 } Optimizing cells in module \top. Performed a total of 5 changes. 73.10.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 2 cells. 73.10.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$22351 ($dff) from module top. Setting constant 1-bit at position 0 on $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procdff$22253 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 8 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 9 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 10 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 11 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 12 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 13 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 14 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 15 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 16 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 17 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 18 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 19 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 20 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 21 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 22 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 23 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 8 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 9 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 10 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 11 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 12 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 13 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 14 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 15 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 24 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 25 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 26 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 27 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 28 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 29 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 30 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 31 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$22574 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$22574 ($dff) from module top. Setting constant 0-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$22574 ($dff) from module top. Setting constant 0-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$22574 ($dff) from module top. Setting constant 0-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$22574 ($dff) from module top. Setting constant 0-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$22574 ($dff) from module top. Setting constant 0-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$22574 ($dff) from module top. Setting constant 0-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$22574 ($dff) from module top. Setting constant 0-bit at position 16 on $flatten\soc_I.\bram_I.$procdff$22574 ($dff) from module top. Setting constant 0-bit at position 17 on $flatten\soc_I.\bram_I.$procdff$22574 ($dff) from module top. Setting constant 0-bit at position 18 on $flatten\soc_I.\bram_I.$procdff$22574 ($dff) from module top. Setting constant 0-bit at position 19 on $flatten\soc_I.\bram_I.$procdff$22574 ($dff) from module top. Setting constant 0-bit at position 20 on $flatten\soc_I.\bram_I.$procdff$22574 ($dff) from module top. Setting constant 0-bit at position 21 on $flatten\soc_I.\bram_I.$procdff$22574 ($dff) from module top. Setting constant 0-bit at position 22 on $flatten\soc_I.\bram_I.$procdff$22574 ($dff) from module top. Setting constant 0-bit at position 23 on $flatten\soc_I.\bram_I.$procdff$22574 ($dff) from module top. Setting constant 0-bit at position 24 on $flatten\soc_I.\bram_I.$procdff$22574 ($dff) from module top. Setting constant 0-bit at position 25 on $flatten\soc_I.\bram_I.$procdff$22574 ($dff) from module top. Setting constant 0-bit at position 26 on $flatten\soc_I.\bram_I.$procdff$22574 ($dff) from module top. Setting constant 0-bit at position 27 on $flatten\soc_I.\bram_I.$procdff$22574 ($dff) from module top. Setting constant 0-bit at position 28 on $flatten\soc_I.\bram_I.$procdff$22574 ($dff) from module top. Setting constant 0-bit at position 29 on $flatten\soc_I.\bram_I.$procdff$22574 ($dff) from module top. Setting constant 0-bit at position 30 on $flatten\soc_I.\bram_I.$procdff$22574 ($dff) from module top. Setting constant 0-bit at position 31 on $flatten\soc_I.\bram_I.$procdff$22574 ($dff) from module top. Setting constant 0-bit at position 8 on $flatten\soc_I.\bram_I.$procdff$22571 ($dff) from module top. Setting constant 0-bit at position 9 on $flatten\soc_I.\bram_I.$procdff$22571 ($dff) from module top. Setting constant 0-bit at position 10 on $flatten\soc_I.\bram_I.$procdff$22571 ($dff) from module top. Setting constant 0-bit at position 11 on $flatten\soc_I.\bram_I.$procdff$22571 ($dff) from module top. Setting constant 0-bit at position 12 on $flatten\soc_I.\bram_I.$procdff$22571 ($dff) from module top. Setting constant 0-bit at position 13 on $flatten\soc_I.\bram_I.$procdff$22571 ($dff) from module top. Setting constant 0-bit at position 14 on $flatten\soc_I.\bram_I.$procdff$22571 ($dff) from module top. Setting constant 0-bit at position 15 on $flatten\soc_I.\bram_I.$procdff$22571 ($dff) from module top. Setting constant 0-bit at position 16 on $flatten\soc_I.\bram_I.$procdff$22571 ($dff) from module top. Setting constant 0-bit at position 17 on $flatten\soc_I.\bram_I.$procdff$22571 ($dff) from module top. Setting constant 0-bit at position 18 on $flatten\soc_I.\bram_I.$procdff$22571 ($dff) from module top. Setting constant 0-bit at position 19 on $flatten\soc_I.\bram_I.$procdff$22571 ($dff) from module top. Setting constant 0-bit at position 20 on $flatten\soc_I.\bram_I.$procdff$22571 ($dff) from module top. Setting constant 0-bit at position 21 on $flatten\soc_I.\bram_I.$procdff$22571 ($dff) from module top. Setting constant 0-bit at position 22 on $flatten\soc_I.\bram_I.$procdff$22571 ($dff) from module top. Setting constant 0-bit at position 23 on $flatten\soc_I.\bram_I.$procdff$22571 ($dff) from module top. Setting constant 0-bit at position 24 on $flatten\soc_I.\bram_I.$procdff$22571 ($dff) from module top. Setting constant 0-bit at position 25 on $flatten\soc_I.\bram_I.$procdff$22571 ($dff) from module top. Setting constant 0-bit at position 26 on $flatten\soc_I.\bram_I.$procdff$22571 ($dff) from module top. Setting constant 0-bit at position 27 on $flatten\soc_I.\bram_I.$procdff$22571 ($dff) from module top. Setting constant 0-bit at position 28 on $flatten\soc_I.\bram_I.$procdff$22571 ($dff) from module top. Setting constant 0-bit at position 29 on $flatten\soc_I.\bram_I.$procdff$22571 ($dff) from module top. Setting constant 0-bit at position 30 on $flatten\soc_I.\bram_I.$procdff$22571 ($dff) from module top. Setting constant 0-bit at position 31 on $flatten\soc_I.\bram_I.$procdff$22571 ($dff) from module top. 73.10.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 6 unused wires. 73.10.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.10.16. Rerunning OPT passes. (Maybe there is more to do..) 73.10.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 73.10.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 73.10.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.10.20. Executing OPT_DFF pass (perform DFF optimizations). 73.10.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 7 unused wires. 73.10.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.10.23. Rerunning OPT passes. (Maybe there is more to do..) 73.10.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 73.10.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 73.10.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.10.27. Executing OPT_DFF pass (perform DFF optimizations). 73.10.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 73.10.29. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.10.30. Finished OPT passes. (There is nothing left to do.) 73.11. Executing FSM pass (extract and optimize FSM). 73.11.1. Executing FSM_DETECT pass (finding FSMs in design). Found FSM state register top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.fsm_state. Found FSM state register top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.fsm_state. Not marking top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5106_EN as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5106_EN as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register top.soc_I.cpu_I.cpu_state. Not marking top.soc_I.cpu_I.mem_state as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register top.soc_I.cpu_I.mem_wordsize. Not marking top.soc_I.e1_buf_I.t_chan as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.iobuf_I.dma_I.state as FSM state register: Users of register don't seem to benefit from recoding. Circuit seems to be self-resetting. Not marking top.soc_I.iobuf_I.epbam_arb_I.sel as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.iobuf_I.spram_arb_I.sel as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.phy_I.dn_state as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.phy_I.dp_state as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.rx_ll_I.dec_eop_state_1 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.rx_ll_I.dec_rep_state_1 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.rx_ll_I.dec_sync_state_1 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.rx_ll_I.samp_cnt as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register top.soc_I.usb_I.rx_pkt_I.state. Not marking top.soc_I.usb_I.trans_I.epfw_state as FSM state register: Users of register don't seem to benefit from recoding. Circuit seems to be self-resetting. Not marking top.soc_I.usb_I.tx_ll_I.out_sym as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.tx_ll_I.state as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register top.soc_I.usb_I.tx_pkt_I.state. 73.11.2. Executing FSM_EXTRACT pass (extracting FSM from design). Extracting FSM `$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.fsm_state' from module `\top'. found $dff cell for state register: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22674 root of input selection tree: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] found reset state: 3'000 (guessed from mux tree) found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$or$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:140$22_Y found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.crc_I.in_valid found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procmux$15154_CMP found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.align_mframe found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procmux$15168_CMP found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.align_frame found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:163$24_Y found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.mfa_timeout [6] found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:186$29_Y found state code: 3'100 found state code: 3'000 found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf found state code: 3'011 found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.fas_pos found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.data [6] found state code: 3'001 found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.data_match_fas found state code: 3'010 found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procmux$15168_CMP found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procmux$15154_CMP found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:378$134_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:312$68_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:312$67_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.align_mframe found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.align_frame ctrl inputs: { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.data [6] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.data_match_fas $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.fas_pos $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.mfa_timeout [6] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$or$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:140$22_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:163$24_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:186$29_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.crc_I.in_valid } ctrl outputs: { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.align_frame $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.align_mframe $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:312$67_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:312$68_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:378$134_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procmux$15154_CMP $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procmux$15168_CMP } transition: 3'000 9'-----0--0 -> 3'000 10'1000011000 transition: 3'000 9'-0---0--1 -> 3'000 10'1000011000 transition: 3'000 9'-1---0--1 -> 3'001 10'1000111000 transition: 3'000 9'-----1--- -> 3'000 10'1000011000 transition: 3'100 9'-----0--0 -> 3'100 10'0010010100 transition: 3'100 9'-----0--1 -> 3'100 10'0010010100 transition: 3'100 9'-----1--- -> 3'000 10'0000010100 transition: 3'010 9'-----0--0 -> 3'010 10'0101001000 transition: 3'010 9'-----00-1 -> 3'010 10'0101001000 transition: 3'010 9'---0001-1 -> 3'010 10'0101001000 transition: 3'010 9'---0101-1 -> 3'011 10'0101101000 transition: 3'010 9'---1-01-1 -> 3'000 10'0100001000 transition: 3'010 9'-----1--- -> 3'000 10'0100001000 transition: 3'001 9'-----0--0 -> 3'001 10'0000111001 transition: 3'001 9'-----00-1 -> 3'001 10'0000111001 transition: 3'001 9'0-0--01-1 -> 3'000 10'0000011001 transition: 3'001 9'1-0--01-1 -> 3'001 10'0000111001 transition: 3'001 9'-01--01-1 -> 3'000 10'0000011001 transition: 3'001 9'-11--01-1 -> 3'010 10'0001011001 transition: 3'001 9'-----1--- -> 3'000 10'0000011001 transition: 3'011 9'-----0--0 -> 3'011 10'0001111010 transition: 3'011 9'-----00-1 -> 3'011 10'0001111010 transition: 3'011 9'---0-0101 -> 3'011 10'0001111010 transition: 3'011 9'---0-0111 -> 3'100 10'0010011010 transition: 3'011 9'---1-01-1 -> 3'000 10'0000011010 transition: 3'011 9'-----1--- -> 3'000 10'0000011010 Extracting FSM `$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.fsm_state' from module `\top'. found $dff cell for state register: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22674 root of input selection tree: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] found reset state: 3'000 (guessed from mux tree) found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$or$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:140$22_Y found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.crc_I.in_valid found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procmux$15154_CMP found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.align_mframe found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procmux$15168_CMP found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.align_frame found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:163$24_Y found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.mfa_timeout [6] found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:186$29_Y found state code: 3'100 found state code: 3'000 found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf found state code: 3'011 found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.fas_pos found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.data [6] found state code: 3'001 found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.data_match_fas found state code: 3'010 found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procmux$15168_CMP found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procmux$15154_CMP found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:378$134_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:312$68_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:312$67_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.align_mframe found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.align_frame ctrl inputs: { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.data [6] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.data_match_fas $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.fas_pos $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.mfa_timeout [6] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$or$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:140$22_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:163$24_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:186$29_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.crc_I.in_valid } ctrl outputs: { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.align_frame $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.align_mframe $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:312$67_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:312$68_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:378$134_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procmux$15154_CMP $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procmux$15168_CMP } transition: 3'000 9'-----0--0 -> 3'000 10'1000011000 transition: 3'000 9'-0---0--1 -> 3'000 10'1000011000 transition: 3'000 9'-1---0--1 -> 3'001 10'1000111000 transition: 3'000 9'-----1--- -> 3'000 10'1000011000 transition: 3'100 9'-----0--0 -> 3'100 10'0010010100 transition: 3'100 9'-----0--1 -> 3'100 10'0010010100 transition: 3'100 9'-----1--- -> 3'000 10'0000010100 transition: 3'010 9'-----0--0 -> 3'010 10'0101001000 transition: 3'010 9'-----00-1 -> 3'010 10'0101001000 transition: 3'010 9'---0001-1 -> 3'010 10'0101001000 transition: 3'010 9'---0101-1 -> 3'011 10'0101101000 transition: 3'010 9'---1-01-1 -> 3'000 10'0100001000 transition: 3'010 9'-----1--- -> 3'000 10'0100001000 transition: 3'001 9'-----0--0 -> 3'001 10'0000111001 transition: 3'001 9'-----00-1 -> 3'001 10'0000111001 transition: 3'001 9'0-0--01-1 -> 3'000 10'0000011001 transition: 3'001 9'1-0--01-1 -> 3'001 10'0000111001 transition: 3'001 9'-01--01-1 -> 3'000 10'0000011001 transition: 3'001 9'-11--01-1 -> 3'010 10'0001011001 transition: 3'001 9'-----1--- -> 3'000 10'0000011001 transition: 3'011 9'-----0--0 -> 3'011 10'0001111010 transition: 3'011 9'-----00-1 -> 3'011 10'0001111010 transition: 3'011 9'---0-0101 -> 3'011 10'0001111010 transition: 3'011 9'---0-0111 -> 3'100 10'0010011010 transition: 3'011 9'---1-01-1 -> 3'000 10'0000011010 transition: 3'011 9'-----1--- -> 3'000 10'0000011010 Extracting FSM `\soc_I.cpu_I.cpu_state' from module `\top'. found $dff cell for state register: $flatten\soc_I.\cpu_I.$procdff$22422 root of input selection tree: $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] found reset state: 8'10000000 (guessed from mux tree) found ctrl input: $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1917$4066_Y found ctrl input: \soc_I.pb_rst_n found state code: 8'01000000 found ctrl input: $auto$opt_reduce.cc:134:opt_mux$22727 found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12123_CMP found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12124_CMP found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12103_CMP found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12104_CMP found ctrl input: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3878_Y found ctrl input: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4025_Y found ctrl input: $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1851$4029_Y found ctrl input: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1810$4007_Y found ctrl input: \soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu found ctrl input: \soc_I.cpu_I.mem_done found ctrl input: \soc_I.cpu_I.is_sll_srl_sra found ctrl input: \soc_I.cpu_I.is_sb_sh_sw found state code: 8'00001000 found state code: 8'00000100 found state code: 8'00000010 found ctrl input: $auto$opt_reduce.cc:134:opt_mux$22695 found ctrl input: \soc_I.cpu_I.is_slli_srli_srai found ctrl input: \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu found state code: 8'00000001 found ctrl input: \soc_I.cpu_I.decoder_trigger found ctrl input: \soc_I.cpu_I.instr_jal found state code: 8'00100000 found state code: 8'10000000 found ctrl output: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3878_Y found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12093_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12103_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12104_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12115_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12123_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12124_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12128_CMP ctrl inputs: { $auto$opt_reduce.cc:134:opt_mux$22727 $auto$opt_reduce.cc:134:opt_mux$22695 \soc_I.pb_rst_n $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1917$4066_Y $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1851$4029_Y $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4025_Y $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1810$4007_Y \soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu \soc_I.cpu_I.is_sll_srl_sra \soc_I.cpu_I.is_sb_sh_sw \soc_I.cpu_I.is_slli_srli_srai \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu \soc_I.cpu_I.decoder_trigger \soc_I.cpu_I.instr_jal \soc_I.cpu_I.mem_done } ctrl outputs: { $flatten\soc_I.\cpu_I.$procmux$12128_CMP $flatten\soc_I.\cpu_I.$procmux$12124_CMP $flatten\soc_I.\cpu_I.$procmux$12123_CMP $flatten\soc_I.\cpu_I.$procmux$12115_CMP $flatten\soc_I.\cpu_I.$procmux$12104_CMP $flatten\soc_I.\cpu_I.$procmux$12103_CMP $flatten\soc_I.\cpu_I.$procmux$12093_CMP $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3878_Y } transition: 8'10000000 15'--00----------- -> 8'01000000 16'1000000010000000 transition: 8'10000000 15'--10----------- -> 8'10000000 16'1000000100000000 transition: 8'10000000 15'---1----------- -> 8'10000000 16'1000000100000000 transition: 8'01000000 15'--00----------- -> 8'01000000 16'0000000010000001 transition: 8'01000000 15'--10--------0-- -> 8'01000000 16'0000000010000001 transition: 8'01000000 15'--10--------10- -> 8'00100000 16'0000000001000001 transition: 8'01000000 15'--10--------11- -> 8'01000000 16'0000000010000001 transition: 8'01000000 15'---1----------- -> 8'10000000 16'0000000100000001 transition: 8'00100000 15'--00----------- -> 8'01000000 16'0000100010000000 transition: 8'00100000 15'-010----0000--- -> 8'00001000 16'0000100000010000 transition: 8'00100000 15'-010-----100--- -> 8'00000010 16'0000100000000100 transition: 8'00100000 15'-010----1-00--- -> 8'00000100 16'0000100000001000 transition: 8'00100000 15'--10-------1--- -> 8'00000001 16'0000100000000010 transition: 8'00100000 15'--10------1---- -> 8'00000100 16'0000100000001000 transition: 8'00100000 15'-110----------- -> 8'00001000 16'0000100000010000 transition: 8'00100000 15'---1----------- -> 8'10000000 16'0000100100000000 transition: 8'00001000 15'--00----------- -> 8'01000000 16'0100000010000000 transition: 8'00001000 15'--10---0------- -> 8'01000000 16'0100000010000000 transition: 8'00001000 15'--10---1------0 -> 8'00001000 16'0100000000010000 transition: 8'00001000 15'--10---1------1 -> 8'01000000 16'0100000010000000 transition: 8'00001000 15'---1----------- -> 8'10000000 16'0100000100000000 transition: 8'00000100 15'--00----------- -> 8'01000000 16'0010000010000000 transition: 8'00000100 15'--10--0-------- -> 8'00000100 16'0010000000001000 transition: 8'00000100 15'--10--1-------- -> 8'01000000 16'0010000010000000 transition: 8'00000100 15'---1----------- -> 8'10000000 16'0010000100000000 transition: 8'00000010 15'--00----------- -> 8'01000000 16'0001000010000000 transition: 8'00000010 15'--10-0--------- -> 8'00000010 16'0001000000000100 transition: 8'00000010 15'--1001--------- -> 8'00000010 16'0001000000000100 transition: 8'00000010 15'--1011--------- -> 8'01000000 16'0001000010000000 transition: 8'00000010 15'---1----------- -> 8'10000000 16'0001000100000000 transition: 8'00000001 15'--00----------- -> 8'01000000 16'0000001010000000 transition: 8'00000001 15'--10-0--------- -> 8'00000001 16'0000001000000010 transition: 8'00000001 15'--1001--------- -> 8'00000001 16'0000001000000010 transition: 8'00000001 15'--1011--------- -> 8'01000000 16'0000001010000000 transition: 8'00000001 15'---1----------- -> 8'10000000 16'0000001100000000 Extracting FSM `\soc_I.cpu_I.mem_wordsize' from module `\top'. found $dff cell for state register: $flatten\soc_I.\cpu_I.$procdff$22409 root of input selection tree: $flatten\soc_I.\cpu_I.$0\mem_wordsize[1:0] found ctrl input: \soc_I.pb_rst_n found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12093_CMP found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12115_CMP found ctrl input: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3878_Y found ctrl input: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4025_Y found ctrl input: \soc_I.cpu_I.mem_do_rdata found ctrl input: \soc_I.cpu_I.instr_lw found ctrl input: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1866$4034_Y found ctrl input: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1865$4033_Y found state code: 2'00 found state code: 2'01 found state code: 2'10 found ctrl input: \soc_I.cpu_I.mem_do_wdata found ctrl input: \soc_I.cpu_I.instr_sw found ctrl input: \soc_I.cpu_I.instr_sh found ctrl input: \soc_I.cpu_I.instr_sb found ctrl output: $flatten\soc_I.\cpu_I.$procmux$14669_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$14676_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$14681_CMP ctrl inputs: { \soc_I.pb_rst_n $flatten\soc_I.\cpu_I.$procmux$12115_CMP $flatten\soc_I.\cpu_I.$procmux$12093_CMP $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1866$4034_Y $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1865$4033_Y $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4025_Y $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3878_Y \soc_I.cpu_I.instr_sw \soc_I.cpu_I.instr_sh \soc_I.cpu_I.instr_sb \soc_I.cpu_I.instr_lw \soc_I.cpu_I.mem_do_wdata \soc_I.cpu_I.mem_do_rdata } ctrl outputs: { $flatten\soc_I.\cpu_I.$procmux$14681_CMP $flatten\soc_I.\cpu_I.$procmux$14676_CMP $flatten\soc_I.\cpu_I.$procmux$14669_CMP $flatten\soc_I.\cpu_I.$0\mem_wordsize[1:0] } transition: 2'00 13'0------------ -> 2'00 5'10000 transition: 2'00 13'100---0------ -> 2'00 5'10000 transition: 2'00 13'1-----1------ -> 2'00 5'10000 transition: 2'00 13'11---0------- -> 2'00 5'10000 transition: 2'00 13'11---1-000-0- -> INVALID_STATE(2'xx) 5'100xx transition: 2'00 13'11---1---1-0- -> 2'10 5'10010 transition: 2'00 13'11---1--1--0- -> 2'01 5'10001 transition: 2'00 13'11---1-1---0- -> 2'00 5'10000 transition: 2'00 13'11---1-----1- -> 2'00 5'10000 transition: 2'00 13'1-1--0------- -> 2'00 5'10000 transition: 2'00 13'1-1001----0-0 -> INVALID_STATE(2'xx) 5'100xx transition: 2'00 13'1-1-11------0 -> 2'10 5'10010 transition: 2'00 13'1-11-1------0 -> 2'01 5'10001 transition: 2'00 13'1-1--1----1-0 -> 2'00 5'10000 transition: 2'00 13'1-1--1------1 -> 2'00 5'10000 transition: 2'10 13'0------------ -> 2'10 5'00110 transition: 2'10 13'100---0------ -> 2'10 5'00110 transition: 2'10 13'1-----1------ -> 2'00 5'00100 transition: 2'10 13'11---0------- -> 2'10 5'00110 transition: 2'10 13'11---1-000-0- -> INVALID_STATE(2'xx) 5'001xx transition: 2'10 13'11---1---1-0- -> 2'10 5'00110 transition: 2'10 13'11---1--1--0- -> 2'01 5'00101 transition: 2'10 13'11---1-1---0- -> 2'00 5'00100 transition: 2'10 13'11---1-----1- -> 2'10 5'00110 transition: 2'10 13'1-1--0------- -> 2'10 5'00110 transition: 2'10 13'1-1001----0-0 -> INVALID_STATE(2'xx) 5'001xx transition: 2'10 13'1-1-11------0 -> 2'10 5'00110 transition: 2'10 13'1-11-1------0 -> 2'01 5'00101 transition: 2'10 13'1-1--1----1-0 -> 2'00 5'00100 transition: 2'10 13'1-1--1------1 -> 2'10 5'00110 transition: 2'01 13'0------------ -> 2'01 5'01001 transition: 2'01 13'100---0------ -> 2'01 5'01001 transition: 2'01 13'1-----1------ -> 2'00 5'01000 transition: 2'01 13'11---0------- -> 2'01 5'01001 transition: 2'01 13'11---1-000-0- -> INVALID_STATE(2'xx) 5'010xx transition: 2'01 13'11---1---1-0- -> 2'10 5'01010 transition: 2'01 13'11---1--1--0- -> 2'01 5'01001 transition: 2'01 13'11---1-1---0- -> 2'00 5'01000 transition: 2'01 13'11---1-----1- -> 2'01 5'01001 transition: 2'01 13'1-1--0------- -> 2'01 5'01001 transition: 2'01 13'1-1001----0-0 -> INVALID_STATE(2'xx) 5'010xx transition: 2'01 13'1-1-11------0 -> 2'10 5'01010 transition: 2'01 13'1-11-1------0 -> 2'01 5'01001 transition: 2'01 13'1-1--1----1-0 -> 2'00 5'01000 transition: 2'01 13'1-1--1------1 -> 2'01 5'01001 Extracting FSM `\soc_I.usb_I.rx_pkt_I.state' from module `\top'. found $adff cell for state register: $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22333 root of input selection tree: \soc_I.usb_I.rx_pkt_I.state_nxt found reset state: 4'0000 (from async reset) found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:375$1399_Y found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11674_CMP found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:341$1385_Y found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:337$1382_Y found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_error[0:0] found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11754_CMP found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:245$1336_Y found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_idle[0:0] found ctrl input: \soc_I.usb_I.rx_ll_I.dec_valid_1 found ctrl input: \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [2] found ctrl input: \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [3] found state code: 4'0011 found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:180$1317_Y found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:158$1311_Y found ctrl input: \soc_I.usb_I.rx_pkt_I.llu_byte_stb found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:173$1315_Y found state code: 4'0110 found state code: 4'0101 found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:153$1310_Y found ctrl input: \soc_I.usb_I.rx_pkt_I.pid_valid found ctrl input: \soc_I.usb_I.rx_pkt_I.pid_is_sof found ctrl input: \soc_I.usb_I.rx_pkt_I.pid_is_token found ctrl input: \soc_I.usb_I.rx_pkt_I.pid_is_data found ctrl input: \soc_I.usb_I.rx_pkt_I.pid_is_handshake found state code: 4'0111 found state code: 4'0100 found state code: 4'0010 found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:126$1306_Y found state code: 4'0001 found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11754_CMP found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11674_CMP found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:375$1399_Y found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:341$1385_Y found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:337$1382_Y found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:245$1336_Y found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_error[0:0] found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_idle[0:0] ctrl inputs: { \soc_I.usb_I.rx_pkt_I.llu_byte_stb \soc_I.usb_I.rx_pkt_I.pid_valid \soc_I.usb_I.rx_pkt_I.pid_is_sof \soc_I.usb_I.rx_pkt_I.pid_is_token \soc_I.usb_I.rx_pkt_I.pid_is_data \soc_I.usb_I.rx_pkt_I.pid_is_handshake $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:126$1306_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:153$1310_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:158$1311_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:173$1315_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:180$1317_Y \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [2] \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [3] \soc_I.usb_I.rx_ll_I.dec_valid_1 } ctrl outputs: { \soc_I.usb_I.rx_pkt_I.state_nxt $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_idle[0:0] $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_error[0:0] $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:245$1336_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:337$1382_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:341$1385_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:375$1399_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11674_CMP $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11754_CMP } transition: 4'0000 14'------0------- -> 4'0000 12'000010000000 transition: 4'0000 14'------1------- -> 4'0001 12'000110000000 transition: 4'0100 14'0-------0----- -> 4'0100 12'010000010000 transition: 4'0100 14'1-------0----- -> 4'0101 12'010100010000 transition: 4'0100 14'--------1----- -> 4'0011 12'001100010000 transition: 4'0010 14'-0------------ -> 4'0011 12'001100000001 transition: 4'0010 14'-10000-------- -> 4'0011 12'001100000001 transition: 4'0010 14'-10001-------- -> 4'0110 12'011000000001 transition: 4'0010 14'-1001--------- -> 4'0111 12'011100000001 transition: 4'0010 14'-101---------- -> 4'0100 12'010000000001 transition: 4'0010 14'-11----------- -> 4'0100 12'010000000001 transition: 4'0110 14'0-------0----- -> 4'0110 12'011000000010 transition: 4'0110 14'1-------0----- -> 4'0011 12'001100000010 transition: 4'0110 14'--------10---- -> 4'0011 12'001100000010 transition: 4'0110 14'--------11---- -> 4'0000 12'000000000010 transition: 4'0001 14'0------------- -> 4'0001 12'000100100000 transition: 4'0001 14'1------------- -> 4'0010 12'001000100000 transition: 4'0101 14'0-------0----- -> 4'0101 12'010100001000 transition: 4'0101 14'1-------0----- -> 4'0110 12'011000001000 transition: 4'0101 14'--------1----- -> 4'0011 12'001100001000 transition: 4'0011 14'-------0------ -> 4'0011 12'001101000000 transition: 4'0011 14'-------1------ -> 4'0000 12'000001000000 transition: 4'0111 14'-------------0 -> 4'0111 12'011100000100 transition: 4'0111 14'-----------001 -> 4'0111 12'011100000100 transition: 4'0111 14'-----------011 -> 4'0011 12'001100000100 transition: 4'0111 14'----------01-1 -> 4'0011 12'001100000100 transition: 4'0111 14'----------11-1 -> 4'0000 12'000000000100 Extracting FSM `\soc_I.usb_I.tx_pkt_I.state' from module `\top'. found $adff cell for state register: $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$22276 root of input selection tree: \soc_I.usb_I.tx_pkt_I.state_nxt found reset state: 4'0000 (from async reset) found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1550_Y found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11425_CMP found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:177$1549_Y found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1551_Y found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$0\ll_start[0:0] found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:203$1567_Y found ctrl input: \soc_I.usb_I.tx_pkt_I.next found state code: 4'0101 found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:112$1524_Y found state code: 4'0100 found ctrl input: \soc_I.usb_I.tx_pkt_I.pid_is_handshake found ctrl input: \soc_I.usb_I.tx_pkt_I.len [10] found state code: 4'0011 found state code: 4'0010 found ctrl input: \soc_I.usb_I.trans_I.txpkt_start_i found state code: 4'0001 found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11425_CMP found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:203$1567_Y found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1551_Y found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1550_Y found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:177$1549_Y found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$0\ll_start[0:0] ctrl inputs: { \soc_I.usb_I.trans_I.txpkt_start_i \soc_I.usb_I.tx_pkt_I.pid_is_handshake \soc_I.usb_I.tx_pkt_I.next \soc_I.usb_I.tx_pkt_I.len [10] $flatten\soc_I.\usb_I.\tx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:112$1524_Y } ctrl outputs: { \soc_I.usb_I.tx_pkt_I.state_nxt $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:177$1549_Y $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1550_Y $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1551_Y $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:203$1567_Y $flatten\soc_I.\usb_I.\tx_pkt_I.$0\ll_start[0:0] $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11425_CMP } transition: 4'0000 5'0---- -> 4'0000 10'0000000100 transition: 4'0000 5'1---- -> 4'0001 10'0001000100 transition: 4'0100 5'--0-- -> 4'0100 10'0100000001 transition: 4'0100 5'--1-- -> 4'0101 10'0101000001 transition: 4'0010 5'--0-- -> 4'0010 10'0010001000 transition: 4'0010 5'-010- -> 4'0011 10'0011001000 transition: 4'0010 5'-011- -> 4'0100 10'0100001000 transition: 4'0010 5'-11-- -> 4'0000 10'0000001000 transition: 4'0001 5'----- -> 4'0010 10'0010000010 transition: 4'0101 5'--0-- -> 4'0101 10'0101010000 transition: 4'0101 5'--1-- -> 4'0000 10'0000010000 transition: 4'0011 5'----0 -> 4'0011 10'0011100000 transition: 4'0011 5'----1 -> 4'0100 10'0100100000 73.11.3. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\soc_I.usb_I.tx_pkt_I.state$22777' from module `\top'. Optimizing FSM `$fsm$\soc_I.usb_I.rx_pkt_I.state$22767' from module `\top'. Optimizing FSM `$fsm$\soc_I.cpu_I.mem_wordsize$22762' from module `\top'. Optimizing FSM `$fsm$\soc_I.cpu_I.cpu_state$22752' from module `\top'. Removing unused input signal $auto$opt_reduce.cc:134:opt_mux$22727. Optimizing FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.fsm_state$22743' from module `\top'. Merging pattern 9'-----0--0 and 9'-----0--1 from group (1 1 10'0010010100). Merging pattern 9'-----0--1 and 9'-----0--0 from group (1 1 10'0010010100). Optimizing FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.fsm_state$22734' from module `\top'. Merging pattern 9'-----0--0 and 9'-----0--1 from group (1 1 10'0010010100). Merging pattern 9'-----0--1 and 9'-----0--0 from group (1 1 10'0010010100). 73.11.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 121 unused cells and 121 unused wires. 73.11.5. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.fsm_state$22734' from module `\top'. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procmux$15168_CMP. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procmux$15154_CMP. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] [0]. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] [1]. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] [2]. Optimizing FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.fsm_state$22743' from module `\top'. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procmux$15168_CMP. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procmux$15154_CMP. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] [0]. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] [1]. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] [2]. Optimizing FSM `$fsm$\soc_I.cpu_I.cpu_state$22752' from module `\top'. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [0]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [1]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [2]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [3]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [4]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [5]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [6]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [7]. Optimizing FSM `$fsm$\soc_I.cpu_I.mem_wordsize$22762' from module `\top'. Removing unused output signal $flatten\soc_I.\cpu_I.$0\mem_wordsize[1:0] [0]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\mem_wordsize[1:0] [1]. Optimizing FSM `$fsm$\soc_I.usb_I.rx_pkt_I.state$22767' from module `\top'. Removing unused output signal $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11754_CMP. Removing unused output signal $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11674_CMP. Removing unused output signal \soc_I.usb_I.rx_pkt_I.state_nxt [0]. Removing unused output signal \soc_I.usb_I.rx_pkt_I.state_nxt [1]. Removing unused output signal \soc_I.usb_I.rx_pkt_I.state_nxt [2]. Removing unused output signal \soc_I.usb_I.rx_pkt_I.state_nxt [3]. Optimizing FSM `$fsm$\soc_I.usb_I.tx_pkt_I.state$22777' from module `\top'. Removing unused output signal \soc_I.usb_I.tx_pkt_I.state_nxt [0]. Removing unused output signal \soc_I.usb_I.tx_pkt_I.state_nxt [1]. Removing unused output signal \soc_I.usb_I.tx_pkt_I.state_nxt [2]. Removing unused output signal \soc_I.usb_I.tx_pkt_I.state_nxt [3]. 73.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). Recoding FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.fsm_state$22734' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 000 -> ----1 100 -> ---1- 010 -> --1-- 001 -> -1--- 011 -> 1---- Recoding FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.fsm_state$22743' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 000 -> ----1 100 -> ---1- 010 -> --1-- 001 -> -1--- 011 -> 1---- Recoding FSM `$fsm$\soc_I.cpu_I.cpu_state$22752' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 10000000 -> ------1 01000000 -> -----1- 00100000 -> ----1-- 00001000 -> ---1--- 00000100 -> --1---- 00000010 -> -1----- 00000001 -> 1------ Recoding FSM `$fsm$\soc_I.cpu_I.mem_wordsize$22762' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 00 -> --1 10 -> -1- 01 -> 1-- Recoding FSM `$fsm$\soc_I.usb_I.rx_pkt_I.state$22767' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 0000 -> -------1 0100 -> ------1- 0010 -> -----1-- 0110 -> ----1--- 0001 -> ---1---- 0101 -> --1----- 0011 -> -1------ 0111 -> 1------- Recoding FSM `$fsm$\soc_I.usb_I.tx_pkt_I.state$22777' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 0000 -> -----1 0100 -> ----1- 0010 -> ---1-- 0001 -> --1--- 0101 -> -1---- 0011 -> 1----- 73.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells). FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.fsm_state$22734' from module `top': ------------------------------------- Information on FSM $fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.fsm_state$22734 ($flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.fsm_state): Number of input signals: 9 Number of output signals: 5 Number of state bits: 5 Input signals: 0: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.crc_I.in_valid 1: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:186$29_Y 2: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:163$24_Y 3: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$or$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:140$22_Y 4: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf 5: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.mfa_timeout [6] 6: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.fas_pos 7: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.data_match_fas 8: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.data [6] Output signals: 0: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:378$134_Y 1: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:312$68_Y 2: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:312$67_Y 3: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.align_mframe 4: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.align_frame State encoding: 0: 5'----1 1: 5'---1- 2: 5'--1-- 3: 5'-1--- 4: 5'1---- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 9'-----0--0 -> 0 5'10110 1: 0 9'-0---0--1 -> 0 5'10110 2: 0 9'-----1--- -> 0 5'10110 3: 0 9'-1---0--1 -> 3 5'10110 4: 1 9'-----1--- -> 0 5'00101 5: 1 9'-----0--- -> 1 5'00101 6: 2 9'---1-01-1 -> 0 5'01010 7: 2 9'-----1--- -> 0 5'01010 8: 2 9'-----0--0 -> 2 5'01010 9: 2 9'-----00-1 -> 2 5'01010 10: 2 9'---0001-1 -> 2 5'01010 11: 2 9'---0101-1 -> 4 5'01010 12: 3 9'0-0--01-1 -> 0 5'00110 13: 3 9'-01--01-1 -> 0 5'00110 14: 3 9'-----1--- -> 0 5'00110 15: 3 9'-11--01-1 -> 2 5'00110 16: 3 9'-----0--0 -> 3 5'00110 17: 3 9'-----00-1 -> 3 5'00110 18: 3 9'1-0--01-1 -> 3 5'00110 19: 4 9'---1-01-1 -> 0 5'00110 20: 4 9'-----1--- -> 0 5'00110 21: 4 9'---0-0111 -> 1 5'00110 22: 4 9'-----0--0 -> 4 5'00110 23: 4 9'---0-0101 -> 4 5'00110 24: 4 9'-----00-1 -> 4 5'00110 ------------------------------------- FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.fsm_state$22743' from module `top': ------------------------------------- Information on FSM $fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.fsm_state$22743 ($flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.fsm_state): Number of input signals: 9 Number of output signals: 5 Number of state bits: 5 Input signals: 0: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.crc_I.in_valid 1: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:186$29_Y 2: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:163$24_Y 3: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$or$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:140$22_Y 4: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf 5: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.mfa_timeout [6] 6: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.fas_pos 7: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.data_match_fas 8: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.data [6] Output signals: 0: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:378$134_Y 1: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:312$68_Y 2: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:312$67_Y 3: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.align_mframe 4: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.align_frame State encoding: 0: 5'----1 1: 5'---1- 2: 5'--1-- 3: 5'-1--- 4: 5'1---- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 9'-----0--0 -> 0 5'10110 1: 0 9'-0---0--1 -> 0 5'10110 2: 0 9'-----1--- -> 0 5'10110 3: 0 9'-1---0--1 -> 3 5'10110 4: 1 9'-----1--- -> 0 5'00101 5: 1 9'-----0--- -> 1 5'00101 6: 2 9'---1-01-1 -> 0 5'01010 7: 2 9'-----1--- -> 0 5'01010 8: 2 9'-----0--0 -> 2 5'01010 9: 2 9'-----00-1 -> 2 5'01010 10: 2 9'---0001-1 -> 2 5'01010 11: 2 9'---0101-1 -> 4 5'01010 12: 3 9'0-0--01-1 -> 0 5'00110 13: 3 9'-01--01-1 -> 0 5'00110 14: 3 9'-----1--- -> 0 5'00110 15: 3 9'-11--01-1 -> 2 5'00110 16: 3 9'-----0--0 -> 3 5'00110 17: 3 9'-----00-1 -> 3 5'00110 18: 3 9'1-0--01-1 -> 3 5'00110 19: 4 9'---1-01-1 -> 0 5'00110 20: 4 9'-----1--- -> 0 5'00110 21: 4 9'---0-0111 -> 1 5'00110 22: 4 9'-----0--0 -> 4 5'00110 23: 4 9'---0-0101 -> 4 5'00110 24: 4 9'-----00-1 -> 4 5'00110 ------------------------------------- FSM `$fsm$\soc_I.cpu_I.cpu_state$22752' from module `top': ------------------------------------- Information on FSM $fsm$\soc_I.cpu_I.cpu_state$22752 (\soc_I.cpu_I.cpu_state): Number of input signals: 14 Number of output signals: 8 Number of state bits: 7 Input signals: 0: \soc_I.cpu_I.mem_done 1: \soc_I.cpu_I.instr_jal 2: \soc_I.cpu_I.decoder_trigger 3: \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu 4: \soc_I.cpu_I.is_slli_srli_srai 5: \soc_I.cpu_I.is_sb_sh_sw 6: \soc_I.cpu_I.is_sll_srl_sra 7: \soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu 8: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1810$4007_Y 9: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4025_Y 10: $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1851$4029_Y 11: $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1917$4066_Y 12: \soc_I.pb_rst_n 13: $auto$opt_reduce.cc:134:opt_mux$22695 Output signals: 0: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3878_Y 1: $flatten\soc_I.\cpu_I.$procmux$12093_CMP 2: $flatten\soc_I.\cpu_I.$procmux$12103_CMP 3: $flatten\soc_I.\cpu_I.$procmux$12104_CMP 4: $flatten\soc_I.\cpu_I.$procmux$12115_CMP 5: $flatten\soc_I.\cpu_I.$procmux$12123_CMP 6: $flatten\soc_I.\cpu_I.$procmux$12124_CMP 7: $flatten\soc_I.\cpu_I.$procmux$12128_CMP State encoding: 0: 7'------1 1: 7'-----1- 2: 7'----1-- 3: 7'---1--- 4: 7'--1---- 5: 7'-1----- 6: 7'1------ Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 14'-10----------- -> 0 8'10000000 1: 0 14'--1----------- -> 0 8'10000000 2: 0 14'-00----------- -> 1 8'10000000 3: 1 14'--1----------- -> 0 8'00000001 4: 1 14'-10--------11- -> 1 8'00000001 5: 1 14'-10--------0-- -> 1 8'00000001 6: 1 14'-00----------- -> 1 8'00000001 7: 1 14'-10--------10- -> 2 8'00000001 8: 2 14'--1----------- -> 0 8'00001000 9: 2 14'-00----------- -> 1 8'00001000 10: 2 14'010----0000--- -> 3 8'00001000 11: 2 14'110----------- -> 3 8'00001000 12: 2 14'010----1-00--- -> 4 8'00001000 13: 2 14'-10------1---- -> 4 8'00001000 14: 2 14'010-----100--- -> 5 8'00001000 15: 2 14'-10-------1--- -> 6 8'00001000 16: 3 14'--1----------- -> 0 8'01000000 17: 3 14'-10---1------1 -> 1 8'01000000 18: 3 14'-10---0------- -> 1 8'01000000 19: 3 14'-00----------- -> 1 8'01000000 20: 3 14'-10---1------0 -> 3 8'01000000 21: 4 14'--1----------- -> 0 8'00100000 22: 4 14'-10--1-------- -> 1 8'00100000 23: 4 14'-00----------- -> 1 8'00100000 24: 4 14'-10--0-------- -> 4 8'00100000 25: 5 14'--1----------- -> 0 8'00010000 26: 5 14'-1011--------- -> 1 8'00010000 27: 5 14'-00----------- -> 1 8'00010000 28: 5 14'-10-0--------- -> 5 8'00010000 29: 5 14'-1001--------- -> 5 8'00010000 30: 6 14'--1----------- -> 0 8'00000010 31: 6 14'-1011--------- -> 1 8'00000010 32: 6 14'-00----------- -> 1 8'00000010 33: 6 14'-10-0--------- -> 6 8'00000010 34: 6 14'-1001--------- -> 6 8'00000010 ------------------------------------- FSM `$fsm$\soc_I.cpu_I.mem_wordsize$22762' from module `top': ------------------------------------- Information on FSM $fsm$\soc_I.cpu_I.mem_wordsize$22762 (\soc_I.cpu_I.mem_wordsize): Number of input signals: 13 Number of output signals: 3 Number of state bits: 3 Input signals: 0: \soc_I.cpu_I.mem_do_rdata 1: \soc_I.cpu_I.mem_do_wdata 2: \soc_I.cpu_I.instr_lw 3: \soc_I.cpu_I.instr_sb 4: \soc_I.cpu_I.instr_sh 5: \soc_I.cpu_I.instr_sw 6: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3878_Y 7: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4025_Y 8: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1865$4033_Y 9: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1866$4034_Y 10: $flatten\soc_I.\cpu_I.$procmux$12093_CMP 11: $flatten\soc_I.\cpu_I.$procmux$12115_CMP 12: \soc_I.pb_rst_n Output signals: 0: $flatten\soc_I.\cpu_I.$procmux$14669_CMP 1: $flatten\soc_I.\cpu_I.$procmux$14676_CMP 2: $flatten\soc_I.\cpu_I.$procmux$14681_CMP State encoding: 0: 3'--1 1: 3'-1- 2: 3'1-- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 13'1-1--1----1-0 -> 0 3'100 1: 0 13'1-1--1------1 -> 0 3'100 2: 0 13'11---1-1---0- -> 0 3'100 3: 0 13'11---1-----1- -> 0 3'100 4: 0 13'100---0------ -> 0 3'100 5: 0 13'1-----1------ -> 0 3'100 6: 0 13'1-1--0------- -> 0 3'100 7: 0 13'11---0------- -> 0 3'100 8: 0 13'0------------ -> 0 3'100 9: 0 13'1-1-11------0 -> 1 3'100 10: 0 13'11---1---1-0- -> 1 3'100 11: 0 13'1-11-1------0 -> 2 3'100 12: 0 13'11---1--1--0- -> 2 3'100 13: 1 13'1-1--1----1-0 -> 0 3'001 14: 1 13'11---1-1---0- -> 0 3'001 15: 1 13'1-----1------ -> 0 3'001 16: 1 13'1-1-11------0 -> 1 3'001 17: 1 13'1-1--1------1 -> 1 3'001 18: 1 13'11---1---1-0- -> 1 3'001 19: 1 13'11---1-----1- -> 1 3'001 20: 1 13'100---0------ -> 1 3'001 21: 1 13'1-1--0------- -> 1 3'001 22: 1 13'11---0------- -> 1 3'001 23: 1 13'0------------ -> 1 3'001 24: 1 13'1-11-1------0 -> 2 3'001 25: 1 13'11---1--1--0- -> 2 3'001 26: 2 13'1-1--1----1-0 -> 0 3'010 27: 2 13'11---1-1---0- -> 0 3'010 28: 2 13'1-----1------ -> 0 3'010 29: 2 13'1-1-11------0 -> 1 3'010 30: 2 13'11---1---1-0- -> 1 3'010 31: 2 13'1-11-1------0 -> 2 3'010 32: 2 13'1-1--1------1 -> 2 3'010 33: 2 13'11---1--1--0- -> 2 3'010 34: 2 13'11---1-----1- -> 2 3'010 35: 2 13'100---0------ -> 2 3'010 36: 2 13'1-1--0------- -> 2 3'010 37: 2 13'11---0------- -> 2 3'010 38: 2 13'0------------ -> 2 3'010 ------------------------------------- FSM `$fsm$\soc_I.usb_I.rx_pkt_I.state$22767' from module `top': ------------------------------------- Information on FSM $fsm$\soc_I.usb_I.rx_pkt_I.state$22767 (\soc_I.usb_I.rx_pkt_I.state): Number of input signals: 14 Number of output signals: 6 Number of state bits: 8 Input signals: 0: \soc_I.usb_I.rx_ll_I.dec_valid_1 1: \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [3] 2: \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [2] 3: $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:180$1317_Y 4: $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:173$1315_Y 5: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:158$1311_Y 6: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:153$1310_Y 7: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:126$1306_Y 8: \soc_I.usb_I.rx_pkt_I.pid_is_handshake 9: \soc_I.usb_I.rx_pkt_I.pid_is_data 10: \soc_I.usb_I.rx_pkt_I.pid_is_token 11: \soc_I.usb_I.rx_pkt_I.pid_is_sof 12: \soc_I.usb_I.rx_pkt_I.pid_valid 13: \soc_I.usb_I.rx_pkt_I.llu_byte_stb Output signals: 0: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:375$1399_Y 1: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:341$1385_Y 2: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:337$1382_Y 3: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:245$1336_Y 4: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_error[0:0] 5: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_idle[0:0] State encoding: 0: 8'-------1 1: 8'------1- 2: 8'-----1-- 3: 8'----1--- 4: 8'---1---- 5: 8'--1----- 6: 8'-1------ 7: 8'1------- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 14'------0------- -> 0 6'100000 1: 0 14'------1------- -> 4 6'100000 2: 1 14'0-------0----- -> 1 6'000100 3: 1 14'1-------0----- -> 5 6'000100 4: 1 14'--------1----- -> 6 6'000100 5: 2 14'-101---------- -> 1 6'000000 6: 2 14'-11----------- -> 1 6'000000 7: 2 14'-10001-------- -> 3 6'000000 8: 2 14'-10000-------- -> 6 6'000000 9: 2 14'-0------------ -> 6 6'000000 10: 2 14'-1001--------- -> 7 6'000000 11: 3 14'--------11---- -> 0 6'000000 12: 3 14'0-------0----- -> 3 6'000000 13: 3 14'--------10---- -> 6 6'000000 14: 3 14'1-------0----- -> 6 6'000000 15: 4 14'1------------- -> 2 6'001000 16: 4 14'0------------- -> 4 6'001000 17: 5 14'1-------0----- -> 3 6'000010 18: 5 14'0-------0----- -> 5 6'000010 19: 5 14'--------1----- -> 6 6'000010 20: 6 14'-------1------ -> 0 6'010000 21: 6 14'-------0------ -> 6 6'010000 22: 7 14'----------11-1 -> 0 6'000001 23: 7 14'-----------011 -> 6 6'000001 24: 7 14'----------01-1 -> 6 6'000001 25: 7 14'-------------0 -> 7 6'000001 26: 7 14'-----------001 -> 7 6'000001 ------------------------------------- FSM `$fsm$\soc_I.usb_I.tx_pkt_I.state$22777' from module `top': ------------------------------------- Information on FSM $fsm$\soc_I.usb_I.tx_pkt_I.state$22777 (\soc_I.usb_I.tx_pkt_I.state): Number of input signals: 5 Number of output signals: 6 Number of state bits: 6 Input signals: 0: $flatten\soc_I.\usb_I.\tx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:112$1524_Y 1: \soc_I.usb_I.tx_pkt_I.len [10] 2: \soc_I.usb_I.tx_pkt_I.next 3: \soc_I.usb_I.tx_pkt_I.pid_is_handshake 4: \soc_I.usb_I.trans_I.txpkt_start_i Output signals: 0: $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11425_CMP 1: $flatten\soc_I.\usb_I.\tx_pkt_I.$0\ll_start[0:0] 2: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:203$1567_Y 3: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1551_Y 4: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1550_Y 5: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:177$1549_Y State encoding: 0: 6'-----1 1: 6'----1- 2: 6'---1-- 3: 6'--1--- 4: 6'-1---- 5: 6'1----- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 5'0---- -> 0 6'000100 1: 0 5'1---- -> 3 6'000100 2: 1 5'--0-- -> 1 6'000001 3: 1 5'--1-- -> 4 6'000001 4: 2 5'-11-- -> 0 6'001000 5: 2 5'-011- -> 1 6'001000 6: 2 5'--0-- -> 2 6'001000 7: 2 5'-010- -> 5 6'001000 8: 3 5'----- -> 2 6'000010 9: 4 5'--1-- -> 0 6'010000 10: 4 5'--0-- -> 4 6'010000 11: 5 5'----1 -> 1 6'100000 12: 5 5'----0 -> 5 6'100000 ------------------------------------- 73.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic). Mapping FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.fsm_state$22734' from module `\top'. Mapping FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.fsm_state$22743' from module `\top'. Mapping FSM `$fsm$\soc_I.cpu_I.cpu_state$22752' from module `\top'. Mapping FSM `$fsm$\soc_I.cpu_I.mem_wordsize$22762' from module `\top'. Mapping FSM `$fsm$\soc_I.usb_I.rx_pkt_I.state$22767' from module `\top'. Mapping FSM `$fsm$\soc_I.usb_I.tx_pkt_I.state$22777' from module `\top'. 73.12. Executing OPT pass (performing simple optimizations). 73.12.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.12.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 32 cells. 73.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 2/4 on $pmux $flatten\soc_I.\cpu_I.$procmux$12708. dead port 2/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$13172. dead port 1/3 on $pmux $flatten\soc_I.\cpu_I.$procmux$13357. Removed 3 multiplexer ports. 73.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$22688: { \soc_I.cpu_I.cpu_state [6:4] \soc_I.cpu_I.cpu_state [2:0] } New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$22686: \soc_I.cpu_I.cpu_state [5:0] New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$22684: { \soc_I.cpu_I.cpu_state [6] \soc_I.cpu_I.cpu_state [4:0] } Optimizing cells in module \top. Performed a total of 3 changes. 73.12.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.12.6. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $flatten\sys_mgr_I.$procdff$22259 ($adff) from module top (D = $flatten\sys_mgr_I.$add$/build/gateware/e1-tracer/rtl/sysmgr.v:85$1592_Y [2:0], Q = \sys_mgr_I.rst_cnt [2:0]). Adding EN signal on $flatten\soc_I.\wb_48m_xclk_I.$procdff$22617 ($dff) from module top (D = \soc_I.wb_48m_xclk_I.m_rdata, Q = \soc_I.wb_48m_xclk_I.m_rdata_i). Adding SRST signal on $flatten\soc_I.\wb_48m_xclk_I.$procdff$22616 ($dff) from module top (D = \soc_I.wb_48m_xclk_I.m_rdata_i, Q = \soc_I.wb_48m_xclk_I.s_rdata, rval = 16'0000000000000000). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.\crc_16_I.$procdff$22222 ($dff) from module top (D = \soc_I.usb_I.tx_pkt_I.crc_16_I.state_nxt, Q = \soc_I.usb_I.tx_pkt_I.crc_16_I.state). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$22274 ($dff) from module top (D = $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1540_Y [3:0], Q = \soc_I.usb_I.tx_pkt_I.shift_bit). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$22273 ($dff) from module top (D = $flatten\soc_I.\usb_I.\tx_pkt_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:172$1546_Y, Q = \soc_I.usb_I.tx_pkt_I.shift_data). Adding SRST signal on $auto$opt_dff.cc:764:run$23335 ($dffe) from module top (D = \soc_I.usb_I.tx_pkt_I.shift_load [7], Q = \soc_I.usb_I.tx_pkt_I.shift_data [7], rval = 1'0). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$22272 ($dff) from module top (D = $flatten\soc_I.\usb_I.\tx_pkt_I.$or$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1553_Y, Q = \soc_I.usb_I.tx_pkt_I.shift_last_byte). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$22271 ($dff) from module top (D = \soc_I.usb_I.tx_pkt_I.state [5], Q = \soc_I.usb_I.tx_pkt_I.shift_data_crc). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$22269 ($dff) from module top (D = $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1563_Y [10:0], Q = \soc_I.usb_I.tx_pkt_I.len). Adding EN signal on $flatten\soc_I.\usb_I.\tx_ll_I.$procdff$22284 ($adff) from module top (D = $flatten\soc_I.\usb_I.\tx_ll_I.$0\state[2:0], Q = \soc_I.usb_I.tx_ll_I.state). Adding EN signal on $flatten\soc_I.\usb_I.\tx_ll_I.$procdff$22282 ($adff) from module top (D = $flatten\soc_I.\usb_I.\tx_ll_I.$and$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:95$1505_Y, Q = \soc_I.usb_I.tx_ll_I.bs_now). Adding EN signal on $flatten\soc_I.\usb_I.\tx_ll_I.$procdff$22281 ($adff) from module top (D = $flatten\soc_I.\usb_I.\tx_ll_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1503_Y [2:0], Q = \soc_I.usb_I.tx_ll_I.bs_cnt). Adding SRST signal on $flatten\soc_I.\usb_I.\tx_ll_I.$procdff$22280 ($dff) from module top (D = $flatten\soc_I.\usb_I.\tx_ll_I.$xor$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:103$1511_Y, Q = \soc_I.usb_I.tx_ll_I.lvl_prev, rval = 1'1). Adding EN signal on $flatten\soc_I.\usb_I.\tx_ll_I.$procdff$22278 ($adff) from module top (D = $flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11507_Y, Q = \soc_I.usb_I.tx_ll_I.out_sym). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22308 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$procmux$11588_Y, Q = \soc_I.usb_I.trans_I.mc_a_reg). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22305 ($dff) from module top (D = \soc_I.usb_I.trans_I.cel_state_i, Q = \soc_I.usb_I.trans_I.trans_cel). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22304 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:286$1437_Y, Q = \soc_I.usb_I.trans_I.trans_dir). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22303 ($dff) from module top (D = \soc_I.usb_I.rx_pkt_I.token_data [10:7], Q = \soc_I.usb_I.trans_I.trans_endp). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22302 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:284$1436_Y, Q = \soc_I.usb_I.trans_I.trans_is_setup). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22299 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$0\bd_state[2:0], Q = \soc_I.usb_I.trans_I.bd_state). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22296 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_trans.v:363$1448_Y, Q = \soc_I.usb_I.trans_I.ep_bd_idx_cur). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22295 ($dff) from module top (D = \soc_I.usb_I.ep_status_I.p_dout_3 [5], Q = \soc_I.usb_I.trans_I.ep_bd_ctrl). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22294 ($dff) from module top (D = \soc_I.usb_I.ep_status_I.p_dout_3 [4], Q = \soc_I.usb_I.trans_I.ep_bd_dual). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22293 ($dff) from module top (D = \soc_I.usb_I.ep_status_I.p_dout_3 [2:0], Q = \soc_I.usb_I.trans_I.ep_type). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22290 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$xor$/build/gateware/cores/no2usb//rtl/usb_trans.v:401$1469_Y, Q = \soc_I.usb_I.trans_I.txpkt_pid). Adding SRST signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22287 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_trans.v:425$1479_Y, Q = \soc_I.usb_I.trans_I.bd_length, rval = 11'00000000000). Adding SRST signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22286 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:429$1481_Y, Q = \soc_I.usb_I.trans_I.xfer_length, rval = 10'0000000000). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22285 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$procmux$11532_Y, Q = \soc_I.usb_I.trans_I.pkt_pid). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.\crc_5_I.$procdff$22221 ($dff) from module top (D = \soc_I.usb_I.rx_pkt_I.crc_5_I.state_nxt, Q = \soc_I.usb_I.rx_pkt_I.crc_5_I.state). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.\crc_16_I.$procdff$22222 ($dff) from module top (D = \soc_I.usb_I.rx_pkt_I.crc_16_I.state_nxt, Q = \soc_I.usb_I.rx_pkt_I.crc_16_I.state). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22330 ($dff) from module top (D = { \soc_I.usb_I.rx_ll_I.dec_bit_1 \soc_I.usb_I.rx_pkt_I.data [7:1] }, Q = \soc_I.usb_I.rx_pkt_I.data). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22329 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11631_Y, Q = \soc_I.usb_I.rx_pkt_I.bit_cnt, rval = 4'0110). Adding EN signal on $auto$opt_dff.cc:702:run$23370 ($sdff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1331_Y [3:0], Q = \soc_I.usb_I.rx_pkt_I.bit_cnt). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22328 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11626_Y, Q = \soc_I.usb_I.rx_pkt_I.bit_eop_ok, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23372 ($sdff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:234$1334_Y, Q = \soc_I.usb_I.rx_pkt_I.bit_eop_ok). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22327 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11621_Y, Q = \soc_I.usb_I.rx_pkt_I.crc_in_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23374 ($sdff) from module top (D = 1'0, Q = \soc_I.usb_I.rx_pkt_I.crc_in_first). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22325 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11611_Y, Q = \soc_I.usb_I.rx_pkt_I.crc16_ok, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23376 ($sdff) from module top (D = \soc_I.usb_I.rx_pkt_I.crc16_match, Q = \soc_I.usb_I.rx_pkt_I.crc16_ok). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22324 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11616_Y, Q = \soc_I.usb_I.rx_pkt_I.crc5_ok, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23378 ($sdff) from module top (D = \soc_I.usb_I.rx_pkt_I.crc5_match, Q = \soc_I.usb_I.rx_pkt_I.crc5_ok). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22323 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:306$1362_Y, Q = \soc_I.usb_I.rx_pkt_I.pid_valid). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22321 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_or$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:329$1380_Y, Q = \soc_I.usb_I.rx_pkt_I.pid_is_handshake). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22320 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_or$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:328$1375_Y, Q = \soc_I.usb_I.rx_pkt_I.pid_is_data). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22319 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_or$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:327$1372_Y, Q = \soc_I.usb_I.rx_pkt_I.pid_is_token). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22318 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:307$1345_Y, Q = \soc_I.usb_I.rx_pkt_I.pid_is_sof). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22317 ($dff) from module top (D = \soc_I.usb_I.rx_pkt_I.data [4:1], Q = \soc_I.usb_I.rx_pkt_I.pid). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22316 ($dff) from module top (D = { \soc_I.usb_I.rx_ll_I.dec_bit_1 \soc_I.usb_I.rx_pkt_I.data [7:1] }, Q = \soc_I.usb_I.rx_pkt_I.token_data [7:0]). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22315 ($dff) from module top (D = \soc_I.usb_I.rx_pkt_I.data [3:1], Q = \soc_I.usb_I.rx_pkt_I.token_data [10:8]). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$22342 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11897_Y, Q = \soc_I.usb_I.rx_ll_I.samp_cnt, rval = 3'101). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$22340 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:115$1294_Y, Q = \soc_I.usb_I.rx_ll_I.dec_bit_1). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$22339 ($dff) from module top (D = { \soc_I.usb_I.phy_I.dp_state [1] \soc_I.usb_I.phy_I.dn_state [1] }, Q = \soc_I.usb_I.rx_ll_I.dec_sym_1). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$22337 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11886_Y, Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$22336 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11881_Y, Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1). Adding SRST signal on $auto$opt_dff.cc:764:run$23392 ($dffe) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11871_Y, Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1, rval = 4'0000). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$22335 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11864_Y, Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1). Adding SRST signal on $auto$opt_dff.cc:764:run$23394 ($dffe) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11854_Y, Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1, rval = 4'0000). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$22334 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:183$1301_Y, Q = \soc_I.usb_I.rx_ll_I.dec_bs_skip_1). Adding EN signal on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$22349 ($dff) from module top (D = \soc_I.usb_I.ep_status_I.dout_2, Q = \soc_I.usb_I.ep_status_I.p_dout_3). Adding EN signal on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$22348 ($dff) from module top (D = $flatten\soc_I.\usb_I.\ep_status_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:82$1267_Y, Q = \soc_I.usb_I.ep_status_I.s_dout_3). Adding SRST signal on $auto$opt_dff.cc:764:run$23398 ($dffe) from module top (D = \soc_I.usb_I.ep_status_I.dout_2, Q = \soc_I.usb_I.ep_status_I.s_dout_3, rval = 16'0000000000000000). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22612 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:413$3200_Y, Q = \soc_I.usb_I.sof_clear, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22611 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:412$3197_Y, Q = \soc_I.usb_I.rst_clear, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22610 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:414$3203_Y, Q = \soc_I.usb_I.evt_rd_ack, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22608 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:410$3191_Y, Q = \soc_I.usb_I.cr_bus_we, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22606 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:411$3194_Y, Q = \soc_I.usb_I.cel_rel, rval = 1'0). Adding EN signal on $flatten\soc_I.\usb_I.$procdff$22605 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [6:0], Q = \soc_I.usb_I.cr_addr). Adding EN signal on $flatten\soc_I.\usb_I.$procdff$22604 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [7], Q = \soc_I.usb_I.cr_addr_chk). Adding EN signal on $flatten\soc_I.\usb_I.$procdff$22603 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [12], Q = \soc_I.usb_I.cr_cel_ena). Adding EN signal on $flatten\soc_I.\usb_I.$procdff$22602 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [15], Q = \soc_I.usb_I.cr_pu_ena). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22601 ($dff) from module top (D = \soc_I.cpu_I.mem_addr [13], Q = \soc_I.usb_I.eps_bus_req, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22600 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:498$3216_Y, Q = \soc_I.usb_I.eps_bus_write, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22599 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:497$3215_Y, Q = \soc_I.usb_I.eps_bus_read, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22596 ($dff) from module top (D = $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:623$3242_Y, Q = \soc_I.usb_I.timeout_suspend, rval = 20'11011100110110000000). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22595 ($dff) from module top (D = $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:632$3246_Y, Q = \soc_I.usb_I.timeout_reset, rval = 20'10001010110100000000). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22593 ($dff) from module top (D = \soc_I.usb_I.cr_pu_ena, Q = \soc_I.usb_I.pad_pu, rval = 1'0). Adding EN signal on $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$procdff$22344 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5111_DATA, Q = \soc_I.uart_I.uart_tx_fifo_I.ram_I.rd_data). Adding EN signal on $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$procdff$22250 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4520_Y [8:0], Q = \soc_I.uart_I.uart_tx_fifo_I.ram_wr_addr). Adding EN signal on $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$procdff$22249 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4522_Y [8:0], Q = \soc_I.uart_I.uart_tx_fifo_I.ram_rd_addr). Adding EN signal on $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$procdff$22248 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$not$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:114$4525_Y, Q = \soc_I.uart_I.uart_tx_fifo_I.rd_valid). Adding SRST signal on $flatten\soc_I.\uart_I.\uart_tx_I.$procdff$22241 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5251_Y [12], Q = \soc_I.uart_I.uart_tx_I.div_cnt [12], rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.\uart_tx_I.$procdff$22240 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_I.$procmux$5469_Y, Q = \soc_I.uart_I.uart_tx_I.bit_cnt, rval = 5'01000). Adding EN signal on $auto$opt_dff.cc:702:run$23420 ($sdff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5254_Y [4:0], Q = \soc_I.uart_I.uart_tx_I.bit_cnt). Adding EN signal on $flatten\soc_I.\uart_I.\uart_tx_I.$procdff$22239 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_I.$0\shift[9:0], Q = \soc_I.uart_I.uart_tx_I.shift). Adding EN signal on $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$procdff$22344 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5111_DATA, Q = \soc_I.uart_I.uart_rx_fifo_I.ram_I.rd_data). Adding EN signal on $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$procdff$22250 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4520_Y [8:0], Q = \soc_I.uart_I.uart_rx_fifo_I.ram_wr_addr). Adding EN signal on $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$procdff$22249 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4522_Y [8:0], Q = \soc_I.uart_I.uart_rx_fifo_I.ram_rd_addr). Adding EN signal on $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$procdff$22248 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$not$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:114$4525_Y, Q = \soc_I.uart_I.uart_rx_fifo_I.rd_valid). Adding SRST signal on $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procdff$22257 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4491_Y, Q = \soc_I.uart_I.uart_rx_I.gf_I.cnt, rval = 2'11). Adding SRST signal on $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procdff$22256 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procmux$5506_Y, Q = \soc_I.uart_I.uart_rx_I.gf_I.state, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23430 ($sdff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procmux$5506_Y, Q = \soc_I.uart_I.uart_rx_I.gf_I.state). Adding SRST signal on $flatten\soc_I.\uart_I.\uart_rx_I.$procdff$22245 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_I.$procmux$5479_Y, Q = \soc_I.uart_I.uart_rx_I.bit_cnt, rval = 5'01000). Adding EN signal on $auto$opt_dff.cc:702:run$23434 ($sdff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5236_Y [4:0], Q = \soc_I.uart_I.uart_rx_I.bit_cnt). Adding EN signal on $flatten\soc_I.\uart_I.\uart_rx_I.$procdff$22244 ($dff) from module top (D = { \soc_I.uart_I.uart_rx_I.gf_I.state \soc_I.uart_I.uart_rx_I.shift [8:1] }, Q = \soc_I.uart_I.uart_rx_I.shift). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$22587 ($dff) from module top (D = $flatten\soc_I.\uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:174$3294_Y, Q = \soc_I.uart_I.ub_wr_div, rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$22586 ($dff) from module top (D = $flatten\soc_I.\uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:173$3291_Y, Q = \soc_I.uart_I.ub_wr_data, rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$22585 ($dff) from module top (D = $flatten\soc_I.\uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:172$3286_Y, Q = \soc_I.uart_I.ub_rd_ctrl, rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$22584 ($dff) from module top (D = $flatten\soc_I.\uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:171$3282_Y, Q = \soc_I.uart_I.ub_rd_data, rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$22583 ($dff) from module top (D = $flatten\soc_I.\uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:181$3301_Y, Q = \soc_I.uart_I.ub_ack, rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$22582 ($dff) from module top (D = { $flatten\soc_I.\uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3306_Y [31] $flatten\soc_I.\uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3306_Y [27:12] $flatten\soc_I.\uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3306_Y [7:0] }, Q = { \soc_I.uart_I.ub_rdata [31] \soc_I.uart_I.ub_rdata [27:12] \soc_I.uart_I.ub_rdata [7:0] }, rval = 25'0000000000000000000000000). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$22582 ($dff) from module top (D = { \soc_I.uart_I.urf_overflow \soc_I.uart_I.uart_tx_fifo_I.rd_empty \soc_I.uart_I.uart_tx_fifo_I.full \soc_I.uart_I.uart_div [11:8] }, Q = { \soc_I.uart_I.ub_rdata [30:28] \soc_I.uart_I.ub_rdata [11:8] }, rval = 7'0000000). Adding EN signal on $flatten\soc_I.\uart_I.$procdff$22581 ($dff) from module top (D = \soc_I.cpu_I.mem_wdata [11:0], Q = \soc_I.uart_I.uart_div). Adding EN signal on $flatten\soc_I.\rgb_I.$procdff$22589 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [4:0], Q = \soc_I.rgb_I.led_ctrl). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$22624 ($adff) from module top (D = \soc_I.iobuf_I.spram_arb_I.mux_wmsk, Q = \soc_I.iobuf_I.spram_arb_I.m_wmsk). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$22623 ($adff) from module top (D = $flatten\soc_I.\iobuf_I.\spram_arb_I.$reduce_or$/build/gateware/common/rtl/wb_arbiter.v:91$4885_Y, Q = \soc_I.iobuf_I.spram_arb_I.m_we). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$22622 ($adff) from module top (D = \soc_I.iobuf_I.spram_arb_I.mux_wdata, Q = \soc_I.iobuf_I.spram_arb_I.m_wdata). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$22621 ($adff) from module top (D = \soc_I.iobuf_I.spram_arb_I.mux_addr, Q = \soc_I.iobuf_I.spram_arb_I.m_addr). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$22620 ($adff) from module top (D = $flatten\soc_I.\iobuf_I.\spram_arb_I.$reduce_or$/build/gateware/common/rtl/wb_arbiter.v:121$4898_Y, Q = \soc_I.iobuf_I.spram_arb_I.busy). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$22619 ($adff) from module top (D = \soc_I.iobuf_I.spram_arb_I.sel_nxt, Q = \soc_I.iobuf_I.spram_arb_I.sel). Adding EN signal on $flatten\soc_I.\iobuf_I.\epbam_arb_I.$procdff$22204 ($adff) from module top (D = $flatten\soc_I.\iobuf_I.\epbam_arb_I.$reduce_or$/build/gateware/common/rtl/wb_arbiter.v:91$4833_Y, Q = \soc_I.iobuf_I.epbam_arb_I.m_we). Adding EN signal on $flatten\soc_I.\iobuf_I.\epbam_arb_I.$procdff$22203 ($adff) from module top (D = \soc_I.iobuf_I.epbam_arb_I.mux_wdata, Q = \soc_I.iobuf_I.epbam_arb_I.m_wdata). Adding EN signal on $flatten\soc_I.\iobuf_I.\epbam_arb_I.$procdff$22202 ($adff) from module top (D = \soc_I.iobuf_I.epbam_arb_I.mux_addr, Q = \soc_I.iobuf_I.epbam_arb_I.m_addr). Adding EN signal on $flatten\soc_I.\iobuf_I.\epbam_arb_I.$procdff$22201 ($adff) from module top (D = $flatten\soc_I.\iobuf_I.\epbam_arb_I.$reduce_or$/build/gateware/common/rtl/wb_arbiter.v:121$4844_Y, Q = \soc_I.iobuf_I.epbam_arb_I.busy). Adding EN signal on $flatten\soc_I.\iobuf_I.\epbam_arb_I.$procdff$22200 ($adff) from module top (D = \soc_I.iobuf_I.epbam_arb_I.sel_nxt, Q = \soc_I.iobuf_I.epbam_arb_I.sel). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$22214 ($adff) from module top (D = \soc_I.iobuf_I.dma_I.state_nxt, Q = \soc_I.iobuf_I.dma_I.state). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$22213 ($dff) from module top (D = $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:144$4777_Y, Q = \soc_I.iobuf_I.dma_I.data_reg). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$22212 ($dff) from module top (D = $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:155$4781_Y [13:0], Q = \soc_I.iobuf_I.dma_I.m0_addr_i). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$22211 ($dff) from module top (D = $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:159$4785_Y [8:0], Q = \soc_I.iobuf_I.dma_I.m1_addr_i). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$22210 ($dff) from module top (D = $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:176$4794_Y [12:0], Q = \soc_I.iobuf_I.dma_I.len). Adding SRST signal on $auto$opt_dff.cc:764:run$23473 ($dffe) from module top (D = $flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$4793_Y [12], Q = \soc_I.iobuf_I.dma_I.len [12], rval = 1'0). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$22209 ($dff) from module top (D = \soc_I.cpu_I.mem_wdata [14], Q = \soc_I.iobuf_I.dma_I.dir). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$22566 ($dff) from module top (D = \soc_I.e1_buf_I.t_nxt_chan, Q = \soc_I.e1_buf_I.t_chan). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$22558 ($dff) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$14806_Y, Q = \soc_I.e1_buf_I.wb_wdata_byte). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$22557 ($dff) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$14821_Y, Q = \soc_I.e1_buf_I.wb_addr_lsb). Adding SRST signal on $auto$opt_dff.cc:764:run$23478 ($dffe) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$14815_Y, Q = \soc_I.e1_buf_I.wb_addr_lsb, rval = 2'00). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$22554 ($dff) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$14836_Y, Q = \soc_I.e1_buf_I.wb_addr). Adding SRST signal on $auto$opt_dff.cc:764:run$23482 ($dffe) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$14830_Y, Q = \soc_I.e1_buf_I.wb_addr, rval = 14'00000000000000). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$22553 ($dff) from module top (D = { \soc_I.e1_buf_I.buf_rx_mf [6:0] \soc_I.e1_buf_I.buf_rx_frame [3:0] \soc_I.e1_buf_I.buf_rx_ts [4:0] }, Q = \soc_I.e1_buf_I.rx_addr_reg[0]). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$22552 ($dff) from module top (D = \soc_I.e1_buf_I.buf_rx_data [7:0], Q = \soc_I.e1_buf_I.rx_data_reg[0]). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$22550 ($dff) from module top (D = { \soc_I.e1_buf_I.buf_rx_mf [13:7] \soc_I.e1_buf_I.buf_rx_frame [7:4] \soc_I.e1_buf_I.buf_rx_ts [9:5] }, Q = \soc_I.e1_buf_I.rx_addr_reg[1]). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$22549 ($dff) from module top (D = \soc_I.e1_buf_I.buf_rx_data [15:8], Q = \soc_I.e1_buf_I.rx_data_reg[1]). Adding SRST signal on $flatten\soc_I.\e1_I.$procdff$22380 ($dff) from module top (D = \soc_I.e1_I.bus_rdata, Q = \soc_I.e1_I.wb_rdata, rval = 16'0000000000000000). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.\crc_I.$procdff$22679 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.\crc_I.$xor$/build/gateware/cores/no2e1//rtl/e1_crc4.v:40$11_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.crc_I.out_crc4). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22677 ($dff) from module top (D = \misc_I.e1_cnt_I[1].sub_I.inc, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.crc_I.in_valid, rval = 1'0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22676 ($dff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.data [6:0] \soc_I.e1_I.lb_bit [1] }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.data). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22675 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:132$20_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.data_match_fas). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22673 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procmux$15131_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.bit_last, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23495 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:210$33_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.bit_last). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22672 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procmux$15136_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.bit_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23497 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:209$32_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.bit_first). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22671 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procmux$15141_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.bit, rval = 3'000). Adding EN signal on $auto$opt_dff.cc:702:run$23499 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:208$31_Y [2:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.bit). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22670 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procmux$15116_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.ts_is_ts31, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23501 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:222$37_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.ts_is_ts31). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22669 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procmux$15121_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.ts_is_ts0, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23503 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.ts_is_ts31, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.ts_is_ts0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22668 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procmux$15126_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.ts, rval = 5'00001). Adding EN signal on $auto$opt_dff.cc:702:run$23505 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:220$36_Y [4:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.ts). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22667 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procmux$15091_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.frame_mf_last, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23507 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:238$43_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.frame_mf_last). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22666 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procmux$15096_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.frame_mf_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23509 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.frame_mf_last, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.frame_mf_first). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22665 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procmux$15101_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.frame_smf_last, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23511 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:236$42_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.frame_smf_last). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22664 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procmux$15106_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.frame_smf_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23513 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.frame_smf_last, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.frame_smf_first). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22663 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procmux$15111_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.frame, rval = 4'0000). Adding EN signal on $auto$opt_dff.cc:702:run$23515 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:234$41_Y [3:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.frame). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22662 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$xor$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:257$49_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.fas_pos, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22661 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procmux$15083_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.mfa_timeout, rval = 7'0111111). Adding EN signal on $auto$opt_dff.cc:702:run$23518 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:265$53_Y [6:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.mfa_timeout). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22660 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procmux$15068_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.ts0_msbs_match_crc, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23520 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:280$59_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.ts0_msbs_match_crc). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22659 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procmux$15073_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23522 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:279$58_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22658 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procmux$15078_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.ts0_msbs, rval = 16'1111111111111111). Adding EN signal on $auto$opt_dff.cc:702:run$23524 ($sdff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.ts0_msbs [14:0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.data [0] }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.ts0_msbs). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22657 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.crc_I.out_crc4, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.crc_smf). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22656 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:320$81_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.ep_nfas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22655 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:321$87_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.ed_nfas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22654 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:318$72_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.ep_fas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22653 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:319$77_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.ed_fas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22652 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:335$100_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.ep_mfa, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22651 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:336$105_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.ed_mfa, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22650 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:333$92_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.ep_crc, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22649 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:334$97_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.ed_crc, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22648 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:349$122_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.ec_mfa, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22647 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:348$118_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.ec_crc, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22646 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:347$114_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.ec_nfas, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22645 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:346$110_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.ec_fas, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22643 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:378$135_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.out_valid, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22642 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:385$137_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.out_last, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22641 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:384$136_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.out_first, rval = 1'1). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22639 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.ts, Q = \soc_I.e1_buf_I.buf_rx_ts [9:5], rval = 5'00000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22638 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.frame, Q = \soc_I.e1_buf_I.buf_rx_frame [7:4], rval = 4'0000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22637 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.data, Q = \soc_I.e1_buf_I.buf_rx_data [15:8], rval = 8'00000000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$procdff$22636 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:378$134_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.aligned, rval = 1'0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\bd_rx_out_I.$procdff$22379 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\bd_rx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4121_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_out_I.data[1]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\bd_rx_out_I.$procdff$22378 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4126_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_out_I.stage[1].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\bd_rx_out_I.$procdff$22377 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\bd_rx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4132_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_out_I.data[2]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\bd_rx_out_I.$procdff$22376 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4137_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_out_I.stage[2].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\bd_rx_out_I.$procdff$22375 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\bd_rx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4143_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_out_I.data[3]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\bd_rx_out_I.$procdff$22374 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4148_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_out_I.stage[3].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\bd_rx_out_I.$procdff$22373 ($adff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_out_I.data[5] [8:7] \soc_I.e1_buf_I.buf_rx_mf [13:7] }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_out_I.data[4]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\bd_rx_out_I.$procdff$22372 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4159_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_out_I.stage[4].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\bd_rx_in_I.$procdff$22371 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\bd_rx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4167_Y, Q = \soc_I.e1_buf_I.buf_rx_mf [13:7]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\bd_rx_in_I.$procdff$22370 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4172_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_in_I.stage[1].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\bd_rx_in_I.$procdff$22369 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\bd_rx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4178_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_in_I.data[2]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\bd_rx_in_I.$procdff$22368 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4183_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_in_I.stage[2].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\bd_rx_in_I.$procdff$22367 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\bd_rx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4189_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_in_I.data[3]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\bd_rx_in_I.$procdff$22366 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4194_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_in_I.stage[3].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\bd_rx_in_I.$procdff$22365 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [6:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_in_I.data[4]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\bd_rx_in_I.$procdff$22364 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4205_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_in_I.stage[4].l_valid). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.$procdff$22237 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:114$5264_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.crx_clear, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.$procdff$22236 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:113$5261_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.$procmux$5455_CMP, rval = 1'0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.$procdff$22234 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bus_rd_rx_status [0]). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.$procdff$22233 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:149$5277_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_out_I.rd_ena, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.$procdff$22232 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:148$5271_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_in_I.wr_ena, rval = 1'0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.\crc_I.$procdff$22679 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.\crc_I.$xor$/build/gateware/cores/no2e1//rtl/e1_crc4.v:40$11_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.crc_I.out_crc4). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22677 ($dff) from module top (D = \misc_I.e1_cnt_I[0].sub_I.inc, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.crc_I.in_valid, rval = 1'0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22676 ($dff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.data [6:0] \soc_I.e1_I.lb_bit [0] }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.data). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22675 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:132$20_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.data_match_fas). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22673 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procmux$15131_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.bit_last, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23579 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:210$33_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.bit_last). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22672 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procmux$15136_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.bit_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23581 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:209$32_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.bit_first). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22671 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procmux$15141_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.bit, rval = 3'000). Adding EN signal on $auto$opt_dff.cc:702:run$23583 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:208$31_Y [2:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.bit). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22670 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procmux$15116_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.ts_is_ts31, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23585 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:222$37_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.ts_is_ts31). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22669 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procmux$15121_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.ts_is_ts0, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23587 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.ts_is_ts31, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.ts_is_ts0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22668 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procmux$15126_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.ts, rval = 5'00001). Adding EN signal on $auto$opt_dff.cc:702:run$23589 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:220$36_Y [4:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.ts). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22667 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procmux$15091_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.frame_mf_last, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23591 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:238$43_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.frame_mf_last). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22666 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procmux$15096_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.frame_mf_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23593 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.frame_mf_last, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.frame_mf_first). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22665 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procmux$15101_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.frame_smf_last, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23595 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:236$42_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.frame_smf_last). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22664 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procmux$15106_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.frame_smf_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23597 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.frame_smf_last, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.frame_smf_first). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22663 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procmux$15111_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.frame, rval = 4'0000). Adding EN signal on $auto$opt_dff.cc:702:run$23599 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:234$41_Y [3:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.frame). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22662 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$xor$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:257$49_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.fas_pos, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22661 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procmux$15083_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.mfa_timeout, rval = 7'0111111). Adding EN signal on $auto$opt_dff.cc:702:run$23602 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:265$53_Y [6:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.mfa_timeout). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22660 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procmux$15068_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_crc, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23604 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:280$59_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_crc). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22659 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procmux$15073_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23606 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:279$58_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22658 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procmux$15078_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.ts0_msbs, rval = 16'1111111111111111). Adding EN signal on $auto$opt_dff.cc:702:run$23608 ($sdff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.ts0_msbs [14:0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.data [0] }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.ts0_msbs). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22657 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.crc_I.out_crc4, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.crc_smf). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22656 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:320$81_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.ep_nfas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22655 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:321$87_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.ed_nfas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22654 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:318$72_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.ep_fas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22653 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:319$77_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.ed_fas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22652 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:335$100_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.ep_mfa, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22651 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:336$105_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.ed_mfa, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22650 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:333$92_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.ep_crc, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22649 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:334$97_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.ed_crc, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22648 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:349$122_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.ec_mfa, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22647 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:348$118_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.ec_crc, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22646 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:347$114_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.ec_nfas, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22645 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:346$110_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.ec_fas, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22643 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:378$135_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.out_valid, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22642 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:385$137_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.out_last, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22641 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:384$136_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.out_first, rval = 1'1). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22639 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.ts, Q = \soc_I.e1_buf_I.buf_rx_ts [4:0], rval = 5'00000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22638 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.frame, Q = \soc_I.e1_buf_I.buf_rx_frame [3:0], rval = 4'0000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22637 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.data, Q = \soc_I.e1_buf_I.buf_rx_data [7:0], rval = 8'00000000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$procdff$22636 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:378$134_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.aligned, rval = 1'0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\bd_rx_out_I.$procdff$22379 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\bd_rx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4121_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_out_I.data[1]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\bd_rx_out_I.$procdff$22378 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4126_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_out_I.stage[1].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\bd_rx_out_I.$procdff$22377 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\bd_rx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4132_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_out_I.data[2]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\bd_rx_out_I.$procdff$22376 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4137_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_out_I.stage[2].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\bd_rx_out_I.$procdff$22375 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\bd_rx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4143_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_out_I.data[3]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\bd_rx_out_I.$procdff$22374 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4148_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_out_I.stage[3].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\bd_rx_out_I.$procdff$22373 ($adff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_out_I.data[5] [8:7] \soc_I.e1_buf_I.buf_rx_mf [6:0] }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_out_I.data[4]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\bd_rx_out_I.$procdff$22372 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4159_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_out_I.stage[4].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\bd_rx_in_I.$procdff$22371 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\bd_rx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4167_Y, Q = \soc_I.e1_buf_I.buf_rx_mf [6:0]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\bd_rx_in_I.$procdff$22370 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4172_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_in_I.stage[1].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\bd_rx_in_I.$procdff$22369 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\bd_rx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4178_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_in_I.data[2]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\bd_rx_in_I.$procdff$22368 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4183_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_in_I.stage[2].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\bd_rx_in_I.$procdff$22367 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\bd_rx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4189_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_in_I.data[3]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\bd_rx_in_I.$procdff$22366 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4194_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_in_I.stage[3].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\bd_rx_in_I.$procdff$22365 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [6:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_in_I.data[4]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\bd_rx_in_I.$procdff$22364 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4205_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_in_I.stage[4].l_valid). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.$procdff$22237 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:114$5264_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.crx_clear, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.$procdff$22236 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:113$5261_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.$procmux$5455_CMP, rval = 1'0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.$procdff$22234 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bus_rd_rx_status [0]). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.$procdff$22233 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:149$5277_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_out_I.rd_ena, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.$procdff$22232 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:148$5271_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_in_I.wr_ena, rval = 1'0). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22539 ($dff) from module top (D = \soc_I.cpu_I.mem_rdata, Q = \soc_I.cpu_I.mem_rdata_q). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22534 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$0\mem_state[1:0], Q = \soc_I.cpu_I.mem_state). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22533 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14397_Y, Q = \soc_I.cpu_I.mem_wstrb). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22532 ($dff) from module top (D = \soc_I.cpu_I.mem_la_wdata, Q = \soc_I.cpu_I.mem_wdata). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22530 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$0\mem_valid[0:0], Q = \soc_I.cpu_I.mem_valid). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22529 ($dff) from module top (D = \soc_I.cpu_I.mem_la_addr, Q = \soc_I.cpu_I.mem_addr). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22513 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$reduce_or$/build/gateware/common/rtl/picorv32.v:846$3583_Y, Q = \soc_I.cpu_I.is_compare, rval = 1'0). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22512 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:860$3603_Y, Q = \soc_I.cpu_I.is_alu_reg_reg). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22511 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:859$3602_Y, Q = \soc_I.cpu_I.is_alu_reg_imm). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22509 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13778_Y, Q = \soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23704 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:856$3599_Y, Q = \soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22506 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$reduce_or$/build/gateware/common/rtl/picorv32.v:842$3579_Y, Q = \soc_I.cpu_I.is_lui_auipc_jal_jalr_addi_add_sub, rval = 1'0). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22505 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1091$3832_Y, Q = \soc_I.cpu_I.is_sll_srl_sra). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22504 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:858$3601_Y, Q = \soc_I.cpu_I.is_sb_sh_sw). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22503 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1082$3821_Y, Q = \soc_I.cpu_I.is_jalr_addi_slti_sltiu_xori_ori_andi). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22502 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1076$3812_Y, Q = \soc_I.cpu_I.is_slli_srli_srai). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22501 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:857$3600_Y, Q = \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22499 ($dff) from module top (D = 1'0, Q = \soc_I.cpu_I.compressed_instr). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$23712 ($dffe) from module top. Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22498 ($dff) from module top (D = { \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [19:12] \soc_I.cpu_I.mem_rdata_latched [20] \soc_I.cpu_I.mem_rdata_latched [30:21] 1'0 }, Q = \soc_I.cpu_I.decoded_imm_uj). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$23713 ($dffe) from module top. Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22497 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824_Y, Q = \soc_I.cpu_I.decoded_imm). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22496 ($dff) from module top (D = \soc_I.cpu_I.mem_rdata_latched [24:20], Q = \soc_I.cpu_I.decoded_rs2). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22495 ($dff) from module top (D = \soc_I.cpu_I.mem_rdata_latched [19:15], Q = \soc_I.cpu_I.decoded_rs1). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22494 ($dff) from module top (D = \soc_I.cpu_I.mem_rdata_latched [11:7], Q = \soc_I.cpu_I.decoded_rd). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22490 ($dff) from module top (D = 1'0, Q = \soc_I.cpu_I.instr_retirq). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$23718 ($dffe) from module top. Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22487 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1068$3779_Y, Q = \soc_I.cpu_I.instr_ecall_ebreak). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22482 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13934_Y, Q = \soc_I.cpu_I.instr_and, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23720 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1059$3748_Y, Q = \soc_I.cpu_I.instr_and). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22481 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13938_Y, Q = \soc_I.cpu_I.instr_or, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23722 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1058$3744_Y, Q = \soc_I.cpu_I.instr_or). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22480 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13942_Y, Q = \soc_I.cpu_I.instr_sra, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23724 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1057$3740_Y, Q = \soc_I.cpu_I.instr_sra). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22479 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13946_Y, Q = \soc_I.cpu_I.instr_srl, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23726 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1056$3736_Y, Q = \soc_I.cpu_I.instr_srl). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22478 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13950_Y, Q = \soc_I.cpu_I.instr_xor, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23728 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1055$3732_Y, Q = \soc_I.cpu_I.instr_xor). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22477 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13954_Y, Q = \soc_I.cpu_I.instr_sltu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23730 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1054$3728_Y, Q = \soc_I.cpu_I.instr_sltu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22476 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13958_Y, Q = \soc_I.cpu_I.instr_slt, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23732 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1053$3724_Y, Q = \soc_I.cpu_I.instr_slt). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22475 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13962_Y, Q = \soc_I.cpu_I.instr_sll, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23734 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1052$3720_Y, Q = \soc_I.cpu_I.instr_sll). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22474 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13966_Y, Q = \soc_I.cpu_I.instr_sub, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23736 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1051$3716_Y, Q = \soc_I.cpu_I.instr_sub). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22473 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13970_Y, Q = \soc_I.cpu_I.instr_add, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23738 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1050$3712_Y, Q = \soc_I.cpu_I.instr_add). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22472 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1048$3708_Y, Q = \soc_I.cpu_I.instr_srai). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22471 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1047$3704_Y, Q = \soc_I.cpu_I.instr_srli). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22470 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1046$3700_Y, Q = \soc_I.cpu_I.instr_slli). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22469 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13980_Y, Q = \soc_I.cpu_I.instr_andi, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23743 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1044$3696_Y, Q = \soc_I.cpu_I.instr_andi). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22468 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13984_Y, Q = \soc_I.cpu_I.instr_ori, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23745 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1043$3694_Y, Q = \soc_I.cpu_I.instr_ori). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22467 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13988_Y, Q = \soc_I.cpu_I.instr_xori, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23747 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1042$3692_Y, Q = \soc_I.cpu_I.instr_xori). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22466 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13992_Y, Q = \soc_I.cpu_I.instr_sltiu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23749 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1041$3690_Y, Q = \soc_I.cpu_I.instr_sltiu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22465 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13996_Y, Q = \soc_I.cpu_I.instr_slti, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23751 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1040$3688_Y, Q = \soc_I.cpu_I.instr_slti). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22464 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14000_Y, Q = \soc_I.cpu_I.instr_addi, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23753 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1039$3686_Y, Q = \soc_I.cpu_I.instr_addi). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22463 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1037$3684_Y, Q = \soc_I.cpu_I.instr_sw). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22462 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1036$3682_Y, Q = \soc_I.cpu_I.instr_sh). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22461 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1035$3680_Y, Q = \soc_I.cpu_I.instr_sb). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22460 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1033$3678_Y, Q = \soc_I.cpu_I.instr_lhu). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22459 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1032$3676_Y, Q = \soc_I.cpu_I.instr_lbu). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22458 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1031$3674_Y, Q = \soc_I.cpu_I.instr_lw). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22457 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1030$3672_Y, Q = \soc_I.cpu_I.instr_lh). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22456 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1029$3670_Y, Q = \soc_I.cpu_I.instr_lb). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22455 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14020_Y, Q = \soc_I.cpu_I.instr_bgeu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23763 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1027$3668_Y, Q = \soc_I.cpu_I.instr_bgeu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22454 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14024_Y, Q = \soc_I.cpu_I.instr_bltu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23765 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1026$3666_Y, Q = \soc_I.cpu_I.instr_bltu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22453 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14028_Y, Q = \soc_I.cpu_I.instr_bge, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23767 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1025$3664_Y, Q = \soc_I.cpu_I.instr_bge). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22452 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14032_Y, Q = \soc_I.cpu_I.instr_blt, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23769 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1024$3662_Y, Q = \soc_I.cpu_I.instr_blt). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22451 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14036_Y, Q = \soc_I.cpu_I.instr_bne, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23771 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1023$3660_Y, Q = \soc_I.cpu_I.instr_bne). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22450 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14040_Y, Q = \soc_I.cpu_I.instr_beq, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23773 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1022$3658_Y, Q = \soc_I.cpu_I.instr_beq). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22449 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:852$3590_Y, Q = \soc_I.cpu_I.instr_jalr). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22448 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:851$3587_Y, Q = \soc_I.cpu_I.instr_jal). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22447 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:850$3586_Y, Q = \soc_I.cpu_I.instr_auipc). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22446 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:849$3585_Y, Q = \soc_I.cpu_I.instr_lui). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22435 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12754_Y, Q = \soc_I.cpu_I.latched_rd, rval = 5'00010). Adding EN signal on $auto$opt_dff.cc:702:run$23779 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12754_Y, Q = \soc_I.cpu_I.latched_rd). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22434 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12780_Y, Q = \soc_I.cpu_I.latched_is_lb, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23787 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12780_Y, Q = \soc_I.cpu_I.latched_is_lb). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22433 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12793_Y, Q = \soc_I.cpu_I.latched_is_lh, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23797 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12793_Y, Q = \soc_I.cpu_I.latched_is_lh). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22432 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12806_Y, Q = \soc_I.cpu_I.latched_is_lu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23807 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12806_Y, Q = \soc_I.cpu_I.latched_is_lu). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22430 ($dff) from module top (D = \soc_I.cpu_I.compressed_instr, Q = \soc_I.cpu_I.latched_compr). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22429 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12851_Y, Q = \soc_I.cpu_I.latched_branch, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23820 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12851_Y, Q = \soc_I.cpu_I.latched_branch). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22428 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12887_Y, Q = \soc_I.cpu_I.latched_stalu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23824 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12887_Y, Q = \soc_I.cpu_I.latched_stalu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22427 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12894_Y, Q = \soc_I.cpu_I.latched_store, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23832 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12894_Y, Q = \soc_I.cpu_I.latched_store). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22416 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12520_Y, Q = \soc_I.cpu_I.decoder_pseudo_trigger, rval = 1'0). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22413 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13158_Y, Q = \soc_I.cpu_I.mem_do_wdata, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23839 ($sdff) from module top (D = 1'0, Q = \soc_I.cpu_I.mem_do_wdata). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22412 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13162_Y, Q = \soc_I.cpu_I.mem_do_rdata, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23841 ($sdff) from module top (D = 1'0, Q = \soc_I.cpu_I.mem_do_rdata). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22411 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13233_Y, Q = \soc_I.cpu_I.mem_do_rinst, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23843 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13233_Y, Q = \soc_I.cpu_I.mem_do_rinst). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22410 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13258_Y, Q = \soc_I.cpu_I.mem_do_prefetch, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23857 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1552$3961_Y, Q = \soc_I.cpu_I.mem_do_prefetch). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12653_Y, Q = \soc_I.cpu_I.reg_out, rval = 1024). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22402 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13360_Y, Q = \soc_I.cpu_I.reg_op2). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22401 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13383_Y [31], Q = \soc_I.cpu_I.reg_op1 [31]). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22401 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13383_Y [30:0], Q = \soc_I.cpu_I.reg_op1 [30:0]). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22400 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$11995_Y, Q = \soc_I.cpu_I.reg_next_pc [31:2], rval = 30'000000000000000000000000000000). Adding EN signal on $auto$opt_dff.cc:702:run$23901 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$11984_Y, Q = \soc_I.cpu_I.reg_next_pc [31:2]). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22399 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13431_Y, Q = \soc_I.cpu_I.reg_pc [31:2], rval = 30'000000000000000000000000000000). Adding EN signal on $auto$opt_dff.cc:702:run$23903 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$3\current_pc[31:0] [31:2], Q = \soc_I.cpu_I.reg_pc [31:2]). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22392 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12736_Y, Q = \soc_I.cpu_I.trap, rval = 1'0). Adding SRST signal on $flatten\soc_I.\bridge_I.$procdff$22361 ($dff) from module top (D = \soc_I.bridge_I.wb_rdata_or, Q = \soc_I.bridge_I.wb_rdata_reg, rval = 0). Adding SRST signal on $flatten\soc_I.\bram_I.$procdff$22576 ($dff) from module top (D = 8'xxxxxxxx, Q = $flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3314_DATA [31:24], rval = 8'00000000). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$23907 ($sdff) from module top. Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$23907 ($sdff) from module top. Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$23907 ($sdff) from module top. Setting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$23907 ($sdff) from module top. Setting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$23907 ($sdff) from module top. Setting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$23907 ($sdff) from module top. Setting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$23907 ($sdff) from module top. Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$23907 ($sdff) from module top. Adding SRST signal on $flatten\soc_I.\bram_I.$procdff$22573 ($dff) from module top (D = 16'xxxxxxxxxxxxxxxx, Q = $flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3313_DATA [31:16], rval = 16'0000000000000000). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$23908 ($sdff) from module top. Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$23908 ($sdff) from module top. Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$23908 ($sdff) from module top. Setting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$23908 ($sdff) from module top. Setting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$23908 ($sdff) from module top. Setting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$23908 ($sdff) from module top. Setting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$23908 ($sdff) from module top. Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$23908 ($sdff) from module top. Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$23908 ($sdff) from module top. Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$23908 ($sdff) from module top. Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$23908 ($sdff) from module top. Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$23908 ($sdff) from module top. Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$23908 ($sdff) from module top. Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$23908 ($sdff) from module top. Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$23908 ($sdff) from module top. Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$23908 ($sdff) from module top. Adding SRST signal on $flatten\soc_I.\bram_I.$procdff$22570 ($dff) from module top (D = 24'xxxxxxxxxxxxxxxxxxxxxxxx, Q = $flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3312_DATA [31:8], rval = 24'000000000000000000000000). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$23909 ($sdff) from module top. Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$23909 ($sdff) from module top. Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$23909 ($sdff) from module top. Setting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$23909 ($sdff) from module top. Setting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$23909 ($sdff) from module top. Setting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$23909 ($sdff) from module top. Setting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$23909 ($sdff) from module top. Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$23909 ($sdff) from module top. Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$23909 ($sdff) from module top. Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$23909 ($sdff) from module top. Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$23909 ($sdff) from module top. Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$23909 ($sdff) from module top. Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$23909 ($sdff) from module top. Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$23909 ($sdff) from module top. Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$23909 ($sdff) from module top. Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$23909 ($sdff) from module top. Setting constant 0-bit at position 16 on $auto$opt_dff.cc:702:run$23909 ($sdff) from module top. Setting constant 0-bit at position 17 on $auto$opt_dff.cc:702:run$23909 ($sdff) from module top. Setting constant 0-bit at position 18 on $auto$opt_dff.cc:702:run$23909 ($sdff) from module top. Setting constant 0-bit at position 19 on $auto$opt_dff.cc:702:run$23909 ($sdff) from module top. Setting constant 0-bit at position 20 on $auto$opt_dff.cc:702:run$23909 ($sdff) from module top. Setting constant 0-bit at position 21 on $auto$opt_dff.cc:702:run$23909 ($sdff) from module top. Setting constant 0-bit at position 22 on $auto$opt_dff.cc:702:run$23909 ($sdff) from module top. Setting constant 0-bit at position 23 on $auto$opt_dff.cc:702:run$23909 ($sdff) from module top. Adding SRST signal on $flatten\misc_I.\dfu_I.\btn_flt_I.$procdff$22219 ($dff) from module top (D = $flatten\misc_I.\dfu_I.\btn_flt_I.$procmux$5390_Y, Q = \misc_I.dfu_I.btn_flt_I.state, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23910 ($sdff) from module top (D = 1'1, Q = \misc_I.dfu_I.btn_flt_I.state). Adding EN signal on $flatten\misc_I.\dfu_I.$procdff$22387 ($adff) from module top (D = $flatten\misc_I.\dfu_I.$procmux$11965_Y, Q = \misc_I.dfu_I.wb_sel). Adding EN signal on $flatten\misc_I.\dfu_I.$procdff$22386 ($adff) from module top (D = $flatten\misc_I.\dfu_I.$procmux$11970_Y, Q = \misc_I.dfu_I.rst_req). Adding SRST signal on $flatten\misc_I.$procdff$22263 ($dff) from module top (D = $flatten\misc_I.$eq$/build/gateware/e1-tracer/rtl/misc.v:70$1585_Y, Q = \misc_I.bus_we_boot, rval = 1'0). Adding SRST signal on $flatten\misc_I.$procdff$22262 ($dff) from module top (D = $flatten\misc_I.$procmux$11404_Y, Q = \misc_I.wb_rdata, rval = 0). Adding EN signal on $flatten\misc_I.$procdff$22261 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [2], Q = \misc_I.boot_now). Adding EN signal on $flatten\misc_I.$procdff$22260 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [1:0], Q = \misc_I.boot_sel). 73.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 428 unused cells and 502 unused wires. 73.12.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.12.9. Rerunning OPT passes. (Maybe there is more to do..) 73.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 73.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 73.12.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 23 cells. 73.12.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$23819 ($dffe) from module top. 73.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 27 unused wires. 73.12.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.12.16. Rerunning OPT passes. (Maybe there is more to do..) 73.12.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 73.12.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 73.12.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.12.20. Executing OPT_DFF pass (perform DFF optimizations). 73.12.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 1 unused wires. 73.12.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.12.23. Rerunning OPT passes. (Maybe there is more to do..) 73.12.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 73.12.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 73.12.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.12.27. Executing OPT_DFF pass (perform DFF optimizations). 73.12.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 73.12.29. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.12.30. Finished OPT passes. (There is nothing left to do.) 73.13. Executing WREDUCE pass (reducing word size of cells). Removed top 24 address bits (of 32) from memory init port top.$flatten\soc_I.\bram_I.$meminit$\mem$/build/gateware/common/rtl/soc_bram.v:0$3338 (soc_I.bram_I.mem). Removed top 2 bits (of 4) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$23663 ($ne). Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23326 ($eq). Removed top 1 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22870 ($eq). Removed top 2 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22866 ($eq). Removed top 2 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22862 ($eq). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$23688 ($ne). Removed top 2 bits (of 3) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$23684 ($ne). Removed top 3 bits (of 5) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$23853 ($ne). Removed top 2 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22899 ($eq). Removed top 1 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22895 ($eq). Removed top 3 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22891 ($eq). Removed top 2 bits (of 4) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$23341 ($ne). Removed top 1 bits (of 6) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23038 ($eq). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$23462 ($ne). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$23464 ($ne). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$23466 ($ne). Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23295 ($eq). Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23226 ($eq). Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23230 ($eq). Removed top 3 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22832 ($eq). Removed top 2 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23265 ($eq). Removed top 3 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22800 ($eq). Removed top 1 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22804 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\e1_buf_I.$eq$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:233$4973 ($eq). Removed top 3 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$4991 ($shl). Removed top 3 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_buf_I.$and$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$4993 ($and). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\e1_buf_I.$ne$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:253$5010 ($ne). Removed top 2 bits (of 4) from mux cell top.$flatten\soc_I.\e1_buf_I.$procmux$14718 ($mux). Removed cell top.$flatten\soc_I.\e1_buf_I.$procmux$14803 ($mux). Removed top 2 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22815 ($eq). Removed top 1 bits (of 2) from mux cell top.$flatten\soc_I.\e1_buf_I.$procmux$14849 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\e1_I.$eq$/build/gateware/cores/no2e1//rtl/e1_wb.v:149$5029 ($eq). Removed top 30 bits (of 32) from mux cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$9 ($mux). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.\crc_I.$xor$/build/gateware/cores/no2e1//rtl/e1_crc4.v:40$11 ($xor). Removed top 1 bits (of 6) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23025 ($eq). Removed top 1 bits (of 16) from FF cell top.$auto$opt_dff.cc:764:run$23609 ($sdffe). Removed top 1 bits (of 7) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23016 ($eq). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:349$122 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:348$118 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:347$114 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:346$110 ($add). Removed top 3 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.\crc_I.$and$/build/gateware/cores/no2e1//rtl/e1_crc4.v:35$3 ($and). Removed top 2 bits (of 6) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:279$58 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:265$53 ($sub). Removed top 25 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:265$53 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:234$41 ($add). Removed top 28 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:234$41 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:220$36 ($add). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:220$36 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:208$31 ($add). Removed top 29 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:208$31 ($add). Removed top 2 bits (of 6) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:132$19 ($eq). Removed top 30 bits (of 32) from mux cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$9 ($mux). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.\crc_I.$xor$/build/gateware/cores/no2e1//rtl/e1_crc4.v:40$11 ($xor). Removed top 1 bits (of 16) from FF cell top.$auto$opt_dff.cc:764:run$23525 ($sdffe). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:349$122 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:348$118 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:347$114 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:346$110 ($add). Removed top 3 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.\crc_I.$and$/build/gateware/cores/no2e1//rtl/e1_crc4.v:35$3 ($and). Removed top 2 bits (of 6) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:279$58 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:265$53 ($sub). Removed top 25 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:265$53 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:234$41 ($add). Removed top 28 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:234$41 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:220$36 ($add). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:220$36 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:208$31 ($add). Removed top 29 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:208$31 ($add). Removed top 2 bits (of 6) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:132$19 ($eq). Removed top 16 bits (of 32) from port B of cell top.$flatten\soc_I.\iobuf_I.$or$/build/gateware/common/rtl/soc_iobuf.v:250$2522 ($or). Removed top 1 bits (of 2) from FF cell top.$auto$opt_dff.cc:764:run$23476 ($dffe). Removed cell top.$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5380 ($mux). Removed cell top.$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5377 ($mux). Removed cell top.$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5373 ($mux). Removed top 20 bits (of 32) from mux cell top.$flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:176$4794 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$4793 ($sub). Removed top 19 bits (of 32) from port Y of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$4793 ($sub). Removed top 23 bits (of 32) from mux cell top.$flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:159$4785 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$4783 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$4783 ($add). Removed top 18 bits (of 32) from mux cell top.$flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:155$4781 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$4779 ($add). Removed top 18 bits (of 32) from port Y of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$4779 ($add). Removed top 3 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5446_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5445_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5444_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5443_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5442_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5441_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5440_CMP0 ($eq). Removed top 3 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5429_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5428_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5427_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5426_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5425_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5424_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5423_CMP0 ($eq). Removed cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11526 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11510_CMP0 ($eq). Removed top 29 bits (of 32) from mux cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1503 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1501 ($add). Removed top 29 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1501 ($add). Removed top 30 bits (of 32) from port A of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1497 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1497 ($add). Removed top 29 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1497 ($add). Removed top 16 bits (of 32) from mux cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.\crc_16_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4698 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1563 ($sub). Removed top 21 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1563 ($sub). Removed top 21 bits (of 32) from port A of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1563 ($sub). Removed top 21 bits (of 32) from mux cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1562 ($mux). Removed top 1 bits (of 8) from mux cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:172$1546 ($mux). Removed top 28 bits (of 32) from port A of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1540 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1540 ($sub). Removed top 28 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1540 ($sub). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:137$1527 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11904_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11903_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11902_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11889_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11878_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11877_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11876_CMP0 ($eq). Removed top 3 bits (of 4) from mux cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11869 ($mux). Removed top 2 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11861_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11860_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11859_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:98$1282 ($eq). Removed top 16 bits (of 32) from mux cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.\crc_16_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4698 ($mux). Removed top 1 bits (of 16) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.\crc_16_I.$eq$/build/gateware/cores/no2usb//rtl/usb_crc.v:44$4701 ($eq). Removed top 29 bits (of 32) from mux cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.\crc_5_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4711 ($mux). Removed top 2 bits (of 5) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.\crc_5_I.$xor$/build/gateware/cores/no2usb//rtl/usb_crc.v:38$4712 ($xor). Removed top 1 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22961 ($eq). Removed top 2 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22957 ($eq). Removed top 2 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22953 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:313$1356 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:311$1352 ($eq). Removed top 3 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:308$1346 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:307$1345 ($eq). Removed top 29 bits (of 32) from port A of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1331 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1331 ($sub). Removed top 28 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1331 ($sub). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$procmux$11591_CMP0 ($eq). Removed top 1 bits (of 4) from mux cell top.$flatten\soc_I.\usb_I.\trans_I.$procmux$11568 ($mux). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$procmux$11566_CMP0 ($eq). Removed cell top.$flatten\soc_I.\usb_I.\trans_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_trans.v:375$1458 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:303$1440 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:207$1418 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:206$1417 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:205$1416 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:204$1415 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:203$1414 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:202$1413 ($eq). Removed top 3 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:201$1412 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:179$1411 ($add). Removed top 24 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:179$1411 ($add). Removed top 2 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22808 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\uart_I.$eq$/build/gateware/cores/no2misc//rtl/uart_wb.v:172$3285 ($eq). Removed top 24 bits (of 32) from mux cell top.$flatten\soc_I.\uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3306 ($mux). Removed top 1 bits (of 5) from FF cell top.$auto$opt_dff.cc:764:run$23449 ($adffe). Removed top 1 bits (of 13) from mux cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$procmux$5475 ($mux). Removed cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$procmux$5464 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5254 ($sub). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5254 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5251 ($sub). Removed top 19 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5251 ($sub). Removed cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$procmux$11911 ($mux). Removed cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$procmux$11913 ($mux). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$procdff$22347 ($dff). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4522 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4522 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4520 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4520 ($add). Removed top 1 bits (of 10) from port B of cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$eq$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:81$4509 ($eq). Removed cell top.$flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procmux$5503 ($mux). Removed top 1 bits (of 2) from mux cell top.$flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procmux$5521 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5236 ($sub). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5236 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5233 ($sub). Removed top 19 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5233 ($sub). Removed top 21 bits (of 32) from port A of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5232 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5232 ($sub). Removed top 20 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5232 ($sub). Removed cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$procmux$11911 ($mux). Removed cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$procmux$11913 ($mux). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$procdff$22347 ($dff). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4522 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4522 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4520 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4520 ($add). Removed top 1 bits (of 10) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$eq$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:81$4509 ($eq). Removed cell top.$flatten\soc_I.\bram_I.$procmux$14855 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$14857 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$14861 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$14863 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$14867 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$14869 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$14873 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$14875 ($mux). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\bram_I.$procdff$22571 ($dff). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\bram_I.$procdff$22574 ($dff). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\bram_I.$procdff$22577 ($dff). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\bram_I.$procdff$22580 ($dff). Removed top 24 bits (of 32) from port A of cell top.$flatten\soc_I.\bridge_I.$or$/build/gateware/common/rtl/soc_picorv32_bridge.v:152$5076 ($or). Removed top 16 bits (of 32) from port B of cell top.$flatten\soc_I.\bridge_I.$or$/build/gateware/common/rtl/soc_picorv32_bridge.v:152$5078 ($or). Removed top 16 bits (of 32) from port B of cell top.$flatten\soc_I.\bridge_I.$or$/build/gateware/common/rtl/soc_picorv32_bridge.v:152$5082 ($or). Removed top 24 bits (of 32) from port B of cell top.$flatten\soc_I.\bridge_I.$or$/build/gateware/common/rtl/soc_picorv32_bridge.v:152$5084 ($or). Removed top 3 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5088 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5089 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5090 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5091 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5092 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5093 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5094 ($eq). Removed top 3 bits (of 4) from port A of cell top.$flatten\soc_I.\cpu_I.$shl$/build/gateware/common/rtl/picorv32.v:403$3507 ($shl). Removed top 30 bits (of 32) from mux cell top.$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:601$3566 ($mux). Removed top 1 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:849$3585 ($eq). Removed top 2 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:850$3586 ($eq). Removed top 5 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:857$3600 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:858$3601 ($eq). Removed top 2 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:859$3602 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:860$3603 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1023$3659 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1031$3673 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1041$3689 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1048$3707 ($eq). Removed top 29 bits (of 32) from port B of cell top.$flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1296$3880 ($add). Removed top 29 bits (of 32) from port B of cell top.$flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1539$3957 ($add). Removed top 29 bits (of 32) from port B of cell top.$flatten\soc_I.\cpu_I.$ge$/build/gateware/common/rtl/picorv32.v:1814$4008 ($ge). Removed top 29 bits (of 32) from port B of cell top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4016 ($sub). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4016 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4023 ($sub). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4023 ($sub). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12382 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12385 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12649 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12651 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12656 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12706 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12726 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12749 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12776 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12778 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12789 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12791 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12802 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12804 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12882 ($mux). Removed top 3 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22923 ($eq). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13170 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13231 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13379 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13381 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13387 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13389 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13404 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13525 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14367 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14371 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14377 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\cpu_I.$procmux$14379_CMP0 ($eq). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14380 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14386 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14420 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14430 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14432 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14436 ($mux). Removed top 24 bits (of 32) from mux cell top.$flatten\soc_I.\cpu_I.$procmux$14663 ($pmux). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\cpu_I.$procmux$14666_CMP0 ($eq). Removed top 16 bits (of 32) from mux cell top.$flatten\soc_I.\cpu_I.$procmux$14672 ($pmux). Removed top 2 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22906 ($eq). Removed top 11 bits (of 31) from FF cell top.$auto$opt_dff.cc:764:run$23713 ($dffe). Removed top 25 bits (of 26) from port B of cell top.$flatten\misc_I.\dfu_I.$add$/build/gateware/common/rtl/dfu_helper.v:113$4087 ($add). Removed top 1 bits (of 4) from port B of cell top.$flatten\misc_I.$procmux$11407_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\misc_I.$procmux$11406_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\misc_I.$procmux$11405_CMP0 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\sys_mgr_I.$add$/build/gateware/e1-tracer/rtl/sysmgr.v:85$1592 ($add). Removed top 28 bits (of 32) from port Y of cell top.$flatten\sys_mgr_I.$add$/build/gateware/e1-tracer/rtl/sysmgr.v:85$1592 ($add). Removed top 1 bits (of 2) from port A of cell top.$flatten\soc_I.\e1_buf_I.$eq$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:233$4973 ($eq). Removed top 1 bits (of 2) from port A of cell top.$flatten\soc_I.\e1_buf_I.$eq$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:241$4976 ($eq). Removed top 1 bits (of 2) from port A of cell top.$flatten\soc_I.\e1_buf_I.$eq$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:241$4979 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$4990 ($shl). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$4991 ($shl). Removed top 2 bits (of 4) from port Y of cell top.$flatten\soc_I.\e1_buf_I.$or$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$4994 ($or). Removed top 2 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_buf_I.$or$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$4994 ($or). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\e1_buf_I.$or$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$4994 ($or). Removed top 2 bits (of 4) from port Y of cell top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$4991 ($shl). Removed top 2 bits (of 4) from port Y of cell top.$flatten\soc_I.\e1_buf_I.$and$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$4993 ($and). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\e1_buf_I.$and$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$4993 ($and). Removed top 2 bits (of 4) from port Y of cell top.$flatten\soc_I.\e1_buf_I.$not$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$4992 ($not). Removed top 2 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_buf_I.$not$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$4992 ($not). Removed top 2 bits (of 4) from port Y of cell top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$4990 ($shl). Removed top 24 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3312_EN[31:0]$3319. Removed top 16 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3313_DATA[31:0]$3321. Removed top 8 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3314_DATA[31:0]$3324. Removed top 8 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3314_EN[31:0]$3325. Removed top 24 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3312_DATA. Removed top 16 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3313_DATA. Removed top 8 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3314_DATA. Removed top 16 bits (of 32) from wire top.$flatten\soc_I.\cpu_I.$2\mem_rdata_word[31:0]. Removed top 24 bits (of 32) from wire top.$flatten\soc_I.\cpu_I.$3\mem_rdata_word[31:0]. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4016_Y. Removed top 29 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:208$31_Y. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:220$36_Y. Removed top 28 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:234$41_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:346$110_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:347$114_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:348$118_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:349$122_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$9_Y. Removed top 3 bits (of 16) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bus_rd_rx_status. Removed top 29 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:208$31_Y. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:220$36_Y. Removed top 28 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:234$41_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:346$110_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:347$114_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:348$118_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:349$122_Y. Removed top 25 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:265$53_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$9_Y. Removed top 3 bits (of 16) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bus_rd_rx_status. Removed top 2 bits (of 4) from wire top.$flatten\soc_I.\e1_buf_I.$and$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$4993_Y. Removed top 2 bits (of 4) from wire top.$flatten\soc_I.\e1_buf_I.$not$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$4992_Y. Removed top 2 bits (of 4) from wire top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$4990_Y. Removed top 18 bits (of 32) from wire top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$4779_Y. Removed top 23 bits (of 32) from wire top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$4783_Y. Removed top 19 bits (of 32) from wire top.$flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$4793_Y. Removed top 18 bits (of 32) from wire top.$flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:155$4781_Y. Removed top 20 bits (of 32) from wire top.$flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:176$4794_Y. Removed top 19 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5232_Y. Removed top 19 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5233_Y. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5236_Y. Removed top 23 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4522_Y. Removed top 1 bits (of 13) from wire top.$flatten\soc_I.\uart_I.\uart_tx_I.$0\div_cnt[12:0]. Removed top 1 bits (of 10) from wire top.$flatten\soc_I.\uart_I.\uart_tx_I.$procmux$5464_Y. Removed top 19 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5251_Y. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5254_Y. Removed top 23 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4522_Y. Removed top 23 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4520_Y. Removed top 3 bits (of 4) from wire top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11869_Y. Removed top 28 bits (of 32) from wire top.$flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1331_Y. Removed top 29 bits (of 32) from wire top.$flatten\soc_I.\usb_I.\rx_pkt_I.\crc_5_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4711_Y. Removed top 1 bits (of 4) from wire top.$flatten\soc_I.\usb_I.\trans_I.$procmux$11568_Y. Removed top 29 bits (of 32) from wire top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1501_Y. Removed top 29 bits (of 32) from wire top.$flatten\soc_I.\usb_I.\tx_ll_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1503_Y. Removed top 28 bits (of 32) from wire top.$flatten\sys_mgr_I.$add$/build/gateware/e1-tracer/rtl/sysmgr.v:85$1592_Y. Removed top 5 bits (of 32) from wire top.wb_rdata[0]. Removed top 24 bits (of 32) from wire top.wb_rdata[1]. Removed top 24 bits (of 64) from wire top.wb_rdata_flat. 73.14. Executing PEEPOPT pass (run peephole optimizers). 73.15. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 117 unused wires. 73.16. Executing SHARE pass (SAT-based resource sharing). 73.17. Executing TECHMAP pass (map to technology primitives). 73.17.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/cmp2lut.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 73.17.2. Continuing TECHMAP pass. No more expansions possible. 73.18. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.19. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 4 unused wires. 73.20. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module top: creating $macc model for $flatten\misc_I.\dfu_I.$add$/build/gateware/common/rtl/dfu_helper.v:113$4087 ($add). creating $macc model for $flatten\misc_I.\dfu_I.\btn_flt_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4724 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1219$4072 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1296$3880 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1539$3957 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1548$3958 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1785$4002 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1848$4027 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1219$4071 ($sub). creating $macc model for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4016 ($sub). creating $macc model for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4023 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:208$31 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:220$36 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:234$41 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:346$110 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:347$114 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:348$118 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:349$122 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:265$53 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:208$31 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:220$36 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:234$41 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:346$110 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:347$114 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:348$118 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:349$122 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:265$53 ($sub). creating $macc model for $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$4779 ($add). creating $macc model for $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$4783 ($add). creating $macc model for $flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$4793 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5232 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5233 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5236 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4491 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4522 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4505 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4520 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5251 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5254 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4522 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4505 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4520 ($add). creating $macc model for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:540$3261 ($add). creating $macc model for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:623$3242 ($add). creating $macc model for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:632$3246 ($add). creating $macc model for $flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1331 ($sub). creating $macc model for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:179$1411 ($add). creating $macc model for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:415$1472 ($add). creating $macc model for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:429$1481 ($add). creating $macc model for $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:258$1428 ($sub). creating $macc model for $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:425$1478 ($sub). creating $macc model for $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1497 ($add). creating $macc model for $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1501 ($add). creating $macc model for $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1540 ($sub). creating $macc model for $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1563 ($sub). creating $macc model for $flatten\sys_mgr_I.$add$/build/gateware/e1-tracer/rtl/sysmgr.v:85$1592 ($add). creating $alu model for $macc $flatten\sys_mgr_I.$add$/build/gateware/e1-tracer/rtl/sysmgr.v:85$1592. creating $alu model for $macc $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1563. creating $alu model for $macc $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1540. creating $alu model for $macc $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1501. creating $alu model for $macc $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1497. creating $alu model for $macc $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:425$1478. creating $alu model for $macc $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:258$1428. creating $alu model for $macc $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:429$1481. creating $alu model for $macc $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:415$1472. creating $alu model for $macc $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:179$1411. creating $alu model for $macc $flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1331. creating $alu model for $macc $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:632$3246. creating $alu model for $macc $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:623$3242. creating $alu model for $macc $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:540$3261. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4520. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4505. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4522. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5254. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5251. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4520. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4505. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4522. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4491. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5236. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5233. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5232. creating $alu model for $macc $flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$4793. creating $alu model for $macc $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$4783. creating $alu model for $macc $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$4779. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:265$53. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:349$122. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:348$118. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:347$114. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:346$110. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:234$41. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:220$36. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:208$31. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:265$53. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:349$122. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:348$118. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:347$114. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:346$110. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:234$41. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:220$36. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:208$31. creating $alu model for $macc $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4023. creating $alu model for $macc $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4016. creating $alu model for $macc $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1219$4071. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1848$4027. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1785$4002. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1548$3958. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1539$3957. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1296$3880. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1219$4072. creating $alu model for $macc $flatten\misc_I.\dfu_I.\btn_flt_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4724. creating $alu model for $macc $flatten\misc_I.\dfu_I.$add$/build/gateware/common/rtl/dfu_helper.v:113$4087. creating $alu model for $flatten\soc_I.\cpu_I.$ge$/build/gateware/common/rtl/picorv32.v:1814$4008 ($ge): new $alu creating $alu model for $flatten\soc_I.\cpu_I.$lt$/build/gateware/common/rtl/picorv32.v:1221$4075 ($lt): new $alu creating $alu model for $flatten\soc_I.\cpu_I.$lt$/build/gateware/common/rtl/picorv32.v:1222$4076 ($lt): new $alu creating $alu model for $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1220$4074 ($eq): merged with $flatten\soc_I.\cpu_I.$lt$/build/gateware/common/rtl/picorv32.v:1222$4076. creating $alu cell for $flatten\soc_I.\cpu_I.$ge$/build/gateware/common/rtl/picorv32.v:1814$4008: $auto$alumacc.cc:485:replace_alu$23978 creating $alu cell for $flatten\misc_I.\dfu_I.$add$/build/gateware/common/rtl/dfu_helper.v:113$4087: $auto$alumacc.cc:485:replace_alu$23987 creating $alu cell for $flatten\misc_I.\dfu_I.\btn_flt_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4724: $auto$alumacc.cc:485:replace_alu$23990 creating $alu cell for $flatten\soc_I.\cpu_I.$lt$/build/gateware/common/rtl/picorv32.v:1222$4076, $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1220$4074: $auto$alumacc.cc:485:replace_alu$23993 creating $alu cell for $flatten\soc_I.\cpu_I.$lt$/build/gateware/common/rtl/picorv32.v:1221$4075: $auto$alumacc.cc:485:replace_alu$24004 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1219$4072: $auto$alumacc.cc:485:replace_alu$24017 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1296$3880: $auto$alumacc.cc:485:replace_alu$24020 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1539$3957: $auto$alumacc.cc:485:replace_alu$24023 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1548$3958: $auto$alumacc.cc:485:replace_alu$24026 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1785$4002: $auto$alumacc.cc:485:replace_alu$24029 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1848$4027: $auto$alumacc.cc:485:replace_alu$24032 creating $alu cell for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1219$4071: $auto$alumacc.cc:485:replace_alu$24035 creating $alu cell for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4016: $auto$alumacc.cc:485:replace_alu$24038 creating $alu cell for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4023: $auto$alumacc.cc:485:replace_alu$24041 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:208$31: $auto$alumacc.cc:485:replace_alu$24044 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:220$36: $auto$alumacc.cc:485:replace_alu$24047 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:234$41: $auto$alumacc.cc:485:replace_alu$24050 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:346$110: $auto$alumacc.cc:485:replace_alu$24053 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:347$114: $auto$alumacc.cc:485:replace_alu$24056 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:348$118: $auto$alumacc.cc:485:replace_alu$24059 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:349$122: $auto$alumacc.cc:485:replace_alu$24062 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:265$53: $auto$alumacc.cc:485:replace_alu$24065 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:208$31: $auto$alumacc.cc:485:replace_alu$24068 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:220$36: $auto$alumacc.cc:485:replace_alu$24071 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:234$41: $auto$alumacc.cc:485:replace_alu$24074 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:346$110: $auto$alumacc.cc:485:replace_alu$24077 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:347$114: $auto$alumacc.cc:485:replace_alu$24080 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:348$118: $auto$alumacc.cc:485:replace_alu$24083 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:349$122: $auto$alumacc.cc:485:replace_alu$24086 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:265$53: $auto$alumacc.cc:485:replace_alu$24089 creating $alu cell for $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$4779: $auto$alumacc.cc:485:replace_alu$24092 creating $alu cell for $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$4783: $auto$alumacc.cc:485:replace_alu$24095 creating $alu cell for $flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$4793: $auto$alumacc.cc:485:replace_alu$24098 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5232: $auto$alumacc.cc:485:replace_alu$24101 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5233: $auto$alumacc.cc:485:replace_alu$24104 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5236: $auto$alumacc.cc:485:replace_alu$24107 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4491: $auto$alumacc.cc:485:replace_alu$24110 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4522: $auto$alumacc.cc:485:replace_alu$24113 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4505: $auto$alumacc.cc:485:replace_alu$24116 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4520: $auto$alumacc.cc:485:replace_alu$24119 creating $alu cell for $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5251: $auto$alumacc.cc:485:replace_alu$24122 creating $alu cell for $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5254: $auto$alumacc.cc:485:replace_alu$24125 creating $alu cell for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4522: $auto$alumacc.cc:485:replace_alu$24128 creating $alu cell for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4505: $auto$alumacc.cc:485:replace_alu$24131 creating $alu cell for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4520: $auto$alumacc.cc:485:replace_alu$24134 creating $alu cell for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:540$3261: $auto$alumacc.cc:485:replace_alu$24137 creating $alu cell for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:623$3242: $auto$alumacc.cc:485:replace_alu$24140 creating $alu cell for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:632$3246: $auto$alumacc.cc:485:replace_alu$24143 creating $alu cell for $flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1331: $auto$alumacc.cc:485:replace_alu$24146 creating $alu cell for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:179$1411: $auto$alumacc.cc:485:replace_alu$24149 creating $alu cell for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:415$1472: $auto$alumacc.cc:485:replace_alu$24152 creating $alu cell for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:429$1481: $auto$alumacc.cc:485:replace_alu$24155 creating $alu cell for $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:258$1428: $auto$alumacc.cc:485:replace_alu$24158 creating $alu cell for $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:425$1478: $auto$alumacc.cc:485:replace_alu$24161 creating $alu cell for $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1497: $auto$alumacc.cc:485:replace_alu$24164 creating $alu cell for $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1501: $auto$alumacc.cc:485:replace_alu$24167 creating $alu cell for $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1540: $auto$alumacc.cc:485:replace_alu$24170 creating $alu cell for $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1563: $auto$alumacc.cc:485:replace_alu$24173 creating $alu cell for $flatten\sys_mgr_I.$add$/build/gateware/e1-tracer/rtl/sysmgr.v:85$1592: $auto$alumacc.cc:485:replace_alu$24176 created 59 $alu and 0 $macc cells. 73.21. Executing OPT pass (performing simple optimizations). 73.21.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.21.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 4 cells. 73.21.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 73.21.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13383: { \soc_I.cpu_I.cpu_state [2] \soc_I.cpu_I.cpu_state [4] $auto$opt_reduce.cc:134:opt_mux$24180 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$14369: { $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:364$3475_Y $flatten\soc_I.\cpu_I.$procmux$14379_CMP $auto$opt_reduce.cc:134:opt_mux$24182 } Optimizing cells in module \top. Performed a total of 2 changes. 73.21.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 1 cells. 73.21.6. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 1-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Setting constant 1-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Setting constant 1-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Setting constant 1-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Setting constant 1-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Setting constant 1-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Setting constant 1-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Setting constant 1-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Setting constant 1-bit at position 8 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Setting constant 1-bit at position 9 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Setting constant 1-bit at position 10 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Setting constant 1-bit at position 11 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Setting constant 1-bit at position 12 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Setting constant 1-bit at position 13 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Setting constant 1-bit at position 14 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Setting constant 1-bit at position 15 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Setting constant 1-bit at position 16 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Setting constant 1-bit at position 17 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Setting constant 1-bit at position 18 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Setting constant 1-bit at position 19 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Setting constant 1-bit at position 20 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Setting constant 1-bit at position 21 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Setting constant 1-bit at position 22 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Setting constant 1-bit at position 23 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Setting constant 1-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$22576 ($dff) from module top. Setting constant 1-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$22576 ($dff) from module top. Setting constant 1-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$22576 ($dff) from module top. Setting constant 1-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$22576 ($dff) from module top. Setting constant 1-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$22576 ($dff) from module top. Setting constant 1-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$22576 ($dff) from module top. Setting constant 1-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$22576 ($dff) from module top. Setting constant 1-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$22576 ($dff) from module top. Setting constant 1-bit at position 8 on $flatten\soc_I.\bram_I.$procdff$22576 ($dff) from module top. Setting constant 1-bit at position 9 on $flatten\soc_I.\bram_I.$procdff$22576 ($dff) from module top. Setting constant 1-bit at position 10 on $flatten\soc_I.\bram_I.$procdff$22576 ($dff) from module top. Setting constant 1-bit at position 11 on $flatten\soc_I.\bram_I.$procdff$22576 ($dff) from module top. Setting constant 1-bit at position 12 on $flatten\soc_I.\bram_I.$procdff$22576 ($dff) from module top. Setting constant 1-bit at position 13 on $flatten\soc_I.\bram_I.$procdff$22576 ($dff) from module top. Setting constant 1-bit at position 14 on $flatten\soc_I.\bram_I.$procdff$22576 ($dff) from module top. Setting constant 1-bit at position 15 on $flatten\soc_I.\bram_I.$procdff$22576 ($dff) from module top. Setting constant 1-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$22573 ($dff) from module top. Setting constant 1-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$22573 ($dff) from module top. Setting constant 1-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$22573 ($dff) from module top. Setting constant 1-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$22573 ($dff) from module top. Setting constant 1-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$22573 ($dff) from module top. Setting constant 1-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$22573 ($dff) from module top. Setting constant 1-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$22573 ($dff) from module top. Setting constant 1-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$22573 ($dff) from module top. Adding SRST signal on $auto$opt_dff.cc:764:run$23691 ($dffe) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14422_Y, Q = \soc_I.cpu_I.mem_valid, rval = 1'0). Adding SRST signal on $auto$opt_dff.cc:764:run$23674 ($dffe) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14369_Y, Q = \soc_I.cpu_I.mem_state, rval = 2'00). Removing never-active SRST on $auto$opt_dff.cc:702:run$23485 ($sdffce) from module top. Removing never-active SRST on $auto$opt_dff.cc:702:run$23481 ($sdffce) from module top. Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$23442 ($sdff) from module top. Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$23442 ($sdff) from module top. Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$23442 ($sdff) from module top. Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$23442 ($sdff) from module top. Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$23442 ($sdff) from module top. Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$23442 ($sdff) from module top. Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$23442 ($sdff) from module top. Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$23442 ($sdff) from module top. Setting constant 0-bit at position 16 on $auto$opt_dff.cc:702:run$23442 ($sdff) from module top. Setting constant 0-bit at position 17 on $auto$opt_dff.cc:702:run$23442 ($sdff) from module top. Setting constant 0-bit at position 18 on $auto$opt_dff.cc:702:run$23442 ($sdff) from module top. Setting constant 0-bit at position 19 on $auto$opt_dff.cc:702:run$23442 ($sdff) from module top. Setting constant 0-bit at position 20 on $auto$opt_dff.cc:702:run$23442 ($sdff) from module top. Setting constant 0-bit at position 21 on $auto$opt_dff.cc:702:run$23442 ($sdff) from module top. Setting constant 0-bit at position 22 on $auto$opt_dff.cc:702:run$23442 ($sdff) from module top. Setting constant 0-bit at position 23 on $auto$opt_dff.cc:702:run$23442 ($sdff) from module top. 73.21.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 13 unused wires. 73.21.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.21.9. Rerunning OPT passes. (Maybe there is more to do..) 73.21.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 73.21.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 73.21.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.21.13. Executing OPT_DFF pass (perform DFF optimizations). 73.21.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 73.21.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.21.16. Finished OPT passes. (There is nothing left to do.) 73.22. Executing MEMORY pass. 73.22.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 73.22.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). Checking cell `$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3339' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3340' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3341' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3342' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5112' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5112' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\bram_I.$memrd$\mem$/build/gateware/common/rtl/soc_bram.v:32$3329' in module `\top': merged data $dff to cell. Checking cell `$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5111' in module `\top': merged data $dff to cell. Checking cell `$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5111' in module `\top': merged data $dff to cell. 73.22.3. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 18 unused cells and 21 unused wires. 73.22.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). Consolidating write ports of memory top.soc_I.bram_I.mem by address: New clock domain: posedge \misc_I.clk Port 0 ($flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3339) has addr \soc_I.cpu_I.mem_addr [9:2]. Active bits: 00000000000000000000000011111111 Port 1 ($flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3340) has addr \soc_I.cpu_I.mem_addr [9:2]. Active bits: 00000000000000001111111100000000 Merging port 0 into this one. Active bits: 00000000000000001111111111111111 Port 2 ($flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3341) has addr \soc_I.cpu_I.mem_addr [9:2]. Active bits: 00000000111111110000000000000000 Merging port 1 into this one. Active bits: 00000000111111111111111111111111 Port 3 ($flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3342) has addr \soc_I.cpu_I.mem_addr [9:2]. Active bits: 11111111000000000000000000000000 Merging port 2 into this one. Active bits: 11111111111111111111111111111111 73.22.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 73.22.6. Executing MEMORY_COLLECT pass (generating $mem cells). Collecting $memrd, $memwr and $meminit for memory `\soc_I.bram_I.mem' in module `\top': $flatten\soc_I.\bram_I.$meminit$\mem$/build/gateware/common/rtl/soc_bram.v:0$3338 ($meminit) $flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3342 ($memwr) $flatten\soc_I.\bram_I.$memrd$\mem$/build/gateware/common/rtl/soc_bram.v:32$3329 ($memrd) Collecting $memrd, $memwr and $meminit for memory `\soc_I.uart_I.uart_rx_fifo_I.ram_I.ram' in module `\top': $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5112 ($memwr) $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5111 ($memrd) Collecting $memrd, $memwr and $meminit for memory `\soc_I.uart_I.uart_tx_fifo_I.ram_I.ram' in module `\top': $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5112 ($memwr) $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5111 ($memrd) 73.23. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 73.24. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). Processing top.soc_I.bram_I.mem: Properties: ports=2 bits=8192 rports=1 wports=1 dbits=32 abits=8 words=256 Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=0 efficiency=100 Storing for later selection. Checking rule #2 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=256 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=768 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 2): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=3072 efficiency=25 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1792 dwaste=0 bwaste=3584 waste=3584 efficiency=12 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=3584 efficiency=12 Storing for later selection. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=256 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=768 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1792 dwaste=0 bwaste=3584 waste=3584 efficiency=12 Rule for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=256 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=768 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1792 dwaste=0 bwaste=3584 waste=3584 efficiency=12 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'max wports 0' not met. Selecting best of 4 rules: Efficiency for rule 4.3: efficiency=12, cells=16, acells=1 Efficiency for rule 4.2: efficiency=25, cells=8, acells=1 Efficiency for rule 4.1: efficiency=50, cells=4, acells=1 Efficiency for rule 1.1: efficiency=100, cells=2, acells=1 Selected rule 1.1 with efficiency 100. Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Creating $__ICE40_RAM4K_M0 cell at grid position <0 0 0>: soc_I.bram_I.mem.0.0.0 Creating $__ICE40_RAM4K_M0 cell at grid position <1 0 0>: soc_I.bram_I.mem.1.0.0 Processing top.soc_I.uart_I.uart_rx_fifo_I.ram_I.ram: Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512 Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #2 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=0 efficiency=100 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 2): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=3072 efficiency=25 Storing for later selection. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'max wports 0' not met. Selecting best of 4 rules: Efficiency for rule 4.3: efficiency=25, cells=4, acells=1 Efficiency for rule 4.2: efficiency=50, cells=2, acells=1 Efficiency for rule 4.1: efficiency=100, cells=1, acells=1 Efficiency for rule 1.1: efficiency=50, cells=2, acells=2 Selected rule 4.1 with efficiency 100. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Creating $__ICE40_RAM4K_M123 cell at grid position <0 0 0>: soc_I.uart_I.uart_rx_fifo_I.ram_I.ram.0.0.0 Processing top.soc_I.uart_I.uart_tx_fifo_I.ram_I.ram: Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512 Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #2 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=0 efficiency=100 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 2): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=3072 efficiency=25 Storing for later selection. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'max wports 0' not met. Selecting best of 4 rules: Efficiency for rule 4.3: efficiency=25, cells=4, acells=1 Efficiency for rule 4.2: efficiency=50, cells=2, acells=1 Efficiency for rule 4.1: efficiency=100, cells=1, acells=1 Efficiency for rule 1.1: efficiency=50, cells=2, acells=2 Selected rule 4.1 with efficiency 100. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Creating $__ICE40_RAM4K_M123 cell at grid position <0 0 0>: soc_I.uart_I.uart_tx_fifo_I.ram_I.ram.0.0.0 73.25. Executing TECHMAP pass (map to technology primitives). 73.25.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/brams_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ICE40_RAM4K'. Generating RTLIL representation for module `\$__ICE40_RAM4K_M0'. Generating RTLIL representation for module `\$__ICE40_RAM4K_M123'. Successfully finished Verilog frontend. 73.25.2. Continuing TECHMAP pass. Using template $paramod\$__ICE40_RAM4K_M123\CFG_ABITS=9\CFG_DBITS=8\CLKPOL2=1\CLKPOL3=1 for cells of type $__ICE40_RAM4K_M123. Using template $paramod$b9e8582c288289ac723b215129f56c6fb55d152a\$__ICE40_RAM4K_M0 for cells of type $__ICE40_RAM4K_M0. Using template $paramod$4db28c01ad2f8fb3d28d8b45acd344e29c76a5e2\$__ICE40_RAM4K_M0 for cells of type $__ICE40_RAM4K_M0. Using template $paramod$66c3fa288a62dc560ce3ddd26d81551ab195105f\$__ICE40_RAM4K for cells of type $__ICE40_RAM4K. Using template $paramod$604ec1e346c2dd44ad2f04f633da753d2abbf02c\$__ICE40_RAM4K for cells of type $__ICE40_RAM4K. Using template $paramod$7577afd8fd444532bbc3532c110d9d682708035f\$__ICE40_RAM4K for cells of type $__ICE40_RAM4K. No more expansions possible. 73.26. Executing ICE40_BRAMINIT pass. Processing soc_I.usb_I.trans_I.mc_rom_I : usb_trans_mc.hex 73.27. Executing OPT pass (performing simple optimizations). 73.27.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.27.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.27.3. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22404 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$0\reg_sh[4:0] [1:0], Q = \soc_I.cpu_I.reg_sh [1:0]). 73.27.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 38 unused cells and 196 unused wires. 73.27.5. Rerunning OPT passes. (Removed registers in this run.) 73.27.6. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.27.7. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.27.8. Executing OPT_DFF pass (perform DFF optimizations). 73.27.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 73.27.10. Finished fast OPT passes. 73.28. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). 73.29. Executing OPT pass (performing simple optimizations). 73.29.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.29.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.29.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 1/2 on $mux $flatten\soc_I.\e1_buf_I.$procmux$14812. dead port 1/2 on $mux $flatten\soc_I.\e1_buf_I.$procmux$14827. Removed 2 multiplexer ports. 73.29.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $techmap$techmap24206\soc_I.bram_I.mem.0.0.0.$reduce_or$/opt/fpga-toolchain/bin/../share/yosys/ice40/brams_map.v:222$24205: { $auto$wreduce.cc:454:run$23918 [7] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3313_EN[31:0]$3322 [15] } New input vector for $reduce_or cell $techmap$techmap24203\soc_I.bram_I.mem.1.0.0.$reduce_or$/opt/fpga-toolchain/bin/../share/yosys/ice40/brams_map.v:222$24202: { $auto$wreduce.cc:454:run$23921 [23] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3315_EN[31:0]$3328 [31] } Consolidated identical input bits for $mux cell $flatten\misc_I.\dfu_I.\btn_flt_I.$procmux$5402: Old ports: A=4'0000, B=4'1111, Y=$flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] New ports: A=1'0, B=1'1, Y=$flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] New connections: $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [3:1] = { $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] } Consolidated identical input bits for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12645: Old ports: A=\soc_I.cpu_I.mem_rdata_word, B={ \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15:0] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7:0] }, Y=$flatten\soc_I.\cpu_I.$procmux$12645_Y New ports: A=\soc_I.cpu_I.mem_rdata_word [31:8], B={ \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15:7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] }, Y=$flatten\soc_I.\cpu_I.$procmux$12645_Y [31:8] New connections: $flatten\soc_I.\cpu_I.$procmux$12645_Y [7:0] = \soc_I.cpu_I.mem_rdata_word [7:0] Consolidated identical input bits for $pmux cell $flatten\soc_I.\cpu_I.$procmux$14688: Old ports: A=\soc_I.cpu_I.reg_op2, B={ \soc_I.cpu_I.reg_op2 [15:0] \soc_I.cpu_I.reg_op2 [15:0] \soc_I.cpu_I.reg_op2 [7:0] \soc_I.cpu_I.reg_op2 [7:0] \soc_I.cpu_I.reg_op2 [7:0] \soc_I.cpu_I.reg_op2 [7:0] }, Y=\soc_I.cpu_I.mem_la_wdata New ports: A=\soc_I.cpu_I.reg_op2 [31:8], B={ \soc_I.cpu_I.reg_op2 [15:0] \soc_I.cpu_I.reg_op2 [15:0] \soc_I.cpu_I.reg_op2 [7:0] \soc_I.cpu_I.reg_op2 [7:0] }, Y=\soc_I.cpu_I.mem_la_wdata [31:8] New connections: \soc_I.cpu_I.mem_la_wdata [7:0] = \soc_I.cpu_I.reg_op2 [7:0] Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1192$3848: Old ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 2'00 }, B={ \soc_I.cpu_I.reg_out [31:1] 1'0 }, Y=\soc_I.cpu_I.next_pc New ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 1'0 }, B=\soc_I.cpu_I.reg_out [31:1], Y=\soc_I.cpu_I.next_pc [31:1] New connections: \soc_I.cpu_I.next_pc [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$3917: Old ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 2'00 }, B={ $auto$opt_expr.cc:205:group_cell_inputs$24271 1'0 }, Y=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$3917_Y New ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 1'0 }, B=$auto$opt_expr.cc:205:group_cell_inputs$24271, Y=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$3917_Y [31:1] New connections: $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$3917_Y [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1621$3970: Old ports: A={ \soc_I.cpu_I.reg_pc [31:2] 2'00 }, B=0, Y=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1621$3970_Y New ports: A=\soc_I.cpu_I.reg_pc [31:2], B=30'000000000000000000000000000000, Y=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1621$3970_Y [31:2] New connections: $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1621$3970_Y [1:0] = 2'00 Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:366$3491: Old ports: A={ \soc_I.cpu_I.reg_op1 [31:2] 2'00 }, B={ \soc_I.cpu_I.next_pc [31:2] 2'00 }, Y=\soc_I.cpu_I.mem_la_addr New ports: A=\soc_I.cpu_I.reg_op1 [31:2], B=\soc_I.cpu_I.next_pc [31:2], Y=\soc_I.cpu_I.mem_la_addr [31:2] New connections: \soc_I.cpu_I.mem_la_addr [1:0] = 2'00 Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3506: Old ports: A=4'0011, B=4'1100, Y=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3506_Y New ports: A=2'01, B=2'10, Y={ $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3506_Y [2] $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3506_Y [0] } New connections: { $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3506_Y [3] $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3506_Y [1] } = { $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3506_Y [2] $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3506_Y [0] } Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:601$3566: Old ports: A=2'11, B=2'00, Y=$flatten\soc_I.\cpu_I.$procmux$14375_Y New ports: A=1'1, B=1'0, Y=$flatten\soc_I.\cpu_I.$procmux$14375_Y [0] New connections: $flatten\soc_I.\cpu_I.$procmux$14375_Y [1] = $flatten\soc_I.\cpu_I.$procmux$14375_Y [0] Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5279: Old ports: A={ 3'000 $auto$wreduce.cc:454:run$23936 [12] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_out_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_out_I.rd_empty $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_in_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_in_I.rd_empty 6'000000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.aligned $auto$wreduce.cc:454:run$23936 [0] }, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_out_I.stage[1].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_out_I.data[1] [8:7] 6'000000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_out_I.data[1] [6:0] }, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5279_Y New ports: A={ 3'000 $auto$wreduce.cc:454:run$23936 [12] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_out_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_out_I.rd_empty $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_in_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_in_I.rd_empty 5'00000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.aligned $auto$wreduce.cc:454:run$23936 [0] }, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_out_I.stage[1].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_out_I.data[1] [8:7] 5'00000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.bd_rx_out_I.data[1] [6:0] }, Y={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5279_Y [15:8] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5279_Y [6:0] } New connections: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5279_Y [7] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.\rx_I.\deframer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$9: Old ports: A=2'00, B=2'11, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [1:0] New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [0] New connections: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [1] = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [0] Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5279: Old ports: A={ 3'000 $auto$wreduce.cc:454:run$23946 [12] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_out_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_out_I.rd_empty $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_in_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_in_I.rd_empty 6'000000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.aligned $auto$wreduce.cc:454:run$23946 [0] }, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_out_I.stage[1].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_out_I.data[1] [8:7] 6'000000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_out_I.data[1] [6:0] }, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5279_Y New ports: A={ 3'000 $auto$wreduce.cc:454:run$23946 [12] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_out_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_out_I.rd_empty $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_in_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_in_I.rd_empty 5'00000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.aligned $auto$wreduce.cc:454:run$23946 [0] }, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_out_I.stage[1].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_out_I.data[1] [8:7] 5'00000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.bd_rx_out_I.data[1] [6:0] }, Y={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5279_Y [15:8] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5279_Y [6:0] } New connections: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5279_Y [7] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.\rx_I.\deframer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$9: Old ports: A=2'00, B=2'11, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [1:0] New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [0] New connections: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [1] = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [0] Consolidated identical input bits for $mux cell $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:115$4761: Old ports: A=2'10, B=2'00, Y=$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5373_Y New ports: A=1'1, B=1'0, Y=$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5373_Y [1] New connections: $flatten\soc_I.\iobuf_I.\dma_I.$procmux$5373_Y [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:205$4811: Old ports: A=16'0000000000000000, B={ \soc_I.iobuf_I.dma_I.state [1] \soc_I.iobuf_I.dma_I.dir 1'0 \soc_I.iobuf_I.dma_I.len }, Y=\soc_I.iobuf_I.wb_rdata_dma [15:0] New ports: A=15'000000000000000, B={ \soc_I.iobuf_I.dma_I.state [1] \soc_I.iobuf_I.dma_I.dir \soc_I.iobuf_I.dma_I.len }, Y={ \soc_I.iobuf_I.wb_rdata_dma [15:14] \soc_I.iobuf_I.wb_rdata_dma [12:0] } New connections: \soc_I.iobuf_I.wb_rdata_dma [13] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$4879: Old ports: A=0, B={ \soc_I.e1_buf_I.wb_wdata_byte \soc_I.e1_buf_I.wb_wdata_byte \soc_I.e1_buf_I.wb_wdata_byte \soc_I.e1_buf_I.wb_wdata_byte }, Y=$flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$4879_Y New ports: A=8'00000000, B=\soc_I.e1_buf_I.wb_wdata_byte, Y=$flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$4879_Y [7:0] New connections: $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$4879_Y [31:8] = { $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$4879_Y [7:0] $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$4879_Y [7:0] $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$4879_Y [7:0] } Consolidated identical input bits for $mux cell $flatten\soc_I.\uart_I.\uart_tx_I.$procmux$5467: Old ports: A={ 1'1 \soc_I.uart_I.uart_tx_I.shift [9:1] }, B={ 1'1 \soc_I.uart_I.uart_tx_fifo_I.ram_I.rd_data 1'0 }, Y=$flatten\soc_I.\uart_I.\uart_tx_I.$0\shift[9:0] New ports: A=\soc_I.uart_I.uart_tx_I.shift [9:1], B={ \soc_I.uart_I.uart_tx_fifo_I.ram_I.rd_data 1'0 }, Y=$flatten\soc_I.\uart_I.\uart_tx_I.$0\shift[9:0] [8:0] New connections: $flatten\soc_I.\uart_I.\uart_tx_I.$0\shift[9:0] [9] = 1'1 Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\rx_pkt_I.\crc_16_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4698: Old ports: A=16'0000000000000000, B=16'1000000000000101, Y=\soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux New ports: A=1'0, B=1'1, Y=\soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux [0] New connections: \soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux [15:1] = { \soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux [0] 12'000000000000 \soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\rx_pkt_I.\crc_5_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4711: Old ports: A=3'000, B=3'101, Y=\soc_I.usb_I.rx_pkt_I.crc_5_I.state_upd_mux [2:0] New ports: A=1'0, B=1'1, Y=\soc_I.usb_I.rx_pkt_I.crc_5_I.state_upd_mux [0] New connections: \soc_I.usb_I.rx_pkt_I.crc_5_I.state_upd_mux [2:1] = { \soc_I.usb_I.rx_pkt_I.crc_5_I.state_upd_mux [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$procmux$11568: Old ports: A=3'000, B=3'110, Y=$auto$wreduce.cc:454:run$23968 [2:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:454:run$23968 [1] New connections: { $auto$wreduce.cc:454:run$23968 [2] $auto$wreduce.cc:454:run$23968 [0] } = { $auto$wreduce.cc:454:run$23968 [1] 1'0 } Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$procmux$11571: Old ports: A={ 1'0 $auto$wreduce.cc:454:run$23968 [2:0] }, B=4'0100, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11571_Y New ports: A=$auto$wreduce.cc:454:run$23968 [2:0], B=3'100, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11571_Y [2:0] New connections: $flatten\soc_I.\usb_I.\trans_I.$procmux$11571_Y [3] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_trans.v:340$1442: Old ports: A={ 8'00000000 \soc_I.usb_I.trans_I.ep_data_toggle \soc_I.usb_I.trans_I.ep_bd_idx_nxt \soc_I.usb_I.trans_I.ep_bd_ctrl \soc_I.usb_I.trans_I.ep_bd_dual 1'0 \soc_I.usb_I.trans_I.ep_type }, B={ \soc_I.usb_I.trans_I.bd_state \soc_I.usb_I.trans_I.trans_is_setup 2'00 \soc_I.usb_I.trans_I.xfer_length }, Y=\soc_I.usb_I.ep_status_I.p_din_0 New ports: A={ 6'000000 \soc_I.usb_I.trans_I.ep_data_toggle \soc_I.usb_I.trans_I.ep_bd_idx_nxt \soc_I.usb_I.trans_I.ep_bd_ctrl \soc_I.usb_I.trans_I.ep_bd_dual 1'0 \soc_I.usb_I.trans_I.ep_type }, B={ \soc_I.usb_I.trans_I.bd_state \soc_I.usb_I.trans_I.trans_is_setup \soc_I.usb_I.trans_I.xfer_length }, Y={ \soc_I.usb_I.ep_status_I.p_din_0 [15:12] \soc_I.usb_I.ep_status_I.p_din_0 [9:0] } New connections: \soc_I.usb_I.ep_status_I.p_din_0 [11:10] = 2'00 Consolidated identical input bits for $pmux cell $flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11519: Old ports: A=3'000, B=6'110111, Y=$flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11519_Y New ports: A=2'00, B=4'1011, Y=$flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11519_Y [1:0] New connections: $flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11519_Y [2] = $flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11519_Y [1] Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\tx_pkt_I.\crc_16_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4698: Old ports: A=16'0000000000000000, B=16'1000000000000101, Y=\soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux New ports: A=1'0, B=1'1, Y=\soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux [0] New connections: \soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux [15:1] = { \soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux [0] 12'000000000000 \soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux [0] 1'0 } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\misc_I.\dfu_I.\btn_flt_I.$procmux$5408: Old ports: A=$flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0], B=4'0001, Y=\misc_I.dfu_I.btn_flt_I.cnt_move New ports: A={ $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] }, B=2'01, Y=\misc_I.dfu_I.btn_flt_I.cnt_move [1:0] New connections: \misc_I.dfu_I.btn_flt_I.cnt_move [3:2] = { \misc_I.dfu_I.btn_flt_I.cnt_move [1] \misc_I.dfu_I.btn_flt_I.cnt_move [1] } Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$procmux$12379: Old ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 2'00 }, B=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$3917_Y, Y={ $flatten\soc_I.\cpu_I.$3\current_pc[31:0] [31:2] $auto$alumacc.cc:501:replace_alu$24024 [1:0] } New ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 1'0 }, B=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$3917_Y [31:1], Y={ $flatten\soc_I.\cpu_I.$3\current_pc[31:0] [31:2] $auto$alumacc.cc:501:replace_alu$24024 [1] } New connections: $auto$alumacc.cc:501:replace_alu$24024 [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5280: Old ports: A=16'0000000000000000, B=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5279_Y, Y=\soc_I.e1_I.bus_rdata_rx[0] New ports: A=15'000000000000000, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5279_Y [15:8] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5015[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5279_Y [6:0] }, Y={ \soc_I.e1_I.bus_rdata_rx[0] [15:8] \soc_I.e1_I.bus_rdata_rx[0] [6:0] } New connections: \soc_I.e1_I.bus_rdata_rx[0] [7] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5280: Old ports: A=16'0000000000000000, B=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5279_Y, Y=\soc_I.e1_I.bus_rdata_rx[1] New ports: A=15'000000000000000, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5279_Y [15:8] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5016[1].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5279_Y [6:0] }, Y={ \soc_I.e1_I.bus_rdata_rx[1] [15:8] \soc_I.e1_I.bus_rdata_rx[1] [6:0] } New connections: \soc_I.e1_I.bus_rdata_rx[1] [7] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$procmux$11571: Old ports: A=$auto$wreduce.cc:454:run$23968 [2:0], B=3'100, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11571_Y [2:0] New ports: A={ $auto$wreduce.cc:454:run$23968 [1] $auto$wreduce.cc:454:run$23968 [1] }, B=2'10, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11571_Y [2:1] New connections: $flatten\soc_I.\usb_I.\trans_I.$procmux$11571_Y [0] = 1'0 Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$procmux$11574: Old ports: A=$flatten\soc_I.\usb_I.\trans_I.$procmux$11571_Y, B=4'1000, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11574_Y New ports: A={ 1'0 $flatten\soc_I.\usb_I.\trans_I.$procmux$11571_Y [2:1] }, B=3'100, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11574_Y [3:1] New connections: $flatten\soc_I.\usb_I.\trans_I.$procmux$11574_Y [0] = 1'0 Optimizing cells in module \top. Performed a total of 32 changes. 73.29.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.29.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$22355 ($dff) from module top (D = \soc_I.cpu_I.mem_wdata [11:10], Q = \soc_I.usb_I.ep_status_I.din_1 [11:10], rval = 2'00). 73.29.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 2 unused wires. 73.29.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.29.9. Rerunning OPT passes. (Maybe there is more to do..) 73.29.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 73.29.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 73.29.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.29.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$23696 ($dffe) from module top. Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$23696 ($dffe) from module top. Setting constant 1-bit at position 9 on $auto$opt_dff.cc:764:run$23424 ($adffe) from module top. 73.29.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 10 unused wires. 73.29.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.29.16. Rerunning OPT passes. (Maybe there is more to do..) 73.29.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 73.29.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 73.29.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.29.20. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$23490 ($sdff) from module top. 73.29.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 73.29.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.29.23. Rerunning OPT passes. (Maybe there is more to do..) 73.29.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 73.29.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 73.29.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.29.27. Executing OPT_DFF pass (perform DFF optimizations). 73.29.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 2 unused wires. 73.29.29. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.29.30. Rerunning OPT passes. (Maybe there is more to do..) 73.29.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 73.29.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 73.29.33. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.29.34. Executing OPT_DFF pass (perform DFF optimizations). 73.29.35. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 73.29.36. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.29.37. Finished OPT passes. (There is nothing left to do.) 73.30. Executing ICE40_WRAPCARRY pass (wrap carries). 73.31. Executing TECHMAP pass (map to technology primitives). 73.31.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/techmap.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 73.31.2. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ice40_alu'. Successfully finished Verilog frontend. 73.31.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $xor. Using extmapper simplemap for cells of type $sdffe. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $reduce_bool. Using extmapper simplemap for cells of type $ne. Using extmapper simplemap for cells of type $sdff. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $dffe. Using extmapper simplemap for cells of type $sdffce. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $adffe. Using extmapper simplemap for cells of type $adff. Using extmapper simplemap for cells of type $mux. Using template $paramod$constmap:a4d8bd4c83ae7aadb9a39a6a6c198c7f62a08526$paramod$39430ff77e1846062046cba1eb3ce5685e03f0fe\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=7\B_WIDTH=1\Y_WIDTH=7 for cells of type $alu. Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu. Using extmapper simplemap for cells of type $logic_and. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=3\Y_WIDTH=3 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=14\Y_WIDTH=14 for cells of type $alu. Using template $paramod\_90_pmux\WIDTH=2\S_WIDTH=3 for cells of type $pmux. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=11\B_WIDTH=1\Y_WIDTH=12 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=13\B_WIDTH=1\Y_WIDTH=13 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=9\Y_WIDTH=9 for cells of type $alu. Using extmapper simplemap for cells of type $reduce_xor. Using extmapper simplemap for cells of type $logic_or. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=20\Y_WIDTH=20 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=1\Y_WIDTH=4 for cells of type $alu. Using template $paramod\_90_pmux\WIDTH=16\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=5 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=2\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=1\Y_WIDTH=4 for cells of type $alu. Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=4 for cells of type $pmux. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=11\B_WIDTH=1\Y_WIDTH=11 for cells of type $alu. Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=6 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=3 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=8 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=6 for cells of type $pmux. Using extmapper simplemap for cells of type $reduce_xnor. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=8\Y_WIDTH=8 for cells of type $alu. Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=3 for cells of type $pmux. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=9\B_WIDTH=1\Y_WIDTH=9 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=2\Y_WIDTH=3 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=10\Y_WIDTH=10 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=11\Y_WIDTH=11 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=1\Y_WIDTH=5 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=10\B_WIDTH=10\Y_WIDTH=10 for cells of type $alu. Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu. Using template $paramod$constmap:66d421c313e4e958be776b99540ac2de3b59fdbc$paramod$9b74a473ccd678a23e1df4cc12019cbbece20051\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=30\Y_WIDTH=30 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=31\B_WIDTH=31\Y_WIDTH=31 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=30\B_WIDTH=30\Y_WIDTH=30 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=26\Y_WIDTH=26 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=1\Y_WIDTH=3 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=1\B_SIGNED=1\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu. Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=3 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=24\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=5 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=4 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=5 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu. Using extmapper simplemap for cells of type $pos. Using template $paramod\_90_lcu\WIDTH=2 for cells of type $lcu. No more expansions possible. 73.32. Executing OPT pass (performing simple optimizations). 73.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 1198 cells. 73.32.3. Executing OPT_DFF pass (perform DFF optimizations). 73.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 587 unused cells and 3850 unused wires. 73.32.5. Finished fast OPT passes. 73.33. Executing ICE40_OPT pass (performing simple optimizations). 73.33.1. Running ICE40 specific optimizations. Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$23978.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$23978.BB [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24020.slice[0].carry: CO=\soc_I.cpu_I.reg_pc [2] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24023.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24023.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24038.slice[0].carry: CO=\soc_I.cpu_I.reg_sh [2] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24041.slice[0].carry: CO=\soc_I.cpu_I.reg_sh [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24044.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24044.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24047.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24047.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24050.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24050.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24065.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24065.A [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24068.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24068.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24071.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24071.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24074.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24074.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24089.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24089.A [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24092.slice[0].carry: CO=\soc_I.iobuf_I.dma_I.m0_addr_i [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24095.slice[0].carry: CO=\soc_I.iobuf_I.dma_I.m1_addr_i [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24098.slice[0].carry: CO=\soc_I.iobuf_I.dma_I.len [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24101.slice[0].carry: CO=\soc_I.uart_I.uart_div [1] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24101.slice[11].carry: CO=$auto$alumacc.cc:485:replace_alu$24101.C [11] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24104.slice[0].carry: CO=\soc_I.uart_I.uart_rx_I.div_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24107.slice[0].carry: CO=\soc_I.uart_I.uart_rx_I.bit_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24113.slice[0].carry: CO=\soc_I.uart_I.uart_rx_fifo_I.ram_rd_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24119.slice[0].carry: CO=\soc_I.uart_I.uart_rx_fifo_I.ram_wr_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24122.slice[0].carry: CO=\soc_I.uart_I.uart_tx_I.div_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24125.slice[0].carry: CO=\soc_I.uart_I.uart_tx_I.bit_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24128.slice[0].carry: CO=\soc_I.uart_I.uart_tx_fifo_I.ram_rd_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24134.slice[0].carry: CO=\soc_I.uart_I.uart_tx_fifo_I.ram_wr_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24146.slice[0].carry: CO=\soc_I.usb_I.rx_pkt_I.bit_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24146.slice[3].carry: CO=$auto$alumacc.cc:485:replace_alu$24146.C [3] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24149.slice[0].carry: CO=\soc_I.usb_I.trans_I.mc_pc [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24164.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24164.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24164.slice[2].carry: CO=1'0 Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24167.slice[0].carry: CO=\soc_I.usb_I.tx_ll_I.bs_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24170.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24170.A [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24173.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24173.A [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24176.slice[0].carry: CO=\sys_mgr_I.rst_cnt [0] 73.33.2. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.33.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.33.4. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$29513 ($_SDFFCE_PP0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11854.B_AND_S [3], Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [3], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$29512 ($_SDFFCE_PP0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11854.Y_B [2], Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [2], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$29511 ($_SDFFCE_PP0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11854.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [1], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$29509 ($_SDFFCE_PN0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11871.B_AND_S [3], Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1 [3], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$29508 ($_SDFFCE_PN0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11871.Y_B [2], Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1 [2], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$29507 ($_SDFFCE_PN0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11871.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1 [1], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$33930 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11404.B_AND_S [31], Q = \misc_I.wb_rdata [31], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$33929 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11404.B_AND_S [30], Q = \misc_I.wb_rdata [30], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$33928 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11404.B_AND_S [29], Q = \misc_I.wb_rdata [29], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$33927 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11404.B_AND_S [28], Q = \misc_I.wb_rdata [28], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$33926 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11404.B_AND_S [27], Q = \misc_I.wb_rdata [27], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$33925 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11404.B_AND_S [26], Q = \misc_I.wb_rdata [26], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$33924 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11404.B_AND_S [25], Q = \misc_I.wb_rdata [25], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$33923 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11404.B_AND_S [24], Q = \misc_I.wb_rdata [24], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$33922 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11404.B_AND_S [23], Q = \misc_I.wb_rdata [23], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$33921 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11404.B_AND_S [22], Q = \misc_I.wb_rdata [22], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$33920 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11404.B_AND_S [21], Q = \misc_I.wb_rdata [21], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$33919 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11404.B_AND_S [20], Q = \misc_I.wb_rdata [20], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$33918 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11404.B_AND_S [19], Q = \misc_I.wb_rdata [19], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$33917 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11404.B_AND_S [18], Q = \misc_I.wb_rdata [18], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$33916 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11404.B_AND_S [17], Q = \misc_I.wb_rdata [17], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$33915 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11404.B_AND_S [16], Q = \misc_I.wb_rdata [16], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$30111 ($_SDFF_PP0_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11897.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.samp_cnt [1], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33731 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824.Y_B [31], Q = \soc_I.cpu_I.decoded_imm [31], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33730 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824.Y_B [30], Q = \soc_I.cpu_I.decoded_imm [30], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33729 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824.Y_B [29], Q = \soc_I.cpu_I.decoded_imm [29], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33728 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824.Y_B [28], Q = \soc_I.cpu_I.decoded_imm [28], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33727 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824.Y_B [27], Q = \soc_I.cpu_I.decoded_imm [27], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33726 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824.Y_B [26], Q = \soc_I.cpu_I.decoded_imm [26], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33725 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824.Y_B [25], Q = \soc_I.cpu_I.decoded_imm [25], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33724 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824.Y_B [24], Q = \soc_I.cpu_I.decoded_imm [24], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33723 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824.Y_B [23], Q = \soc_I.cpu_I.decoded_imm [23], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33722 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824.Y_B [22], Q = \soc_I.cpu_I.decoded_imm [22], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33721 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824.Y_B [21], Q = \soc_I.cpu_I.decoded_imm [21], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33720 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824.Y_B [20], Q = \soc_I.cpu_I.decoded_imm [20], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33719 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824.Y_B [19], Q = \soc_I.cpu_I.decoded_imm [19], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33718 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824.Y_B [18], Q = \soc_I.cpu_I.decoded_imm [18], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33717 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824.Y_B [17], Q = \soc_I.cpu_I.decoded_imm [17], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33716 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824.Y_B [16], Q = \soc_I.cpu_I.decoded_imm [16], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33715 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824.Y_B [15], Q = \soc_I.cpu_I.decoded_imm [15], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33714 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824.Y_B [14], Q = \soc_I.cpu_I.decoded_imm [14], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33713 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824.Y_B [13], Q = \soc_I.cpu_I.decoded_imm [13], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33712 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824.Y_B [12], Q = \soc_I.cpu_I.decoded_imm [12], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33711 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824.Y_B [11], Q = \soc_I.cpu_I.decoded_imm [11], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33710 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824.Y_B [10], Q = \soc_I.cpu_I.decoded_imm [10], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33709 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824.Y_B [9], Q = \soc_I.cpu_I.decoded_imm [9], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33708 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824.Y_B [8], Q = \soc_I.cpu_I.decoded_imm [8], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33707 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824.Y_B [7], Q = \soc_I.cpu_I.decoded_imm [7], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33706 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824.Y_B [6], Q = \soc_I.cpu_I.decoded_imm [6], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33705 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824.Y_B [5], Q = \soc_I.cpu_I.decoded_imm [5], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33704 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824.Y_B [4], Q = \soc_I.cpu_I.decoded_imm [4], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33703 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824.Y_B [3], Q = \soc_I.cpu_I.decoded_imm [3], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33702 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824.Y_B [2], Q = \soc_I.cpu_I.decoded_imm [2], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33701 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13824.Y_B [1], Q = \soc_I.cpu_I.decoded_imm [1], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$29503 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11886.B_AND_S [2], Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [2], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$29502 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11886.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [1], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$29501 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11886.Y_B [0], Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [0], rval = 1'0). 73.33.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 58 unused cells and 27 unused wires. 73.33.6. Rerunning OPT passes. (Removed registers in this run.) 73.33.7. Running ICE40 specific optimizations. 73.33.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.33.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 36 cells. 73.33.10. Executing OPT_DFF pass (perform DFF optimizations). 73.33.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 36 unused wires. 73.33.12. Rerunning OPT passes. (Removed registers in this run.) 73.33.13. Running ICE40 specific optimizations. 73.33.14. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.33.15. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.33.16. Executing OPT_DFF pass (perform DFF optimizations). 73.33.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 73.33.18. Finished OPT passes. (There is nothing left to do.) 73.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 73.35. Executing TECHMAP pass (map to technology primitives). 73.35.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. Successfully finished Verilog frontend. 73.35.2. Continuing TECHMAP pass. Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_. Using template \$_DFF_P_ for cells of type $_DFF_P_. Using template \$_SDFFCE_PP0P_ for cells of type $_SDFFCE_PP0P_. Using template \$_SDFFCE_PP1P_ for cells of type $_SDFFCE_PP1P_. Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_. Using template \$_DFF_PP0_ for cells of type $_DFF_PP0_. Using template \$_DFFE_PP0P_ for cells of type $_DFFE_PP0P_. Using template \$_DFF_PP1_ for cells of type $_DFF_PP1_. Using template \$_DFFE_PP1P_ for cells of type $_DFFE_PP1P_. No more expansions possible. 73.36. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). Mapping top.$auto$alumacc.cc:485:replace_alu$24020.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24023.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24038.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24041.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24044.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24047.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24050.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24065.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24068.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24071.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24074.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24089.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24092.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24095.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24098.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24101.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24101.slice[11].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24104.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24107.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24113.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24119.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24122.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24125.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24128.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24134.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24146.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24146.slice[3].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24149.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24164.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24164.slice[2].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24167.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24170.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24173.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24176.slice[0].carry ($lut). 73.38. Executing ICE40_OPT pass (performing simple optimizations). 73.38.1. Running ICE40 specific optimizations. 73.38.2. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.38.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 440 cells. 73.38.4. Executing OPT_DFF pass (perform DFF optimizations). 73.38.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 9856 unused wires. 73.38.6. Rerunning OPT passes. (Removed registers in this run.) 73.38.7. Running ICE40 specific optimizations. 73.38.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.38.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.38.10. Executing OPT_DFF pass (perform DFF optimizations). 73.38.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 73.38.12. Finished OPT passes. (There is nothing left to do.) 73.39. Executing TECHMAP pass (map to technology primitives). 73.39.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/latches_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/latches_map.v' to AST representation. Generating RTLIL representation for module `\$_DLATCH_N_'. Generating RTLIL representation for module `\$_DLATCH_P_'. Successfully finished Verilog frontend. 73.39.2. Continuing TECHMAP pass. No more expansions possible. 73.40. Executing ABC pass (technology mapping using ABC). 73.40.1. Extracting gate netlist of module `\top' to `/input.blif'.. Extracted 5822 gates and 7936 wires to a netlist network with 2112 inputs and 1574 outputs. 73.40.1.1. Executing ABC. Running ABC command: /yosys-abc -s -f /abc.script 2>&1 ABC: ABC command line: "source /abc.script". ABC: ABC: + read_blif /input.blif ABC: + read_lut /lutdefs.txt ABC: + strash ABC: + ifraig ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + strash ABC: + dch -f ABC: + if ABC: + mfs2 ABC: + lutpack -S 1 ABC: + dress ABC: Total number of equiv classes = 1961. ABC: Participating nodes from both networks = 4117. ABC: Participating nodes from the first network = 1970. ( 78.11 % of nodes) ABC: Participating nodes from the second network = 2147. ( 85.13 % of nodes) ABC: Node pairs (any polarity) = 1970. ( 78.11 % of names can be moved) ABC: Node pairs (same polarity) = 1691. ( 67.05 % of names can be moved) ABC: Total runtime = 0.08 sec ABC: + write_blif /output.blif 73.40.1.2. Re-integrating ABC results. ABC RESULTS: $lut cells: 2521 ABC RESULTS: internal signals: 4250 ABC RESULTS: input signals: 2112 ABC RESULTS: output signals: 1574 Removing temp directory. 73.41. Executing ICE40_WRAPCARRY pass (wrap carries). 73.42. Executing TECHMAP pass (map to technology primitives). 73.42.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. Successfully finished Verilog frontend. 73.42.2. Continuing TECHMAP pass. No more expansions possible. Removed 112 unused cells and 5236 unused wires. 73.43. Executing OPT_LUT pass (optimize LUTs). Discovering LUTs. Number of LUTs: 3007 1-LUT 121 2-LUT 762 3-LUT 1047 4-LUT 1077 Eliminating LUTs. Number of LUTs: 3007 1-LUT 121 2-LUT 762 3-LUT 1047 4-LUT 1077 Combining LUTs. Number of LUTs: 2824 1-LUT 120 2-LUT 548 3-LUT 937 4-LUT 1219 Eliminated 0 LUTs. Combined 183 LUTs. 73.44. Executing TECHMAP pass (map to technology primitives). 73.44.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v' to AST representation. Generating RTLIL representation for module `\$lut'. Successfully finished Verilog frontend. 73.44.2. Continuing TECHMAP pass. Using template $paramod\$lut\WIDTH=2\LUT=4'0001 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'0100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'1000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100101000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011010111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0110100110010110 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00110101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101110011001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111010001000111 for cells of type $lut. Using template $paramod\$lut\WIDTH=1\LUT=2'01 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101110111011 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011110011001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011111110011111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1001011001101001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011101100001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00000111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0010111111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000110011001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110101100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'1011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111001111110101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011000010111011 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100011101110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00010100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000011101110111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110000011101110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000011100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111100000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111110111011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000110000001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'1110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101001111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00001011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11101111 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'0110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010101010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100111000001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101011111100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100111110100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111110000001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011110011111010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111111111110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101000001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100101011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000010111011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000010001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001001100111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000010111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100001101010001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000100011110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010110000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000001110111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10101100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000001001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000001100000101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110111000001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1001011010010110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011001100110101 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011101111110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10111100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0110000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111111110 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'0111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011010100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01010011 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01001011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000111111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111011111110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00011111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11000101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111110011111010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011101011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000110000000101 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11101000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101111100001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111100011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'1001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111110000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111010001000100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000011111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000011111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100010111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111100010001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101001100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111000001110111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00001101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000111110001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1101000000110011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111110110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111001011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000011100001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011101111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010110011001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00111010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010110010100011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000001000100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011110010101010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000001100001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111001111111010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100111101000100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100111110110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011101000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111010100110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011101001000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000011111001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001111101 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11100111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100010011110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111011001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11111110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101001100110011 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01011100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000010001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100101110110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111110010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100000011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00001110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011101100110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010010111110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00011000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0110000000001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111010111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110110000110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011101110110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001010000101000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000110100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111010000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111011101110 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11010100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11110001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000110000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111010000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100000000000010 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10110010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110101110111110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010001111001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011011100110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010101011000011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010001000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111111110000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001010000010100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000101110111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110111111000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100000011001110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101001101011100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101110001010011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100110101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1001110010011100 for cells of type $lut. No more expansions possible. Removed 0 unused cells and 5999 unused wires. 73.45. Executing AUTONAME pass. Renamed 147974 objects in module top (106 iterations). 73.46. Executing HIERARCHY pass (managing design hierarchy). 73.46.1. Analyzing design hierarchy.. Top module: \top 73.46.2. Analyzing design hierarchy.. Top module: \top Removed 0 unused modules. 73.47. Printing statistics. === top === Number of wires: 3132 Number of wire bits: 16115 Number of public wires: 3132 Number of public wire bits: 16115 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 5237 SB_CARRY 545 SB_DFF 201 SB_DFFE 535 SB_DFFER 295 SB_DFFES 10 SB_DFFESR 192 SB_DFFESS 56 SB_DFFR 141 SB_DFFS 29 SB_DFFSR 302 SB_DFFSS 28 SB_GB 1 SB_GB_IO 1 SB_IO 13 SB_LEDDA_IP 1 SB_LUT4 2857 SB_MAC16 3 SB_PLL40_2F_CORE 1 SB_RAM40_4K 14 SB_RAM40_4KNR 4 SB_RGBA_DRV 1 SB_SPI 2 SB_SPRAM256KA 4 SB_WARMBOOT 1 73.48. Executing CHECK pass (checking for obvious problems). checking module top.. found and reported 0 problems. 73.49. Executing JSON backend. Warnings: 9 unique messages, 15 total End of script. Logfile hash: 1c4af7748e, CPU: user 18.44s system 0.14s, MEM: 281.14 MB peak Yosys 0.9+3568 (open-tool-forge build) (git sha1 859e52af, gcc 9.3.0-10ubuntu2 -Os) Time spent: 21% 33x opt_expr (4 sec), 18% 31x opt_clean (3 sec), ... nextpnr-ice40 --no-promote-globals --pre-pack data/clocks.py --seed 19 --timing-allow-fail \ --up5k --package sg48 \ -l /build/gateware/e1-tracer/build-tmp/e1-tracer.pnr.rpt \ --json /build/gateware/e1-tracer/build-tmp/e1-tracer.json \ --pcf /build/gateware/e1-tracer/data/top-e1-tracer.pcf \ --asc /build/gateware/e1-tracer/build-tmp/e1-tracer.asc Info: constrained 'e1A_rx_data' to bel 'X7/Y0/io1' Info: constrained 'e1A_rx_clk' to bel 'X6/Y0/io1' Info: constrained 'e1B_rx_data' to bel 'X6/Y0/io0' Info: constrained 'e1B_rx_clk' to bel 'X5/Y0/io0' Info: constrained 'liu_mosi' to bel 'X16/Y31/io1' Info: constrained 'liu_miso' to bel 'X16/Y31/io0' Info: constrained 'liu_clk' to bel 'X13/Y31/io1' Info: constrained 'liu_cs_n[0]' to bel 'X8/Y31/io0' Info: constrained 'liu_cs_n[1]' to bel 'X9/Y31/io0' Info: constrained 'usb_dp' to bel 'X16/Y0/io0' Info: constrained 'usb_dn' to bel 'X15/Y0/io0' Info: constrained 'usb_pu' to bel 'X13/Y0/io1' Info: constrained 'flash_mosi' to bel 'X23/Y0/io0' Info: constrained 'flash_miso' to bel 'X23/Y0/io1' Info: constrained 'flash_clk' to bel 'X24/Y0/io0' Info: constrained 'flash_cs_n' to bel 'X24/Y0/io1' Info: constrained 'vio_pdm' to bel 'X21/Y0/io1' Info: constrained 'btn' to bel 'X19/Y31/io1' Info: constrained 'clk_in' to bel 'X19/Y0/io1' Info: constrained 'dbg_tx' to bel 'X8/Y31/io1' Info: constrained 'rgb[0]' to bel 'X4/Y31/io0' Info: constrained 'rgb[1]' to bel 'X5/Y31/io0' Info: constrained 'rgb[2]' to bel 'X6/Y31/io0' Info: constraining clock net 'clk_sys' to 24.00 MHz Info: constraining clock net 'clk_48m' to 48.00 MHz Info: Packing constants.. Info: Packing IOs.. Info: btn feeds SB_IO misc_I.dfu_I.btn_iob_I, removing $nextpnr_ibuf btn. Info: clk_in feeds SB_IO sys_mgr_I.gb_in, removing $nextpnr_ibuf clk_in. Info: e1A_rx_clk feeds SB_IO e1A_rx_clk_SB_IO_PACKAGE_PIN, removing $nextpnr_ibuf e1A_rx_clk. Info: e1A_rx_data feeds SB_IO e1A_rx_data_SB_IO_PACKAGE_PIN, removing $nextpnr_ibuf e1A_rx_data. Info: e1B_rx_clk feeds SB_IO e1B_rx_clk_SB_IO_PACKAGE_PIN, removing $nextpnr_ibuf e1B_rx_clk. Info: e1B_rx_data feeds SB_IO e1B_rx_data_SB_IO_PACKAGE_PIN, removing $nextpnr_ibuf e1B_rx_data. Info: flash_clk feeds SB_IO spi_io_I[0], removing $nextpnr_iobuf flash_clk. Info: flash_miso feeds SB_IO spi_io_I[1], removing $nextpnr_iobuf flash_miso. Info: flash_mosi feeds SB_IO spi_io_I[2], removing $nextpnr_iobuf flash_mosi. Info: liu_clk feeds SB_IO spi_I.spi_io_I[0], removing $nextpnr_iobuf liu_clk. Info: liu_miso feeds SB_IO spi_I.spi_io_I[1], removing $nextpnr_iobuf liu_miso. Info: liu_mosi feeds SB_IO spi_I.spi_io_I[2], removing $nextpnr_iobuf liu_mosi. Info: usb_dn feeds SB_IO soc_I.usb_I.phy_I.io_dn_I, removing $nextpnr_iobuf usb_dn. Info: usb_dp feeds SB_IO soc_I.usb_I.phy_I.io_dp_I, removing $nextpnr_iobuf usb_dp. Info: rgb[0] use by SB_RGBA_DRV/SB_RGB_DRV soc_I.rgb_I.rgb_drv_I, not creating SB_IO Info: rgb[1] use by SB_RGBA_DRV/SB_RGB_DRV soc_I.rgb_I.rgb_drv_I, not creating SB_IO Info: rgb[2] use by SB_RGBA_DRV/SB_RGB_DRV soc_I.rgb_I.rgb_drv_I, not creating SB_IO Info: Packing LUT-FFs.. Info: 1538 LCs used as LUT4 only Info: 1319 LCs used as LUT4 and DFF Info: Packing non-LUT FFs.. Info: 470 LCs used as DFF only Info: Packing carries.. Info: 221 LCs used as CARRY only Info: Packing RAMs.. Info: Placing PLLs.. Info: constrained PLL 'sys_mgr_I.pll_I' to X12/Y31/pll_3 Info: Packing special functions.. Info: constrained SB_LEDDA_IP 'soc_I.rgb_I.led_I' to X0/Y31/ledda_ip_2 Info: constrained SB_RGBA_DRV 'soc_I.rgb_I.rgb_drv_I' to X0/Y30/rgba_drv_0 Info: constrained SB_SPI 'soc_I.spi_I.spi_I' to X0/Y0/spi_0 Info: constrained SB_SPI 'spi_I.spi_I' to X25/Y0/spi_1 Info: PLL 'sys_mgr_I.pll_I' has LOCK output, need to pass all outputs via LUT Info: constrained 'sys_mgr_I.pll_lock_SB_LUT4_I3_LC' to X1/Y30/lc0 Info: Constraining chains... Info: 162 LCs used to legalise carry chains. Info: Checksum: 0x8dafe541 Info: Annotating ports with timing budgets for target frequency 12.00 MHz Info: Checksum: 0x13b31195 Info: Device utilisation: Info: ICESTORM_LC: 3712/ 5280 70% Info: ICESTORM_RAM: 18/ 30 60% Info: SB_IO: 20/ 96 20% Info: SB_GB: 4/ 8 50% Info: ICESTORM_PLL: 1/ 1 100% Info: SB_WARMBOOT: 1/ 1 100% Info: ICESTORM_DSP: 3/ 8 37% Info: ICESTORM_HFOSC: 0/ 1 0% Info: ICESTORM_LFOSC: 0/ 1 0% Info: SB_I2C: 0/ 2 0% Info: SB_SPI: 2/ 2 100% Info: IO_I3C: 0/ 2 0% Info: SB_LEDDA_IP: 1/ 1 100% Info: SB_RGBA_DRV: 1/ 1 100% Info: ICESTORM_SPRAM: 4/ 4 100% Info: Placed 29 cells based on constraints. Info: Creating initial analytic placement for 3034 cells, random placement wirelen = 93517. Info: at initial placer iter 0, wirelen = 3459 Info: at initial placer iter 1, wirelen = 3443 Info: at initial placer iter 2, wirelen = 3482 Info: at initial placer iter 3, wirelen = 3448 Info: Running main analytical placer. Info: at iteration #1, type ALL: wirelen solved = 3484, spread = 33030, legal = 45699; time = 0.15s Info: at iteration #2, type ALL: wirelen solved = 4435, spread = 31099, legal = 43776; time = 0.17s Info: at iteration #3, type ALL: wirelen solved = 5727, spread = 29312, legal = 43001; time = 0.13s Info: at iteration #4, type ALL: wirelen solved = 6495, spread = 29388, legal = 41069; time = 0.12s Info: at iteration #5, type ALL: wirelen solved = 7205, spread = 28882, legal = 39333; time = 0.10s Info: at iteration #6, type ALL: wirelen solved = 7555, spread = 27297, legal = 38991; time = 0.11s Info: at iteration #7, type ALL: wirelen solved = 8148, spread = 27646, legal = 38459; time = 0.12s Info: at iteration #8, type ALL: wirelen solved = 8805, spread = 27301, legal = 38247; time = 0.13s Info: at iteration #9, type ALL: wirelen solved = 9225, spread = 26239, legal = 38119; time = 0.11s Info: at iteration #10, type ALL: wirelen solved = 9828, spread = 25279, legal = 38191; time = 0.10s Info: at iteration #11, type ALL: wirelen solved = 10230, spread = 24862, legal = 36347; time = 0.11s Info: at iteration #12, type ALL: wirelen solved = 11275, spread = 24345, legal = 36118; time = 0.10s Info: at iteration #13, type ALL: wirelen solved = 11735, spread = 24406, legal = 37211; time = 0.10s Info: at iteration #14, type ALL: wirelen solved = 12128, spread = 24335, legal = 34953; time = 0.10s Info: at iteration #15, type ALL: wirelen solved = 12677, spread = 24444, legal = 34456; time = 0.11s Info: at iteration #16, type ALL: wirelen solved = 13717, spread = 24139, legal = 33819; time = 0.10s Info: at iteration #17, type ALL: wirelen solved = 13944, spread = 23488, legal = 32365; time = 0.09s Info: at iteration #18, type ALL: wirelen solved = 14482, spread = 23812, legal = 36150; time = 0.10s Info: at iteration #19, type ALL: wirelen solved = 14395, spread = 24389, legal = 36617; time = 0.10s Info: at iteration #20, type ALL: wirelen solved = 14506, spread = 24377, legal = 33895; time = 0.09s Info: at iteration #21, type ALL: wirelen solved = 15899, spread = 23907, legal = 34334; time = 0.09s Info: at iteration #22, type ALL: wirelen solved = 15248, spread = 24234, legal = 35471; time = 0.09s Info: HeAP Placer Time: 2.97s Info: of which solving equations: 1.05s Info: of which spreading cells: 0.21s Info: of which strict legalisation: 1.16s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 477, wirelen = 32365 Info: at iteration #5: temp = 0.000000, timing cost = 303, wirelen = 27831 Info: at iteration #10: temp = 0.000000, timing cost = 281, wirelen = 26568 Info: at iteration #15: temp = 0.000000, timing cost = 260, wirelen = 25781 Info: at iteration #20: temp = 0.000000, timing cost = 262, wirelen = 25424 Info: at iteration #25: temp = 0.000000, timing cost = 263, wirelen = 25359 Info: at iteration #30: temp = 0.000000, timing cost = 262, wirelen = 25325 Info: at iteration #32: temp = 0.000000, timing cost = 262, wirelen = 25323 Info: SA placement time 3.60s Info: Max frequency for clock 'clk_sys': 31.40 MHz (PASS at 24.00 MHz) Info: Max frequency for clock 'clk_48m': 52.63 MHz (PASS at 48.00 MHz) Info: Max delay -> posedge clk_sys: 9.50 ns Info: Max delay posedge clk_48m -> : 3.15 ns Info: Max delay posedge clk_48m -> posedge clk_sys: 6.32 ns Info: Max delay posedge clk_sys -> : 10.15 ns Info: Max delay posedge clk_sys -> posedge clk_48m: 16.10 ns Info: Slack histogram: Info: legend: * represents 34 endpoint(s) Info: + represents [1,34) endpoint(s) Info: [ 1833, 5751) |*+ Info: [ 5751, 9669) |****+ Info: [ 9669, 13587) |************+ Info: [ 13587, 17505) |******************************+ Info: [ 17505, 21423) |******+ Info: [ 21423, 25341) |************+ Info: [ 25341, 29259) |***************************+ Info: [ 29259, 33177) |***************************************+ Info: [ 33177, 37095) |************************************************************ Info: [ 37095, 41013) |**********************+ Info: [ 41013, 44931) | Info: [ 44931, 48849) | Info: [ 48849, 52767) | Info: [ 52767, 56685) | Info: [ 56685, 60603) | Info: [ 60603, 64521) | Info: [ 64521, 68439) | Info: [ 68439, 72357) | Info: [ 72357, 76275) |+ Info: [ 76275, 80193) |+ Info: Checksum: 0x1df68b05 Info: Routing.. Info: Setting up routing queue. Info: Routing 12756 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 1000 | 27 972 | 27 972 | 11785| 0.07 0.07| Info: 2000 | 67 1932 | 40 960 | 10828| 0.11 0.18| Info: 3000 | 170 2829 | 103 897 | 9952| 0.19 0.37| Info: 4000 | 309 3690 | 139 861 | 9163| 0.22 0.59| Info: 5000 | 536 4463 | 227 773 | 8509| 0.23 0.83| Info: 6000 | 724 5275 | 188 812 | 7784| 0.21 1.04| Info: 7000 | 1035 5964 | 311 689 | 7296| 0.45 1.48| Info: 8000 | 1405 6594 | 370 630 | 6874| 0.55 2.03| Info: 9000 | 1742 7257 | 337 663 | 6405| 0.49 2.52| Info: 10000 | 2154 7845 | 412 588 | 6100| 0.77 3.29| Info: 11000 | 2714 8285 | 560 440 | 5966| 0.72 4.01| Info: 12000 | 3182 8817 | 468 532 | 5754| 0.80 4.82| Info: 13000 | 3633 9366 | 451 549 | 5496| 0.66 5.47| Info: 14000 | 4143 9856 | 510 490 | 5338| 0.63 6.11| Info: 15000 | 4606 10393 | 463 537 | 5165| 0.56 6.67| Info: 16000 | 5075 10924 | 469 531 | 4925| 0.67 7.34| Info: 17000 | 5587 11412 | 512 488 | 4777| 0.91 8.25| Info: 18000 | 6099 11900 | 512 488 | 4602| 0.81 9.05| Info: 19000 | 6587 12412 | 488 512 | 4425| 0.77 9.82| Info: 20000 | 7107 12892 | 520 480 | 4253| 0.77 10.59| Info: 21000 | 7550 13449 | 443 557 | 4004| 0.62 11.21| Info: 22000 | 8056 13943 | 506 494 | 3761| 0.63 11.84| Info: 23000 | 8522 14477 | 466 534 | 3491| 0.77 12.61| Info: 24000 | 9069 14930 | 547 453 | 3393| 0.88 13.49| Info: 25000 | 9644 15355 | 575 425 | 3345| 1.56 15.04| Info: 26000 | 10216 15783 | 572 428 | 3276| 1.13 16.17| Info: 27000 | 10818 16181 | 602 398 | 3232| 0.92 17.08| Info: 28000 | 11346 16653 | 528 472 | 3172| 0.71 17.80| Info: 29000 | 11911 17088 | 565 435 | 3086| 0.77 18.57| Info: 30000 | 12390 17609 | 479 521 | 2979| 0.71 19.28| Info: 31000 | 12935 18064 | 545 455 | 2944| 1.05 20.33| Info: 32000 | 13474 18525 | 539 461 | 2879| 1.02 21.35| Info: 33000 | 14015 18984 | 541 459 | 2841| 1.17 22.52| Info: 34000 | 14544 19455 | 529 471 | 2745| 1.00 23.51| Info: 35000 | 15121 19878 | 577 423 | 2733| 0.71 24.22| Info: 36000 | 15696 20303 | 575 425 | 2646| 0.71 24.93| Info: 37000 | 16268 20731 | 572 428 | 2632| 0.94 25.87| Info: 38000 | 16836 21163 | 568 432 | 2583| 1.12 26.99| Info: 39000 | 17398 21601 | 562 438 | 2540| 0.99 27.98| Info: 40000 | 17907 22092 | 509 491 | 2419| 1.09 29.07| Info: 41000 | 18507 22492 | 600 400 | 2341| 0.84 29.91| Info: 42000 | 19112 22887 | 605 395 | 2356| 0.67 30.58| Info: 43000 | 19725 23274 | 613 387 | 2343| 1.19 31.78| Info: 44000 | 20289 23710 | 564 436 | 2276| 1.08 32.86| Info: 45000 | 20889 24110 | 600 400 | 2194| 1.26 34.12| Info: 46000 | 21511 24488 | 622 378 | 2175| 0.85 34.97| Info: 47000 | 22133 24866 | 622 378 | 2138| 0.86 35.82| Info: 48000 | 22786 25213 | 653 347 | 2132| 0.83 36.65| Info: 49000 | 23406 25593 | 620 380 | 2080| 1.11 37.77| Info: 50000 | 23950 26049 | 544 456 | 2036| 1.44 39.21| Info: 51000 | 24591 26408 | 641 359 | 1971| 1.25 40.46| Info: 52000 | 25130 26869 | 539 461 | 1934| 0.94 41.39| Info: 53000 | 25704 27295 | 574 426 | 1860| 0.96 42.36| Info: 54000 | 26305 27694 | 601 399 | 1725| 0.84 43.20| Info: 55000 | 26719 28280 | 414 586 | 1283| 0.60 43.80| Info: 56000 | 27133 28866 | 414 586 | 875| 2.33 46.13| Info: 57000 | 27707 29292 | 574 426 | 855| 1.26 47.39| Info: 58000 | 28243 29756 | 536 464 | 604| 1.66 49.05| Info: 59000 | 28647 30352 | 404 596 | 178| 0.88 49.93| Info: 59183 | 28651 30532 | 4 180 | 0| 0.07 50.00| Info: Routing complete. Info: Router1 time 50.00s Info: Checksum: 0x691df3de Info: Critical path report for clock 'clk_sys' (posedge -> posedge): Info: curr total Info: 1.4 1.4 Source soc_I.cpu_I.latched_is_lh_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_LUT4_O_5_LC.O Info: 2.4 3.8 Net soc_I.cpu_I.reg_out[1] budget 3.189000 ns (9,28) -> (9,27) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_O_LC.I1 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:160.52-160.59 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: 1.2 5.0 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_O_LC.O Info: 5.3 10.4 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2[0] budget 3.746000 ns (9,27) -> (4,16) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_LC.I1 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 1.2 11.6 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_LC.O Info: 1.8 13.4 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O[0] budget 2.756000 ns (4,16) -> (4,17) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0$CARRY.I1 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:29.22-29.23 Info: 0.7 14.0 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0$CARRY.COUT Info: 0.0 14.0 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[1] budget 0.000000 ns (4,17) -> (4,17) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_19_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 14.3 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_19_LC.COUT Info: 0.0 14.3 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[2] budget 0.000000 ns (4,17) -> (4,17) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_8_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 14.6 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_8_LC.COUT Info: 0.0 14.6 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[3] budget 0.000000 ns (4,17) -> (4,17) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_6_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 14.9 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_6_LC.COUT Info: 0.0 14.9 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[4] budget 0.000000 ns (4,17) -> (4,17) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_5_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 15.1 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_5_LC.COUT Info: 0.0 15.1 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[5] budget 0.000000 ns (4,17) -> (4,17) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_4_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 15.4 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_4_LC.COUT Info: 0.0 15.4 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[6] budget 0.000000 ns (4,17) -> (4,17) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_3_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 15.7 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_3_LC.COUT Info: 0.0 15.7 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[7] budget 0.000000 ns (4,17) -> (4,17) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_2_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 16.0 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_2_LC.COUT Info: 0.6 16.5 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[8] budget 0.560000 ns (4,17) -> (4,18) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_1_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 16.8 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_1_LC.COUT Info: 0.0 16.8 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[9] budget 0.000000 ns (4,18) -> (4,18) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 17.1 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_LC.COUT Info: 0.0 17.1 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[10] budget 0.000000 ns (4,18) -> (4,18) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_29_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 17.4 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_29_LC.COUT Info: 0.0 17.4 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[11] budget 0.000000 ns (4,18) -> (4,18) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_28_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 17.6 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_28_LC.COUT Info: 0.0 17.6 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[12] budget 0.000000 ns (4,18) -> (4,18) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_27_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 17.9 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_27_LC.COUT Info: 0.0 17.9 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[13] budget 0.000000 ns (4,18) -> (4,18) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_26_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 18.2 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_26_LC.COUT Info: 0.0 18.2 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[14] budget 0.000000 ns (4,18) -> (4,18) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_25_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 18.5 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_25_LC.COUT Info: 0.0 18.5 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[15] budget 0.000000 ns (4,18) -> (4,18) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_24_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 18.8 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_24_LC.COUT Info: 0.6 19.3 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[16] budget 0.560000 ns (4,18) -> (4,19) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_23_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 19.6 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_23_LC.COUT Info: 0.0 19.6 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[17] budget 0.000000 ns (4,19) -> (4,19) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_22_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 19.9 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_22_LC.COUT Info: 0.0 19.9 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[18] budget 0.000000 ns (4,19) -> (4,19) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_21_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 20.1 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_21_LC.COUT Info: 0.0 20.1 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[19] budget 0.000000 ns (4,19) -> (4,19) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_20_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 20.4 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_20_LC.COUT Info: 0.0 20.4 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[20] budget 0.000000 ns (4,19) -> (4,19) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_18_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 20.7 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_18_LC.COUT Info: 0.0 20.7 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[21] budget 0.000000 ns (4,19) -> (4,19) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_17_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 21.0 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_17_LC.COUT Info: 0.0 21.0 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[22] budget 0.000000 ns (4,19) -> (4,19) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_16_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 21.3 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_16_LC.COUT Info: 0.0 21.3 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[23] budget 0.000000 ns (4,19) -> (4,19) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_15_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 21.5 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_15_LC.COUT Info: 0.6 22.1 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[24] budget 0.560000 ns (4,19) -> (4,20) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_14_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 22.4 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_14_LC.COUT Info: 0.0 22.4 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[25] budget 0.000000 ns (4,20) -> (4,20) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_13_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 22.6 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_13_LC.COUT Info: 0.0 22.6 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[26] budget 0.000000 ns (4,20) -> (4,20) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_12_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 22.9 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_12_LC.COUT Info: 0.0 22.9 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[27] budget 0.000000 ns (4,20) -> (4,20) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_11_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 23.2 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_11_LC.COUT Info: 0.0 23.2 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[28] budget 0.000000 ns (4,20) -> (4,20) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_10_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 23.5 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_10_LC.COUT Info: 0.0 23.5 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[29] budget 0.000000 ns (4,20) -> (4,20) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_9_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 23.8 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_9_LC.COUT Info: 0.7 24.4 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[30] budget 0.660000 ns (4,20) -> (4,20) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_7_LC.I3 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.9 25.3 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_7_LC.O Info: 3.0 28.2 Net soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_29_D_SB_LUT4_O_I0[30] budget 4.011000 ns (4,20) -> (1,24) Info: Sink soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_LC.I0 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:33.26-33.27 Info: 1.3 29.5 Source soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_LC.O Info: 3.0 32.5 Net soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_D_SB_LUT4_O_I1[0] budget 3.613000 ns (1,24) -> (3,21) Info: Sink soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_D_SB_LUT4_O_LC.I1 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 1.2 33.7 Setup soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_D_SB_LUT4_O_LC.I1 Info: 15.9 ns logic, 17.7 ns routing Info: Critical path report for clock 'clk_48m' (posedge -> posedge): Info: curr total Info: 1.4 1.4 Source soc_I.usb_I.trans_I.trans_cel_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_LC.O Info: 2.4 3.8 Net soc_I.usb_I.trans_I.mc_a_reg[0] budget 1.459000 ns (17,10) -> (18,9) Info: Sink soc_I.usb_I.trans_I.mc_match_bits_SB_LUT4_O_3_LC.I2 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:82.14-82.22 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: 1.2 5.0 Source soc_I.usb_I.trans_I.mc_match_bits_SB_LUT4_O_3_LC.O Info: 1.8 6.8 Net soc_I.usb_I.trans_I.mc_match_bits[0] budget 1.126000 ns (18,9) -> (17,10) Info: Sink soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_I0_SB_LUT4_O_LC.I0 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:85.32-85.45 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: 1.3 8.0 Source soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_I0_SB_LUT4_O_LC.O Info: 1.8 9.8 Net soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_I0[0] budget 1.313000 ns (17,10) -> (17,11) Info: Sink soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_LC.I0 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 1.3 11.1 Source soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_LC.O Info: 1.8 12.9 Net soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_O[0] budget 1.269000 ns (17,11) -> (18,10) Info: Sink soc_I.usb_I.trans_I.mc_pc_SB_LUT4_O_7_LC.I2 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 1.2 14.1 Source soc_I.usb_I.trans_I.mc_pc_SB_LUT4_O_7_LC.O Info: 1.8 15.8 Net soc_I.usb_I.trans_I.mc_pc[0] budget 1.126000 ns (18,10) -> (18,11) Info: Sink $nextpnr_ICESTORM_LC_148.I1 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.7 16.5 Source $nextpnr_ICESTORM_LC_148.COUT Info: 0.0 16.5 Net $nextpnr_ICESTORM_LC_148$O budget 0.000000 ns (18,11) -> (18,11) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_6_LC.CIN Info: 0.3 16.8 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_6_LC.COUT Info: 0.0 16.8 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[2] budget 0.000000 ns (18,11) -> (18,11) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_5_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 17.1 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_5_LC.COUT Info: 0.0 17.1 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[3] budget 0.000000 ns (18,11) -> (18,11) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_4_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 17.3 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_4_LC.COUT Info: 0.0 17.3 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[4] budget 0.000000 ns (18,11) -> (18,11) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_3_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 17.6 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_3_LC.COUT Info: 0.0 17.6 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[5] budget 0.000000 ns (18,11) -> (18,11) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_2_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 17.9 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_2_LC.COUT Info: 0.0 17.9 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[6] budget 0.000000 ns (18,11) -> (18,11) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_1_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 18.2 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_1_LC.COUT Info: 0.7 18.8 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[7] budget 0.660000 ns (18,11) -> (18,11) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_LC.I3 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.8 19.6 Setup soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_LC.I3 Info: 9.5 ns logic, 10.1 ns routing Info: Critical path report for cross-domain path '' -> 'posedge clk_sys': Info: curr total Info: 0.0 0.0 Source spi_io_I[2].D_IN_0 Info: 8.8 8.8 Net flash_mosi_i budget 40.166000 ns (23,0) -> (0,0) Info: Sink soc_I.spi_I.spi_I.SI Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2ice40//rtl/ice40_spi_wb.v:30.21-30.31 Info: /build/gateware/common/rtl/soc_base.v:304.4-324.3 Info: 1.5 10.3 Setup soc_I.spi_I.spi_I.SI Info: 1.5 ns logic, 8.8 ns routing Info: Critical path report for cross-domain path 'posedge clk_48m' -> '': Info: curr total Info: 1.4 1.4 Source soc_I.usb_I.pad_pu_SB_DFFSR_Q_DFFLC.O Info: 1.8 3.2 Net usb_pu$SB_IO_OUT budget 81.943001 ns (14,1) -> (13,0) Info: Sink usb_pu$sb_io.D_OUT_0 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:33.14-33.20 Info: 1.4 ns logic, 1.8 ns routing Info: Critical path report for cross-domain path 'posedge clk_48m' -> 'posedge clk_sys': Info: curr total Info: 1.4 1.4 Source soc_I.wb_48m_xclk_I.m_rdata_SB_LUT4_O_2_LC.O Info: 3.6 5.0 Net soc_I.wb_48m_xclk_I.m_rdata_i[13] budget 39.042000 ns (13,13) -> (18,18) Info: Sink soc_I.wb_48m_xclk_I.s_rdata_SB_DFFSR_Q_2_DFFLC.I0 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2misc//rtl/xclk_wb.v:53.15-53.24 Info: /build/gateware/common/rtl/soc_base.v:400.4-416.3 Info: 1.2 6.2 Setup soc_I.wb_48m_xclk_I.s_rdata_SB_DFFSR_Q_2_DFFLC.I0 Info: 2.6 ns logic, 3.6 ns routing Info: Critical path report for cross-domain path 'posedge clk_sys' -> '': Info: curr total Info: 1.5 1.5 Source soc_I.spi_I.spi_I.SO Info: 8.2 9.7 Net flash_miso_o budget 81.833000 ns (0,0) -> (23,0) Info: Sink spi_io_I[1].D_OUT_0 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2ice40//rtl/ice40_spi_wb.v:35.21-35.31 Info: /build/gateware/common/rtl/soc_base.v:304.4-324.3 Info: 1.5 ns logic, 8.2 ns routing Info: Critical path report for cross-domain path 'posedge clk_sys' -> 'posedge clk_48m': Info: curr total Info: 1.4 1.4 Source soc_I.cpu_I.mem_wstrb_SB_DFFE_Q_3_D_SB_LUT4_O_LC.O Info: 1.8 3.2 Net wb_wmsk[0] budget 2.754000 ns (14,26) -> (15,25) Info: Sink misc_I.wb_we_SB_LUT4_O_LC.I0 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:75.18-75.25 Info: 1.3 4.4 Source misc_I.wb_we_SB_LUT4_O_LC.O Info: 2.4 6.8 Net wb_we budget 3.874000 ns (15,25) -> (16,24) Info: Sink soc_I.wb_48m_xclk_I.m_ack_SB_LUT4_O_LC.I1 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:76.18-76.23 Info: 1.2 8.1 Source soc_I.wb_48m_xclk_I.m_ack_SB_LUT4_O_LC.O Info: 5.6 13.7 Net soc_I.ub_ack budget 5.257000 ns (16,24) -> (14,6) Info: Sink soc_I.wb_48m_xclk_I.xclk_ack.src_SB_LUT4_I3_LC.I2 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2misc//rtl/xclk_wb.v:107.14-113.3 Info: /build/gateware/cores/no2misc//rtl/xclk_strobe.v:18.14-18.20 Info: /build/gateware/common/rtl/soc_base.v:400.4-416.3 Info: 1.2 14.8 Setup soc_I.wb_48m_xclk_I.xclk_ack.src_SB_LUT4_I3_LC.I2 Info: 5.1 ns logic, 9.8 ns routing Info: Max frequency for clock 'clk_sys': 29.70 MHz (PASS at 24.00 MHz) Info: Max frequency for clock 'clk_48m': 50.90 MHz (PASS at 48.00 MHz) Info: Max delay -> posedge clk_sys: 10.33 ns Info: Max delay posedge clk_48m -> : 3.15 ns Info: Max delay posedge clk_48m -> posedge clk_sys: 6.22 ns Info: Max delay posedge clk_sys -> : 9.74 ns Info: Max delay posedge clk_sys -> posedge clk_48m: 14.84 ns Info: Slack histogram: Info: legend: * represents 35 endpoint(s) Info: + represents [1,35) endpoint(s) Info: [ 1185, 5135) |+ Info: [ 5135, 9085) |***+ Info: [ 9085, 13035) |*************+ Info: [ 13035, 16985) |*******************************+ Info: [ 16985, 20935) |*****+ Info: [ 20935, 24885) |***********+ Info: [ 24885, 28835) |****************+ Info: [ 28835, 32785) |*********************************************+ Info: [ 32785, 36735) |************************************************************ Info: [ 36735, 40685) |***********************+ Info: [ 40685, 44635) | Info: [ 44635, 48585) | Info: [ 48585, 52535) | Info: [ 52535, 56485) | Info: [ 56485, 60435) | Info: [ 60435, 64385) | Info: [ 64385, 68335) | Info: [ 68335, 72285) | Info: [ 72285, 76235) |+ Info: [ 76235, 80185) |+ icepack -s /build/gateware/e1-tracer/build-tmp/e1-tracer.asc /build/gateware/e1-tracer/build-tmp/e1-tracer.bin make: Leaving directory '/build/gateware/e1-tracer' =============== gateware/icE1usb GATEWARE ============== make: Entering directory '/build/gateware/icE1usb' make: Leaving directory '/build/gateware/icE1usb' make: Entering directory '/build/gateware/icE1usb' /build/gateware/cores/no2usb//utils/microcode.py > /build/gateware/icE1usb/build-tmp/usb_trans_mc.hex cp -a /build/gateware/cores/no2usb//data/usb_ep_status.hex /build/gateware/icE1usb/build-tmp/usb_ep_status.hex cp ../common/fw/boot.hex /build/gateware/icE1usb/build-tmp/boot.hex cd /build/gateware/icE1usb/build-tmp && \ yosys -s /build/gateware/icE1usb/build-tmp/icE1usb.ys \ -l /build/gateware/icE1usb/build-tmp/icE1usb.synth.rpt /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9+3568 (open-tool-forge build) (git sha1 859e52af, gcc 9.3.0-10ubuntu2 -Os) -- Executing script file `/build/gateware/icE1usb/build-tmp/icE1usb.ys' -- 1. Executing Verilog-2005 frontend: /build/gateware/icE1usb/rtl/top.v Parsing Verilog input from `/build/gateware/icE1usb/rtl/top.v' to AST representation. Generating RTLIL representation for module `\top'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_crc4.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_crc4.v' to AST representation. Generating RTLIL representation for module `\e1_crc4'. Successfully finished Verilog frontend. 3. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v' to AST representation. Generating RTLIL representation for module `\e1_rx_clock_recovery'. Successfully finished Verilog frontend. 4. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v' to AST representation. Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:65) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:204) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:208) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:208) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:209) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:210) is not recognized unless read_verilog is called with -sv! Generating RTLIL representation for module `\e1_rx_deframer'. Successfully finished Verilog frontend. 5. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx_filter.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx_filter.v' to AST representation. Generating RTLIL representation for module `\e1_rx_filter'. Successfully finished Verilog frontend. 6. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx_phy.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx_phy.v' to AST representation. Generating RTLIL representation for module `\e1_rx_phy'. Successfully finished Verilog frontend. 7. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx_liu.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx_liu.v' to AST representation. Generating RTLIL representation for module `\e1_rx_liu'. Successfully finished Verilog frontend. 8. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx.v' to AST representation. Generating RTLIL representation for module `\e1_rx'. Successfully finished Verilog frontend. 9. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_tx_framer.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_tx_framer.v' to AST representation. Generating RTLIL representation for module `\e1_tx_framer'. Successfully finished Verilog frontend. 10. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_tx_phy.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_tx_phy.v' to AST representation. Generating RTLIL representation for module `\e1_tx_phy'. Successfully finished Verilog frontend. 11. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_tx_liu.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_tx_liu.v' to AST representation. Generating RTLIL representation for module `\e1_tx_liu'. Successfully finished Verilog frontend. 12. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_tx.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_tx.v' to AST representation. Generating RTLIL representation for module `\e1_tx'. Successfully finished Verilog frontend. 13. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v' to AST representation. Generating RTLIL representation for module `\e1_buf_if_wb'. Warning: Replacing memory \tx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:165 Warning: Replacing memory \tx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:145 Warning: Replacing memory \rx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:103 Warning: Replacing memory \rx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:102 Successfully finished Verilog frontend. 14. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_wb_rx.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_wb_rx.v' to AST representation. Generating RTLIL representation for module `\e1_wb_rx'. Successfully finished Verilog frontend. 15. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_wb_tx.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_wb_tx.v' to AST representation. Generating RTLIL representation for module `\e1_wb_tx'. Successfully finished Verilog frontend. 16. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_wb.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_wb.v' to AST representation. Generating RTLIL representation for module `\e1_wb'. Successfully finished Verilog frontend. 17. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/hdb3_dec.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/hdb3_dec.v' to AST representation. Generating RTLIL representation for module `\hdb3_dec'. Successfully finished Verilog frontend. 18. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/hdb3_enc.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/hdb3_enc.v' to AST representation. Generating RTLIL representation for module `\hdb3_enc'. Successfully finished Verilog frontend. 19. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_ebr.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_ebr.v' to AST representation. Generating RTLIL representation for module `\ice40_ebr'. Successfully finished Verilog frontend. 20. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_i2c_wb.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_i2c_wb.v' to AST representation. Generating RTLIL representation for module `\ice40_i2c_wb'. Successfully finished Verilog frontend. 21. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v' to AST representation. Generating RTLIL representation for module `\ice40_rgb_wb'. Successfully finished Verilog frontend. 22. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_spi_wb.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_spi_wb.v' to AST representation. Generating RTLIL representation for module `\ice40_spi_wb'. Successfully finished Verilog frontend. 23. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v' to AST representation. Generating RTLIL representation for module `\ice40_spram_gen'. ice40_spram_gen: (32768x32) -> 2x2 array of SPRAM Successfully finished Verilog frontend. 24. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v' to AST representation. Generating RTLIL representation for module `\ice40_spram_wb'. Successfully finished Verilog frontend. 25. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_iserdes.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_iserdes.v' to AST representation. Generating RTLIL representation for module `\ice40_iserdes'. Successfully finished Verilog frontend. 26. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_oserdes.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_oserdes.v' to AST representation. Generating RTLIL representation for module `\ice40_oserdes'. Successfully finished Verilog frontend. 27. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_serdes_crg.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_serdes_crg.v' to AST representation. Generating RTLIL representation for module `\ice40_serdes_crg'. Successfully finished Verilog frontend. 28. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_serdes_dff.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_serdes_dff.v' to AST representation. Generating RTLIL representation for module `\ice40_serdes_dff'. Successfully finished Verilog frontend. 29. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_serdes_sync.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_serdes_sync.v' to AST representation. Generating RTLIL representation for module `\ice40_serdes_sync'. Successfully finished Verilog frontend. 30. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/delay.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/delay.v' to AST representation. Generating RTLIL representation for module `\delay_bit'. Generating RTLIL representation for module `\delay_bus'. Warning: Replacing memory \dl with list of registers. See /build/gateware/cores/no2misc//rtl/delay.v:59 Generating RTLIL representation for module `\delay_toggle'. Successfully finished Verilog frontend. 31. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/fifo_sync_ram.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v' to AST representation. Generating RTLIL representation for module `\fifo_sync_ram'. Successfully finished Verilog frontend. 32. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/fifo_sync_shift.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v' to AST representation. Generating RTLIL representation for module `\fifo_sync_shift'. Successfully finished Verilog frontend. 33. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/glitch_filter.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/glitch_filter.v' to AST representation. Generating RTLIL representation for module `\glitch_filter'. Successfully finished Verilog frontend. 34. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/i2c_master.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/i2c_master.v' to AST representation. Generating RTLIL representation for module `\i2c_master'. Successfully finished Verilog frontend. 35. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/i2c_master_wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/i2c_master_wb.v' to AST representation. Generating RTLIL representation for module `\i2c_master_wb'. Successfully finished Verilog frontend. 36. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/muacm2wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/muacm2wb.v' to AST representation. Generating RTLIL representation for module `\muacm2wb'. Successfully finished Verilog frontend. 37. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/prims.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/prims.v' to AST representation. Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:31) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:75) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:117) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:150) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:186) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:237) is not recognized unless read_verilog is called with -sv! Generating RTLIL representation for module `\lut4_n'. Generating RTLIL representation for module `\lut4_carry_n'. Generating RTLIL representation for module `\dff_n'. Generating RTLIL representation for module `\dffe_n'. Generating RTLIL representation for module `\dffer_n'. Generating RTLIL representation for module `\dffesr_n'. Successfully finished Verilog frontend. 38. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/pdm.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/pdm.v' to AST representation. Warning: Yosys has only limited support for tri-state logic at the moment. (/build/gateware/cores/no2misc//rtl/pdm.v:91) Generating RTLIL representation for module `\pdm'. Generating RTLIL representation for module `\pdm_lfsr'. Successfully finished Verilog frontend. 39. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/pwm.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/pwm.v' to AST representation. Warning: Yosys has only limited support for tri-state logic at the moment. (/build/gateware/cores/no2misc//rtl/pwm.v:69) Generating RTLIL representation for module `\pwm'. Successfully finished Verilog frontend. 40. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/ram_sdp.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/ram_sdp.v' to AST representation. Generating RTLIL representation for module `\ram_sdp'. Successfully finished Verilog frontend. 41. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/stream2wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/stream2wb.v' to AST representation. Generating RTLIL representation for module `\stream2wb'. Successfully finished Verilog frontend. 42. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/uart2wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/uart2wb.v' to AST representation. Generating RTLIL representation for module `\uart2wb'. Successfully finished Verilog frontend. 43. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/uart_rx.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/uart_rx.v' to AST representation. Generating RTLIL representation for module `\uart_rx'. Successfully finished Verilog frontend. 44. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/uart_tx.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/uart_tx.v' to AST representation. Generating RTLIL representation for module `\uart_tx'. Successfully finished Verilog frontend. 45. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/uart_wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/uart_wb.v' to AST representation. Generating RTLIL representation for module `\uart_wb'. Successfully finished Verilog frontend. 46. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/xclk_strobe.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/xclk_strobe.v' to AST representation. Generating RTLIL representation for module `\xclk_strobe'. Successfully finished Verilog frontend. 47. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/xclk_wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/xclk_wb.v' to AST representation. Generating RTLIL representation for module `\xclk_wb'. Successfully finished Verilog frontend. 48. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb.v' to AST representation. Generating RTLIL representation for module `\usb'. Successfully finished Verilog frontend. 49. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_crc.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_crc.v' to AST representation. Generating RTLIL representation for module `\usb_crc'. Successfully finished Verilog frontend. 50. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_ep_buf.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_ep_buf.v' to AST representation. Generating RTLIL representation for module `\usb_ep_buf'. READ_MODE : 3 WRITE_MODE : 3 Successfully finished Verilog frontend. 51. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_ep_status.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_ep_status.v' to AST representation. Generating RTLIL representation for module `\usb_ep_status'. Successfully finished Verilog frontend. 52. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_phy.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_phy.v' to AST representation. Generating RTLIL representation for module `\usb_phy'. Successfully finished Verilog frontend. 53. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_rx_ll.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_rx_ll.v' to AST representation. Generating RTLIL representation for module `\usb_rx_ll'. Successfully finished Verilog frontend. 54. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_rx_pkt.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v' to AST representation. Generating RTLIL representation for module `\usb_rx_pkt'. Successfully finished Verilog frontend. 55. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_trans.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_trans.v' to AST representation. Generating RTLIL representation for module `\usb_trans'. Successfully finished Verilog frontend. 56. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_tx_ll.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_tx_ll.v' to AST representation. Generating RTLIL representation for module `\usb_tx_ll'. Successfully finished Verilog frontend. 57. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_tx_pkt.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v' to AST representation. Generating RTLIL representation for module `\usb_tx_pkt'. Successfully finished Verilog frontend. 58. Executing Verilog-2005 frontend: /build/gateware/icE1usb/rtl/led_blinker.v Parsing Verilog input from `/build/gateware/icE1usb/rtl/led_blinker.v' to AST representation. Generating RTLIL representation for module `\led_blinker'. Successfully finished Verilog frontend. 59. Executing Verilog-2005 frontend: /build/gateware/icE1usb/rtl/misc.v Parsing Verilog input from `/build/gateware/icE1usb/rtl/misc.v' to AST representation. Generating RTLIL representation for module `\misc'. Warning: Replacing memory \pdm_e1 with list of registers. See /build/gateware/icE1usb/rtl/misc.v:264 Warning: Replacing memory \pdm_clk with list of registers. See /build/gateware/icE1usb/rtl/misc.v:262 Successfully finished Verilog frontend. 60. Executing Verilog-2005 frontend: /build/gateware/icE1usb/rtl/sr_btn_if.v Parsing Verilog input from `/build/gateware/icE1usb/rtl/sr_btn_if.v' to AST representation. Generating RTLIL representation for module `\sr_btn_if'. Successfully finished Verilog frontend. 61. Executing Verilog-2005 frontend: /build/gateware/icE1usb/rtl/sysmgr.v Parsing Verilog input from `/build/gateware/icE1usb/rtl/sysmgr.v' to AST representation. Generating RTLIL representation for module `\sysmgr'. Successfully finished Verilog frontend. 62. Executing Verilog-2005 frontend: /build/gateware/common/rtl/capcnt.v Parsing Verilog input from `/build/gateware/common/rtl/capcnt.v' to AST representation. Generating RTLIL representation for module `\capcnt'. Successfully finished Verilog frontend. 63. Executing Verilog-2005 frontend: /build/gateware/common/rtl/capcnt_sb_mac16.v Parsing Verilog input from `/build/gateware/common/rtl/capcnt_sb_mac16.v' to AST representation. Generating RTLIL representation for module `\capcnt16_sb_mac16'. Generating RTLIL representation for module `\capcnt32_sb_mac16'. Successfully finished Verilog frontend. 64. Executing Verilog-2005 frontend: /build/gateware/common/rtl/dfu_helper.v Parsing Verilog input from `/build/gateware/common/rtl/dfu_helper.v' to AST representation. Generating RTLIL representation for module `\dfu_helper'. Successfully finished Verilog frontend. 65. Executing Verilog-2005 frontend: /build/gateware/common/rtl/picorv32.v Parsing Verilog input from `/build/gateware/common/rtl/picorv32.v' to AST representation. Generating RTLIL representation for module `\picorv32'. Generating RTLIL representation for module `\picorv32_regs'. Generating RTLIL representation for module `\picorv32_pcpi_mul'. Generating RTLIL representation for module `\picorv32_pcpi_fast_mul'. Generating RTLIL representation for module `\picorv32_pcpi_div'. Generating RTLIL representation for module `\picorv32_axi'. Generating RTLIL representation for module `\picorv32_axi_adapter'. Generating RTLIL representation for module `\picorv32_wb'. Successfully finished Verilog frontend. 66. Executing Verilog-2005 frontend: /build/gateware/common/rtl/picorv32_ice40_regs.v Parsing Verilog input from `/build/gateware/common/rtl/picorv32_ice40_regs.v' to AST representation. Generating RTLIL representation for module `\picorv32_ice40_regs'. Successfully finished Verilog frontend. 67. Executing Verilog-2005 frontend: /build/gateware/common/rtl/soc_base.v Parsing Verilog input from `/build/gateware/common/rtl/soc_base.v' to AST representation. Generating RTLIL representation for module `\soc_base'. Successfully finished Verilog frontend. 68. Executing Verilog-2005 frontend: /build/gateware/common/rtl/soc_bram.v Parsing Verilog input from `/build/gateware/common/rtl/soc_bram.v' to AST representation. Generating RTLIL representation for module `\soc_bram'. Successfully finished Verilog frontend. 69. Executing Verilog-2005 frontend: /build/gateware/common/rtl/soc_iobuf.v Parsing Verilog input from `/build/gateware/common/rtl/soc_iobuf.v' to AST representation. Generating RTLIL representation for module `\soc_iobuf'. Successfully finished Verilog frontend. 70. Executing Verilog-2005 frontend: /build/gateware/common/rtl/soc_picorv32_bridge.v Parsing Verilog input from `/build/gateware/common/rtl/soc_picorv32_bridge.v' to AST representation. Generating RTLIL representation for module `\soc_picorv32_bridge'. Successfully finished Verilog frontend. 71. Executing Verilog-2005 frontend: /build/gateware/common/rtl/soc_spram.v Parsing Verilog input from `/build/gateware/common/rtl/soc_spram.v' to AST representation. Generating RTLIL representation for module `\soc_spram'. Successfully finished Verilog frontend. 72. Executing Verilog-2005 frontend: /build/gateware/common/rtl/wb_arbiter.v Parsing Verilog input from `/build/gateware/common/rtl/wb_arbiter.v' to AST representation. Generating RTLIL representation for module `\wb_arbiter'. Successfully finished Verilog frontend. 73. Executing Verilog-2005 frontend: /build/gateware/common/rtl/wb_dma.v Parsing Verilog input from `/build/gateware/common/rtl/wb_dma.v' to AST representation. Generating RTLIL representation for module `\wb_dma'. Successfully finished Verilog frontend. 74. Executing Verilog-2005 frontend: /build/gateware/common/rtl/wb_epbuf.v Parsing Verilog input from `/build/gateware/common/rtl/wb_epbuf.v' to AST representation. Generating RTLIL representation for module `\wb_epbuf'. Successfully finished Verilog frontend. 75. Executing SYNTH_ICE40 pass. 75.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v' to AST representation. Generating RTLIL representation for module `\SB_IO'. Generating RTLIL representation for module `\SB_GB_IO'. Generating RTLIL representation for module `\SB_GB'. Generating RTLIL representation for module `\SB_LUT4'. Generating RTLIL representation for module `\SB_CARRY'. Generating RTLIL representation for module `\SB_DFF'. Generating RTLIL representation for module `\SB_DFFE'. Generating RTLIL representation for module `\SB_DFFSR'. Generating RTLIL representation for module `\SB_DFFR'. Generating RTLIL representation for module `\SB_DFFSS'. Generating RTLIL representation for module `\SB_DFFS'. Generating RTLIL representation for module `\SB_DFFESR'. Generating RTLIL representation for module `\SB_DFFER'. Generating RTLIL representation for module `\SB_DFFESS'. Generating RTLIL representation for module `\SB_DFFES'. Generating RTLIL representation for module `\SB_DFFN'. Generating RTLIL representation for module `\SB_DFFNE'. Generating RTLIL representation for module `\SB_DFFNSR'. Generating RTLIL representation for module `\SB_DFFNR'. Generating RTLIL representation for module `\SB_DFFNSS'. Generating RTLIL representation for module `\SB_DFFNS'. Generating RTLIL representation for module `\SB_DFFNESR'. Generating RTLIL representation for module `\SB_DFFNER'. Generating RTLIL representation for module `\SB_DFFNESS'. Generating RTLIL representation for module `\SB_DFFNES'. Generating RTLIL representation for module `\SB_RAM40_4K'. Generating RTLIL representation for module `\SB_RAM40_4KNR'. Generating RTLIL representation for module `\SB_RAM40_4KNW'. Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. Generating RTLIL representation for module `\ICESTORM_LC'. Generating RTLIL representation for module `\SB_PLL40_CORE'. Generating RTLIL representation for module `\SB_PLL40_PAD'. Generating RTLIL representation for module `\SB_PLL40_2_PAD'. Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. Generating RTLIL representation for module `\SB_WARMBOOT'. Generating RTLIL representation for module `\SB_SPRAM256KA'. Generating RTLIL representation for module `\SB_HFOSC'. Generating RTLIL representation for module `\SB_LFOSC'. Generating RTLIL representation for module `\SB_RGBA_DRV'. Generating RTLIL representation for module `\SB_LED_DRV_CUR'. Generating RTLIL representation for module `\SB_RGB_DRV'. Generating RTLIL representation for module `\SB_I2C'. Generating RTLIL representation for module `\SB_SPI'. Generating RTLIL representation for module `\SB_LEDDA_IP'. Generating RTLIL representation for module `\SB_FILTER_50NS'. Generating RTLIL representation for module `\SB_IO_I3C'. Generating RTLIL representation for module `\SB_IO_OD'. Generating RTLIL representation for module `\SB_MAC16'. Generating RTLIL representation for module `\ICESTORM_RAM'. Successfully finished Verilog frontend. 75.2. Executing HIERARCHY pass (managing design hierarchy). 75.2.1. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: \sr_btn_if Used module: \led_blinker Used module: \i2c_master_wb Used module: \i2c_master Used module: \uart_wb Used module: \fifo_sync_ram Used module: \ram_sdp Used module: \uart_rx Used module: \glitch_filter Used module: \uart_tx Used module: \misc Used module: \pdm Used module: \capcnt Used module: \capcnt16_sb_mac16 Used module: \dfu_helper Used module: \soc_base Used module: \e1_buf_if_wb Used module: \e1_wb Used module: \e1_wb_tx Used module: \e1_tx Used module: \e1_tx_phy Used module: \hdb3_enc Used module: \e1_tx_framer Used module: \e1_crc4 Used module: \fifo_sync_shift Used module: \e1_wb_rx Used module: \e1_rx Used module: \hdb3_dec Used module: \e1_rx_clock_recovery Used module: \e1_rx_filter Used module: \e1_rx_phy Used module: \e1_rx_deframer Used module: \soc_iobuf Used module: \wb_dma Used module: \wb_arbiter Used module: \wb_epbuf Used module: \ice40_spram_wb Used module: \ice40_spram_gen Used module: \xclk_strobe Used module: \xclk_wb Used module: \usb Used module: \usb_ep_status Used module: \usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: \usb_crc Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: \usb_phy Used module: \ice40_rgb_wb Used module: \ice40_spi_wb Used module: \soc_spram Used module: \soc_bram Used module: \soc_picorv32_bridge Used module: \picorv32 Used module: \picorv32_ice40_regs Used module: \ice40_ebr Parameter \TICK_LOG2_DIV = 3 75.2.2. Executing AST frontend in derive mode using pre-parsed AST for module `\sr_btn_if'. Parameter \TICK_LOG2_DIV = 3 Generating RTLIL representation for module `$paramod\sr_btn_if\TICK_LOG2_DIV=3'. Parameter \DW = 4 Parameter \FIFO_DEPTH = 0 75.2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\i2c_master_wb'. Parameter \DW = 4 Parameter \FIFO_DEPTH = 0 Generating RTLIL representation for module `$paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0'. Parameter \DIV_WIDTH = 12 Parameter \DW = 32 75.2.4. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_wb'. Parameter \DIV_WIDTH = 12 Parameter \DW = 32 Generating RTLIL representation for module `$paramod\uart_wb\DIV_WIDTH=12\DW=32'. Parameter \WB_N = 3 Parameter \E1_N = 2 Parameter \E1_UNIT_HAS_RX = 2'01 Parameter \E1_UNIT_HAS_TX = 2'01 Parameter \E1_LIU = 0 75.2.5. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_base'. Parameter \WB_N = 3 Parameter \E1_N = 2 Parameter \E1_UNIT_HAS_RX = 2'01 Parameter \E1_UNIT_HAS_TX = 2'01 Parameter \E1_LIU = 0 Generating RTLIL representation for module `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base'. Parameter \N = 1 Parameter \UNIT_HAS_RX = 1'1 Parameter \UNIT_HAS_TX = 1'1 Parameter \MFW = 7 Parameter \DW = 32 75.2.6. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_buf_if_wb'. Parameter \N = 1 Parameter \UNIT_HAS_RX = 1'1 Parameter \UNIT_HAS_TX = 1'1 Parameter \MFW = 7 Parameter \DW = 32 Generating RTLIL representation for module `$paramod\e1_buf_if_wb\N=1\UNIT_HAS_RX=1'1\UNIT_HAS_TX=1'1\MFW=7\DW=32'. Warning: Replacing memory \tx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:165 Warning: Replacing memory \tx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:145 Warning: Replacing memory \rx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:103 Warning: Replacing memory \rx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:102 Parameter \N = 1 Parameter \UNIT_HAS_RX = 1'1 Parameter \UNIT_HAS_TX = 1'1 Parameter \LIU = 0 Parameter \MFW = 7 75.2.7. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_wb'. Parameter \N = 1 Parameter \UNIT_HAS_RX = 1'1 Parameter \UNIT_HAS_TX = 1'1 Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_wb\N=1\UNIT_HAS_RX=1'1\UNIT_HAS_TX=1'1\LIU=0\MFW=7'. Parameter \DW = 16 Parameter \AW = 12 75.2.8. Executing AST frontend in derive mode using pre-parsed AST for module `\xclk_wb'. Parameter \DW = 16 Parameter \AW = 12 Generating RTLIL representation for module `$paramod\xclk_wb\DW=16\AW=12'. Parameter \EPDW = 32 75.2.9. Executing AST frontend in derive mode using pre-parsed AST for module `\usb'. Parameter \EPDW = 32 Generating RTLIL representation for module `$paramod\usb\EPDW=32'. Parameter \CURRENT_MODE = 24'001100000110001000110001 Parameter \RGB0_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB1_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB2_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 75.2.10. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_rgb_wb'. Parameter \CURRENT_MODE = 24'001100000110001000110001 Parameter \RGB0_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB1_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB2_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Generating RTLIL representation for module `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb'. Parameter \DIV_WIDTH = 12 Parameter \DW = 32 Found cached RTLIL representation for module `$paramod\uart_wb\DIV_WIDTH=12\DW=32'. Parameter \N_CS = 1 Parameter \WITH_IOB = 0 Parameter \UNIT = 0 75.2.11. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_spi_wb'. Parameter \N_CS = 1 Parameter \WITH_IOB = 0 Parameter \UNIT = 0 Generating RTLIL representation for module `$paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0'. Parameter \AW = 14 75.2.12. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_spram'. Parameter \AW = 14 Generating RTLIL representation for module `$paramod\soc_spram\AW=14'. Parameter \AW = 8 Parameter \INIT_FILE = 64'0110001001101111011011110111010000101110011010000110010101111000 75.2.13. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_bram'. Parameter \AW = 8 Parameter \INIT_FILE = 64'0110001001101111011011110111010000101110011010000110010101111000 Generating RTLIL representation for module `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram'. Parameter \WB_N = 9 Parameter \WB_DW = 32 Parameter \WB_AW = 16 Parameter \WB_AI = 2 Parameter \WB_REG = 4 75.2.14. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_picorv32_bridge'. Parameter \WB_N = 9 Parameter \WB_DW = 32 Parameter \WB_AW = 16 Parameter \WB_AI = 2 Parameter \WB_REG = 4 Generating RTLIL representation for module `$paramod\soc_picorv32_bridge\WB_N=9\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4'. Parameter \ENABLE_COUNTERS = 0 Parameter \BARREL_SHIFTER = 0 Parameter \TWO_CYCLE_COMPARE = 0 Parameter \TWO_CYCLE_ALU = 1 Parameter \COMPRESSED_ISA = 0 Parameter \CATCH_MISALIGN = 0 Parameter \CATCH_ILLINSN = 0 Parameter \ENABLE_MUL = 0 Parameter \ENABLE_DIV = 0 Parameter \ENABLE_IRQ = 0 Parameter \ENABLE_IRQ_QREGS = 0 Parameter \PROGADDR_RESET = 0 Parameter \STACKADDR = 1024 75.2.15. Executing AST frontend in derive mode using pre-parsed AST for module `\picorv32'. Parameter \ENABLE_COUNTERS = 0 Parameter \BARREL_SHIFTER = 0 Parameter \TWO_CYCLE_COMPARE = 0 Parameter \TWO_CYCLE_ALU = 1 Parameter \COMPRESSED_ISA = 0 Parameter \CATCH_MISALIGN = 0 Parameter \CATCH_ILLINSN = 0 Parameter \ENABLE_MUL = 0 Parameter \ENABLE_DIV = 0 Parameter \ENABLE_IRQ = 0 Parameter \ENABLE_IRQ_QREGS = 0 Parameter \PROGADDR_RESET = 0 Parameter \STACKADDR = 1024 Generating RTLIL representation for module `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32'. Parameter \WIDTH = 8 Parameter \DITHER = 16'0100111001001111 Parameter \PHY = 40'0100100101000011010001010011010000110000 75.2.16. Executing AST frontend in derive mode using pre-parsed AST for module `\pdm'. Parameter \WIDTH = 8 Parameter \DITHER = 16'0100111001001111 Parameter \PHY = 40'0100100101000011010001010011010000110000 Generating RTLIL representation for module `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm'. Parameter \WIDTH = 8 Parameter \DITHER = 16'0100111001001111 Parameter \PHY = 40'0100100101000011010001010011010000110000 Found cached RTLIL representation for module `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm'. Parameter \WIDTH = 12 Parameter \DITHER = 24'010110010100010101010011 Parameter \PHY = 40'0100100101000011010001010011010000110000 75.2.17. Executing AST frontend in derive mode using pre-parsed AST for module `\pdm'. Parameter \WIDTH = 12 Parameter \DITHER = 24'010110010100010101010011 Parameter \PHY = 40'0100100101000011010001010011010000110000 Generating RTLIL representation for module `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm'. Parameter \WIDTH = 12 Parameter \DITHER = 24'010110010100010101010011 Parameter \PHY = 40'0100100101000011010001010011010000110000 Found cached RTLIL representation for module `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm'. Parameter \W = 16 75.2.18. Executing AST frontend in derive mode using pre-parsed AST for module `\capcnt'. Parameter \W = 16 Generating RTLIL representation for module `$paramod\capcnt\W=16'. Parameter \W = 16 Found cached RTLIL representation for module `$paramod\capcnt\W=16'. Parameter \W = 16 Found cached RTLIL representation for module `$paramod\capcnt\W=16'. Parameter \W = 16 Found cached RTLIL representation for module `$paramod\capcnt\W=16'. Parameter \TIMER_WIDTH = 26 Parameter \BTN_MODE = 0 Parameter \DFU_MODE = 0 75.2.19. Executing AST frontend in derive mode using pre-parsed AST for module `\dfu_helper'. Parameter \TIMER_WIDTH = 26 Parameter \BTN_MODE = 0 Parameter \DFU_MODE = 0 Generating RTLIL representation for module `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0'. Parameter \W = 32 75.2.20. Executing AST frontend in derive mode using pre-parsed AST for module `\capcnt'. Parameter \W = 32 Generating RTLIL representation for module `$paramod\capcnt\W=32'. Parameter \L = 2 Parameter \RST_VAL = 1'0 Parameter \WITH_SYNCHRONIZER = 1 75.2.21. Executing AST frontend in derive mode using pre-parsed AST for module `\glitch_filter'. Parameter \L = 2 Parameter \RST_VAL = 1'0 Parameter \WITH_SYNCHRONIZER = 1 Generating RTLIL representation for module `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1'. Parameter \DEPTH = 512 Parameter \WIDTH = 8 75.2.22. Executing AST frontend in derive mode using pre-parsed AST for module `\fifo_sync_ram'. Parameter \DEPTH = 512 Parameter \WIDTH = 8 Generating RTLIL representation for module `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8'. Parameter \DIV_WIDTH = 8 Parameter \GLITCH_FILTER = 2 75.2.23. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'. Parameter \DIV_WIDTH = 8 Parameter \GLITCH_FILTER = 2 Generating RTLIL representation for module `$paramod\uart_rx\DIV_WIDTH=8\GLITCH_FILTER=2'. Parameter \DEPTH = 512 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8'. Parameter \DIV_WIDTH = 8 75.2.24. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'. Parameter \DIV_WIDTH = 8 Generating RTLIL representation for module `$paramod\uart_tx\DIV_WIDTH=8'. Parameter \L = 2 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 75.2.25. Executing AST frontend in derive mode using pre-parsed AST for module `\glitch_filter'. Parameter \L = 2 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Generating RTLIL representation for module `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1'. Parameter \DW = 3 Parameter \TW = 0 Parameter \CLOCK_STRETCH = 0 75.2.26. Executing AST frontend in derive mode using pre-parsed AST for module `\i2c_master'. Parameter \DW = 3 Parameter \TW = 0 Parameter \CLOCK_STRETCH = 0 Generating RTLIL representation for module `$paramod\i2c_master\DW=3\TW=0\CLOCK_STRETCH=0'. Parameter \LIU = 0 Parameter \MFW = 7 75.2.27. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_rx'. Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_rx\LIU=0\MFW=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 75.2.28. Executing AST frontend in derive mode using pre-parsed AST for module `\fifo_sync_shift'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 Generating RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 75.2.29. Executing AST frontend in derive mode using pre-parsed AST for module `\fifo_sync_shift'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 Generating RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7'. Parameter \LIU = 0 Parameter \MFW = 7 75.2.30. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_tx'. Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_tx\LIU=0\MFW=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9'. Parameter \LIU = 0 Parameter \MFW = 7 75.2.31. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_wb_tx'. Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_wb_tx\LIU=0\MFW=7'. Parameter \LIU = 0 Parameter \MFW = 7 75.2.32. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_wb_rx'. Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_wb_rx\LIU=0\MFW=7'. Parameter \ADDR_WIDTH = 14 Parameter \DATA_WIDTH = 32 75.2.33. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_spram_gen'. Parameter \ADDR_WIDTH = 14 Parameter \DATA_WIDTH = 32 Generating RTLIL representation for module `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32'. ice40_spram_gen: (16384x32) -> 1x2 array of SPRAM Parameter \AWIDTH = 8 Parameter \DWIDTH = 16 75.2.34. Executing AST frontend in derive mode using pre-parsed AST for module `\ram_sdp'. Parameter \AWIDTH = 8 Parameter \DWIDTH = 16 Generating RTLIL representation for module `$paramod\ram_sdp\AWIDTH=8\DWIDTH=16'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 16 Parameter \WWIDTH = 8 75.2.35. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_ep_buf'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 16 Parameter \WWIDTH = 8 Generating RTLIL representation for module `$paramod$7d82212fad3e4929db14b64ca83adffce21ba555\usb_ep_buf'. READ_MODE : 2 WRITE_MODE : 3 Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 8 Parameter \WWIDTH = 16 75.2.36. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_ep_buf'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 8 Parameter \WWIDTH = 16 Generating RTLIL representation for module `$paramod$e9a8417cc0e9fc03e370009e77135e9e1e2b5499\usb_ep_buf'. READ_MODE : 3 WRITE_MODE : 2 Parameter \TARGET = 40'0100100101000011010001010011010000110000 75.2.37. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_phy'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Generating RTLIL representation for module `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000'. Parameter \WIDTH = 16 Parameter \POLY = 16'1000000000000101 Parameter \MATCH = 16'1000000000001101 75.2.38. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_crc'. Parameter \WIDTH = 16 Parameter \POLY = 16'1000000000000101 Parameter \MATCH = 16'1000000000001101 Generating RTLIL representation for module `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101'. Parameter \WIDTH = 16 Parameter \POLY = 16'1000000000000101 Parameter \MATCH = 16'1000000000001101 Found cached RTLIL representation for module `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101'. Parameter \WIDTH = 5 Parameter \POLY = 5'00101 Parameter \MATCH = 5'01100 75.2.39. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_crc'. Parameter \WIDTH = 5 Parameter \POLY = 5'00101 Parameter \MATCH = 5'01100 Generating RTLIL representation for module `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100'. Parameter \L = 4 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Parameter \WITH_SAMP_COND = 1'0 75.2.40. Executing AST frontend in derive mode using pre-parsed AST for module `\glitch_filter'. Parameter \L = 4 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Parameter \WITH_SAMP_COND = 1'0 Generating RTLIL representation for module `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0'. Parameter \READ_MODE = 0 Parameter \WRITE_MODE = 0 Parameter \MASK_WORKAROUND = 0 Parameter \NEG_WR_CLK = 0 Parameter \NEG_RD_CLK = 1 75.2.41. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_ebr'. Parameter \READ_MODE = 0 Parameter \WRITE_MODE = 0 Parameter \MASK_WORKAROUND = 0 Parameter \NEG_WR_CLK = 0 Parameter \NEG_RD_CLK = 1 Generating RTLIL representation for module `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr'. Parameter \READ_MODE = 0 Parameter \WRITE_MODE = 0 Parameter \MASK_WORKAROUND = 0 Parameter \NEG_WR_CLK = 0 Parameter \NEG_RD_CLK = 1 Found cached RTLIL representation for module `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr'. Parameter \READ_MODE = 0 Parameter \WRITE_MODE = 0 Parameter \MASK_WORKAROUND = 0 Parameter \NEG_WR_CLK = 0 Parameter \NEG_RD_CLK = 1 Found cached RTLIL representation for module `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr'. Parameter \READ_MODE = 0 Parameter \WRITE_MODE = 0 Parameter \MASK_WORKAROUND = 0 Parameter \NEG_WR_CLK = 0 Parameter \NEG_RD_CLK = 1 Found cached RTLIL representation for module `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr'. Parameter \ADDR_WIDTH = 14 Parameter \DATA_WIDTH = 32 Found cached RTLIL representation for module `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32'. Parameter \A0W = 14 Parameter \A1W = 9 Parameter \DW = 32 75.2.42. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_dma'. Parameter \A0W = 14 Parameter \A1W = 9 Parameter \DW = 32 Generating RTLIL representation for module `$paramod\wb_dma\A0W=14\A1W=9\DW=32'. Parameter \N = 2 Parameter \DW = 32 Parameter \AW = 9 75.2.43. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_arbiter'. Parameter \N = 2 Parameter \DW = 32 Parameter \AW = 9 Generating RTLIL representation for module `$paramod\wb_arbiter\N=2\DW=32\AW=9'. Parameter \AW = 9 Parameter \DW = 32 75.2.44. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_epbuf'. Parameter \AW = 9 Parameter \DW = 32 Generating RTLIL representation for module `$paramod\wb_epbuf\AW=9\DW=32'. Parameter \N = 3 Parameter \DW = 32 Parameter \AW = 14 75.2.45. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_arbiter'. Parameter \N = 3 Parameter \DW = 32 Parameter \AW = 14 Generating RTLIL representation for module `$paramod\wb_arbiter\N=3\DW=32\AW=14'. Parameter \AW = 14 Parameter \DW = 32 Parameter \ZERO_RDATA = 0 75.2.46. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_spram_wb'. Parameter \AW = 14 Parameter \DW = 32 Parameter \ZERO_RDATA = 0 Generating RTLIL representation for module `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0'. 75.2.47. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: $paramod\sr_btn_if\TICK_LOG2_DIV=3 Used module: \led_blinker Used module: $paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0 Used module: \i2c_master Used module: $paramod\uart_wb\DIV_WIDTH=12\DW=32 Used module: \fifo_sync_ram Used module: $paramod\ram_sdp\AWIDTH=8\DWIDTH=16 Used module: \uart_rx Used module: $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1 Used module: \uart_tx Used module: \misc Used module: $paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm Used module: $paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm Used module: \pdm_lfsr Used module: $paramod\capcnt\W=16 Used module: \capcnt16_sb_mac16 Used module: $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0 Used module: \glitch_filter Used module: $paramod\capcnt\W=32 Used module: \capcnt32_sb_mac16 Used module: $paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1 Used module: $paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base Used module: \e1_buf_if_wb Used module: \e1_wb Used module: $paramod\e1_wb_tx\LIU=0\MFW=7 Used module: \e1_tx Used module: \e1_tx_phy Used module: \hdb3_enc Used module: \e1_tx_framer Used module: \e1_crc4 Used module: \fifo_sync_shift Used module: $paramod\e1_wb_rx\LIU=0\MFW=7 Used module: \e1_rx Used module: \hdb3_dec Used module: \e1_rx_clock_recovery Used module: \e1_rx_filter Used module: \e1_rx_phy Used module: \e1_rx_deframer Used module: \soc_iobuf Used module: $paramod\wb_dma\A0W=14\A1W=9\DW=32 Used module: $paramod\wb_arbiter\N=2\DW=32\AW=9 Used module: $paramod\wb_epbuf\AW=9\DW=32 Used module: $paramod\wb_arbiter\N=3\DW=32\AW=14 Used module: $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0 Used module: \ice40_spram_gen Used module: \xclk_strobe Used module: \xclk_wb Used module: \usb Used module: \usb_ep_status Used module: $paramod$7d82212fad3e4929db14b64ca83adffce21ba555\usb_ep_buf Used module: $paramod$e9a8417cc0e9fc03e370009e77135e9e1e2b5499\usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101 Used module: $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100 Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000 Used module: \ice40_rgb_wb Used module: \uart_wb Used module: $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8 Used module: \ram_sdp Used module: $paramod\uart_rx\DIV_WIDTH=8\GLITCH_FILTER=2 Used module: $paramod\uart_tx\DIV_WIDTH=8 Used module: \ice40_spi_wb Used module: \soc_spram Used module: $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32 Used module: \soc_bram Used module: \soc_picorv32_bridge Used module: \picorv32 Used module: \picorv32_ice40_regs Used module: $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr Parameter \L = 4 Parameter \RST_VAL = 1'0 Parameter \WITH_SYNCHRONIZER = 1 Parameter \WITH_SAMP_COND = 1'0 75.2.48. Executing AST frontend in derive mode using pre-parsed AST for module `\glitch_filter'. Parameter \L = 4 Parameter \RST_VAL = 1'0 Parameter \WITH_SYNCHRONIZER = 1 Parameter \WITH_SAMP_COND = 1'0 Generating RTLIL representation for module `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0'. Parameter \WIDTH = 8 Parameter \POLY = 8'01110001 75.2.49. Executing AST frontend in derive mode using pre-parsed AST for module `\pdm_lfsr'. Parameter \WIDTH = 8 Parameter \POLY = 8'01110001 Generating RTLIL representation for module `$paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001'. Parameter \DW = 4 Parameter \TW = 0 Parameter \CLOCK_STRETCH = 0 75.2.50. Executing AST frontend in derive mode using pre-parsed AST for module `\i2c_master'. Parameter \DW = 4 Parameter \TW = 0 Parameter \CLOCK_STRETCH = 0 Generating RTLIL representation for module `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0'. Parameter \DEPTH = 512 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8'. Parameter \DIV_WIDTH = 12 Parameter \GLITCH_FILTER = 2 75.2.51. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'. Parameter \DIV_WIDTH = 12 Parameter \GLITCH_FILTER = 2 Generating RTLIL representation for module `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2'. Parameter \DEPTH = 512 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8'. Parameter \DIV_WIDTH = 12 75.2.52. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'. Parameter \DIV_WIDTH = 12 Generating RTLIL representation for module `$paramod\uart_tx\DIV_WIDTH=12'. Parameter \N = 2 Parameter \UNIT_HAS_RX = 2'01 Parameter \UNIT_HAS_TX = 2'01 Parameter \MFW = 7 Parameter \DW = 32 75.2.53. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_buf_if_wb'. Parameter \N = 2 Parameter \UNIT_HAS_RX = 2'01 Parameter \UNIT_HAS_TX = 2'01 Parameter \MFW = 7 Parameter \DW = 32 Generating RTLIL representation for module `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32'. Warning: Replacing memory \tx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:165 Warning: Replacing memory \tx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:145 Warning: Replacing memory \rx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:103 Warning: Replacing memory \rx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:102 Parameter \N = 2 Parameter \UNIT_HAS_RX = 2'01 Parameter \UNIT_HAS_TX = 2'01 Parameter \LIU = 0 Parameter \MFW = 7 75.2.54. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_wb'. Parameter \N = 2 Parameter \UNIT_HAS_RX = 2'01 Parameter \UNIT_HAS_TX = 2'01 Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7'. Parameter \DW = 16 Parameter \AW = 12 Found cached RTLIL representation for module `$paramod\xclk_wb\DW=16\AW=12'. Parameter \EPDW = 32 Found cached RTLIL representation for module `$paramod\usb\EPDW=32'. Parameter \CURRENT_MODE = 24'001100000110001000110001 Parameter \RGB0_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB1_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB2_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Found cached RTLIL representation for module `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb'. Parameter \DIV_WIDTH = 12 Parameter \DW = 32 Found cached RTLIL representation for module `$paramod\uart_wb\DIV_WIDTH=12\DW=32'. Parameter \N_CS = 1 Parameter \WITH_IOB = 0 Parameter \UNIT = 0 Found cached RTLIL representation for module `$paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0'. Parameter \AW = 14 Found cached RTLIL representation for module `$paramod\soc_spram\AW=14'. Parameter \AW = 8 Parameter \INIT_FILE = 64'0110001001101111011011110111010000101110011010000110010101111000 Found cached RTLIL representation for module `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram'. Parameter \WB_N = 11 Parameter \WB_DW = 32 Parameter \WB_AW = 16 Parameter \WB_AI = 2 Parameter \WB_REG = 4 75.2.55. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_picorv32_bridge'. Parameter \WB_N = 11 Parameter \WB_DW = 32 Parameter \WB_AW = 16 Parameter \WB_AI = 2 Parameter \WB_REG = 4 Generating RTLIL representation for module `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4'. Parameter \ENABLE_COUNTERS = 0 Parameter \BARREL_SHIFTER = 0 Parameter \TWO_CYCLE_COMPARE = 0 Parameter \TWO_CYCLE_ALU = 1 Parameter \COMPRESSED_ISA = 0 Parameter \CATCH_MISALIGN = 0 Parameter \CATCH_ILLINSN = 0 Parameter \ENABLE_MUL = 0 Parameter \ENABLE_DIV = 0 Parameter \ENABLE_IRQ = 0 Parameter \ENABLE_IRQ_QREGS = 0 Parameter \PROGADDR_RESET = 0 Parameter \STACKADDR = 1024 Found cached RTLIL representation for module `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32'. Parameter \AWIDTH = 9 Parameter \DWIDTH = 8 75.2.56. Executing AST frontend in derive mode using pre-parsed AST for module `\ram_sdp'. Parameter \AWIDTH = 9 Parameter \DWIDTH = 8 Generating RTLIL representation for module `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8'. Parameter \L = 2 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Found cached RTLIL representation for module `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1'. Parameter \LIU = 0 Parameter \MFW = 7 Found cached RTLIL representation for module `$paramod\e1_tx\LIU=0\MFW=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9'. Parameter \LIU = 0 Parameter \MFW = 7 Found cached RTLIL representation for module `$paramod\e1_rx\LIU=0\MFW=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7'. Parameter \ADDR_WIDTH = 14 Parameter \DATA_WIDTH = 32 Found cached RTLIL representation for module `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32'. 75.2.57. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: $paramod\sr_btn_if\TICK_LOG2_DIV=3 Used module: \led_blinker Used module: $paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0 Used module: $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0 Used module: $paramod\uart_wb\DIV_WIDTH=12\DW=32 Used module: $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8 Used module: $paramod\ram_sdp\AWIDTH=9\DWIDTH=8 Used module: $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2 Used module: \glitch_filter Used module: $paramod\uart_tx\DIV_WIDTH=12 Used module: \misc Used module: $paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm Used module: $paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm Used module: $paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001 Used module: $paramod\capcnt\W=16 Used module: \capcnt16_sb_mac16 Used module: $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0 Used module: $paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0 Used module: $paramod\capcnt\W=32 Used module: \capcnt32_sb_mac16 Used module: $paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1 Used module: $paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base Used module: $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32 Used module: $paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7 Used module: \e1_wb_tx Used module: $paramod\e1_tx\LIU=0\MFW=7 Used module: \e1_tx_phy Used module: \hdb3_enc Used module: \e1_tx_framer Used module: \e1_crc4 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9 Used module: \e1_wb_rx Used module: $paramod\e1_rx\LIU=0\MFW=7 Used module: \hdb3_dec Used module: \e1_rx_clock_recovery Used module: \e1_rx_filter Used module: \e1_rx_phy Used module: \e1_rx_deframer Used module: \soc_iobuf Used module: $paramod\wb_dma\A0W=14\A1W=9\DW=32 Used module: $paramod\wb_arbiter\N=2\DW=32\AW=9 Used module: $paramod\wb_epbuf\AW=9\DW=32 Used module: $paramod\wb_arbiter\N=3\DW=32\AW=14 Used module: $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0 Used module: $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32 Used module: \xclk_strobe Used module: $paramod\xclk_wb\DW=16\AW=12 Used module: $paramod\usb\EPDW=32 Used module: \usb_ep_status Used module: \usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101 Used module: $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100 Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: \usb_phy Used module: $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb Used module: $paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0 Used module: $paramod\soc_spram\AW=14 Used module: \ice40_spram_gen Used module: $paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram Used module: $paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4 Used module: $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32 Used module: \picorv32_ice40_regs Used module: $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 32 Parameter \WWIDTH = 8 75.2.58. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_ep_buf'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 32 Parameter \WWIDTH = 8 Generating RTLIL representation for module `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf'. READ_MODE : 1 WRITE_MODE : 3 Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 8 Parameter \WWIDTH = 32 75.2.59. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_ep_buf'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 8 Parameter \WWIDTH = 32 Generating RTLIL representation for module `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf'. READ_MODE : 3 WRITE_MODE : 1 Parameter \TARGET = 40'0100100101000011010001010011010000110000 Found cached RTLIL representation for module `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000'. Parameter \ADDR_WIDTH = 14 Parameter \DATA_WIDTH = 32 Found cached RTLIL representation for module `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32'. Parameter \L = 2 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Found cached RTLIL representation for module `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1'. Parameter \LIU = 0 Parameter \MFW = 7 Found cached RTLIL representation for module `$paramod\e1_wb_tx\LIU=0\MFW=7'. Parameter \LIU = 0 Parameter \MFW = 7 Found cached RTLIL representation for module `$paramod\e1_wb_rx\LIU=0\MFW=7'. 75.2.60. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: $paramod\sr_btn_if\TICK_LOG2_DIV=3 Used module: \led_blinker Used module: $paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0 Used module: $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0 Used module: $paramod\uart_wb\DIV_WIDTH=12\DW=32 Used module: $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8 Used module: $paramod\ram_sdp\AWIDTH=9\DWIDTH=8 Used module: $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2 Used module: $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1 Used module: $paramod\uart_tx\DIV_WIDTH=12 Used module: \misc Used module: $paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm Used module: $paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm Used module: $paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001 Used module: $paramod\capcnt\W=16 Used module: \capcnt16_sb_mac16 Used module: $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0 Used module: $paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0 Used module: $paramod\capcnt\W=32 Used module: \capcnt32_sb_mac16 Used module: $paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1 Used module: $paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base Used module: $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32 Used module: $paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7 Used module: $paramod\e1_wb_tx\LIU=0\MFW=7 Used module: $paramod\e1_tx\LIU=0\MFW=7 Used module: \e1_tx_phy Used module: \hdb3_enc Used module: \e1_tx_framer Used module: \e1_crc4 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9 Used module: $paramod\e1_wb_rx\LIU=0\MFW=7 Used module: $paramod\e1_rx\LIU=0\MFW=7 Used module: \hdb3_dec Used module: \e1_rx_clock_recovery Used module: \e1_rx_filter Used module: \e1_rx_phy Used module: \e1_rx_deframer Used module: \soc_iobuf Used module: $paramod\wb_dma\A0W=14\A1W=9\DW=32 Used module: $paramod\wb_arbiter\N=2\DW=32\AW=9 Used module: $paramod\wb_epbuf\AW=9\DW=32 Used module: $paramod\wb_arbiter\N=3\DW=32\AW=14 Used module: $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0 Used module: $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32 Used module: \xclk_strobe Used module: $paramod\xclk_wb\DW=16\AW=12 Used module: $paramod\usb\EPDW=32 Used module: \usb_ep_status Used module: $paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf Used module: $paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101 Used module: $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100 Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000 Used module: $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb Used module: $paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0 Used module: $paramod\soc_spram\AW=14 Used module: $paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram Used module: $paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4 Used module: $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32 Used module: \picorv32_ice40_regs Used module: $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr 75.2.61. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: $paramod\sr_btn_if\TICK_LOG2_DIV=3 Used module: \led_blinker Used module: $paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0 Used module: $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0 Used module: $paramod\uart_wb\DIV_WIDTH=12\DW=32 Used module: $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8 Used module: $paramod\ram_sdp\AWIDTH=9\DWIDTH=8 Used module: $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2 Used module: $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1 Used module: $paramod\uart_tx\DIV_WIDTH=12 Used module: \misc Used module: $paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm Used module: $paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm Used module: $paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001 Used module: $paramod\capcnt\W=16 Used module: \capcnt16_sb_mac16 Used module: $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0 Used module: $paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0 Used module: $paramod\capcnt\W=32 Used module: \capcnt32_sb_mac16 Used module: $paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1 Used module: $paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base Used module: $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32 Used module: $paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7 Used module: $paramod\e1_wb_tx\LIU=0\MFW=7 Used module: $paramod\e1_tx\LIU=0\MFW=7 Used module: \e1_tx_phy Used module: \hdb3_enc Used module: \e1_tx_framer Used module: \e1_crc4 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9 Used module: $paramod\e1_wb_rx\LIU=0\MFW=7 Used module: $paramod\e1_rx\LIU=0\MFW=7 Used module: \hdb3_dec Used module: \e1_rx_clock_recovery Used module: \e1_rx_filter Used module: \e1_rx_phy Used module: \e1_rx_deframer Used module: \soc_iobuf Used module: $paramod\wb_dma\A0W=14\A1W=9\DW=32 Used module: $paramod\wb_arbiter\N=2\DW=32\AW=9 Used module: $paramod\wb_epbuf\AW=9\DW=32 Used module: $paramod\wb_arbiter\N=3\DW=32\AW=14 Used module: $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0 Used module: $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32 Used module: \xclk_strobe Used module: $paramod\xclk_wb\DW=16\AW=12 Used module: $paramod\usb\EPDW=32 Used module: \usb_ep_status Used module: $paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf Used module: $paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101 Used module: $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100 Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000 Used module: $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb Used module: $paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0 Used module: $paramod\soc_spram\AW=14 Used module: $paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram Used module: $paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4 Used module: $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32 Used module: \picorv32_ice40_regs Used module: $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr Removing unused module `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0'. Removing unused module `$paramod$e9a8417cc0e9fc03e370009e77135e9e1e2b5499\usb_ep_buf'. Removing unused module `$paramod$7d82212fad3e4929db14b64ca83adffce21ba555\usb_ep_buf'. Removing unused module `$paramod\ram_sdp\AWIDTH=8\DWIDTH=16'. Removing unused module `$paramod\i2c_master\DW=3\TW=0\CLOCK_STRETCH=0'. Removing unused module `$paramod\uart_tx\DIV_WIDTH=8'. Removing unused module `$paramod\uart_rx\DIV_WIDTH=8\GLITCH_FILTER=2'. Removing unused module `$paramod\soc_picorv32_bridge\WB_N=9\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4'. Removing unused module `$paramod\e1_wb\N=1\UNIT_HAS_RX=1'1\UNIT_HAS_TX=1'1\LIU=0\MFW=7'. Removing unused module `$paramod\e1_buf_if_wb\N=1\UNIT_HAS_RX=1'1\UNIT_HAS_TX=1'1\MFW=7\DW=32'. Removing unused module `\wb_epbuf'. Removing unused module `\wb_dma'. Removing unused module `\wb_arbiter'. Removing unused module `\soc_spram'. Removing unused module `\soc_picorv32_bridge'. Removing unused module `\soc_bram'. Removing unused module `\soc_base'. Removing unused module `\picorv32_wb'. Removing unused module `\picorv32_axi_adapter'. Removing unused module `\picorv32_axi'. Removing unused module `\picorv32_pcpi_div'. Removing unused module `\picorv32_pcpi_fast_mul'. Removing unused module `\picorv32_pcpi_mul'. Removing unused module `\picorv32_regs'. Removing unused module `\picorv32'. Removing unused module `\dfu_helper'. Removing unused module `\capcnt'. Removing unused module `\sr_btn_if'. Removing unused module `\usb_phy'. Removing unused module `\usb_ep_buf'. Removing unused module `\usb_crc'. Removing unused module `\usb'. Removing unused module `\xclk_wb'. Removing unused module `\uart_wb'. Removing unused module `\uart_tx'. Removing unused module `\uart_rx'. Removing unused module `\uart2wb'. Removing unused module `\stream2wb'. Removing unused module `\ram_sdp'. Removing unused module `\pwm'. Removing unused module `\pdm_lfsr'. Removing unused module `\pdm'. Removing unused module `\dffesr_n'. Removing unused module `\dffer_n'. Removing unused module `\dffe_n'. Removing unused module `\dff_n'. Removing unused module `\lut4_carry_n'. Removing unused module `\lut4_n'. Removing unused module `\muacm2wb'. Removing unused module `\i2c_master_wb'. Removing unused module `\i2c_master'. Removing unused module `\glitch_filter'. Removing unused module `\fifo_sync_shift'. Removing unused module `\fifo_sync_ram'. Removing unused module `\delay_bus'. Removing unused module `\delay_bit'. Removing unused module `\ice40_serdes_sync'. Removing unused module `\ice40_serdes_dff'. Removing unused module `\ice40_serdes_crg'. Removing unused module `\ice40_oserdes'. Removing unused module `\ice40_iserdes'. Removing unused module `\ice40_spram_wb'. Removing unused module `\ice40_spram_gen'. Removing unused module `\ice40_spi_wb'. Removing unused module `\ice40_rgb_wb'. Removing unused module `\ice40_i2c_wb'. Removing unused module `\ice40_ebr'. Removing unused module `\e1_wb'. Removing unused module `\e1_wb_tx'. Removing unused module `\e1_wb_rx'. Removing unused module `\e1_buf_if_wb'. Removing unused module `\e1_tx'. Removing unused module `\e1_tx_liu'. Removing unused module `\e1_rx'. Removing unused module `\e1_rx_liu'. Removed 75 unused modules. 75.3. Executing PROC pass (convert processes to netlists). 75.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5567'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5512'. Removing empty process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4807'. Found and cleaned up 1 empty switch in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4284'. Found and cleaned up 15 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. Found and cleaned up 1 empty switch in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$4077'. Found and cleaned up 6 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:530$3723'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:530$3723'. Found and cleaned up 1 empty switch in `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:0$3529'. Removing empty process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:0$3529'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:471$3439'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:471$3439'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:360$135'. Cleaned up 26 empty switches. 75.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$3058 in module SB_DFFNES. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1274$3051 in module SB_DFFNESS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$3047 in module SB_DFFNER. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1143$3040 in module SB_DFFNESR. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1074$3037 in module SB_DFFNS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1026$3034 in module SB_DFFNSS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:957$3031 in module SB_DFFNR. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:909$3028 in module SB_DFFNSR. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$3020 in module SB_DFFES. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:697$3013 in module SB_DFFESS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$3009 in module SB_DFFER. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:566$3002 in module SB_DFFESR. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:497$2999 in module SB_DFFS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:449$2996 in module SB_DFFSS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:380$2993 in module SB_DFFR. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:332$2990 in module SB_DFFSR. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$5184 in module $paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$5180 in module $paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$5176 in module $paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$5168 in module $paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v:50$5165 in module $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_arbiter.v:116$5144 in module $paramod\wb_arbiter\N=3\DW=32\AW=14. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_arbiter.v:80$5132 in module $paramod\wb_arbiter\N=3\DW=32\AW=14. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_epbuf.v:51$5101 in module $paramod\wb_epbuf\AW=9\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_arbiter.v:116$5090 in module $paramod\wb_arbiter\N=2\DW=32\AW=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_arbiter.v:80$5080 in module $paramod\wb_arbiter\N=2\DW=32\AW=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_dma.v:190$5048 in module $paramod\wb_dma\A0W=14\A1W=9\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_dma.v:98$5009 in module $paramod\wb_dma\A0W=14\A1W=9\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_dma.v:92$5008 in module $paramod\wb_dma\A0W=14\A1W=9\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_dma.v:86$5004 in module $paramod\wb_dma\A0W=14\A1W=9\DW=32. Removed 2 dead cases from process $proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4925 in module $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4925 in module $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:163$5446 in module $paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4. Marked 16 switch rules as full_case in process $proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650 in module $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:246$4628 in module $paramod\e1_wb_rx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:239$4626 in module $paramod\e1_wb_rx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$4608 in module $paramod\e1_wb_rx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$4607 in module $paramod\e1_wb_rx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$4599 in module $paramod\e1_wb_rx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:265$4593 in module $paramod\e1_wb_tx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:258$4591 in module $paramod\e1_wb_tx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:152$4568 in module $paramod\e1_wb_tx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:122$4567 in module $paramod\e1_wb_tx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:112$4559 in module $paramod\e1_wb_tx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/sysmgr.v:84$1713 in module sysmgr. Marked 1 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/sysmgr.v:76$1708 in module sysmgr. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:160$4554 in module $paramod\e1_tx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:93$4544 in module $paramod\e1_tx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/misc.v:302$1633 in module misc. Marked 1 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/misc.v:260$1632 in module misc. Marked 1 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/misc.v:183$1631 in module misc. Marked 1 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/misc.v:170$1630 in module misc. Marked 2 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/misc.v:130$1629 in module misc. Marked 1 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/misc.v:110$1619 in module misc. Marked 1 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/led_blinker.v:89$1601 in module led_blinker. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:159$1544 in module usb_tx_pkt. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:126$1528 in module usb_tx_pkt. Marked 8 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:86$1526 in module usb_tx_pkt. Removed 1 dead cases from process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1523 in module usb_tx_ll. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1523 in module usb_tx_ll. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1501 in module usb_tx_ll. Marked 4 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1495 in module usb_tx_ll. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:236$1491 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:421$1480 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:387$1464 in module usb_trans. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1449 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:345$1446 in module usb_trans. Marked 5 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1441 in module usb_trans. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1430 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:225$1425 in module usb_trans. Removed 1 dead cases from process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1422 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1422 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:175$1413 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:162$1404 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1341 in module usb_rx_pkt. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:244$1338 in module usb_rx_pkt. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:230$1335 in module usb_rx_pkt. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:220$1332 in module usb_rx_pkt. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:188$1322 in module usb_rx_pkt. Marked 18 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:117$1306 in module usb_rx_pkt. Removed 1 dead cases from process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1301 in module usb_rx_ll. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1301 in module usb_rx_ll. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:137$1300 in module usb_rx_ll. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:124$1299 in module usb_rx_ll. Removed 1 dead cases from process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1283 in module usb_rx_ll. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1283 in module usb_rx_ll. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:67$1273 in module usb_rx_ll. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4534 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4532 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4523 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4521 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4512 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4510 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4501 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4499 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4488 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4486 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4477 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4475 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4466 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4464 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4455 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4453 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:199$4442 in module $paramod\e1_rx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:184$4432 in module $paramod\e1_rx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:125$5368 in module $paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4394 in module $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4390 in module $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4386 in module $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4378 in module $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:40$1101 in module xclk_strobe. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:34$1100 in module xclk_strobe. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:28$1098 in module xclk_strobe. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:153$5343 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5336 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$5325 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32. Marked 5 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5292 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:206$5287 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32. Marked 4 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$5285 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5257 in module $paramod\uart_tx\DIV_WIDTH=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:51$5254 in module $paramod\uart_tx\DIV_WIDTH=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:42$5250 in module $paramod\uart_tx\DIV_WIDTH=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:35$5246 in module $paramod\uart_tx\DIV_WIDTH=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4339 in module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4333 in module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4331 in module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:83$4322 in module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:67$4316 in module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4310 in module $paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4306 in module $paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4302 in module $paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4294 in module $paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/dfu_helper.v:149$4293 in module $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0. Marked 2 switch rules as full_case in process $proc$/build/gateware/common/rtl/dfu_helper.v:120$4284 in module $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/dfu_helper.v:109$4280 in module $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/dfu_helper.v:103$4278 in module $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/pdm.v:42$4271 in module $paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/pdm.v:42$4267 in module $paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm. Marked 37 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:1375$4091 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 2 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:1288$4063 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 2 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:1274$4058 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 8 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:1165$4023 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 3 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:840$3763 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 3 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:791$3761 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 2 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:760$3757 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 47 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:684$3756 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 4 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:549$3732 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:414$3694 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Removed 2 dead cases from process $proc$/build/gateware/common/rtl/picorv32.v:385$3691 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 2 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:385$3691 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:374$3686 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:309$3612 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:88$5236 in module $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:77$5232 in module $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:70$5228 in module $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3493 in module $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:536$3487 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:643$3479 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:636$3475 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:628$3471 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:619$3467 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:514$3453 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3440 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3438 in module $paramod\usb\EPDW=32. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:442$3434 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3416 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:99$3412 in module $paramod\xclk_wb\DW=16\AW=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:73$3405 in module $paramod\xclk_wb\DW=16\AW=12. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:214$5215 in module $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:204$5212 in module $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:159$5208 in module $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0. Removed 1 dead cases from process $proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:141$5204 in module $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:141$5204 in module $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:129$5200 in module $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0. Marked 7 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:87$5194 in module $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:81$5193 in module $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/pdm.v:133$5192 in module $paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/soc_base.v:185$3316 in module $paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:185$3300 in module $paramod\uart_wb\DIV_WIDTH=12\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:177$3290 in module $paramod\uart_wb\DIV_WIDTH=12\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3273 in module $paramod\uart_wb\DIV_WIDTH=12\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:154$3268 in module $paramod\uart_wb\DIV_WIDTH=12\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/i2c_master_wb.v:91$3263 in module $paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0. Marked 9 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:121$3199 in module $paramod\sr_btn_if\TICK_LOG2_DIV=3. Marked 1 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:114$3198 in module $paramod\sr_btn_if\TICK_LOG2_DIV=3. Marked 4 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:45$441 in module hdb3_enc. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:43$437 in module hdb3_dec. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:248$246 in module e1_tx_framer. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:236$244 in module e1_tx_framer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:204$231 in module e1_tx_framer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:194$228 in module e1_tx_framer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:187$224 in module e1_tx_framer. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:167$220 in module e1_tx_framer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:148$218 in module e1_tx_framer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:135$213 in module e1_tx_framer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:120$210 in module e1_tx_framer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:113$208 in module e1_tx_framer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:97$200 in module e1_tx_framer. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:71$163 in module e1_rx_filter. Marked 5 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:46$144 in module e1_rx_filter. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:395$141 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:360$135 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:339$109 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:324$91 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:310$69 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:269$57 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:261$53 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:253$49 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:226$41 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:214$37 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:202$33 in module e1_rx_deframer. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:146$26 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:139$24 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:118$19 in module e1_rx_deframer. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:39$17 in module e1_rx_clock_recovery. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:33$15 in module e1_rx_clock_recovery. Removed a total of 9 dead cases. 75.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 153 redundant assignments. Promoted 315 assignments to connections. 75.3.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3061'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3057'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3050'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3046'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3039'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3036'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3033'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3030'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3027'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3025'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3023'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3019'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3012'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3008'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3001'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2998'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2995'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2992'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2989'. Set init value: \Q = 1'0 Found init rule in `\SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2987'. Set init value: \Q = 1'0 Found init rule in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:49$1305'. Set init value: \dec_sym_1 = 2'00 75.3.5. Executing PROC_ARST pass (detect async resets in processes). Found async reset \S in `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$3058'. Found async reset \R in `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$3047'. Found async reset \S in `\SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1074$3037'. Found async reset \R in `\SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:957$3031'. Found async reset \S in `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$3020'. Found async reset \R in `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$3009'. Found async reset \S in `\SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:497$2999'. Found async reset \R in `\SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:380$2993'. Found async reset \rst in `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v:50$5165'. Found async reset \rst in `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5144'. Found async reset \rst in `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5132'. Found async reset \rst in `$paramod\wb_epbuf\AW=9\DW=32.$proc$/build/gateware/common/rtl/wb_epbuf.v:51$5101'. Found async reset \rst in `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5090'. Found async reset \rst in `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5080'. Found async reset \rst in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$5048'. Found async reset \rst in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:92$5008'. Found async reset \rst in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:86$5004'. Found async reset \rst in `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4925'. Found async reset \rst in `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:246$4628'. Found async reset \rst in `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:239$4626'. Found async reset \rst in `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$4607'. Found async reset \rst in `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:265$4593'. Found async reset \rst in `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:258$4591'. Found async reset \rst in `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:122$4567'. Found async reset \rst_30m72_i in `\sysmgr.$proc$/build/gateware/icE1usb/rtl/sysmgr.v:84$1713'. Found async reset \pll_lock in `\sysmgr.$proc$/build/gateware/icE1usb/rtl/sysmgr.v:76$1708'. Found async reset \rst in `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:93$4544'. Found async reset \rst in `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:302$1633'. Found async reset \rst in `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:260$1632'. Found async reset \rst in `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:183$1631'. Found async reset \rst in `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:170$1630'. Found async reset \rst in `\led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:89$1601'. Found async reset \rst in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:126$1528'. Found async reset \rst in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1523'. Found async reset \ll_start in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1501'. Found async reset \rst in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1495'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:387$1464'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:345$1446'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1441'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1430'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:225$1425'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:175$1413'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:162$1404'. Found async reset \rst in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:188$1322'. Found async reset \rst in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:67$1273'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4534'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4532'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4523'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4521'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4512'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4510'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4501'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4499'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4488'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4486'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4477'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4475'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4466'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4464'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4455'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4453'. Found async reset \rst in `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:199$4442'. Found async reset \rst in `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:184$4432'. Found async reset \rst in `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:40$1101'. Found async reset \rst in `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:34$1100'. Found async reset \rst in `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:28$1098'. Found async reset \rst in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:153$5343'. Found async reset \rst in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5336'. Found async reset \rst in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:206$5287'. Found async reset \rst in `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5257'. Found async reset \rst in `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:35$5246'. Found async reset \rst in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4339'. Found async reset \rst in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4333'. Found async reset \rst in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4331'. Found async reset \rst in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:83$4322'. Found async reset \rst in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:67$4316'. Found async reset \rst in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:149$4293'. Found async reset \rst in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4284'. Found async reset \rst in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:109$4280'. Found async reset \rst in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:103$4278'. Found async reset \rst in `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:70$5228'. Found async reset \rst in `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.$proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3493'. Found async reset \rst in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:536$3487'. Found async reset \rst in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:636$3475'. Found async reset \rst in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:514$3453'. Found async reset \rst in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3438'. Found async reset \rst in `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:99$3412'. Found async reset \rst_sys in `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:185$3316'. Found async reset \rst in `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:154$3268'. Found async reset \rst in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:248$246'. Found async reset \rst in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:236$244'. Found async reset \rst in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:204$231'. Found async reset \rst in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:194$228'. Found async reset \rst in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:187$224'. Found async reset \rst in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:148$218'. Found async reset \rst in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:135$213'. Found async reset \rst in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:120$210'. Found async reset \rst in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:113$208'. Found async reset \rst in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:97$200'. 75.3.6. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3061'. Creating decoders for process `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$3058'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3057'. Creating decoders for process `\SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1274$3051'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3050'. Creating decoders for process `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$3047'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3046'. Creating decoders for process `\SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1143$3040'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3039'. Creating decoders for process `\SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1074$3037'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3036'. Creating decoders for process `\SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1026$3034'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3033'. Creating decoders for process `\SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:957$3031'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3030'. Creating decoders for process `\SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:909$3028'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3027'. Creating decoders for process `\SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:866$3026'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3025'. Creating decoders for process `\SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:830$3024'. Creating decoders for process `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3023'. Creating decoders for process `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$3020'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3019'. Creating decoders for process `\SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:697$3013'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3012'. Creating decoders for process `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$3009'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3008'. Creating decoders for process `\SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:566$3002'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3001'. Creating decoders for process `\SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:497$2999'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2998'. Creating decoders for process `\SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:449$2996'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2995'. Creating decoders for process `\SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:380$2993'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2992'. Creating decoders for process `\SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:332$2990'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2989'. Creating decoders for process `\SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:289$2988'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2987'. Creating decoders for process `\SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:253$2986'. Creating decoders for process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$5189'. Creating decoders for process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$5184'. 1/2: $0\fall[0:0] 2/2: $0\rise[0:0] Creating decoders for process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$5180'. 1/1: $0\state[0:0] Creating decoders for process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$5176'. 1/1: $0\cnt[3:0] Creating decoders for process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$5168'. 1/2: $2\cnt_move[3:0] 2/2: $1\cnt_move[3:0] Creating decoders for process `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v:50$5165'. 1/1: $0\ack_i[0:0] Creating decoders for process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5144'. 1/2: $0\busy[0:0] 2/2: $0\sel[2:0] Creating decoders for process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$5135'. 1/3: $0\sel_nxt[2:0] [2] 2/3: $0\sel_nxt[2:0] [0] 3/3: $0\sel_nxt[2:0] [1] Creating decoders for process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5132'. 1/4: $0\m_wmsk[3:0] 2/4: $0\m_we[0:0] 3/4: $0\m_wdata[31:0] 4/4: $0\m_addr[13:0] Creating decoders for process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5113'. Creating decoders for process `$paramod\wb_epbuf\AW=9\DW=32.$proc$/build/gateware/common/rtl/wb_epbuf.v:51$5101'. 1/1: $0\ack_i[0:0] Creating decoders for process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5090'. 1/2: $0\busy[0:0] 2/2: $0\sel[1:0] Creating decoders for process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$5083'. 1/2: $0\sel_nxt[1:0] [1] 2/2: $0\sel_nxt[1:0] [0] Creating decoders for process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5080'. 1/4: $0\m_wmsk[3:0] 2/4: $0\m_we[0:0] 3/4: $0\m_wdata[31:0] 4/4: $0\m_addr[8:0] Creating decoders for process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5067'. Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$5048'. 1/3: $0\ctl_ack_i[0:0] 2/3: $0\ctl_do_read[0:0] 3/3: $0\ctl_do_write[0:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:178$5044'. 1/1: $0\dir[0:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:174$5041'. 1/1: $0\len[12:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:157$5031'. 1/1: $0\m1_addr_i[8:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:153$5027'. 1/1: $0\m0_addr_i[13:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:142$5025'. 1/1: $0\data_reg[31:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:98$5009'. 1/1: $0\state_nxt[1:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:92$5008'. 1/1: $0\state[1:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:86$5004'. 1/1: $0\go[0:0] Creating decoders for process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$5000'. Creating decoders for process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4996'. Creating decoders for process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4992'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5563'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5559'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5555'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5551'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5547'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5543'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5539'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5535'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5531'. Creating decoders for process `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4962'. 1/1: $0\state[4:0] Creating decoders for process `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4949'. 1/1: $0\state[15:0] Creating decoders for process `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4925'. 1/2: $0\dn_state[2:0] 2/2: $0\dp_state[2:0] Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5508'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5504'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5500'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5496'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5492'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5488'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5484'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5480'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5476'. Creating decoders for process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5452'. 1/4: $0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 2/4: $0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_DATA[7:0]$5454 3/4: $0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_ADDR[8:0]$5453 4/4: $0\rd_data[7:0] Creating decoders for process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:163$5446'. 1/1: $0\wb_rdata_reg[31:0] Creating decoders for process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:160$5444'. Creating decoders for process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:147$5417'. Creating decoders for process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:91$5414'. Creating decoders for process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4806'. Creating decoders for process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650'. 1/320: $8\mem_dm_w[7:0] [7] 2/320: $8\mem_dm_w[7:0] [4] 3/320: $8\mem_dm_w[7:0] [2] 4/320: $8\mem_dm_w[7:0] [0] 5/320: $8\mem_dm_w[7:0] [6] 6/320: $8\mem_dm_w[7:0] [1] 7/320: $8\mem_dm_w[7:0] [3] 8/320: $8\mem_dm_w[7:0] [5] 9/320: $8\mem_di_w[31:0] [31] 10/320: $8\mem_di_w[31:0] [24] 11/320: $8\mem_di_w[31:0] [22] 12/320: $8\mem_di_w[31:0] [20] 13/320: $8\mem_di_w[31:0] [18] 14/320: $8\mem_di_w[31:0] [16] 15/320: $8\mem_di_w[31:0] [14] 16/320: $8\mem_di_w[31:0] [12] 17/320: $8\mem_di_w[31:0] [10] 18/320: $8\mem_di_w[31:0] [8] 19/320: $8\mem_di_w[31:0] [6] 20/320: $8\mem_di_w[31:0] [4] 21/320: $8\mem_di_w[31:0] [2] 22/320: $8\mem_di_w[31:0] [0] 23/320: $8\mem_di_w[31:0] [30] 24/320: $8\mem_di_w[31:0] [27] 25/320: $8\mem_di_w[31:0] [23] 26/320: $8\mem_di_w[31:0] [21] 27/320: $8\mem_di_w[31:0] [17] 28/320: $8\mem_di_w[31:0] [13] 29/320: $8\mem_di_w[31:0] [9] 30/320: $8\mem_di_w[31:0] [5] 31/320: $8\mem_di_w[31:0] [1] 32/320: $8\mem_di_w[31:0] [28] 33/320: $8\mem_di_w[31:0] [26] 34/320: $8\mem_di_w[31:0] [15] 35/320: $8\mem_di_w[31:0] [3] 36/320: $8\mem_di_w[31:0] [7] 37/320: $8\mem_di_w[31:0] [25] 38/320: $8\mem_di_w[31:0] [19] 39/320: $8\mem_di_w[31:0] [29] 40/320: $8\mem_di_w[31:0] [11] 41/320: $7\mem_dm_w[7:0] [7] 42/320: $7\mem_dm_w[7:0] [4] 43/320: $7\mem_dm_w[7:0] [2] 44/320: $7\mem_dm_w[7:0] [0] 45/320: $7\mem_dm_w[7:0] [6] 46/320: $7\mem_dm_w[7:0] [1] 47/320: $7\mem_dm_w[7:0] [3] 48/320: $7\mem_dm_w[7:0] [5] 49/320: $7\mem_di_w[31:0] [31] 50/320: $7\mem_di_w[31:0] [24] 51/320: $7\mem_di_w[31:0] [22] 52/320: $7\mem_di_w[31:0] [20] 53/320: $7\mem_di_w[31:0] [18] 54/320: $7\mem_di_w[31:0] [16] 55/320: $7\mem_di_w[31:0] [14] 56/320: $7\mem_di_w[31:0] [12] 57/320: $7\mem_di_w[31:0] [10] 58/320: $7\mem_di_w[31:0] [8] 59/320: $7\mem_di_w[31:0] [6] 60/320: $7\mem_di_w[31:0] [4] 61/320: $7\mem_di_w[31:0] [2] 62/320: $7\mem_di_w[31:0] [0] 63/320: $7\mem_di_w[31:0] [30] 64/320: $7\mem_di_w[31:0] [27] 65/320: $7\mem_di_w[31:0] [23] 66/320: $7\mem_di_w[31:0] [21] 67/320: $7\mem_di_w[31:0] [17] 68/320: $7\mem_di_w[31:0] [13] 69/320: $7\mem_di_w[31:0] [9] 70/320: $7\mem_di_w[31:0] [5] 71/320: $7\mem_di_w[31:0] [1] 72/320: $7\mem_di_w[31:0] [28] 73/320: $7\mem_di_w[31:0] [26] 74/320: $7\mem_di_w[31:0] [15] 75/320: $7\mem_di_w[31:0] [3] 76/320: $7\mem_di_w[31:0] [7] 77/320: $7\mem_di_w[31:0] [25] 78/320: $7\mem_di_w[31:0] [19] 79/320: $7\mem_di_w[31:0] [29] 80/320: $7\mem_di_w[31:0] [11] 81/320: $6\mem_dm_w[7:0] [7] 82/320: $6\mem_dm_w[7:0] [4] 83/320: $6\mem_dm_w[7:0] [2] 84/320: $6\mem_dm_w[7:0] [0] 85/320: $6\mem_dm_w[7:0] [6] 86/320: $6\mem_dm_w[7:0] [1] 87/320: $6\mem_dm_w[7:0] [3] 88/320: $6\mem_dm_w[7:0] [5] 89/320: $6\mem_di_w[31:0] [31] 90/320: $6\mem_di_w[31:0] [24] 91/320: $6\mem_di_w[31:0] [22] 92/320: $6\mem_di_w[31:0] [20] 93/320: $6\mem_di_w[31:0] [18] 94/320: $6\mem_di_w[31:0] [16] 95/320: $6\mem_di_w[31:0] [14] 96/320: $6\mem_di_w[31:0] [12] 97/320: $6\mem_di_w[31:0] [10] 98/320: $6\mem_di_w[31:0] [8] 99/320: $6\mem_di_w[31:0] [6] 100/320: $6\mem_di_w[31:0] [4] 101/320: $6\mem_di_w[31:0] [2] 102/320: $6\mem_di_w[31:0] [0] 103/320: $6\mem_di_w[31:0] [30] 104/320: $6\mem_di_w[31:0] [27] 105/320: $6\mem_di_w[31:0] [23] 106/320: $6\mem_di_w[31:0] [21] 107/320: $6\mem_di_w[31:0] [17] 108/320: $6\mem_di_w[31:0] [13] 109/320: $6\mem_di_w[31:0] [9] 110/320: $6\mem_di_w[31:0] [5] 111/320: $6\mem_di_w[31:0] [1] 112/320: $6\mem_di_w[31:0] [28] 113/320: $6\mem_di_w[31:0] [26] 114/320: $6\mem_di_w[31:0] [15] 115/320: $6\mem_di_w[31:0] [3] 116/320: $6\mem_di_w[31:0] [7] 117/320: $6\mem_di_w[31:0] [25] 118/320: $6\mem_di_w[31:0] [19] 119/320: $6\mem_di_w[31:0] [29] 120/320: $6\mem_di_w[31:0] [11] 121/320: $5\mem_dm_w[7:0] [7] 122/320: $5\mem_dm_w[7:0] [4] 123/320: $5\mem_dm_w[7:0] [2] 124/320: $5\mem_dm_w[7:0] [0] 125/320: $5\mem_dm_w[7:0] [6] 126/320: $5\mem_dm_w[7:0] [1] 127/320: $5\mem_dm_w[7:0] [3] 128/320: $5\mem_dm_w[7:0] [5] 129/320: $5\mem_di_w[31:0] [31] 130/320: $5\mem_di_w[31:0] [24] 131/320: $5\mem_di_w[31:0] [22] 132/320: $5\mem_di_w[31:0] [20] 133/320: $5\mem_di_w[31:0] [18] 134/320: $5\mem_di_w[31:0] [16] 135/320: $5\mem_di_w[31:0] [14] 136/320: $5\mem_di_w[31:0] [12] 137/320: $5\mem_di_w[31:0] [10] 138/320: $5\mem_di_w[31:0] [8] 139/320: $5\mem_di_w[31:0] [6] 140/320: $5\mem_di_w[31:0] [4] 141/320: $5\mem_di_w[31:0] [2] 142/320: $5\mem_di_w[31:0] [0] 143/320: $5\mem_di_w[31:0] [30] 144/320: $5\mem_di_w[31:0] [27] 145/320: $5\mem_di_w[31:0] [23] 146/320: $5\mem_di_w[31:0] [21] 147/320: $5\mem_di_w[31:0] [17] 148/320: $5\mem_di_w[31:0] [13] 149/320: $5\mem_di_w[31:0] [9] 150/320: $5\mem_di_w[31:0] [5] 151/320: $5\mem_di_w[31:0] [1] 152/320: $5\mem_di_w[31:0] [28] 153/320: $5\mem_di_w[31:0] [26] 154/320: $5\mem_di_w[31:0] [15] 155/320: $5\mem_di_w[31:0] [3] 156/320: $5\mem_di_w[31:0] [7] 157/320: $5\mem_di_w[31:0] [25] 158/320: $5\mem_di_w[31:0] [19] 159/320: $5\mem_di_w[31:0] [29] 160/320: $5\mem_di_w[31:0] [11] 161/320: $4\mem_dm_w[7:0] [7] 162/320: $4\mem_dm_w[7:0] [4] 163/320: $4\mem_dm_w[7:0] [2] 164/320: $4\mem_dm_w[7:0] [0] 165/320: $4\mem_dm_w[7:0] [6] 166/320: $4\mem_dm_w[7:0] [1] 167/320: $4\mem_dm_w[7:0] [3] 168/320: $4\mem_dm_w[7:0] [5] 169/320: $4\mem_di_w[31:0] [31] 170/320: $4\mem_di_w[31:0] [24] 171/320: $4\mem_di_w[31:0] [22] 172/320: $4\mem_di_w[31:0] [20] 173/320: $4\mem_di_w[31:0] [18] 174/320: $4\mem_di_w[31:0] [16] 175/320: $4\mem_di_w[31:0] [14] 176/320: $4\mem_di_w[31:0] [12] 177/320: $4\mem_di_w[31:0] [10] 178/320: $4\mem_di_w[31:0] [8] 179/320: $4\mem_di_w[31:0] [6] 180/320: $4\mem_di_w[31:0] [4] 181/320: $4\mem_di_w[31:0] [2] 182/320: $4\mem_di_w[31:0] [0] 183/320: $4\mem_di_w[31:0] [30] 184/320: $4\mem_di_w[31:0] [27] 185/320: $4\mem_di_w[31:0] [23] 186/320: $4\mem_di_w[31:0] [21] 187/320: $4\mem_di_w[31:0] [17] 188/320: $4\mem_di_w[31:0] [13] 189/320: $4\mem_di_w[31:0] [9] 190/320: $4\mem_di_w[31:0] [5] 191/320: $4\mem_di_w[31:0] [1] 192/320: $4\mem_di_w[31:0] [28] 193/320: $4\mem_di_w[31:0] [26] 194/320: $4\mem_di_w[31:0] [15] 195/320: $4\mem_di_w[31:0] [3] 196/320: $4\mem_di_w[31:0] [7] 197/320: $4\mem_di_w[31:0] [25] 198/320: $4\mem_di_w[31:0] [19] 199/320: $4\mem_di_w[31:0] [29] 200/320: $4\mem_di_w[31:0] [11] 201/320: $3\mem_dm_w[7:0] [7] 202/320: $3\mem_dm_w[7:0] [4] 203/320: $3\mem_dm_w[7:0] [2] 204/320: $3\mem_dm_w[7:0] [0] 205/320: $3\mem_dm_w[7:0] [6] 206/320: $3\mem_dm_w[7:0] [1] 207/320: $3\mem_dm_w[7:0] [3] 208/320: $3\mem_dm_w[7:0] [5] 209/320: $3\mem_di_w[31:0] [31] 210/320: $3\mem_di_w[31:0] [24] 211/320: $3\mem_di_w[31:0] [22] 212/320: $3\mem_di_w[31:0] [20] 213/320: $3\mem_di_w[31:0] [18] 214/320: $3\mem_di_w[31:0] [16] 215/320: $3\mem_di_w[31:0] [14] 216/320: $3\mem_di_w[31:0] [12] 217/320: $3\mem_di_w[31:0] [10] 218/320: $3\mem_di_w[31:0] [8] 219/320: $3\mem_di_w[31:0] [6] 220/320: $3\mem_di_w[31:0] [4] 221/320: $3\mem_di_w[31:0] [2] 222/320: $3\mem_di_w[31:0] [0] 223/320: $3\mem_di_w[31:0] [30] 224/320: $3\mem_di_w[31:0] [27] 225/320: $3\mem_di_w[31:0] [23] 226/320: $3\mem_di_w[31:0] [21] 227/320: $3\mem_di_w[31:0] [17] 228/320: $3\mem_di_w[31:0] [13] 229/320: $3\mem_di_w[31:0] [9] 230/320: $3\mem_di_w[31:0] [5] 231/320: $3\mem_di_w[31:0] [1] 232/320: $3\mem_di_w[31:0] [28] 233/320: $3\mem_di_w[31:0] [26] 234/320: $3\mem_di_w[31:0] [15] 235/320: $3\mem_di_w[31:0] [3] 236/320: $3\mem_di_w[31:0] [7] 237/320: $3\mem_di_w[31:0] [25] 238/320: $3\mem_di_w[31:0] [19] 239/320: $3\mem_di_w[31:0] [29] 240/320: $3\mem_di_w[31:0] [11] 241/320: $2\mem_dm_w[7:0] [7] 242/320: $2\mem_dm_w[7:0] [4] 243/320: $2\mem_dm_w[7:0] [2] 244/320: $2\mem_dm_w[7:0] [0] 245/320: $2\mem_dm_w[7:0] [6] 246/320: $2\mem_dm_w[7:0] [1] 247/320: $2\mem_dm_w[7:0] [3] 248/320: $2\mem_dm_w[7:0] [5] 249/320: $2\mem_di_w[31:0] [31] 250/320: $2\mem_di_w[31:0] [24] 251/320: $2\mem_di_w[31:0] [22] 252/320: $2\mem_di_w[31:0] [20] 253/320: $2\mem_di_w[31:0] [18] 254/320: $2\mem_di_w[31:0] [16] 255/320: $2\mem_di_w[31:0] [14] 256/320: $2\mem_di_w[31:0] [12] 257/320: $2\mem_di_w[31:0] [10] 258/320: $2\mem_di_w[31:0] [8] 259/320: $2\mem_di_w[31:0] [6] 260/320: $2\mem_di_w[31:0] [4] 261/320: $2\mem_di_w[31:0] [2] 262/320: $2\mem_di_w[31:0] [0] 263/320: $2\mem_di_w[31:0] [30] 264/320: $2\mem_di_w[31:0] [27] 265/320: $2\mem_di_w[31:0] [23] 266/320: $2\mem_di_w[31:0] [21] 267/320: $2\mem_di_w[31:0] [17] 268/320: $2\mem_di_w[31:0] [13] 269/320: $2\mem_di_w[31:0] [9] 270/320: $2\mem_di_w[31:0] [5] 271/320: $2\mem_di_w[31:0] [1] 272/320: $2\mem_di_w[31:0] [28] 273/320: $2\mem_di_w[31:0] [26] 274/320: $2\mem_di_w[31:0] [15] 275/320: $2\mem_di_w[31:0] [3] 276/320: $2\mem_di_w[31:0] [7] 277/320: $2\mem_di_w[31:0] [25] 278/320: $2\mem_di_w[31:0] [19] 279/320: $2\mem_di_w[31:0] [29] 280/320: $2\mem_di_w[31:0] [11] 281/320: $1\mem_dm_w[7:0] [7] 282/320: $1\mem_dm_w[7:0] [4] 283/320: $1\mem_dm_w[7:0] [2] 284/320: $1\mem_dm_w[7:0] [0] 285/320: $1\mem_dm_w[7:0] [6] 286/320: $1\mem_dm_w[7:0] [1] 287/320: $1\mem_dm_w[7:0] [3] 288/320: $1\mem_dm_w[7:0] [5] 289/320: $1\mem_di_w[31:0] [31] 290/320: $1\mem_di_w[31:0] [24] 291/320: $1\mem_di_w[31:0] [22] 292/320: $1\mem_di_w[31:0] [20] 293/320: $1\mem_di_w[31:0] [18] 294/320: $1\mem_di_w[31:0] [16] 295/320: $1\mem_di_w[31:0] [14] 296/320: $1\mem_di_w[31:0] [12] 297/320: $1\mem_di_w[31:0] [10] 298/320: $1\mem_di_w[31:0] [8] 299/320: $1\mem_di_w[31:0] [6] 300/320: $1\mem_di_w[31:0] [4] 301/320: $1\mem_di_w[31:0] [2] 302/320: $1\mem_di_w[31:0] [0] 303/320: $1\mem_di_w[31:0] [30] 304/320: $1\mem_di_w[31:0] [27] 305/320: $1\mem_di_w[31:0] [23] 306/320: $1\mem_di_w[31:0] [21] 307/320: $1\mem_di_w[31:0] [17] 308/320: $1\mem_di_w[31:0] [13] 309/320: $1\mem_di_w[31:0] [9] 310/320: $1\mem_di_w[31:0] [5] 311/320: $1\mem_di_w[31:0] [1] 312/320: $1\mem_di_w[31:0] [28] 313/320: $1\mem_di_w[31:0] [26] 314/320: $1\mem_di_w[31:0] [15] 315/320: $1\mem_di_w[31:0] [3] 316/320: $1\mem_di_w[31:0] [7] 317/320: $1\mem_di_w[31:0] [25] 318/320: $1\mem_di_w[31:0] [19] 319/320: $1\mem_di_w[31:0] [29] 320/320: $1\mem_di_w[31:0] [11] Creating decoders for process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:73$4649'. 1/1: $0\addr_r[13:0] Creating decoders for process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:253$4632'. Creating decoders for process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:246$4628'. 1/1: $0\rx_overflow[0:0] Creating decoders for process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:239$4626'. 1/1: $0\rx_rst[0:0] Creating decoders for process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$4608'. 1/2: $0\bro_rden[0:0] 2/2: $0\bri_wren[0:0] Creating decoders for process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$4607'. 1/2: $0\rx_mode[1:0] 2/2: $0\rx_enabled[0:0] Creating decoders for process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$4599'. 1/2: $0\crx_clear[0:0] 2/2: $0\crx_wren[0:0] Creating decoders for process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:265$4593'. 1/1: $0\tx_underflow[0:0] Creating decoders for process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:258$4591'. 1/1: $0\tx_rst[0:0] Creating decoders for process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:152$4568'. 1/2: $0\bto_rden[0:0] 2/2: $0\bti_wren[0:0] Creating decoders for process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:122$4567'. 1/5: $0\tx_loopback[1:0] 2/5: $0\tx_alarm[0:0] 3/5: $0\tx_time_src[0:0] 4/5: $0\tx_mode[1:0] 5/5: $0\tx_enabled[0:0] Creating decoders for process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:112$4559'. 1/2: $0\ctx_clear[0:0] 2/2: $0\ctx_wren[0:0] Creating decoders for process `\sysmgr.$proc$/build/gateware/icE1usb/rtl/sysmgr.v:84$1713'. 1/1: $0\rst_48m_i[0:0] Creating decoders for process `\sysmgr.$proc$/build/gateware/icE1usb/rtl/sysmgr.v:76$1708'. 1/1: $0\rst_cnt[3:0] Creating decoders for process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:160$4554'. 1/2: $0\pg_lo[4:0] 2/2: $0\pg_hi[4:0] Creating decoders for process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:100$4546'. Creating decoders for process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:93$4544'. 1/1: $0\mf_valid[0:0] Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1648'. Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1646'. Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1644'. Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1642'. Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1640'. Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1638'. Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1636'. Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1634'. Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:302$1633'. 1/2: $0\boot_now[0:0] 2/2: $0\boot_sel[1:0] Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:260$1632'. 1/4: $0\pdm_e1[1][8:0] 2/4: $0\pdm_e1[0][8:0] 3/4: $0\pdm_clk[1][12:0] 4/4: $0\pdm_clk[0][12:0] Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:183$1631'. 1/1: $0\e1_led[8:0] Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:170$1630'. 1/2: $0\gpio_out[3:0] 2/2: $0\gpio_oe[3:0] Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:130$1629'. 1/1: $0\wb_rdata[31:0] Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:110$1619'. 1/7: $0\bus_we_pdm_e1[1:0] [1] 2/7: $0\bus_we_pdm_e1[1:0] [0] 3/7: $0\bus_we_pdm_clk[1:0] [1] 4/7: $0\bus_we_pdm_clk[1:0] [0] 5/7: $0\bus_we_led[0:0] 6/7: $0\bus_we_gpio[0:0] 7/7: $0\bus_we_boot[0:0] Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:104$1614'. Creating decoders for process `\led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:89$1601'. 1/1: $0\sr_go[0:0] Creating decoders for process `\led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:77$1592'. Creating decoders for process `\led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:65$1588'. Creating decoders for process `\led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:55$1584'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:241$1576'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:229$1573'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:202$1567'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:191$1563'. 1/1: $0\len[10:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:182$1557'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:175$1550'. 1/2: $0\shift_last_byte[0:0] 2/2: $0\shift_data_crc[0:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:170$1548'. 1/1: $0\shift_data[7:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:159$1544'. 1/1: $0\shift_load[7:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:152$1541'. 1/1: $0\shift_bit[3:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:136$1529'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:126$1528'. 1/1: $0\state[3:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:86$1526'. 1/8: $8\state_nxt[3:0] 2/8: $7\state_nxt[3:0] 3/8: $6\state_nxt[3:0] 4/8: $5\state_nxt[3:0] 5/8: $4\state_nxt[3:0] 6/8: $3\state_nxt[3:0] 7/8: $2\state_nxt[3:0] 8/8: $1\state_nxt[3:0] Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:134$1525'. Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1523'. 1/1: $0\out_sym[1:0] Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:110$1516'. Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:102$1511'. Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1501'. 1/2: $0\bs_now[0:0] 2/2: $0\bs_cnt[2:0] Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:79$1498'. Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1495'. 1/1: $0\state[2:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:236$1491'. 1/1: $0\pkt_pid[3:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:428$1483'. Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:421$1480'. 1/1: $0\bd_length[10:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:414$1474'. Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:403$1473'. Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:399$1470'. 1/1: $0\txpkt_pid[3:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:387$1464'. 1/1: $0\cel_state_i[0:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:380$1462'. Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1449'. 1/7: $0\bd_state[2:0] 2/7: $0\ep_data_toggle[0:0] 3/7: $0\ep_bd_idx_nxt[0:0] 4/7: $0\ep_bd_idx_cur[0:0] 5/7: $0\ep_bd_ctrl[0:0] 6/7: $0\ep_bd_dual[0:0] 7/7: $0\ep_type[2:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:345$1446'. 1/1: $0\epfw_cap_dl[5:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1441'. 1/1: $0\epfw_state[3:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1437'. 1/4: $0\trans_cel[0:0] 2/4: $0\trans_dir[0:0] 3/4: $0\trans_endp[3:0] 4/4: $0\trans_is_setup[0:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1430'. 1/1: $0\rto_cnt[9:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:225$1425'. 1/1: $0\evt[3:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1422'. 1/1: $0\mc_a_reg[3:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:175$1413'. 1/1: $0\mc_pc_nxt[7:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:162$1404'. 1/1: $0\mc_rst_n[0:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:374$1401'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:353$1392'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:349$1390'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:340$1387'. 1/1: $0\token_data[10:8] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:336$1384'. 1/1: $0\token_data[7:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1367'. 1/5: $0\pid_is_handshake[0:0] 2/5: $0\pid_is_data[0:0] 3/5: $0\pid_is_token[0:0] 4/5: $0\pid_is_sof[0:0] 5/5: $0\pid[3:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:318$1366'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:304$1345'. 1/1: $0\pid_valid[0:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1341'. 1/2: $0\crc16_ok[0:0] 2/2: $0\crc5_ok[0:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:284$1340'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:244$1338'. 1/1: $0\crc_in_first[0:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:230$1335'. 1/1: $0\bit_eop_ok[0:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:220$1332'. 1/1: $0\bit_cnt[3:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:215$1331'. 1/1: $0\data[7:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:198$1323'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:188$1322'. 1/1: $0\state[3:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:117$1306'. 1/18: $18\state_nxt[3:0] 2/18: $17\state_nxt[3:0] 3/18: $16\state_nxt[3:0] 4/18: $15\state_nxt[3:0] 5/18: $14\state_nxt[3:0] 6/18: $13\state_nxt[3:0] 7/18: $12\state_nxt[3:0] 8/18: $11\state_nxt[3:0] 9/18: $10\state_nxt[3:0] 10/18: $9\state_nxt[3:0] 11/18: $8\state_nxt[3:0] 12/18: $7\state_nxt[3:0] 13/18: $6\state_nxt[3:0] 14/18: $5\state_nxt[3:0] 15/18: $4\state_nxt[3:0] 16/18: $3\state_nxt[3:0] 17/18: $2\state_nxt[3:0] 18/18: $1\state_nxt[3:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:49$1305'. Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:181$1303'. 1/1: $0\dec_bs_skip_1[0:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1301'. 1/1: $0\dec_rep_state_1[3:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:137$1300'. 1/1: $0\dec_sync_state_1[3:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:124$1299'. 1/1: $0\dec_eop_state_1[2:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:120$1298'. Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:111$1291'. 1/2: $0\dec_bit_1[0:0] 2/2: $0\dec_sym_1[1:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:97$1284'. Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1283'. 1/1: $0\samp_cnt[2:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:67$1273'. 1/1: $0\samp_active[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4543'. Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4534'. 1/1: $0\stage[4].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4532'. 1/1: $0\stage[4].l_data[6:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4523'. 1/1: $0\stage[3].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4521'. 1/1: $0\stage[3].l_data[6:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4512'. 1/1: $0\stage[2].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4510'. 1/1: $0\stage[2].l_data[6:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4501'. 1/1: $0\stage[1].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4499'. 1/1: $0\stage[1].l_data[6:0] Creating decoders for process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:80$1269'. 1/1: $0\s_dout_3[15:0] Creating decoders for process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:76$1267'. 1/1: $0\p_dout_3[15:0] Creating decoders for process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1264'. Creating decoders for process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1256'. Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4497'. Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4488'. 1/1: $0\stage[4].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4486'. 1/1: $0\stage[4].l_data[8:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4477'. 1/1: $0\stage[3].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4475'. 1/1: $0\stage[3].l_data[8:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4466'. 1/1: $0\stage[2].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4464'. 1/1: $0\stage[2].l_data[8:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4455'. 1/1: $0\stage[1].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4453'. 1/1: $0\stage[1].l_data[8:0] Creating decoders for process `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:199$4442'. 1/1: $0\bd_crc_e[1:0] Creating decoders for process `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:192$4436'. Creating decoders for process `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:184$4432'. 1/1: $0\mf_valid[0:0] Creating decoders for process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:0$5373'. Creating decoders for process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:125$5368'. 1/1: $0\wb_rdata[15:0] Creating decoders for process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:117$5363'. Creating decoders for process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:106$5358'. Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4399'. Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4394'. 1/2: $0\fall[0:0] 2/2: $0\rise[0:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4390'. 1/1: $0\state[0:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4386'. 1/1: $0\cnt[1:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4378'. 1/2: $2\cnt_move[1:0] 2/2: $1\cnt_move[1:0] Creating decoders for process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:40$1101'. 1/1: $0\out_stb[0:0] Creating decoders for process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:34$1100'. 1/1: $0\dst[1:0] Creating decoders for process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:28$1098'. 1/1: $0\src[0:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5349'. Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:163$5348'. 1/1: $0\tx_data_reg[0][7:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:153$5343'. 1/1: $0\tx_pending[0:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:143$5342'. 1/1: $0\tx_addr_reg[0][15:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:123$5341'. Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5336'. 1/1: $0\rx_pending[0:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5335'. 1/2: $0\rx_addr_reg[0][15:0] 2/2: $0\rx_data_reg[0][7:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$5325'. 1/3: $1\t_done[3:0] 2/3: $1$bitselwrite$data$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:268$5284[3:0]$5329 3/3: $1$bitselwrite$mask$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:268$5283[3:0]$5328 Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5292'. 1/20: $2$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$5278[15:0]$5321 2/20: $2$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$5277[15:0]$5320 3/20: $2$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$5276[15:0]$5318 4/20: $2$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$5275[15:0]$5317 5/20: $2$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$5272[15:0]$5315 6/20: $2$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$5271[15:0]$5314 7/20: $2$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$5270[15:0]$5312 8/20: $2$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$5269[15:0]$5311 9/20: $1\mux.j[31:0] 10/20: $1$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$5278[15:0]$5309 11/20: $1$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$5277[15:0]$5308 12/20: $1$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$5276[15:0]$5307 13/20: $1$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$5275[15:0]$5306 14/20: $1$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$5272[15:0]$5305 15/20: $1$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$5271[15:0]$5304 16/20: $1$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$5270[15:0]$5303 17/20: $1$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$5269[15:0]$5302 18/20: $0\wb_wdata_byte[7:0] 19/20: $0\wb_addr_lsb[1:0] 20/20: $0\wb_addr[13:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:212$5289'. 1/1: $0\t_chan[1:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:206$5287'. 1/1: $0\t_busy[0:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$5285'. 1/4: $4\t_nxt_chan[1:0] 2/4: $3\t_nxt_chan[1:0] 3/4: $2\t_nxt_chan[1:0] 4/4: $1\t_nxt_chan[1:0] Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:67$5258'. Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5257'. 1/1: $0\shift[9:0] Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:51$5254'. 1/1: $0\bit_cnt[4:0] Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:42$5250'. 1/1: $0\div_cnt[12:0] Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:35$5246'. 1/1: $0\active[0:0] Creating decoders for process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4339'. 1/1: $0\rd_valid[0:0] Creating decoders for process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4333'. 1/1: $0\ram_rd_addr[8:0] Creating decoders for process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4331'. 1/1: $0\ram_wr_addr[8:0] Creating decoders for process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:83$4322'. 1/1: $0\full[0:0] Creating decoders for process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:67$4316'. 1/1: $0\level[9:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4315'. Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4310'. 1/2: $0\fall[0:0] 2/2: $0\rise[0:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4306'. 1/1: $0\state[0:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4302'. 1/1: $0\cnt[1:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4294'. 1/2: $2\cnt_move[1:0] 2/2: $1\cnt_move[1:0] Creating decoders for process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:149$4293'. 1/1: $0\wb_now[0:0] Creating decoders for process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4284'. 1/3: $0\wb_req[0:0] 2/3: $0\wb_sel[1:0] 3/3: $0\rst_req[0:0] Creating decoders for process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:109$4280'. 1/1: $0\timer[25:0] Creating decoders for process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:103$4278'. 1/1: $0\armed[0:0] Creating decoders for process `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:67$4274'. Creating decoders for process `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:42$4271'. 1/1: $0\acc[12:0] Creating decoders for process `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:72$4270'. Creating decoders for process `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:42$4267'. 1/1: $0\acc[8:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. 1/82: $0\reg_next_pc[31:0] [31:2] 2/82: $0\reg_next_pc[31:0] [1:0] 3/82: $0\reg_pc[31:0] [1:0] 4/82: $18\next_irq_pending[2:2] 5/82: $17\next_irq_pending[2:2] 6/82: $16\next_irq_pending[2:2] 7/82: $15\next_irq_pending[2:2] 8/82: $14\next_irq_pending[2:2] 9/82: $13\next_irq_pending[2:2] 10/82: $4\next_irq_pending[31:0] [31:2] 11/82: $3\set_mem_do_rdata[0:0] 12/82: $4\next_irq_pending[31:0] [1] 13/82: $3\set_mem_do_wdata[0:0] 14/82: $4\next_irq_pending[31:0] [0] 15/82: $4\set_mem_do_rinst[0:0] 16/82: $3\set_mem_do_rinst[0:0] 17/82: $4\set_mem_do_wdata[0:0] 18/82: $11\next_irq_pending[1:1] 19/82: $10\next_irq_pending[1:1] 20/82: $9\next_irq_pending[1:1] 21/82: $4\set_mem_do_rdata[0:0] 22/82: $7\next_irq_pending[1:1] 23/82: $6\next_irq_pending[1:1] 24/82: $12\next_irq_pending[1:1] 25/82: $5\set_mem_do_rinst[0:0] 26/82: $8\next_irq_pending[1:1] 27/82: $5\next_irq_pending[31:0] 28/82: $3\current_pc[31:0] 29/82: $2\current_pc[31:0] 30/82: $2\set_mem_do_wdata[0:0] 31/82: $2\set_mem_do_rdata[0:0] 32/82: $2\set_mem_do_rinst[0:0] 33/82: $3\next_irq_pending[31:0] 34/82: $1\current_pc[31:0] 35/82: $1\set_mem_do_wdata[0:0] 36/82: $1\set_mem_do_rdata[0:0] 37/82: $1\set_mem_do_rinst[0:0] 38/82: $0\trace_data[35:0] 39/82: $2\next_irq_pending[0:0] 40/82: $1\next_irq_pending[0:0] 41/82: $0\count_instr[63:0] 42/82: $0\count_cycle[63:0] 43/82: $0\trace_valid[0:0] 44/82: $0\do_waitirq[0:0] 45/82: $0\decoder_pseudo_trigger[0:0] 46/82: $0\decoder_trigger[0:0] 47/82: $0\alu_wait_2[0:0] 48/82: $0\alu_wait[0:0] 49/82: $0\reg_out[31:0] 50/82: $0\reg_sh[4:0] 51/82: $0\trap[0:0] 52/82: $0\pcpi_timeout[0:0] 53/82: $0\latched_rd[4:0] 54/82: $0\latched_is_lb[0:0] 55/82: $0\latched_is_lh[0:0] 56/82: $0\latched_is_lu[0:0] 57/82: $0\latched_trace[0:0] 58/82: $0\latched_compr[0:0] 59/82: $0\latched_branch[0:0] 60/82: $0\latched_stalu[0:0] 61/82: $0\latched_store[0:0] 62/82: $0\irq_state[1:0] 63/82: $0\cpu_state[7:0] 64/82: $0\dbg_rs2val_valid[0:0] 65/82: $0\dbg_rs1val_valid[0:0] 66/82: $0\dbg_rs2val[31:0] 67/82: $0\dbg_rs1val[31:0] 68/82: $0\mem_do_wdata[0:0] 69/82: $0\mem_do_rdata[0:0] 70/82: $0\mem_do_rinst[0:0] 71/82: $0\mem_do_prefetch[0:0] 72/82: $0\mem_wordsize[1:0] 73/82: $0\irq_mask[31:0] 74/82: $0\irq_active[0:0] 75/82: $0\irq_delay[0:0] 76/82: $0\reg_op2[31:0] 77/82: $0\reg_op1[31:0] 78/82: $0\reg_pc[31:0] [31:2] 79/82: $19\next_irq_pending[2:2] 80/82: $0\eoi[31:0] 81/82: $0\pcpi_valid[0:0] 82/82: $0\timer[31:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$4077'. Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1288$4063'. 1/4: $2\cpuregs_write[0:0] 2/4: $2\cpuregs_wrdata[31:0] 3/4: $1\cpuregs_wrdata[31:0] 4/4: $1\cpuregs_write[0:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1274$4058'. 1/2: $2\clear_prefetched_high_word[0:0] 2/2: $1\clear_prefetched_high_word[0:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1272$4057'. Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1228$4035'. 1/2: $1\alu_out[31:0] 2/2: $1\alu_out_0[0:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1165$4023'. 1/8: $8\dbg_ascii_state[127:0] 2/8: $7\dbg_ascii_state[127:0] 3/8: $6\dbg_ascii_state[127:0] 4/8: $5\dbg_ascii_state[127:0] 5/8: $4\dbg_ascii_state[127:0] 6/8: $3\dbg_ascii_state[127:0] 7/8: $2\dbg_ascii_state[127:0] 8/8: $1\dbg_ascii_state[127:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. 1/76: $0\decoded_rs1[4:0] [4] 2/76: $0\decoded_imm_uj[31:0] [10] 3/76: $0\decoded_imm_uj[31:0] [7] 4/76: $0\decoded_imm_uj[31:0] [6] 5/76: $0\decoded_imm_uj[31:0] [3:1] 6/76: $0\decoded_imm_uj[31:0] [5] 7/76: $0\decoded_imm_uj[31:0] [9:8] 8/76: $0\decoded_imm_uj[31:0] [31:20] 9/76: $0\decoded_imm_uj[31:0] [4] 10/76: $0\decoded_imm_uj[31:0] [11] 11/76: $0\decoded_imm_uj[31:0] [0] 12/76: $0\decoded_rs1[4:0] [3:0] 13/76: $0\is_lui_auipc_jal_jalr_addi_add_sub[0:0] 14/76: $0\is_alu_reg_reg[0:0] 15/76: $0\is_alu_reg_imm[0:0] 16/76: $0\is_beq_bne_blt_bge_bltu_bgeu[0:0] 17/76: $0\is_sll_srl_sra[0:0] 18/76: $0\is_sb_sh_sw[0:0] 19/76: $0\is_jalr_addi_slti_sltiu_xori_ori_andi[0:0] 20/76: $0\is_slli_srli_srai[0:0] 21/76: $0\is_lb_lh_lw_lbu_lhu[0:0] 22/76: $0\compressed_instr[0:0] 23/76: $0\is_compare[0:0] 24/76: $0\decoded_imm[31:0] 25/76: $0\decoded_rs2[4:0] 26/76: $0\decoded_imm_uj[31:0] [19:12] 27/76: $0\decoded_rd[4:0] 28/76: $0\instr_timer[0:0] 29/76: $0\instr_waitirq[0:0] 30/76: $0\instr_maskirq[0:0] 31/76: $0\instr_retirq[0:0] 32/76: $0\instr_setq[0:0] 33/76: $0\instr_getq[0:0] 34/76: $0\instr_ecall_ebreak[0:0] 35/76: $0\instr_rdinstrh[0:0] 36/76: $0\instr_rdinstr[0:0] 37/76: $0\instr_rdcycleh[0:0] 38/76: $0\instr_rdcycle[0:0] 39/76: $0\instr_and[0:0] 40/76: $0\instr_or[0:0] 41/76: $0\instr_sra[0:0] 42/76: $0\instr_srl[0:0] 43/76: $0\instr_xor[0:0] 44/76: $0\instr_sltu[0:0] 45/76: $0\instr_slt[0:0] 46/76: $0\instr_sll[0:0] 47/76: $0\instr_sub[0:0] 48/76: $0\instr_add[0:0] 49/76: $0\instr_srai[0:0] 50/76: $0\instr_srli[0:0] 51/76: $0\instr_slli[0:0] 52/76: $0\instr_andi[0:0] 53/76: $0\instr_ori[0:0] 54/76: $0\instr_xori[0:0] 55/76: $0\instr_sltiu[0:0] 56/76: $0\instr_slti[0:0] 57/76: $0\instr_addi[0:0] 58/76: $0\instr_sw[0:0] 59/76: $0\instr_sh[0:0] 60/76: $0\instr_sb[0:0] 61/76: $0\instr_lhu[0:0] 62/76: $0\instr_lbu[0:0] 63/76: $0\instr_lw[0:0] 64/76: $0\instr_lh[0:0] 65/76: $0\instr_lb[0:0] 66/76: $0\instr_bgeu[0:0] 67/76: $0\instr_bltu[0:0] 68/76: $0\instr_bge[0:0] 69/76: $0\instr_blt[0:0] 70/76: $0\instr_bne[0:0] 71/76: $0\instr_beq[0:0] 72/76: $0\instr_jalr[0:0] 73/76: $0\instr_jal[0:0] 74/76: $0\instr_auipc[0:0] 75/76: $0\instr_lui[0:0] 76/76: $0\pcpi_insn[31:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3761'. 1/13: $3\dbg_insn_opcode[31:0] 2/13: $2\dbg_insn_rd[4:0] 3/13: $2\dbg_insn_rs2[4:0] 4/13: $2\dbg_insn_rs1[4:0] 5/13: $2\dbg_insn_opcode[31:0] 6/13: $2\dbg_insn_imm[31:0] 7/13: $2\dbg_ascii_instr[63:0] 8/13: $1\dbg_insn_rd[4:0] 9/13: $1\dbg_insn_rs2[4:0] 10/13: $1\dbg_insn_rs1[4:0] 11/13: $1\dbg_insn_imm[31:0] 12/13: $1\dbg_ascii_instr[63:0] 13/13: $1\dbg_insn_opcode[31:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3757'. 1/8: $0\cached_insn_rd[4:0] 2/8: $0\cached_insn_rs2[4:0] 3/8: $0\cached_insn_rs1[4:0] 4/8: $0\cached_insn_opcode[31:0] 5/8: $0\cached_insn_imm[31:0] 6/8: $0\cached_ascii_instr[63:0] 7/8: $0\dbg_valid_insn[0:0] 8/8: $0\dbg_insn_addr[31:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:684$3756'. 1/47: $47\new_ascii_instr[63:0] 2/47: $46\new_ascii_instr[63:0] 3/47: $45\new_ascii_instr[63:0] 4/47: $44\new_ascii_instr[63:0] 5/47: $43\new_ascii_instr[63:0] 6/47: $42\new_ascii_instr[63:0] 7/47: $41\new_ascii_instr[63:0] 8/47: $40\new_ascii_instr[63:0] 9/47: $39\new_ascii_instr[63:0] 10/47: $38\new_ascii_instr[63:0] 11/47: $37\new_ascii_instr[63:0] 12/47: $36\new_ascii_instr[63:0] 13/47: $35\new_ascii_instr[63:0] 14/47: $34\new_ascii_instr[63:0] 15/47: $33\new_ascii_instr[63:0] 16/47: $32\new_ascii_instr[63:0] 17/47: $31\new_ascii_instr[63:0] 18/47: $30\new_ascii_instr[63:0] 19/47: $29\new_ascii_instr[63:0] 20/47: $28\new_ascii_instr[63:0] 21/47: $27\new_ascii_instr[63:0] 22/47: $26\new_ascii_instr[63:0] 23/47: $25\new_ascii_instr[63:0] 24/47: $24\new_ascii_instr[63:0] 25/47: $23\new_ascii_instr[63:0] 26/47: $22\new_ascii_instr[63:0] 27/47: $21\new_ascii_instr[63:0] 28/47: $20\new_ascii_instr[63:0] 29/47: $19\new_ascii_instr[63:0] 30/47: $18\new_ascii_instr[63:0] 31/47: $17\new_ascii_instr[63:0] 32/47: $16\new_ascii_instr[63:0] 33/47: $15\new_ascii_instr[63:0] 34/47: $14\new_ascii_instr[63:0] 35/47: $13\new_ascii_instr[63:0] 36/47: $12\new_ascii_instr[63:0] 37/47: $11\new_ascii_instr[63:0] 38/47: $10\new_ascii_instr[63:0] 39/47: $9\new_ascii_instr[63:0] 40/47: $8\new_ascii_instr[63:0] 41/47: $7\new_ascii_instr[63:0] 42/47: $6\new_ascii_instr[63:0] 43/47: $5\new_ascii_instr[63:0] 44/47: $4\new_ascii_instr[63:0] 45/47: $3\new_ascii_instr[63:0] 46/47: $2\new_ascii_instr[63:0] 47/47: $1\new_ascii_instr[63:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3732'. 1/9: $0\mem_16bit_buffer[15:0] 2/9: $0\prefetched_high_word[0:0] 3/9: $0\mem_la_secondword[0:0] 4/9: $0\mem_state[1:0] 5/9: $0\mem_wstrb[3:0] 6/9: $0\mem_wdata[31:0] 7/9: $0\mem_instr[0:0] 8/9: $0\mem_valid[0:0] 9/9: $0\mem_addr[31:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1209$4256'. Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:414$3694'. 1/9: $0\mem_rdata_q[31:0] [31] 2/9: $0\mem_rdata_q[31:0] [7] 3/9: $0\mem_rdata_q[31:0] [24:20] 4/9: $0\mem_rdata_q[31:0] [19:15] 5/9: $0\mem_rdata_q[31:0] [6:0] 6/9: $0\mem_rdata_q[31:0] [14:12] 7/9: $0\mem_rdata_q[31:0] [11:8] 8/9: $0\mem_rdata_q[31:0] [30:25] 9/9: $0\next_insn_opcode[31:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3691'. 1/5: $3\mem_rdata_word[31:0] 2/5: $2\mem_rdata_word[31:0] 3/5: $1\mem_rdata_word[31:0] 4/5: $1\mem_la_wstrb[3:0] 5/5: $1\mem_la_wdata[31:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:374$3686'. 1/2: $0\last_mem_valid[0:0] 2/2: $0\mem_la_firstword_reg[0:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3612'. 1/2: $1\pcpi_int_rd[31:0] 2/2: $1\pcpi_int_wr[0:0] Creating decoders for process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:102$5240'. Creating decoders for process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:95$5239'. 1/1: $0\shift[8:0] Creating decoders for process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:88$5236'. 1/1: $0\bit_cnt[4:0] Creating decoders for process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:77$5232'. 1/1: $0\div_cnt[12:0] Creating decoders for process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:70$5228'. 1/1: $0\active[0:0] Creating decoders for process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3502'. 1/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3498_EN[31:0]$3505 2/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3498_DATA[31:0]$3504 3/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3498_ADDR[7:0]$3503 4/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3499_EN[31:0]$3508 5/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3499_DATA[31:0]$3507 6/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3499_ADDR[7:0]$3506 7/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3500_EN[31:0]$3511 8/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3500_DATA[31:0]$3510 9/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3500_ADDR[7:0]$3509 10/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3501_EN[31:0]$3514 11/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3501_DATA[31:0]$3513 12/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3501_ADDR[7:0]$3512 Creating decoders for process `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.$proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3493'. 1/1: $0\led_ctrl[4:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:536$3487'. 1/1: $0\evt_cnt[3:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:656$3482'. Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:653$3480'. Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:643$3479'. 1/1: $0\pad_pu[0:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:636$3475'. 1/1: $0\rst_pending[0:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:628$3471'. 1/1: $0\timeout_reset[19:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:619$3467'. 1/1: $0\timeout_suspend[19:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:514$3453'. 1/1: $0\eps_bus_ack_wait[0:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:510$3450'. Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3440'. 1/3: $0\eps_bus_req[0:0] 2/3: $0\eps_bus_write[0:0] 3/3: $0\eps_bus_read[0:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:697$3491'. Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3438'. 1/4: $0\cr_addr[6:0] 2/4: $0\cr_addr_chk[0:0] 3/4: $0\cr_cel_ena[0:0] 4/4: $0\cr_pu_ena[0:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:442$3434'. 1/2: $2\csr_bus_dout[15:0] 2/2: $1\csr_bus_dout[15:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3416'. 1/7: $0\ir_bus_we[0:0] 2/7: $0\evt_rd_ack[0:0] 3/7: $0\sof_clear[0:0] 4/7: $0\rst_clear[0:0] 5/7: $0\cel_rel[0:0] 6/7: $0\cr_bus_we[0:0] 7/7: $0\csr_bus_req[0:0] Creating decoders for process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:99$3412'. 1/1: $0\m_cyc_i[0:0] Creating decoders for process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:83$3408'. Creating decoders for process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:73$3405'. 1/1: $0\s_rdata[15:0] Creating decoders for process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:68$3404'. 1/1: $0\m_rdata_i[15:0] Creating decoders for process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:0$5224'. Creating decoders for process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:0$5223'. Creating decoders for process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:214$5215'. 1/1: $0\sda_oe[0:0] Creating decoders for process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:204$5212'. 1/1: $0\scl_oe[0:0] Creating decoders for process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:159$5208'. 1/1: $0\data_reg[8:0] Creating decoders for process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:141$5204'. 1/1: $0\bit_cnt[3:0] Creating decoders for process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:129$5200'. 1/1: $0\cyc_cnt[4:0] Creating decoders for process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:121$5199'. 1/1: $0\cmd_cur[1:0] Creating decoders for process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:87$5194'. 1/7: $7\state_nxt[2:0] 2/7: $6\state_nxt[2:0] 3/7: $5\state_nxt[2:0] 4/7: $4\state_nxt[2:0] 5/7: $3\state_nxt[2:0] 6/7: $2\state_nxt[2:0] 7/7: $1\state_nxt[2:0] Creating decoders for process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:81$5193'. 1/1: $0\state[2:0] Creating decoders for process `$paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:133$5192'. 1/1: $0\out[7:0] Creating decoders for process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3321'. Creating decoders for process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3319'. Creating decoders for process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3317'. Creating decoders for process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:185$3316'. 1/1: $0\pb_rst_n[0:0] Creating decoders for process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:193$3302'. 1/1: $0\uart_div[11:0] Creating decoders for process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:185$3300'. 1/1: $0\ub_rdata[31:0] Creating decoders for process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:177$3290'. 1/1: $0\ub_ack[0:0] Creating decoders for process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3273'. 1/4: $0\ub_wr_div[0:0] 2/4: $0\ub_wr_data[0:0] 3/4: $0\ub_rd_ctrl[0:0] 4/4: $0\ub_rd_data[0:0] Creating decoders for process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:154$3268'. 1/1: $0\urf_overflow[0:0] Creating decoders for process `$paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master_wb.v:91$3263'. 1/1: $0\wb_rdata[31:0] Creating decoders for process `$paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master_wb.v:85$3255'. Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:291$3253'. 1/4: $0\srio_rclk_oe[0:0] 2/4: $0\srio_rclk_o[0:0] 3/4: $0\srio_dat_o[0:0] 4/4: $0\srio_clk_o[0:0] Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:279$3252'. 1/1: $0\shift_data[7:0] Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:270$3240'. Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:262$3233'. Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:243$3227'. Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:227$3220'. Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:214$3214'. Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:206$3213'. Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:197$3211'. Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:121$3199'. 1/9: $9\state_nxt[2:0] 2/9: $8\state_nxt[2:0] 3/9: $7\state_nxt[2:0] 4/9: $6\state_nxt[2:0] 5/9: $5\state_nxt[2:0] 6/9: $4\state_nxt[2:0] 7/9: $3\state_nxt[2:0] 8/9: $2\state_nxt[2:0] 9/9: $1\state_nxt[2:0] Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:114$3198'. 1/1: $0\state[2:0] Creating decoders for process `\hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:45$441'. 1/9: $0\d_neg[3:0] [3] 2/9: $0\d_pos[3:0] [3] 3/9: $0\d_neg[3:0] [2:1] 4/9: $0\d_neg[3:0] [0] 5/9: $0\d_pos[3:0] [0] 6/9: $0\zcnt[1:0] 7/9: $0\d_pos[3:0] [2:1] 8/9: $0\vstate[0:0] 9/9: $0\pstate[0:0] Creating decoders for process `\hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:41$440'. Creating decoders for process `\hdb3_dec.$proc$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:43$437'. 1/2: $0\pstate[0:0] 2/2: $0\data[3:0] Creating decoders for process `\hdb3_dec.$proc$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:37$432'. Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:248$246'. 1/2: $0\out_valid[0:0] 2/2: $0\out_bit[0:0] Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:236$244'. 1/1: $0\crc_smf[3:0] Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:224$243'. Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:204$231'. 1/3: $0\shift_at_crc[0:0] 2/3: $0\shift_at_last[0:0] 3/3: $0\shift_at_first[0:0] Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:194$228'. 1/1: $0\shift_data[7:0] Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:187$224'. 1/1: $0\bit_cnt[3:0] Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:167$220'. 1/1: $0\shift_data_nxt[7:0] Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:148$218'. 1/1: $0\fetch_done[0:0] Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:144$217'. Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:135$213'. 1/2: $0\in_mf_last[0:0] 2/2: $0\in_mf_first[0:0] Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:120$210'. 1/3: $0\fetch_ts_is31[0:0] 2/3: $0\fetch_ts_is0[0:0] 3/3: $0\fetch_ts[4:0] Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:113$208'. 1/1: $0\fetch_frame[3:0] Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:103$204'. Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:97$200'. 1/1: $0\tick_cnt[4:0] Creating decoders for process `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:71$163'. 1/3: $0\out_stb[0:0] 2/3: $0\out_lo[0:0] 3/3: $0\out_hi[0:0] Creating decoders for process `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:46$144'. 1/2: $0\cnt_lo[1:0] 2/2: $0\cnt_hi[1:0] Creating decoders for process `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:39$143'. Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:395$141'. 1/1: $0\aligned[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:360$135'. 1/7: $0\out_last[0:0] 2/7: $0\out_first[0:0] 3/7: $0\out_ts_is0[0:0] 4/7: $0\out_ts[4:0] 5/7: $0\out_frame[3:0] 6/7: $0\out_data[7:0] 7/7: $0\out_valid[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$127'. Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:339$109'. 1/4: $0\ec_mfa[1:0] 2/4: $0\ec_crc[1:0] 3/4: $0\ec_nfas[1:0] 4/4: $0\ec_fas[1:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:324$91'. 1/4: $0\ed_mfa[0:0] 2/4: $0\ep_mfa[0:0] 3/4: $0\ed_crc[0:0] 4/4: $0\ep_crc[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:310$69'. 1/4: $0\ed_nfas[0:0] 2/4: $0\ep_nfas[0:0] 3/4: $0\ed_fas[0:0] 4/4: $0\ep_fas[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:301$68'. 1/1: $0\crc_smf[3:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:269$57'. 1/3: $0\ts0_msbs_match_crc[0:0] 2/3: $0\ts0_msbs_match_mf[0:0] 3/3: $0\ts0_msbs[15:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:261$53'. 1/1: $0\mfa_timeout[6:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:253$49'. 1/1: $0\fas_pos[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:226$41'. 1/5: $0\frame_mf_last[0:0] 2/5: $0\frame_mf_first[0:0] 3/5: $0\frame_smf_last[0:0] 4/5: $0\frame_smf_first[0:0] 5/5: $0\frame[3:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:214$37'. 1/3: $0\ts_is_ts31[0:0] 2/3: $0\ts_is_ts0[0:0] 3/3: $0\ts[4:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:202$33'. 1/3: $0\bit_last[0:0] 2/3: $0\bit_first[0:0] 3/3: $0\bit[2:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:146$26'. 1/1: $0\fsm_state_nxt[2:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:139$24'. 1/1: $0\fsm_state[2:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:130$21'. 1/1: $0\data_match_fas[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:125$20'. 1/1: $0\data[7:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:118$19'. 1/1: $0\strobe[0:0] Creating decoders for process `\e1_rx_clock_recovery.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:39$17'. 1/1: $0\cnt[5:0] Creating decoders for process `\e1_rx_clock_recovery.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:33$15'. 1/1: $0\enabled[0:0] Creating decoders for process `\e1_crc4.$proc$/build/gateware/cores/no2e1//rtl/e1_crc4.v:38$13'. 1/1: $0\state[3:0] 75.3.7. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\cnt_move' from process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$5168'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\sel_nxt' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$5135'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\prio.i' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$5135'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\mux_addr' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5113'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\mux_wdata' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5113'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\mux_wmsk' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5113'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\mux.i' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5113'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\sel_nxt' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$5083'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\prio.i' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$5083'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\mux_addr' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5067'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\mux_wdata' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5067'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\mux_wmsk' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5067'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\mux.i' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5067'. No latch inferred for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\state_nxt' from process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:98$5009'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:92$4988$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$5000'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:92$4991$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$5000'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:92$4991$\sig' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$5000'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:91$4987$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4996'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:91$4990$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4996'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:91$4990$\sig' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4996'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:81$4986$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4992'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:81$4989$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4992'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:81$4989$\sig' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4992'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5521$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5563'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5530$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5563'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5530$\wdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5563'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5520$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5559'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5529$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5559'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5529$\rdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5559'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5519$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5555'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5528$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5555'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5528$\wdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5555'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5518$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5551'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5527$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5551'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5527$\rdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5551'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5517$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5547'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5526$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5547'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5526$\wdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5547'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5516$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5543'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5525$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5543'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5525$\rdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5543'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5515$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5539'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5524$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5539'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5524$\wdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5539'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5514$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5535'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5523$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5535'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5523$\rdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5535'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:220$5513$\ram_wr_shuffle_32' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5531'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:220$5522$\ram_wr_shuffle_32' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5531'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:220$5522$\src' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5531'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5466$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5508'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5475$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5508'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5475$\wdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5508'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5465$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5504'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5474$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5504'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5474$\rdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5504'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5464$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5500'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5473$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5500'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5473$\wdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5500'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5463$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5496'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5472$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5496'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5472$\rdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5496'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5462$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5492'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5471$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5492'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5471$\wdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5492'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5461$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5488'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5470$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5488'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5470$\rdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5488'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5460$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5484'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5469$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5484'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5469$\wdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5484'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5459$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5480'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5468$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5480'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5468$\rdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5480'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:211$5458$\ram_rd_shuffle_32' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5476'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:211$5467$\ram_rd_shuffle_32' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5476'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:211$5467$\src' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5476'. No latch inferred for signal `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.\wb_rdata_or' from process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:147$5417'. No latch inferred for signal `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.\wb_or.i' from process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:147$5417'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_do_m[0]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4806'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di[0]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4806'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di[1]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4806'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm[0]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4806'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm[1]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4806'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\rd_data' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\map.n' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\map.x' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\map.o' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650'. Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [0]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$16032 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [1]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$16147 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [2]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$16310 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [3]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$16521 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [4]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$16732 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [5]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$16943 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [6]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$17154 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [7]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$17365 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [8]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$17576 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [9]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$17787 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [10]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$17998 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [11]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$18209 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [12]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$18420 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [13]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$18631 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [14]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$18842 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [15]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$19053 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [16]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$19264 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [17]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$19475 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [18]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$19686 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [19]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$19897 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [20]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$20108 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [21]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$20319 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [22]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$20530 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [23]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$20741 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [24]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$20952 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [25]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$21163 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [26]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$21374 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [27]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$21585 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [28]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$21796 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [29]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$22007 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [30]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$22218 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [31]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$22429 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [0]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$22496 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [1]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$22563 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [2]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$22630 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [3]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$22697 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [4]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$22764 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [5]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$22831 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [6]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$22898 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [7]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650': $auto$proc_dlatch.cc:430:proc_dlatch$22965 No latch inferred for signal `\misc.$mem2bits$\pdm_e1$/build/gateware/icE1usb/rtl/misc.v:293$1613' from process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1648'. No latch inferred for signal `\misc.$mem2bits$\pdm_e1$/build/gateware/icE1usb/rtl/misc.v:293$1612' from process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1646'. No latch inferred for signal `\misc.$mem2bits$\pdm_e1$/build/gateware/icE1usb/rtl/misc.v:292$1611' from process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1644'. No latch inferred for signal `\misc.$mem2bits$\pdm_e1$/build/gateware/icE1usb/rtl/misc.v:292$1610' from process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1642'. No latch inferred for signal `\misc.$mem2bits$\pdm_clk$/build/gateware/icE1usb/rtl/misc.v:281$1609' from process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1640'. No latch inferred for signal `\misc.$mem2bits$\pdm_clk$/build/gateware/icE1usb/rtl/misc.v:281$1608' from process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1638'. No latch inferred for signal `\misc.$mem2bits$\pdm_clk$/build/gateware/icE1usb/rtl/misc.v:280$1607' from process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1636'. No latch inferred for signal `\misc.$mem2bits$\pdm_clk$/build/gateware/icE1usb/rtl/misc.v:280$1606' from process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1634'. No latch inferred for signal `\led_blinker.\led' from process `\led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:77$1592'. No latch inferred for signal `\led_blinker.\led_state_proc.i' from process `\led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:77$1592'. No latch inferred for signal `\usb_tx_pkt.\shift_load' from process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:159$1544'. No latch inferred for signal `\usb_tx_pkt.\state_nxt' from process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:86$1526'. No latch inferred for signal `\usb_rx_pkt.\state_nxt' from process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:117$1306'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[0]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4543'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[1]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4543'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[2]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4543'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[3]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4543'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[4]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4543'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[5]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4543'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[0]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4497'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[1]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4497'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[2]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4497'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[3]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4497'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[4]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4497'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[5]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4497'. No latch inferred for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.\bus_rdata_rx[1]' from process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:0$5373'. No latch inferred for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.\bus_rdata_tx[1]' from process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:0$5373'. No latch inferred for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.\bus_rdata' from process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:117$5363'. No latch inferred for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.\rdata_or.j' from process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:117$5363'. No latch inferred for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\cnt_move' from process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4378'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\t_done' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$5325'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$bitselwrite$mask$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:268$5283' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$5325'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$bitselwrite$data$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:268$5284' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$5325'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\t_nxt_busy' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$5285'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\t_nxt_chan' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$5285'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\next_sel.j' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$5285'. No latch inferred for signal `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.\cnt_move' from process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4294'. No latch inferred for signal `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm.\dither' from process `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:72$4270'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cpuregs_rs1' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$4077'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cpuregs_rs2' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$4077'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\decoded_rs' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$4077'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cpuregs_write' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1288$4063'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cpuregs_wrdata' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1288$4063'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\clear_prefetched_high_word' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1274$4058'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_out' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1228$4035'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_out_0' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1228$4035'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_ascii_state' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1165$4023'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_insn_opcode' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3761'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_ascii_instr' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3761'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_insn_imm' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3761'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_insn_rs1' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3761'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_insn_rs2' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3761'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_insn_rd' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3761'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\new_ascii_instr' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:684$3756'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_la_wdata' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3691'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_la_wstrb' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3691'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_rdata_word' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3691'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\pcpi_int_wr' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3612'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\pcpi_int_rd' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3612'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\pcpi_int_wait' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3612'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\pcpi_int_ready' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3612'. No latch inferred for signal `$paramod\usb\EPDW=32.\irq' from process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:697$3491'. No latch inferred for signal `$paramod\usb\EPDW=32.\csr_bus_dout' from process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:442$3434'. No latch inferred for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\scl_ir' from process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:0$5224'. No latch inferred for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\to_cnt' from process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:0$5223'. No latch inferred for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\to_latch' from process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:0$5223'. No latch inferred for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\state_nxt' from process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:87$5194'. No latch inferred for signal `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.\wb_rdata[3] [31:16]' from process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3321'. No latch inferred for signal `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.\wb_rdata[5]' from process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3321'. No latch inferred for signal `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.\wb_rdata[6]' from process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3321'. No latch inferred for signal `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.\wb_rdata[7] [31:16]' from process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3321'. No latch inferred for signal `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$mem2bits$\wb_rdata$/build/gateware/common/rtl/soc_base.v:499$3315' from process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3319'. No latch inferred for signal `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$mem2bits$\wb_rdata$/build/gateware/common/rtl/soc_base.v:402$3314' from process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3317'. No latch inferred for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\state_nxt' from process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:121$3199'. No latch inferred for signal `\e1_rx_deframer.\fsm_state_nxt' from process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:146$26'. 75.3.8. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$3058'. created $adff cell `$procdff$22966' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1274$3051'. created $dff cell `$procdff$22967' with negative edge clock. Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$3047'. created $adff cell `$procdff$22968' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1143$3040'. created $dff cell `$procdff$22969' with negative edge clock. Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1074$3037'. created $adff cell `$procdff$22970' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1026$3034'. created $dff cell `$procdff$22971' with negative edge clock. Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:957$3031'. created $adff cell `$procdff$22972' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:909$3028'. created $dff cell `$procdff$22973' with negative edge clock. Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:866$3026'. created $dff cell `$procdff$22974' with negative edge clock. Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:830$3024'. created $dff cell `$procdff$22975' with negative edge clock. Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$3020'. created $adff cell `$procdff$22976' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:697$3013'. created $dff cell `$procdff$22977' with positive edge clock. Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$3009'. created $adff cell `$procdff$22978' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:566$3002'. created $dff cell `$procdff$22979' with positive edge clock. Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:497$2999'. created $adff cell `$procdff$22980' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:449$2996'. created $dff cell `$procdff$22981' with positive edge clock. Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:380$2993'. created $adff cell `$procdff$22982' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:332$2990'. created $dff cell `$procdff$22983' with positive edge clock. Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:289$2988'. created $dff cell `$procdff$22984' with positive edge clock. Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:253$2986'. created $dff cell `$procdff$22985' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\sync' using process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$5189'. created $dff cell `$procdff$22986' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\rise' using process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$5184'. created $dff cell `$procdff$22987' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\fall' using process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$5184'. created $dff cell `$procdff$22988' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\state' using process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$5180'. created $dff cell `$procdff$22989' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\cnt' using process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$5176'. created $dff cell `$procdff$22990' with positive edge clock. Creating register for signal `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0.\ack_i' using process `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v:50$5165'. created $adff cell `$procdff$22991' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\sel' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5144'. created $adff cell `$procdff$22992' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\busy' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5144'. created $adff cell `$procdff$22993' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\m_addr' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5132'. created $adff cell `$procdff$22994' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\m_wdata' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5132'. created $adff cell `$procdff$22995' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\m_we' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5132'. created $adff cell `$procdff$22996' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\m_wmsk' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5132'. created $adff cell `$procdff$22997' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_epbuf\AW=9\DW=32.\ack_i' using process `$paramod\wb_epbuf\AW=9\DW=32.$proc$/build/gateware/common/rtl/wb_epbuf.v:51$5101'. created $adff cell `$procdff$22998' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\sel' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5090'. created $adff cell `$procdff$22999' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\busy' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5090'. created $adff cell `$procdff$23000' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\m_addr' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5080'. created $adff cell `$procdff$23001' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\m_wdata' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5080'. created $adff cell `$procdff$23002' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\m_we' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5080'. created $adff cell `$procdff$23003' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\m_wmsk' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5080'. created $adff cell `$procdff$23004' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\ctl_do_write' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$5048'. created $adff cell `$procdff$23005' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\ctl_do_read' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$5048'. created $adff cell `$procdff$23006' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\ctl_ack_i' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$5048'. created $adff cell `$procdff$23007' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\dir' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:178$5044'. created $dff cell `$procdff$23008' with positive edge clock. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\len' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:174$5041'. created $dff cell `$procdff$23009' with positive edge clock. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\m1_addr_i' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:157$5031'. created $dff cell `$procdff$23010' with positive edge clock. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\m0_addr_i' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:153$5027'. created $dff cell `$procdff$23011' with positive edge clock. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\data_reg' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:142$5025'. created $dff cell `$procdff$23012' with positive edge clock. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\state' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:92$5008'. created $adff cell `$procdff$23013' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\go' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:86$5004'. created $adff cell `$procdff$23014' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100.\state' using process `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4962'. created $dff cell `$procdff$23015' with positive edge clock. Creating register for signal `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101.\state' using process `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4949'. created $dff cell `$procdff$23016' with positive edge clock. Creating register for signal `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.\dp_state' using process `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4925'. created $adff cell `$procdff$23017' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.\dn_state' using process `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4925'. created $adff cell `$procdff$23018' with positive edge clock and positive level reset. Creating register for signal `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.\rd_data' using process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5452'. created $dff cell `$procdff$23019' with positive edge clock. Creating register for signal `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_ADDR' using process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5452'. created $dff cell `$procdff$23020' with positive edge clock. Creating register for signal `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_DATA' using process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5452'. created $dff cell `$procdff$23021' with positive edge clock. Creating register for signal `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN' using process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5452'. created $dff cell `$procdff$23022' with positive edge clock. Creating register for signal `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.\wb_rdata_reg' using process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:163$5446'. created $dff cell `$procdff$23023' with positive edge clock. Creating register for signal `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.\wb_rdy_reg' using process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:160$5444'. created $dff cell `$procdff$23024' with positive edge clock. Creating register for signal `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.\ram_rdy' using process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:91$5414'. created $dff cell `$procdff$23025' with positive edge clock. Creating register for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\addr_r' using process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:73$4649'. created $dff cell `$procdff$23026' with positive edge clock. Creating register for signal `$paramod\e1_wb_rx\LIU=0\MFW=7.\tx_crc_e_auto' using process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:253$4632'. created $dff cell `$procdff$23027' with positive edge clock. Creating register for signal `$paramod\e1_wb_rx\LIU=0\MFW=7.\rx_overflow' using process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:246$4628'. created $adff cell `$procdff$23028' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_rx\LIU=0\MFW=7.\rx_rst' using process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:239$4626'. created $adff cell `$procdff$23029' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_rx\LIU=0\MFW=7.\bri_wren' using process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$4608'. created $dff cell `$procdff$23030' with positive edge clock. Creating register for signal `$paramod\e1_wb_rx\LIU=0\MFW=7.\bro_rden' using process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$4608'. created $dff cell `$procdff$23031' with positive edge clock. Creating register for signal `$paramod\e1_wb_rx\LIU=0\MFW=7.\rx_enabled' using process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$4607'. created $adff cell `$procdff$23032' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_rx\LIU=0\MFW=7.\rx_mode' using process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$4607'. created $adff cell `$procdff$23033' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_rx\LIU=0\MFW=7.\crx_wren' using process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$4599'. created $dff cell `$procdff$23034' with positive edge clock. Creating register for signal `$paramod\e1_wb_rx\LIU=0\MFW=7.\crx_clear' using process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$4599'. created $dff cell `$procdff$23035' with positive edge clock. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\tx_underflow' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:265$4593'. created $adff cell `$procdff$23036' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\tx_rst' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:258$4591'. created $adff cell `$procdff$23037' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\bti_wren' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:152$4568'. created $dff cell `$procdff$23038' with positive edge clock. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\bto_rden' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:152$4568'. created $dff cell `$procdff$23039' with positive edge clock. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\tx_enabled' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:122$4567'. created $adff cell `$procdff$23040' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\tx_mode' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:122$4567'. created $adff cell `$procdff$23041' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\tx_time_src' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:122$4567'. created $adff cell `$procdff$23042' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\tx_alarm' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:122$4567'. created $adff cell `$procdff$23043' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\tx_loopback' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:122$4567'. created $adff cell `$procdff$23044' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\ctx_wren' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:112$4559'. created $dff cell `$procdff$23045' with positive edge clock. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\ctx_clear' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:112$4559'. created $dff cell `$procdff$23046' with positive edge clock. Creating register for signal `\sysmgr.\rst_48m_i' using process `\sysmgr.$proc$/build/gateware/icE1usb/rtl/sysmgr.v:84$1713'. created $adff cell `$procdff$23047' with positive edge clock and positive level reset. Creating register for signal `\sysmgr.\rst_cnt' using process `\sysmgr.$proc$/build/gateware/icE1usb/rtl/sysmgr.v:76$1708'. created $adff cell `$procdff$23048' with positive edge clock and negative level reset. Creating register for signal `$paramod\e1_tx\LIU=0\MFW=7.\pg_hi' using process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:160$4554'. created $dff cell `$procdff$23049' with positive edge clock. Creating register for signal `$paramod\e1_tx\LIU=0\MFW=7.\pg_lo' using process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:160$4554'. created $dff cell `$procdff$23050' with positive edge clock. Creating register for signal `$paramod\e1_tx\LIU=0\MFW=7.\bd_done' using process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:100$4546'. created $dff cell `$procdff$23051' with positive edge clock. Creating register for signal `$paramod\e1_tx\LIU=0\MFW=7.\bd_miss' using process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:100$4546'. created $dff cell `$procdff$23052' with positive edge clock. Creating register for signal `$paramod\e1_tx\LIU=0\MFW=7.\mf_valid' using process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:93$4544'. created $adff cell `$procdff$23053' with positive edge clock and positive level reset. Creating register for signal `\misc.\boot_sel' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:302$1633'. created $adff cell `$procdff$23054' with positive edge clock and positive level reset. Creating register for signal `\misc.\boot_now' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:302$1633'. created $adff cell `$procdff$23055' with positive edge clock and positive level reset. Creating register for signal `\misc.\pdm_clk[0]' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:260$1632'. created $adff cell `$procdff$23056' with positive edge clock and positive level reset. Creating register for signal `\misc.\pdm_clk[1]' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:260$1632'. created $adff cell `$procdff$23057' with positive edge clock and positive level reset. Creating register for signal `\misc.\pdm_e1[0]' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:260$1632'. created $adff cell `$procdff$23058' with positive edge clock and positive level reset. Creating register for signal `\misc.\pdm_e1[1]' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:260$1632'. created $adff cell `$procdff$23059' with positive edge clock and positive level reset. Creating register for signal `\misc.\e1_led' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:183$1631'. created $adff cell `$procdff$23060' with positive edge clock and positive level reset. Creating register for signal `\misc.\gpio_oe' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:170$1630'. created $adff cell `$procdff$23061' with positive edge clock and positive level reset. Creating register for signal `\misc.\gpio_out' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:170$1630'. created $adff cell `$procdff$23062' with positive edge clock and positive level reset. Creating register for signal `\misc.\wb_rdata' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:130$1629'. created $dff cell `$procdff$23063' with positive edge clock. Creating register for signal `\misc.\bus_we_boot' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:110$1619'. created $dff cell `$procdff$23064' with positive edge clock. Creating register for signal `\misc.\bus_we_gpio' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:110$1619'. created $dff cell `$procdff$23065' with positive edge clock. Creating register for signal `\misc.\bus_we_led' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:110$1619'. created $dff cell `$procdff$23066' with positive edge clock. Creating register for signal `\misc.\bus_we_pdm_clk' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:110$1619'. created $dff cell `$procdff$23067' with positive edge clock. Creating register for signal `\misc.\bus_we_pdm_e1' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:110$1619'. created $dff cell `$procdff$23068' with positive edge clock. Creating register for signal `\misc.\wb_ack' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:104$1614'. created $dff cell `$procdff$23069' with positive edge clock. Creating register for signal `\led_blinker.\sr_go' using process `\led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:89$1601'. created $adff cell `$procdff$23070' with positive edge clock and positive level reset. Creating register for signal `\led_blinker.\cycle' using process `\led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:65$1588'. created $dff cell `$procdff$23071' with positive edge clock. Creating register for signal `\led_blinker.\tick_cnt' using process `\led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:55$1584'. created $dff cell `$procdff$23072' with positive edge clock. Creating register for signal `\usb_tx_pkt.\pkt_done' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:241$1576'. created $dff cell `$procdff$23073' with positive edge clock. Creating register for signal `\usb_tx_pkt.\pkt_data_ack' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:241$1576'. created $dff cell `$procdff$23074' with positive edge clock. Creating register for signal `\usb_tx_pkt.\ll_start' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:229$1573'. created $dff cell `$procdff$23075' with positive edge clock. Creating register for signal `\usb_tx_pkt.\crc_in_first' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:202$1567'. created $dff cell `$procdff$23076' with positive edge clock. Creating register for signal `\usb_tx_pkt.\len' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:191$1563'. created $dff cell `$procdff$23077' with positive edge clock. Creating register for signal `\usb_tx_pkt.\shift_new_bit' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:182$1557'. created $dff cell `$procdff$23078' with positive edge clock. Creating register for signal `\usb_tx_pkt.\shift_data_crc' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:175$1550'. created $dff cell `$procdff$23079' with positive edge clock. Creating register for signal `\usb_tx_pkt.\shift_last_byte' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:175$1550'. created $dff cell `$procdff$23080' with positive edge clock. Creating register for signal `\usb_tx_pkt.\shift_data' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:170$1548'. created $dff cell `$procdff$23081' with positive edge clock. Creating register for signal `\usb_tx_pkt.\shift_bit' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:152$1541'. created $dff cell `$procdff$23082' with positive edge clock. Creating register for signal `\usb_tx_pkt.\pid_is_handshake' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:136$1529'. created $dff cell `$procdff$23083' with positive edge clock. Creating register for signal `\usb_tx_pkt.\state' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:126$1528'. created $adff cell `$procdff$23084' with positive edge clock and positive level reset. Creating register for signal `\usb_tx_ll.\out_active' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:134$1525'. created $dff cell `$procdff$23085' with positive edge clock. Creating register for signal `\usb_tx_ll.\out_sym' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1523'. created $adff cell `$procdff$23086' with positive edge clock and positive level reset. Creating register for signal `\usb_tx_ll.\ll_ack' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:110$1516'. created $dff cell `$procdff$23087' with positive edge clock. Creating register for signal `\usb_tx_ll.\lvl_prev' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:102$1511'. created $dff cell `$procdff$23088' with positive edge clock. Creating register for signal `\usb_tx_ll.\bs_cnt' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1501'. created $adff cell `$procdff$23089' with positive edge clock and positive level reset. Creating register for signal `\usb_tx_ll.\bs_now' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1501'. created $adff cell `$procdff$23090' with positive edge clock and positive level reset. Creating register for signal `\usb_tx_ll.\br_cnt' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:79$1498'. created $dff cell `$procdff$23091' with positive edge clock. Creating register for signal `\usb_tx_ll.\state' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1495'. created $adff cell `$procdff$23092' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\pkt_pid' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:236$1491'. created $dff cell `$procdff$23093' with positive edge clock. Creating register for signal `\usb_trans.\xfer_length' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:428$1483'. created $dff cell `$procdff$23094' with positive edge clock. Creating register for signal `\usb_trans.\bd_length' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:421$1480'. created $dff cell `$procdff$23095' with positive edge clock. Creating register for signal `\usb_trans.\addr' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:414$1474'. created $dff cell `$procdff$23096' with positive edge clock. Creating register for signal `\usb_trans.\txpkt_start_i' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:403$1473'. created $dff cell `$procdff$23097' with positive edge clock. Creating register for signal `\usb_trans.\txpkt_pid' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:399$1470'. created $dff cell `$procdff$23098' with positive edge clock. Creating register for signal `\usb_trans.\cel_state_i' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:387$1464'. created $adff cell `$procdff$23099' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\epfw_issue_wb' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:380$1462'. created $dff cell `$procdff$23100' with positive edge clock. Creating register for signal `\usb_trans.\ep_type' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1449'. created $dff cell `$procdff$23101' with positive edge clock. Creating register for signal `\usb_trans.\ep_bd_dual' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1449'. created $dff cell `$procdff$23102' with positive edge clock. Creating register for signal `\usb_trans.\ep_bd_ctrl' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1449'. created $dff cell `$procdff$23103' with positive edge clock. Creating register for signal `\usb_trans.\ep_bd_idx_cur' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1449'. created $dff cell `$procdff$23104' with positive edge clock. Creating register for signal `\usb_trans.\ep_bd_idx_nxt' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1449'. created $dff cell `$procdff$23105' with positive edge clock. Creating register for signal `\usb_trans.\ep_data_toggle' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1449'. created $dff cell `$procdff$23106' with positive edge clock. Creating register for signal `\usb_trans.\bd_state' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1449'. created $dff cell `$procdff$23107' with positive edge clock. Creating register for signal `\usb_trans.\epfw_cap_dl' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:345$1446'. created $adff cell `$procdff$23108' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\epfw_state' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1441'. created $adff cell `$procdff$23109' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\trans_is_setup' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1437'. created $dff cell `$procdff$23110' with positive edge clock. Creating register for signal `\usb_trans.\trans_endp' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1437'. created $dff cell `$procdff$23111' with positive edge clock. Creating register for signal `\usb_trans.\trans_dir' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1437'. created $dff cell `$procdff$23112' with positive edge clock. Creating register for signal `\usb_trans.\trans_cel' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1437'. created $dff cell `$procdff$23113' with positive edge clock. Creating register for signal `\usb_trans.\rto_cnt' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1430'. created $adff cell `$procdff$23114' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\evt' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:225$1425'. created $adff cell `$procdff$23115' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\mc_a_reg' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1422'. created $dff cell `$procdff$23116' with positive edge clock. Creating register for signal `\usb_trans.\mc_pc_nxt' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:175$1413'. created $adff cell `$procdff$23117' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\mc_rst_n' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:162$1404'. created $adff cell `$procdff$23118' with positive edge clock and positive level reset. Creating register for signal `\usb_rx_pkt.\pkt_data_stb' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:374$1401'. created $dff cell `$procdff$23119' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pkt_done_ok' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:353$1392'. created $dff cell `$procdff$23120' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pkt_done_err' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:353$1392'. created $dff cell `$procdff$23121' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pkt_start' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:349$1390'. created $dff cell `$procdff$23122' with positive edge clock. Creating register for signal `\usb_rx_pkt.\token_data [10:8]' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:340$1387'. created $dff cell `$procdff$23123' with positive edge clock. Creating register for signal `\usb_rx_pkt.\token_data [7:0]' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:336$1384'. created $dff cell `$procdff$23124' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1367'. created $dff cell `$procdff$23125' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_is_sof' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1367'. created $dff cell `$procdff$23126' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_is_token' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1367'. created $dff cell `$procdff$23127' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_is_data' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1367'. created $dff cell `$procdff$23128' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_is_handshake' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1367'. created $dff cell `$procdff$23129' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_cap_r' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:318$1366'. created $dff cell `$procdff$23130' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_valid' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:304$1345'. created $dff cell `$procdff$23131' with positive edge clock. Creating register for signal `\usb_rx_pkt.\crc5_ok' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1341'. created $dff cell `$procdff$23132' with positive edge clock. Creating register for signal `\usb_rx_pkt.\crc16_ok' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1341'. created $dff cell `$procdff$23133' with positive edge clock. Creating register for signal `\usb_rx_pkt.\crc_cap' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:284$1340'. created $dff cell `$procdff$23134' with positive edge clock. Creating register for signal `\usb_rx_pkt.\crc_in_first' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:244$1338'. created $dff cell `$procdff$23135' with positive edge clock. Creating register for signal `\usb_rx_pkt.\bit_eop_ok' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:230$1335'. created $dff cell `$procdff$23136' with positive edge clock. Creating register for signal `\usb_rx_pkt.\bit_cnt' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:220$1332'. created $dff cell `$procdff$23137' with positive edge clock. Creating register for signal `\usb_rx_pkt.\data' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:215$1331'. created $dff cell `$procdff$23138' with positive edge clock. Creating register for signal `\usb_rx_pkt.\state_prev_idle' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:198$1323'. created $dff cell `$procdff$23139' with positive edge clock. Creating register for signal `\usb_rx_pkt.\state_prev_error' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:198$1323'. created $dff cell `$procdff$23140' with positive edge clock. Creating register for signal `\usb_rx_pkt.\state' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:188$1322'. created $adff cell `$procdff$23141' with positive edge clock and positive level reset. Creating register for signal `\usb_rx_ll.\dec_bs_skip_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:181$1303'. created $dff cell `$procdff$23142' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_rep_state_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1301'. created $dff cell `$procdff$23143' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_sync_state_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:137$1300'. created $dff cell `$procdff$23144' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_eop_state_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:124$1299'. created $dff cell `$procdff$23145' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_valid_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:120$1298'. created $dff cell `$procdff$23146' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_sym_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:111$1291'. created $dff cell `$procdff$23147' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_bit_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:111$1291'. created $dff cell `$procdff$23148' with positive edge clock. Creating register for signal `\usb_rx_ll.\samp_valid_0' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:97$1284'. created $dff cell `$procdff$23149' with positive edge clock. Creating register for signal `\usb_rx_ll.\samp_cnt' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1283'. created $dff cell `$procdff$23150' with positive edge clock. Creating register for signal `\usb_rx_ll.\samp_active' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:67$1273'. created $adff cell `$procdff$23151' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[4].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4534'. created $adff cell `$procdff$23152' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[4].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4532'. created $adff cell `$procdff$23153' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[3].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4523'. created $adff cell `$procdff$23154' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[3].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4521'. created $adff cell `$procdff$23155' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[2].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4512'. created $adff cell `$procdff$23156' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[2].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4510'. created $adff cell `$procdff$23157' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[1].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4501'. created $adff cell `$procdff$23158' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[1].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4499'. created $adff cell `$procdff$23159' with positive edge clock and positive level reset. Creating register for signal `\usb_ep_status.\s_dout_3' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:80$1269'. created $dff cell `$procdff$23160' with positive edge clock. Creating register for signal `\usb_ep_status.\p_dout_3' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:76$1267'. created $dff cell `$procdff$23161' with positive edge clock. Creating register for signal `\usb_ep_status.\p_read_2' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1264'. created $dff cell `$procdff$23162' with positive edge clock. Creating register for signal `\usb_ep_status.\p_zero_2' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1264'. created $dff cell `$procdff$23163' with positive edge clock. Creating register for signal `\usb_ep_status.\s_read_2' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1264'. created $dff cell `$procdff$23164' with positive edge clock. Creating register for signal `\usb_ep_status.\s_zero_2' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1264'. created $dff cell `$procdff$23165' with positive edge clock. Creating register for signal `\usb_ep_status.\addr_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1256'. created $dff cell `$procdff$23166' with positive edge clock. Creating register for signal `\usb_ep_status.\din_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1256'. created $dff cell `$procdff$23167' with positive edge clock. Creating register for signal `\usb_ep_status.\we_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1256'. created $dff cell `$procdff$23168' with positive edge clock. Creating register for signal `\usb_ep_status.\p_read_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1256'. created $dff cell `$procdff$23169' with positive edge clock. Creating register for signal `\usb_ep_status.\p_zero_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1256'. created $dff cell `$procdff$23170' with positive edge clock. Creating register for signal `\usb_ep_status.\s_read_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1256'. created $dff cell `$procdff$23171' with positive edge clock. Creating register for signal `\usb_ep_status.\s_zero_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1256'. created $dff cell `$procdff$23172' with positive edge clock. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[4].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4488'. created $adff cell `$procdff$23173' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[4].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4486'. created $adff cell `$procdff$23174' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[3].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4477'. created $adff cell `$procdff$23175' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[3].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4475'. created $adff cell `$procdff$23176' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[2].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4466'. created $adff cell `$procdff$23177' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[2].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4464'. created $adff cell `$procdff$23178' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[1].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4455'. created $adff cell `$procdff$23179' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[1].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4453'. created $adff cell `$procdff$23180' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_rx\LIU=0\MFW=7.\bd_crc_e' using process `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:199$4442'. created $adff cell `$procdff$23181' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_rx\LIU=0\MFW=7.\bd_done' using process `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:192$4436'. created $dff cell `$procdff$23182' with positive edge clock. Creating register for signal `$paramod\e1_rx\LIU=0\MFW=7.\bd_miss' using process `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:192$4436'. created $dff cell `$procdff$23183' with positive edge clock. Creating register for signal `$paramod\e1_rx\LIU=0\MFW=7.\mf_valid' using process `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:184$4432'. created $adff cell `$procdff$23184' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.\wb_rdata' using process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:125$5368'. created $dff cell `$procdff$23185' with positive edge clock. Creating register for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.\wb_ack' using process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:106$5358'. created $dff cell `$procdff$23186' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\sync' using process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4399'. created $dff cell `$procdff$23187' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\rise' using process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4394'. created $dff cell `$procdff$23188' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\fall' using process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4394'. created $dff cell `$procdff$23189' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\state' using process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4390'. created $dff cell `$procdff$23190' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\cnt' using process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4386'. created $dff cell `$procdff$23191' with positive edge clock. Creating register for signal `\xclk_strobe.\out_stb' using process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:40$1101'. created $adff cell `$procdff$23192' with positive edge clock and positive level reset. Creating register for signal `\xclk_strobe.\dst' using process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:34$1100'. created $adff cell `$procdff$23193' with positive edge clock and positive level reset. Creating register for signal `\xclk_strobe.\src' using process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:28$1098'. created $adff cell `$procdff$23194' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\tx_pending [1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5349'. created $dff cell `$procdff$23195' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\tx_addr_reg[1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5349'. created $dff cell `$procdff$23196' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\tx_data_reg[1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5349'. created $dff cell `$procdff$23197' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\tx_data_reg[0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:163$5348'. created $dff cell `$procdff$23198' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\tx_pending [0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:153$5343'. created $adff cell `$procdff$23199' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\tx_addr_reg[0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:143$5342'. created $dff cell `$procdff$23200' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\rx_pending [1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:123$5341'. created $dff cell `$procdff$23201' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\rx_data_reg[1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:123$5341'. created $dff cell `$procdff$23202' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\rx_addr_reg[1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:123$5341'. created $dff cell `$procdff$23203' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\rx_pending [0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5336'. created $adff cell `$procdff$23204' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\rx_data_reg[0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5335'. created $dff cell `$procdff$23205' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\rx_addr_reg[0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5335'. created $dff cell `$procdff$23206' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\wb_addr' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5292'. created $dff cell `$procdff$23207' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\wb_addr_lsb' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5292'. created $dff cell `$procdff$23208' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\wb_wdata_byte' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5292'. created $dff cell `$procdff$23209' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\mux.j' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5292'. created $dff cell `$procdff$23210' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$5269' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5292'. created $dff cell `$procdff$23211' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$5270' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5292'. created $dff cell `$procdff$23212' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$5271' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5292'. created $dff cell `$procdff$23213' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$5272' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5292'. created $dff cell `$procdff$23214' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$5275' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5292'. created $dff cell `$procdff$23215' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$5276' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5292'. created $dff cell `$procdff$23216' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$5277' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5292'. created $dff cell `$procdff$23217' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$5278' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5292'. created $dff cell `$procdff$23218' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\t_chan' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:212$5289'. created $dff cell `$procdff$23219' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\t_busy' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:206$5287'. created $adff cell `$procdff$23220' with positive edge clock and positive level reset. Creating register for signal `$paramod\uart_tx\DIV_WIDTH=12.\ack' using process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:67$5258'. created $dff cell `$procdff$23221' with positive edge clock. Creating register for signal `$paramod\uart_tx\DIV_WIDTH=12.\shift' using process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5257'. created $adff cell `$procdff$23222' with positive edge clock and positive level reset. Creating register for signal `$paramod\uart_tx\DIV_WIDTH=12.\bit_cnt' using process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:51$5254'. created $dff cell `$procdff$23223' with positive edge clock. Creating register for signal `$paramod\uart_tx\DIV_WIDTH=12.\div_cnt' using process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:42$5250'. created $dff cell `$procdff$23224' with positive edge clock. Creating register for signal `$paramod\uart_tx\DIV_WIDTH=12.\active' using process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:35$5246'. created $adff cell `$procdff$23225' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.\rd_valid' using process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4339'. created $adff cell `$procdff$23226' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.\ram_rd_addr' using process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4333'. created $adff cell `$procdff$23227' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.\ram_wr_addr' using process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4331'. created $adff cell `$procdff$23228' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.\full' using process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:83$4322'. created $adff cell `$procdff$23229' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.\level' using process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:67$4316'. created $adff cell `$procdff$23230' with positive edge clock and positive level reset. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.\sync' using process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4315'. created $dff cell `$procdff$23231' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.\rise' using process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4310'. created $dff cell `$procdff$23232' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.\fall' using process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4310'. created $dff cell `$procdff$23233' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.\state' using process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4306'. created $dff cell `$procdff$23234' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.\cnt' using process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4302'. created $dff cell `$procdff$23235' with positive edge clock. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.\wb_now' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:149$4293'. created $adff cell `$procdff$23236' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.\rst_req' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4284'. created $adff cell `$procdff$23237' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.\wb_sel' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4284'. created $adff cell `$procdff$23238' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.\wb_req' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4284'. created $adff cell `$procdff$23239' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.\timer' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:109$4280'. created $adff cell `$procdff$23240' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.\armed' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:103$4278'. created $adff cell `$procdff$23241' with positive edge clock and positive level reset. Creating register for signal `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm.\dither' using process `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:67$4274'. created $dff cell `$procdff$23242' with positive edge clock. Creating register for signal `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm.\acc' using process `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:42$4271'. created $dff cell `$procdff$23243' with positive edge clock. Creating register for signal `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm.\acc' using process `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:42$4267'. created $dff cell `$procdff$23244' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\timer' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23245' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\trap' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23246' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\pcpi_valid' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23247' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\eoi' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23248' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\trace_valid' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23249' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\trace_data' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23250' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\count_cycle' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23251' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\count_instr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23252' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\reg_pc' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23253' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\reg_next_pc' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23254' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\reg_op1' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23255' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\reg_op2' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23256' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\reg_out' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23257' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\reg_sh' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23258' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\irq_delay' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23259' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\irq_active' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23260' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\irq_mask' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23261' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\irq_pending' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23262' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_wordsize' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23263' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_do_prefetch' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23264' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_do_rinst' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23265' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_do_rdata' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23266' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_do_wdata' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23267' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\decoder_trigger' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23268' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\decoder_trigger_q' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23269' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\decoder_pseudo_trigger' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23270' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\decoder_pseudo_trigger_q' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23271' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_rs1val' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23272' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_rs2val' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23273' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_rs1val_valid' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23274' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_rs2val_valid' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23275' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cpu_state' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23276' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\irq_state' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23277' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\set_mem_do_rinst' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23278' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\set_mem_do_rdata' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23279' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\set_mem_do_wdata' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23280' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\latched_store' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23281' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\latched_stalu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23282' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\latched_branch' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23283' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\latched_compr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23284' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\latched_trace' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23285' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\latched_is_lu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23286' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\latched_is_lh' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23287' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\latched_is_lb' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23288' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\latched_rd' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23289' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\current_pc' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23290' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\pcpi_timeout' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23291' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\next_irq_pending' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23292' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\do_waitirq' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23293' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_out_q' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23294' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_out_0_q' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23295' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_wait' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23296' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_wait_2' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. created $dff cell `$procdff$23297' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\clear_prefetched_high_word_q' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1272$4057'. created $dff cell `$procdff$23298' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\pcpi_insn' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23299' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_lui' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23300' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_auipc' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23301' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_jal' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23302' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_jalr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23303' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_beq' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23304' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_bne' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23305' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_blt' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23306' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_bge' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23307' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_bltu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23308' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_bgeu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23309' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_lb' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23310' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_lh' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23311' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_lw' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23312' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_lbu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23313' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_lhu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23314' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_sb' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23315' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_sh' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23316' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_sw' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23317' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_addi' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23318' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_slti' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23319' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_sltiu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23320' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_xori' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23321' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_ori' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23322' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_andi' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23323' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_slli' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23324' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_srli' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23325' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_srai' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23326' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_add' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23327' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_sub' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23328' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_sll' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23329' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_slt' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23330' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_sltu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23331' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_xor' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23332' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_srl' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23333' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_sra' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23334' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_or' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23335' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_and' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23336' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_rdcycle' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23337' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_rdcycleh' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23338' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_rdinstr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23339' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_rdinstrh' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23340' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_ecall_ebreak' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23341' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_getq' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23342' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_setq' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23343' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_retirq' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23344' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_maskirq' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23345' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_waitirq' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23346' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_timer' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23347' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\decoded_rd' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23348' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\decoded_rs1' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23349' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\decoded_rs2' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23350' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\decoded_imm' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23351' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\decoded_imm_uj' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23352' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\compressed_instr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23353' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_lui_auipc_jal' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23354' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_lb_lh_lw_lbu_lhu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23355' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_slli_srli_srai' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23356' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_jalr_addi_slti_sltiu_xori_ori_andi' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23357' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_sb_sh_sw' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23358' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_sll_srl_sra' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23359' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_lui_auipc_jal_jalr_addi_add_sub' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23360' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_slti_blt_slt' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23361' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_sltiu_bltu_sltu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23362' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_beq_bne_blt_bge_bltu_bgeu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23363' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_lbu_lhu_lw' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23364' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_alu_reg_imm' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23365' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_alu_reg_reg' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23366' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_compare' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. created $dff cell `$procdff$23367' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_insn_addr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3757'. created $dff cell `$procdff$23368' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\q_ascii_instr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3757'. created $dff cell `$procdff$23369' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\q_insn_imm' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3757'. created $dff cell `$procdff$23370' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\q_insn_opcode' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3757'. created $dff cell `$procdff$23371' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\q_insn_rs1' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3757'. created $dff cell `$procdff$23372' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\q_insn_rs2' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3757'. created $dff cell `$procdff$23373' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\q_insn_rd' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3757'. created $dff cell `$procdff$23374' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_next' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3757'. created $dff cell `$procdff$23375' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_valid_insn' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3757'. created $dff cell `$procdff$23376' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cached_ascii_instr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3757'. created $dff cell `$procdff$23377' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cached_insn_imm' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3757'. created $dff cell `$procdff$23378' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cached_insn_opcode' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3757'. created $dff cell `$procdff$23379' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cached_insn_rs1' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3757'. created $dff cell `$procdff$23380' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cached_insn_rs2' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3757'. created $dff cell `$procdff$23381' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cached_insn_rd' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3757'. created $dff cell `$procdff$23382' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_addr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3732'. created $dff cell `$procdff$23383' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_valid' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3732'. created $dff cell `$procdff$23384' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_instr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3732'. created $dff cell `$procdff$23385' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_wdata' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3732'. created $dff cell `$procdff$23386' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_wstrb' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3732'. created $dff cell `$procdff$23387' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_state' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3732'. created $dff cell `$procdff$23388' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_la_secondword' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3732'. created $dff cell `$procdff$23389' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\prefetched_high_word' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3732'. created $dff cell `$procdff$23390' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_16bit_buffer' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3732'. created $dff cell `$procdff$23391' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_add_sub' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1209$4256'. created $dff cell `$procdff$23392' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_shl' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1209$4256'. created $dff cell `$procdff$23393' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_shr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1209$4256'. created $dff cell `$procdff$23394' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_eq' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1209$4256'. created $dff cell `$procdff$23395' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_ltu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1209$4256'. created $dff cell `$procdff$23396' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_lts' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1209$4256'. created $dff cell `$procdff$23397' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\next_insn_opcode' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:414$3694'. created $dff cell `$procdff$23398' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_rdata_q' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:414$3694'. created $dff cell `$procdff$23399' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_la_firstword_reg' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:374$3686'. created $dff cell `$procdff$23400' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\last_mem_valid' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:374$3686'. created $dff cell `$procdff$23401' with positive edge clock. Creating register for signal `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.\stb' using process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:102$5240'. created $dff cell `$procdff$23402' with positive edge clock. Creating register for signal `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.\shift' using process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:95$5239'. created $dff cell `$procdff$23403' with positive edge clock. Creating register for signal `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.\bit_cnt' using process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:88$5236'. created $dff cell `$procdff$23404' with positive edge clock. Creating register for signal `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.\div_cnt' using process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:77$5232'. created $dff cell `$procdff$23405' with positive edge clock. Creating register for signal `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.\active' using process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:70$5228'. created $adff cell `$procdff$23406' with positive edge clock and positive level reset. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.\rdata' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3502'. created $dff cell `$procdff$23407' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3498_ADDR' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3502'. created $dff cell `$procdff$23408' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3498_DATA' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3502'. created $dff cell `$procdff$23409' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3498_EN' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3502'. created $dff cell `$procdff$23410' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3499_ADDR' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3502'. created $dff cell `$procdff$23411' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3499_DATA' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3502'. created $dff cell `$procdff$23412' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3499_EN' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3502'. created $dff cell `$procdff$23413' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3500_ADDR' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3502'. created $dff cell `$procdff$23414' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3500_DATA' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3502'. created $dff cell `$procdff$23415' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3500_EN' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3502'. created $dff cell `$procdff$23416' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3501_ADDR' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3502'. created $dff cell `$procdff$23417' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3501_DATA' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3502'. created $dff cell `$procdff$23418' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3501_EN' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3502'. created $dff cell `$procdff$23419' with positive edge clock. Creating register for signal `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.\led_ctrl' using process `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.$proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3493'. created $adff cell `$procdff$23420' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\evt_cnt' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:536$3487'. created $adff cell `$procdff$23421' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\sof_pending' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:656$3482'. created $dff cell `$procdff$23422' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\sof_ind' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:653$3480'. created $dff cell `$procdff$23423' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\pad_pu' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:643$3479'. created $dff cell `$procdff$23424' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\rst_pending' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:636$3475'. created $adff cell `$procdff$23425' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\timeout_reset' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:628$3471'. created $dff cell `$procdff$23426' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\timeout_suspend' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:619$3467'. created $dff cell `$procdff$23427' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\eps_bus_ack_wait' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:514$3453'. created $adff cell `$procdff$23428' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\eps_bus_req_ok_dly' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:510$3450'. created $dff cell `$procdff$23429' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\eps_bus_read' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3440'. created $dff cell `$procdff$23430' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\eps_bus_write' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3440'. created $dff cell `$procdff$23431' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\eps_bus_req' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3440'. created $dff cell `$procdff$23432' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\cr_pu_ena' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3438'. created $adff cell `$procdff$23433' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\cr_cel_ena' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3438'. created $adff cell `$procdff$23434' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\cr_addr_chk' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3438'. created $adff cell `$procdff$23435' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\cr_addr' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3438'. created $adff cell `$procdff$23436' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\cel_rel' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3416'. created $dff cell `$procdff$23437' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\csr_bus_req' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3416'. created $dff cell `$procdff$23438' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\cr_bus_we' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3416'. created $dff cell `$procdff$23439' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\ir_bus_we' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3416'. created $dff cell `$procdff$23440' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\evt_rd_ack' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3416'. created $dff cell `$procdff$23441' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\rst_clear' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3416'. created $dff cell `$procdff$23442' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\sof_clear' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3416'. created $dff cell `$procdff$23443' with positive edge clock. Creating register for signal `$paramod\xclk_wb\DW=16\AW=12.\m_cyc_i' using process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:99$3412'. created $adff cell `$procdff$23444' with positive edge clock and positive level reset. Creating register for signal `$paramod\xclk_wb\DW=16\AW=12.\s_cyc_d' using process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:83$3408'. created $dff cell `$procdff$23445' with positive edge clock. Creating register for signal `$paramod\xclk_wb\DW=16\AW=12.\s_ack_d' using process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:83$3408'. created $dff cell `$procdff$23446' with positive edge clock. Creating register for signal `$paramod\xclk_wb\DW=16\AW=12.\s_rdata' using process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:73$3405'. created $dff cell `$procdff$23447' with positive edge clock. Creating register for signal `$paramod\xclk_wb\DW=16\AW=12.\m_rdata_i' using process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:68$3404'. created $dff cell `$procdff$23448' with positive edge clock. Creating register for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\sda_oe' using process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:214$5215'. created $dff cell `$procdff$23449' with positive edge clock. Creating register for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\scl_oe' using process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:204$5212'. created $dff cell `$procdff$23450' with positive edge clock. Creating register for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\data_reg' using process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:159$5208'. created $dff cell `$procdff$23451' with positive edge clock. Creating register for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\bit_cnt' using process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:141$5204'. created $dff cell `$procdff$23452' with positive edge clock. Creating register for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\cyc_cnt' using process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:129$5200'. created $dff cell `$procdff$23453' with positive edge clock. Creating register for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\cmd_cur' using process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:121$5199'. created $dff cell `$procdff$23454' with positive edge clock. Creating register for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\state' using process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:81$5193'. created $dff cell `$procdff$23455' with positive edge clock. Creating register for signal `$paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001.\out' using process `$paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:133$5192'. created $dff cell `$procdff$23456' with positive edge clock. Creating register for signal `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.\pb_rst_n' using process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:185$3316'. created $adff cell `$procdff$23457' with positive edge clock and positive level reset. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\uart_div' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:193$3302'. created $dff cell `$procdff$23458' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_rdata' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:185$3300'. created $dff cell `$procdff$23459' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_ack' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:177$3290'. created $dff cell `$procdff$23460' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_rd_data' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3273'. created $dff cell `$procdff$23461' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_rd_ctrl' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3273'. created $dff cell `$procdff$23462' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_wr_data' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3273'. created $dff cell `$procdff$23463' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_wr_div' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3273'. created $dff cell `$procdff$23464' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\urf_overflow' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:154$3268'. created $adff cell `$procdff$23465' with positive edge clock and positive level reset. Creating register for signal `$paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0.\wb_rdata' using process `$paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master_wb.v:91$3263'. created $dff cell `$procdff$23466' with positive edge clock. Creating register for signal `$paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0.\wb_ack' using process `$paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master_wb.v:85$3255'. created $dff cell `$procdff$23467' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\srio_clk_o' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:291$3253'. created $dff cell `$procdff$23468' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\srio_dat_o' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:291$3253'. created $dff cell `$procdff$23469' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\srio_rclk_o' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:291$3253'. created $dff cell `$procdff$23470' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\srio_rclk_oe' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:291$3253'. created $dff cell `$procdff$23471' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\shift_data' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:279$3252'. created $dff cell `$procdff$23472' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\btn_stb' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:270$3240'. created $dff cell `$procdff$23473' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\btn_val' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:262$3233'. created $dff cell `$procdff$23474' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\sense_cnt_in' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:243$3227'. created $dff cell `$procdff$23475' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\sense_cnt' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:243$3227'. created $dff cell `$procdff$23476' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\bit_cnt' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:227$3220'. created $dff cell `$procdff$23477' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\tick_cnt' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:214$3214'. created $dff cell `$procdff$23478' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\btn_sync' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:206$3213'. created $dff cell `$procdff$23479' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\sio_sel' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:197$3211'. created $dff cell `$procdff$23480' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\state' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:114$3198'. created $dff cell `$procdff$23481' with positive edge clock. Creating register for signal `\hdb3_enc.\pstate' using process `\hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:45$441'. created $dff cell `$procdff$23482' with positive edge clock. Creating register for signal `\hdb3_enc.\d_pos' using process `\hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:45$441'. created $dff cell `$procdff$23483' with positive edge clock. Creating register for signal `\hdb3_enc.\d_neg' using process `\hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:45$441'. created $dff cell `$procdff$23484' with positive edge clock. Creating register for signal `\hdb3_enc.\zcnt' using process `\hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:45$441'. created $dff cell `$procdff$23485' with positive edge clock. Creating register for signal `\hdb3_enc.\vstate' using process `\hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:45$441'. created $dff cell `$procdff$23486' with positive edge clock. Creating register for signal `\hdb3_enc.\out_valid' using process `\hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:41$440'. created $dff cell `$procdff$23487' with positive edge clock. Creating register for signal `\hdb3_dec.\data' using process `\hdb3_dec.$proc$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:43$437'. created $dff cell `$procdff$23488' with positive edge clock. Creating register for signal `\hdb3_dec.\pstate' using process `\hdb3_dec.$proc$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:43$437'. created $dff cell `$procdff$23489' with positive edge clock. Creating register for signal `\hdb3_dec.\out_valid' using process `\hdb3_dec.$proc$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:37$432'. created $dff cell `$procdff$23490' with positive edge clock. Creating register for signal `\e1_tx_framer.\out_valid' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:248$246'. created $adff cell `$procdff$23491' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\out_bit' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:248$246'. created $adff cell `$procdff$23492' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\crc_smf' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:236$244'. created $adff cell `$procdff$23493' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\crc_capture' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:224$243'. created $dff cell `$procdff$23494' with positive edge clock. Creating register for signal `\e1_tx_framer.\shift_at_first' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:204$231'. created $adff cell `$procdff$23495' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\shift_at_last' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:204$231'. created $adff cell `$procdff$23496' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\shift_at_crc' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:204$231'. created $adff cell `$procdff$23497' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\shift_data' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:194$228'. created $adff cell `$procdff$23498' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\bit_cnt' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:187$224'. created $adff cell `$procdff$23499' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\shift_data_nxt' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:167$220'. created $dff cell `$procdff$23500' with positive edge clock. Creating register for signal `\e1_tx_framer.\fetch_done' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:148$218'. created $adff cell `$procdff$23501' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\in_req' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:144$217'. created $dff cell `$procdff$23502' with positive edge clock. Creating register for signal `\e1_tx_framer.\in_mf_first' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:135$213'. created $adff cell `$procdff$23503' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\in_mf_last' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:135$213'. created $adff cell `$procdff$23504' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\fetch_ts' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:120$210'. created $adff cell `$procdff$23505' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\fetch_ts_is0' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:120$210'. created $adff cell `$procdff$23506' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\fetch_ts_is31' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:120$210'. created $adff cell `$procdff$23507' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\fetch_frame' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:113$208'. created $adff cell `$procdff$23508' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\strobe' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:103$204'. created $dff cell `$procdff$23509' with positive edge clock. Creating register for signal `\e1_tx_framer.\tick_cnt' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:97$200'. created $adff cell `$procdff$23510' with positive edge clock and positive level reset. Creating register for signal `\e1_rx_filter.\out_hi' using process `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:71$163'. created $dff cell `$procdff$23511' with positive edge clock. Creating register for signal `\e1_rx_filter.\out_lo' using process `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:71$163'. created $dff cell `$procdff$23512' with positive edge clock. Creating register for signal `\e1_rx_filter.\out_stb' using process `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:71$163'. created $dff cell `$procdff$23513' with positive edge clock. Creating register for signal `\e1_rx_filter.\cnt_hi' using process `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:46$144'. created $dff cell `$procdff$23514' with positive edge clock. Creating register for signal `\e1_rx_filter.\cnt_lo' using process `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:46$144'. created $dff cell `$procdff$23515' with positive edge clock. Creating register for signal `\e1_rx_filter.\in_hi_r' using process `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:39$143'. created $dff cell `$procdff$23516' with positive edge clock. Creating register for signal `\e1_rx_filter.\in_lo_r' using process `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:39$143'. created $dff cell `$procdff$23517' with positive edge clock. Creating register for signal `\e1_rx_deframer.\aligned' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:395$141'. created $dff cell `$procdff$23518' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_data' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:360$135'. created $dff cell `$procdff$23519' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_frame' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:360$135'. created $dff cell `$procdff$23520' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_ts' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:360$135'. created $dff cell `$procdff$23521' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_ts_is0' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:360$135'. created $dff cell `$procdff$23522' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_first' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:360$135'. created $dff cell `$procdff$23523' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_last' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:360$135'. created $dff cell `$procdff$23524' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_valid' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:360$135'. created $dff cell `$procdff$23525' with positive edge clock. Creating register for signal `\e1_rx_deframer.\error' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$127'. created $dff cell `$procdff$23526' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ec_fas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:339$109'. created $dff cell `$procdff$23527' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ec_nfas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:339$109'. created $dff cell `$procdff$23528' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ec_crc' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:339$109'. created $dff cell `$procdff$23529' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ec_mfa' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:339$109'. created $dff cell `$procdff$23530' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ed_crc' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:324$91'. created $dff cell `$procdff$23531' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ep_crc' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:324$91'. created $dff cell `$procdff$23532' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ed_mfa' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:324$91'. created $dff cell `$procdff$23533' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ep_mfa' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:324$91'. created $dff cell `$procdff$23534' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ed_fas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:310$69'. created $dff cell `$procdff$23535' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ep_fas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:310$69'. created $dff cell `$procdff$23536' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ed_nfas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:310$69'. created $dff cell `$procdff$23537' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ep_nfas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:310$69'. created $dff cell `$procdff$23538' with positive edge clock. Creating register for signal `\e1_rx_deframer.\crc_smf' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:301$68'. created $dff cell `$procdff$23539' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts0_msbs' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:269$57'. created $dff cell `$procdff$23540' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts0_msbs_match_mf' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:269$57'. created $dff cell `$procdff$23541' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts0_msbs_match_crc' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:269$57'. created $dff cell `$procdff$23542' with positive edge clock. Creating register for signal `\e1_rx_deframer.\mfa_timeout' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:261$53'. created $dff cell `$procdff$23543' with positive edge clock. Creating register for signal `\e1_rx_deframer.\fas_pos' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:253$49'. created $dff cell `$procdff$23544' with positive edge clock. Creating register for signal `\e1_rx_deframer.\frame' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:226$41'. created $dff cell `$procdff$23545' with positive edge clock. Creating register for signal `\e1_rx_deframer.\frame_smf_first' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:226$41'. created $dff cell `$procdff$23546' with positive edge clock. Creating register for signal `\e1_rx_deframer.\frame_smf_last' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:226$41'. created $dff cell `$procdff$23547' with positive edge clock. Creating register for signal `\e1_rx_deframer.\frame_mf_first' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:226$41'. created $dff cell `$procdff$23548' with positive edge clock. Creating register for signal `\e1_rx_deframer.\frame_mf_last' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:226$41'. created $dff cell `$procdff$23549' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:214$37'. created $dff cell `$procdff$23550' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts_is_ts0' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:214$37'. created $dff cell `$procdff$23551' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts_is_ts31' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:214$37'. created $dff cell `$procdff$23552' with positive edge clock. Creating register for signal `\e1_rx_deframer.\bit' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:202$33'. created $dff cell `$procdff$23553' with positive edge clock. Creating register for signal `\e1_rx_deframer.\bit_first' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:202$33'. created $dff cell `$procdff$23554' with positive edge clock. Creating register for signal `\e1_rx_deframer.\bit_last' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:202$33'. created $dff cell `$procdff$23555' with positive edge clock. Creating register for signal `\e1_rx_deframer.\fsm_state' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:139$24'. created $dff cell `$procdff$23556' with positive edge clock. Creating register for signal `\e1_rx_deframer.\data_match_fas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:130$21'. created $dff cell `$procdff$23557' with positive edge clock. Creating register for signal `\e1_rx_deframer.\data' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:125$20'. created $dff cell `$procdff$23558' with positive edge clock. Creating register for signal `\e1_rx_deframer.\strobe' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:118$19'. created $dff cell `$procdff$23559' with positive edge clock. Creating register for signal `\e1_rx_clock_recovery.\cnt' using process `\e1_rx_clock_recovery.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:39$17'. created $dff cell `$procdff$23560' with positive edge clock. Creating register for signal `\e1_rx_clock_recovery.\enabled' using process `\e1_rx_clock_recovery.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:33$15'. created $dff cell `$procdff$23561' with positive edge clock. Creating register for signal `\e1_crc4.\state' using process `\e1_crc4.$proc$/build/gateware/cores/no2e1//rtl/e1_crc4.v:38$13'. created $dff cell `$procdff$23562' with positive edge clock. 75.3.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3061'. Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$3058'. Removing empty process `SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$3058'. Removing empty process `SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3057'. Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1274$3051'. Removing empty process `SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1274$3051'. Removing empty process `SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3050'. Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$3047'. Removing empty process `SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$3047'. Removing empty process `SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3046'. Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1143$3040'. Removing empty process `SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1143$3040'. Removing empty process `SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3039'. Removing empty process `SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1074$3037'. Removing empty process `SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3036'. Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1026$3034'. Removing empty process `SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1026$3034'. Removing empty process `SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3033'. Removing empty process `SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:957$3031'. Removing empty process `SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3030'. Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:909$3028'. Removing empty process `SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:909$3028'. Removing empty process `SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3027'. Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:866$3026'. Removing empty process `SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:866$3026'. Removing empty process `SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3025'. Removing empty process `SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:830$3024'. Removing empty process `SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3023'. Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$3020'. Removing empty process `SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$3020'. Removing empty process `SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3019'. Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:697$3013'. Removing empty process `SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:697$3013'. Removing empty process `SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3012'. Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$3009'. Removing empty process `SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$3009'. Removing empty process `SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3008'. Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:566$3002'. Removing empty process `SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:566$3002'. Removing empty process `SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3001'. Removing empty process `SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:497$2999'. Removing empty process `SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2998'. Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:449$2996'. Removing empty process `SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:449$2996'. Removing empty process `SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2995'. Removing empty process `SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:380$2993'. Removing empty process `SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2992'. Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:332$2990'. Removing empty process `SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:332$2990'. Removing empty process `SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2989'. Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:289$2988'. Removing empty process `SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:289$2988'. Removing empty process `SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2987'. Removing empty process `SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:253$2986'. Removing empty process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$5189'. Found and cleaned up 1 empty switch in `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$5184'. Removing empty process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$5184'. Found and cleaned up 3 empty switches in `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$5180'. Removing empty process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$5180'. Found and cleaned up 1 empty switch in `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$5176'. Removing empty process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$5176'. Found and cleaned up 2 empty switches in `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$5168'. Removing empty process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$5168'. Removing empty process `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v:50$5165'. Found and cleaned up 1 empty switch in `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5144'. Removing empty process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5144'. Found and cleaned up 3 empty switches in `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$5135'. Removing empty process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$5135'. Found and cleaned up 1 empty switch in `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5132'. Removing empty process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5132'. Removing empty process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5113'. Removing empty process `$paramod\wb_epbuf\AW=9\DW=32.$proc$/build/gateware/common/rtl/wb_epbuf.v:51$5101'. Found and cleaned up 1 empty switch in `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5090'. Removing empty process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5090'. Found and cleaned up 2 empty switches in `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$5083'. Removing empty process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$5083'. Found and cleaned up 1 empty switch in `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5080'. Removing empty process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5080'. Removing empty process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5067'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$5048'. Found and cleaned up 1 empty switch in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:178$5044'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:178$5044'. Found and cleaned up 1 empty switch in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:174$5041'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:174$5041'. Found and cleaned up 1 empty switch in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:157$5031'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:157$5031'. Found and cleaned up 1 empty switch in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:153$5027'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:153$5027'. Found and cleaned up 1 empty switch in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:142$5025'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:142$5025'. Found and cleaned up 4 empty switches in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:98$5009'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:98$5009'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:92$5008'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:86$5004'. Removing empty process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$5000'. Removing empty process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4996'. Removing empty process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4992'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5563'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5559'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5555'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5551'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5547'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5543'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5539'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5535'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5531'. Found and cleaned up 1 empty switch in `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4962'. Removing empty process `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4962'. Found and cleaned up 1 empty switch in `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4949'. Removing empty process `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4949'. Found and cleaned up 2 empty switches in `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4925'. Removing empty process `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4925'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5508'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5504'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5500'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5496'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5492'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5488'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5484'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5480'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5476'. Found and cleaned up 2 empty switches in `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5452'. Removing empty process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5452'. Found and cleaned up 1 empty switch in `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:163$5446'. Removing empty process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:163$5446'. Removing empty process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:160$5444'. Removing empty process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:147$5417'. Removing empty process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:91$5414'. Removing empty process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4806'. Found and cleaned up 16 empty switches in `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650'. Removing empty process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4650'. Found and cleaned up 1 empty switch in `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:73$4649'. Removing empty process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:73$4649'. Removing empty process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:253$4632'. Removing empty process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:246$4628'. Removing empty process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:239$4626'. Found and cleaned up 1 empty switch in `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$4608'. Removing empty process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$4608'. Found and cleaned up 1 empty switch in `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$4607'. Removing empty process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$4607'. Found and cleaned up 1 empty switch in `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$4599'. Removing empty process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$4599'. Removing empty process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:265$4593'. Removing empty process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:258$4591'. Found and cleaned up 1 empty switch in `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:152$4568'. Removing empty process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:152$4568'. Found and cleaned up 1 empty switch in `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:122$4567'. Removing empty process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:122$4567'. Found and cleaned up 1 empty switch in `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:112$4559'. Removing empty process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:112$4559'. Removing empty process `sysmgr.$proc$/build/gateware/icE1usb/rtl/sysmgr.v:84$1713'. Found and cleaned up 1 empty switch in `\sysmgr.$proc$/build/gateware/icE1usb/rtl/sysmgr.v:76$1708'. Removing empty process `sysmgr.$proc$/build/gateware/icE1usb/rtl/sysmgr.v:76$1708'. Found and cleaned up 2 empty switches in `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:160$4554'. Removing empty process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:160$4554'. Removing empty process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:100$4546'. Found and cleaned up 1 empty switch in `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:93$4544'. Removing empty process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:93$4544'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1648'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1646'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1644'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1642'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1640'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1638'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1636'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1634'. Found and cleaned up 1 empty switch in `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:302$1633'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:302$1633'. Found and cleaned up 4 empty switches in `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:260$1632'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:260$1632'. Found and cleaned up 1 empty switch in `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:183$1631'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:183$1631'. Found and cleaned up 1 empty switch in `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:170$1630'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:170$1630'. Found and cleaned up 2 empty switches in `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:130$1629'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:130$1629'. Found and cleaned up 1 empty switch in `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:110$1619'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:110$1619'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:104$1614'. Removing empty process `led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:89$1601'. Removing empty process `led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:77$1592'. Removing empty process `led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:65$1588'. Removing empty process `led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:55$1584'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:241$1576'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:229$1573'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:202$1567'. Found and cleaned up 1 empty switch in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:191$1563'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:191$1563'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:182$1557'. Found and cleaned up 1 empty switch in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:175$1550'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:175$1550'. Found and cleaned up 1 empty switch in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:170$1548'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:170$1548'. Found and cleaned up 1 empty switch in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:159$1544'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:159$1544'. Found and cleaned up 1 empty switch in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:152$1541'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:152$1541'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:136$1529'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:126$1528'. Found and cleaned up 8 empty switches in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:86$1526'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:86$1526'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:134$1525'. Found and cleaned up 2 empty switches in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1523'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1523'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:110$1516'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:102$1511'. Found and cleaned up 1 empty switch in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1501'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1501'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:79$1498'. Found and cleaned up 4 empty switches in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1495'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1495'. Found and cleaned up 2 empty switches in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:236$1491'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:236$1491'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:428$1483'. Found and cleaned up 1 empty switch in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:421$1480'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:421$1480'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:414$1474'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:403$1473'. Found and cleaned up 1 empty switch in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:399$1470'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:399$1470'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:387$1464'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:380$1462'. Found and cleaned up 2 empty switches in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1449'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1449'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:345$1446'. Found and cleaned up 4 empty switches in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1441'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1441'. Found and cleaned up 1 empty switch in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1437'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1437'. Found and cleaned up 1 empty switch in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1430'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1430'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:225$1425'. Found and cleaned up 2 empty switches in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1422'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1422'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:175$1413'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:162$1404'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:374$1401'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:353$1392'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:349$1390'. Found and cleaned up 1 empty switch in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:340$1387'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:340$1387'. Found and cleaned up 1 empty switch in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:336$1384'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:336$1384'. Found and cleaned up 1 empty switch in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1367'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1367'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:318$1366'. Found and cleaned up 1 empty switch in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:304$1345'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:304$1345'. Found and cleaned up 2 empty switches in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1341'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1341'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:284$1340'. Found and cleaned up 2 empty switches in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:244$1338'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:244$1338'. Found and cleaned up 2 empty switches in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:230$1335'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:230$1335'. Found and cleaned up 2 empty switches in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:220$1332'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:220$1332'. Found and cleaned up 1 empty switch in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:215$1331'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:215$1331'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:198$1323'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:188$1322'. Found and cleaned up 18 empty switches in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:117$1306'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:117$1306'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:49$1305'. Found and cleaned up 1 empty switch in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:181$1303'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:181$1303'. Found and cleaned up 3 empty switches in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1301'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1301'. Found and cleaned up 3 empty switches in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:137$1300'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:137$1300'. Found and cleaned up 2 empty switches in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:124$1299'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:124$1299'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:120$1298'. Found and cleaned up 1 empty switch in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:111$1291'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:111$1291'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:97$1284'. Found and cleaned up 2 empty switches in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1283'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1283'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:67$1273'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4543'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4534'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4534'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4532'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4532'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4523'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4523'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4521'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4521'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4512'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4512'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4510'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4510'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4501'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4501'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4499'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4499'. Found and cleaned up 1 empty switch in `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:80$1269'. Removing empty process `usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:80$1269'. Found and cleaned up 1 empty switch in `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:76$1267'. Removing empty process `usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:76$1267'. Removing empty process `usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1264'. Removing empty process `usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1256'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4497'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4488'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4488'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4486'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4486'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4477'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4477'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4475'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4475'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4466'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4466'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4464'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4464'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4455'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4455'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4453'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4453'. Removing empty process `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:199$4442'. Removing empty process `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:192$4436'. Removing empty process `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:184$4432'. Removing empty process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:0$5373'. Found and cleaned up 1 empty switch in `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:125$5368'. Removing empty process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:125$5368'. Removing empty process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:117$5363'. Removing empty process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:106$5358'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4399'. Found and cleaned up 1 empty switch in `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4394'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4394'. Found and cleaned up 3 empty switches in `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4390'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4390'. Found and cleaned up 1 empty switch in `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4386'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4386'. Found and cleaned up 2 empty switches in `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4378'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4378'. Removing empty process `xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:40$1101'. Removing empty process `xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:34$1100'. Removing empty process `xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:28$1098'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5349'. Found and cleaned up 1 empty switch in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:163$5348'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:163$5348'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:153$5343'. Found and cleaned up 1 empty switch in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:143$5342'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:143$5342'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:123$5341'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5336'. Found and cleaned up 1 empty switch in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5335'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5335'. Found and cleaned up 1 empty switch in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$5325'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$5325'. Found and cleaned up 5 empty switches in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5292'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5292'. Found and cleaned up 1 empty switch in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:212$5289'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:212$5289'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:206$5287'. Found and cleaned up 4 empty switches in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$5285'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$5285'. Removing empty process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:67$5258'. Found and cleaned up 2 empty switches in `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5257'. Removing empty process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5257'. Found and cleaned up 2 empty switches in `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:51$5254'. Removing empty process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:51$5254'. Found and cleaned up 1 empty switch in `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:42$5250'. Removing empty process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:42$5250'. Removing empty process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:35$5246'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4339'. Removing empty process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4339'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4333'. Removing empty process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4333'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4331'. Removing empty process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4331'. Removing empty process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:83$4322'. Removing empty process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:67$4316'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4315'. Found and cleaned up 1 empty switch in `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4310'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4310'. Found and cleaned up 3 empty switches in `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4306'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4306'. Found and cleaned up 1 empty switch in `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4302'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4302'. Found and cleaned up 2 empty switches in `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4294'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4294'. Removing empty process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:149$4293'. Found and cleaned up 2 empty switches in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4284'. Removing empty process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4284'. Removing empty process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:109$4280'. Removing empty process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:103$4278'. Removing empty process `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:67$4274'. Found and cleaned up 1 empty switch in `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:42$4271'. Removing empty process `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:42$4271'. Removing empty process `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:72$4270'. Found and cleaned up 1 empty switch in `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:42$4267'. Removing empty process `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:42$4267'. Found and cleaned up 55 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4091'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$4077'. Found and cleaned up 2 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1288$4063'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1288$4063'. Found and cleaned up 2 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1274$4058'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1274$4058'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1272$4057'. Found and cleaned up 2 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1228$4035'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1228$4035'. Found and cleaned up 8 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1165$4023'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1165$4023'. Found and cleaned up 22 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3763'. Found and cleaned up 3 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3761'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3761'. Found and cleaned up 5 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3757'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3757'. Found and cleaned up 47 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:684$3756'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:684$3756'. Found and cleaned up 16 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3732'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3732'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1209$4256'. Found and cleaned up 19 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:414$3694'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:414$3694'. Found and cleaned up 3 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3691'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3691'. Found and cleaned up 2 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:374$3686'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:374$3686'. Found and cleaned up 1 empty switch in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3612'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3612'. Removing empty process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:102$5240'. Found and cleaned up 1 empty switch in `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:95$5239'. Removing empty process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:95$5239'. Found and cleaned up 2 empty switches in `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:88$5236'. Removing empty process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:88$5236'. Found and cleaned up 2 empty switches in `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:77$5232'. Removing empty process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:77$5232'. Removing empty process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:70$5228'. Found and cleaned up 4 empty switches in `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3502'. Removing empty process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3502'. Found and cleaned up 1 empty switch in `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.$proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3493'. Removing empty process `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.$proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3493'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:536$3487'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:656$3482'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:653$3480'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:643$3479'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:643$3479'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:636$3475'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:628$3471'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:628$3471'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:619$3467'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:619$3467'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:514$3453'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:510$3450'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3440'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3440'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:697$3491'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3438'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3438'. Found and cleaned up 2 empty switches in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:442$3434'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:442$3434'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3416'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3416'. Removing empty process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:99$3412'. Removing empty process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:83$3408'. Found and cleaned up 1 empty switch in `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:73$3405'. Removing empty process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:73$3405'. Found and cleaned up 1 empty switch in `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:68$3404'. Removing empty process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:68$3404'. Removing empty process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:0$5224'. Removing empty process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:0$5223'. Found and cleaned up 6 empty switches in `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:214$5215'. Removing empty process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:214$5215'. Found and cleaned up 4 empty switches in `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:204$5212'. Removing empty process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:204$5212'. Found and cleaned up 2 empty switches in `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:159$5208'. Removing empty process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:159$5208'. Found and cleaned up 3 empty switches in `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:141$5204'. Removing empty process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:141$5204'. Found and cleaned up 1 empty switch in `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:129$5200'. Removing empty process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:129$5200'. Found and cleaned up 1 empty switch in `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:121$5199'. Removing empty process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:121$5199'. Found and cleaned up 7 empty switches in `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:87$5194'. Removing empty process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:87$5194'. Found and cleaned up 1 empty switch in `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:81$5193'. Removing empty process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:81$5193'. Found and cleaned up 1 empty switch in `$paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:133$5192'. Removing empty process `$paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:133$5192'. Removing empty process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3321'. Removing empty process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3319'. Removing empty process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3317'. Removing empty process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:185$3316'. Found and cleaned up 1 empty switch in `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:193$3302'. Removing empty process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:193$3302'. Found and cleaned up 1 empty switch in `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:185$3300'. Removing empty process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:185$3300'. Found and cleaned up 1 empty switch in `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:177$3290'. Removing empty process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:177$3290'. Found and cleaned up 1 empty switch in `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3273'. Removing empty process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3273'. Removing empty process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:154$3268'. Found and cleaned up 1 empty switch in `$paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master_wb.v:91$3263'. Removing empty process `$paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master_wb.v:91$3263'. Removing empty process `$paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master_wb.v:85$3255'. Found and cleaned up 1 empty switch in `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:291$3253'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:291$3253'. Found and cleaned up 1 empty switch in `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:279$3252'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:279$3252'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:270$3240'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:262$3233'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:243$3227'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:227$3220'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:214$3214'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:206$3213'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:197$3211'. Found and cleaned up 9 empty switches in `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:121$3199'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:121$3199'. Found and cleaned up 1 empty switch in `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:114$3198'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:114$3198'. Found and cleaned up 5 empty switches in `\hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:45$441'. Removing empty process `hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:45$441'. Removing empty process `hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:41$440'. Found and cleaned up 4 empty switches in `\hdb3_dec.$proc$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:43$437'. Removing empty process `hdb3_dec.$proc$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:43$437'. Removing empty process `hdb3_dec.$proc$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:37$432'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:248$246'. Found and cleaned up 2 empty switches in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:236$244'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:236$244'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:224$243'. Found and cleaned up 1 empty switch in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:204$231'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:204$231'. Found and cleaned up 1 empty switch in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:194$228'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:194$228'. Found and cleaned up 1 empty switch in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:187$224'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:187$224'. Found and cleaned up 2 empty switches in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:167$220'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:167$220'. Found and cleaned up 1 empty switch in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:148$218'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:148$218'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:144$217'. Found and cleaned up 1 empty switch in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:135$213'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:135$213'. Found and cleaned up 1 empty switch in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:120$210'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:120$210'. Found and cleaned up 1 empty switch in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:113$208'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:113$208'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:103$204'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:97$200'. Found and cleaned up 4 empty switches in `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:71$163'. Removing empty process `e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:71$163'. Found and cleaned up 5 empty switches in `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:46$144'. Removing empty process `e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:46$144'. Removing empty process `e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:39$143'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:395$141'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:395$141'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:360$135'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:360$135'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$127'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:339$109'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:339$109'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:324$91'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:324$91'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:310$69'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:310$69'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:301$68'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:301$68'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:269$57'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:269$57'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:261$53'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:261$53'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:253$49'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:253$49'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:226$41'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:226$41'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:214$37'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:214$37'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:202$33'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:202$33'. Found and cleaned up 10 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:146$26'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:146$26'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:139$24'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:139$24'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:130$21'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:130$21'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:125$20'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:125$20'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:118$19'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:118$19'. Found and cleaned up 4 empty switches in `\e1_rx_clock_recovery.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:39$17'. Removing empty process `e1_rx_clock_recovery.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:39$17'. Found and cleaned up 1 empty switch in `\e1_rx_clock_recovery.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:33$15'. Removing empty process `e1_rx_clock_recovery.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:33$15'. Found and cleaned up 1 empty switch in `\e1_crc4.$proc$/build/gateware/cores/no2e1//rtl/e1_crc4.v:38$13'. Removing empty process `e1_crc4.$proc$/build/gateware/cores/no2e1//rtl/e1_crc4.v:38$13'. Cleaned up 540 empty switches. 75.4. Executing FLATTEN pass (flatten design). Deleting now unused module $paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0. Deleting now unused module $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0. Deleting now unused module $paramod\wb_arbiter\N=3\DW=32\AW=14. Deleting now unused module $paramod\wb_epbuf\AW=9\DW=32. Deleting now unused module $paramod\wb_arbiter\N=2\DW=32\AW=9. Deleting now unused module soc_iobuf. Deleting now unused module $paramod\wb_dma\A0W=14\A1W=9\DW=32. Deleting now unused module $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr. Deleting now unused module picorv32_ice40_regs. Deleting now unused module $paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf. Deleting now unused module $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100. Deleting now unused module $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101. Deleting now unused module $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000. Deleting now unused module $paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf. Deleting now unused module $paramod\ram_sdp\AWIDTH=9\DWIDTH=8. Deleting now unused module $paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4. Deleting now unused module $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32. Deleting now unused module $paramod\e1_wb_rx\LIU=0\MFW=7. Deleting now unused module capcnt32_sb_mac16. Deleting now unused module capcnt16_sb_mac16. Deleting now unused module $paramod\e1_wb_tx\LIU=0\MFW=7. Deleting now unused module sysmgr. Deleting now unused module $paramod\e1_tx\LIU=0\MFW=7. Deleting now unused module misc. Deleting now unused module led_blinker. Deleting now unused module usb_tx_pkt. Deleting now unused module usb_tx_ll. Deleting now unused module usb_trans. Deleting now unused module usb_rx_pkt. Deleting now unused module usb_rx_ll. Deleting now unused module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Deleting now unused module usb_ep_status. Deleting now unused module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Deleting now unused module $paramod\e1_rx\LIU=0\MFW=7. Deleting now unused module $paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7. Deleting now unused module $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1. Deleting now unused module xclk_strobe. Deleting now unused module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32. Deleting now unused module $paramod\uart_tx\DIV_WIDTH=12. Deleting now unused module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Deleting now unused module $paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1. Deleting now unused module $paramod\capcnt\W=32. Deleting now unused module $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0. Deleting now unused module $paramod\capcnt\W=16. Deleting now unused module $paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm. Deleting now unused module $paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm. Deleting now unused module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Deleting now unused module $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2. Deleting now unused module $paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram. Deleting now unused module $paramod\soc_spram\AW=14. Deleting now unused module $paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0. Deleting now unused module $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb. Deleting now unused module $paramod\usb\EPDW=32. Deleting now unused module $paramod\xclk_wb\DW=16\AW=12. Deleting now unused module $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0. Deleting now unused module $paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001. Deleting now unused module $paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base. Deleting now unused module $paramod\uart_wb\DIV_WIDTH=12\DW=32. Deleting now unused module $paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0. Deleting now unused module $paramod\sr_btn_if\TICK_LOG2_DIV=3. Deleting now unused module hdb3_enc. Deleting now unused module hdb3_dec. Deleting now unused module e1_tx_phy. Deleting now unused module e1_tx_framer. Deleting now unused module e1_rx_phy. Deleting now unused module e1_rx_filter. Deleting now unused module e1_rx_deframer. Deleting now unused module e1_rx_clock_recovery. Deleting now unused module e1_crc4. 75.5. Executing TRIBUF pass. 75.6. Executing DEMINOUT pass (demote inout ports to input or output). Demoting inout port top.flash_cs_n to output. 75.7. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.8. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 967 unused cells and 14471 unused wires. 75.9. Executing CHECK pass (checking for obvious problems). checking module top.. found and reported 0 problems. 75.10. Executing OPT pass (performing simple optimizations). 75.10.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.10.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 516 cells. 75.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port A of cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\clock_I.$procmux$15950: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.clock_I.cnt -> { 1'0 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.clock_I.cnt [4:0] } Replacing known input bits on port B of cell $flatten\misc_I.\dfu_I.$procmux$12487: \misc_I.dfu_I.wb_req -> 1'1 Replacing known input bits on port B of cell $flatten\sys_mgr_I.$procmux$11667: \sys_mgr_I.rst_cnt -> { 1'1 \sys_mgr_I.rst_cnt [2:0] } Analyzing evaluation results. dead port 1/2 on $mux $flatten\gps_uart_I.\uart_rx_I.\gf_I.$procmux$12289. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12617. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12623. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12626. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12638. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12645. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12648. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12661. dead port 1/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12671. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12673. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12676. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12685. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12688. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12696. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12698. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12701. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12762. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12764. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12767. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12849. dead port 1/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12852. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12854. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12857. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12896. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12899. dead port 1/3 on $pmux $flatten\soc_I.\cpu_I.$procmux$12910. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12942. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12955. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12968. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$13007. dead port 3/4 on $pmux $flatten\soc_I.\cpu_I.$procmux$13102. dead port 4/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13116. dead port 5/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13116. dead port 6/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13116. dead port 7/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13116. dead port 8/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13116. dead port 10/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13116. dead port 11/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13116. dead port 3/4 on $pmux $flatten\soc_I.\cpu_I.$procmux$13145. dead port 4/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13158. dead port 5/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13158. dead port 6/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13158. dead port 7/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13158. dead port 8/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13158. dead port 10/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13158. dead port 11/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13158. dead port 1/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13204. dead port 2/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13204. dead port 3/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13204. dead port 4/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13204. dead port 5/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13204. dead port 6/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13204. dead port 1/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$13210. dead port 2/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$13210. dead port 3/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$13210. dead port 4/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$13210. dead port 5/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$13210. dead port 4/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13243. dead port 5/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13243. dead port 6/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13243. dead port 7/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13243. dead port 8/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13243. dead port 10/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13243. dead port 11/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13243. dead port 1/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13448. dead port 2/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13448. dead port 3/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13448. dead port 4/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13448. dead port 5/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13448. dead port 6/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13448. dead port 3/4 on $pmux $flatten\soc_I.\cpu_I.$procmux$13512. dead port 4/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13531. dead port 5/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13531. dead port 6/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13531. dead port 7/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13531. dead port 8/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13531. dead port 10/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13531. dead port 11/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13531. dead port 3/4 on $pmux $flatten\soc_I.\cpu_I.$procmux$13713. dead port 4/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13729. dead port 5/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13729. dead port 6/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13729. dead port 7/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13729. dead port 8/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13729. dead port 10/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13729. dead port 11/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13729. dead port 4/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13891. dead port 5/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13891. dead port 6/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13891. dead port 7/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13891. dead port 8/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13891. dead port 10/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13891. dead port 11/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13891. dead port 1/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13942. dead port 2/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13942. dead port 3/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13942. dead port 4/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13942. dead port 5/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13942. dead port 7/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13942. dead port 8/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13942. dead port 1/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$14039. dead port 2/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$14039. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$14044. dead port 1/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$14048. dead port 2/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$14048. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$14053. dead port 1/8 on $pmux $flatten\soc_I.\cpu_I.$procmux$14068. dead port 2/8 on $pmux $flatten\soc_I.\cpu_I.$procmux$14068. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$15199. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$15206. dead port 2/2 on $mux $flatten\i2c_I.\core_I.$procmux$15391. dead port 2/2 on $mux $flatten\i2c_I.\core_I.$procmux$15398. dead port 2/2 on $mux $flatten\i2c_I.\core_I.$procmux$15407. dead port 2/2 on $mux $flatten\i2c_I.\core_I.$procmux$15409. dead port 2/2 on $mux $flatten\i2c_I.\core_I.$procmux$15417. dead port 2/2 on $mux $flatten\i2c_I.\core_I.$procmux$15426. dead port 2/2 on $mux $flatten\i2c_I.\core_I.$procmux$15436. dead port 1/2 on $mux $flatten\soc_I.\e1_buf_I.$procmux$12434. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10004. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10004. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10004. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10004. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10004. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10026. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10026. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10026. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10026. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10026. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10060. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10060. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10060. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10060. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10090. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10090. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10090. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10090. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10102. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10102. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10102. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10102. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10102. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10120. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10120. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10120. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10120. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10128. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10128. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10128. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10128. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10128. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10154. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10154. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10154. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10154. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10154. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10212. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10212. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10212. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10212. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10212. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10225. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10225. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10225. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10225. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10225. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10240. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10240. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10240. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10240. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10240. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10257. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10257. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10257. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10257. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10257. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10276. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10276. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10276. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10276. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10297. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10297. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10297. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10297. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10320. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10320. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10320. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10320. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10320. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10345. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10345. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10345. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10345. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10345. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10372. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10372. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10372. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10372. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10372. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10401. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10401. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10401. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10401. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10401. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10432. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10432. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10432. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10432. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10432. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10465. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10465. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10465. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10465. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10465. dead port 1/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10500. dead port 2/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10500. dead port 3/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10500. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10540. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10540. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10540. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10540. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10540. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10550. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10550. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10550. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10550. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10550. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10564. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10564. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10564. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10564. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10564. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10580. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10580. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10580. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10580. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10580. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10600. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10600. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10600. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10600. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10624. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10624. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10624. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10624. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10624. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10652. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10652. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10652. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10652. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10652. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10684. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10684. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10684. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10684. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10684. dead port 1/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10720. dead port 2/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10720. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10727. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10727. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10727. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10727. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10727. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10738. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10738. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10738. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10738. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10738. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10760. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10760. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10760. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10760. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10760. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10794. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10794. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10794. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10794. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10824. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10824. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10824. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10824. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10824. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10836. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10836. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10836. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10836. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10836. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10854. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10854. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10854. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10854. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10862. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10862. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10862. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10862. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10862. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10888. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10888. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10888. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10888. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10888. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10946. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10946. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10946. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10946. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10946. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10959. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10959. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10959. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10959. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10959. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10974. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10974. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10974. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10974. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10974. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10991. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10991. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10991. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10991. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10991. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11010. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11010. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11010. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11010. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11010. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11031. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11031. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11031. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11031. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11031. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11054. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11054. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11054. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11054. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11054. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11079. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11079. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11079. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11079. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11079. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11106. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11106. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11106. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11106. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11106. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11135. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11135. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11135. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11135. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11135. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11166. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11166. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11166. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11166. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11166. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11199. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11199. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11199. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11199. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11199. dead port 1/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11234. dead port 2/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11234. dead port 4/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11234. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11274. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11274. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11274. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11274. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11274. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11284. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11284. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11284. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11284. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11284. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11298. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11298. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11298. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11298. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11298. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11314. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11314. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11314. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11314. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11314. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11334. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11334. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11334. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11334. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11334. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11358. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11358. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11358. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11358. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11358. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11386. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11386. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11386. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11386. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11386. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11418. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11418. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11418. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11418. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11418. dead port 1/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11454. dead port 3/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11454. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11461. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11461. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11461. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11461. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11461. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11472. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11472. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11472. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11472. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11472. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11494. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11494. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11494. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11494. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11494. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11528. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11528. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11528. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11528. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11558. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11558. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11558. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11558. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11558. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11570. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11570. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11570. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11570. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11570. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11588. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11588. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11588. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11588. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11588. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11596. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11596. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11596. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11596. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11596. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11622. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11622. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11622. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11622. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$11622. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5808. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5808. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5808. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5808. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5821. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5821. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5821. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5821. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5836. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5836. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5836. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5836. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5853. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5853. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5853. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5853. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5872. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5872. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5872. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5872. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5893. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5893. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5893. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5893. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5916. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5916. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5916. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5916. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5941. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5941. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5941. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5941. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5968. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5968. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5968. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5968. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5997. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5997. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5997. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$5997. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6028. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6028. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6028. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6028. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6061. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6061. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6061. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6061. dead port 1/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6096. dead port 2/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6096. dead port 3/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6096. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6136. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6136. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6136. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6136. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6146. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6146. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6146. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6146. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6160. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6160. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6160. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6160. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6176. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6176. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6176. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6176. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6196. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6196. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6196. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6196. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6220. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6220. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6220. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6220. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6248. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6248. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6248. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6248. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6280. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6280. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6280. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6280. dead port 1/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6316. dead port 2/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6316. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6323. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6323. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6323. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6323. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6334. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6334. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6334. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6334. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6356. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6356. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6356. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6356. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6390. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6390. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6390. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6390. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6420. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6420. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6420. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6420. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6432. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6432. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6432. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6432. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6450. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6450. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6450. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6450. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6458. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6458. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6458. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6458. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6484. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6484. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6484. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6484. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6542. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6542. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6542. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6542. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6542. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6555. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6555. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6555. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6555. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6570. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6570. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6570. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6570. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6587. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6587. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6587. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6587. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6606. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6606. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6606. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6606. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6627. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6627. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6627. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6627. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6650. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6650. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6650. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6650. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6675. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6675. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6675. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6675. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6702. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6702. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6702. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6702. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6731. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6731. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6731. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6731. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6762. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6762. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6762. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6762. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6795. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6795. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6795. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6795. dead port 1/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6830. dead port 2/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6830. dead port 3/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6830. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6870. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6870. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6870. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6870. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6870. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6880. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6880. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6880. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6880. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6894. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6894. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6894. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6894. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6910. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6910. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6910. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6910. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6930. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6930. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6930. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6930. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6954. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6954. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6954. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6954. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6982. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6982. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6982. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$6982. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7014. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7014. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7014. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7014. dead port 1/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7050. dead port 2/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7050. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7057. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7057. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7057. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7057. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7057. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7068. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7068. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7068. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7068. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7090. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7090. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7090. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7090. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7124. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7124. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7124. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7124. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7154. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7154. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7154. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7154. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7166. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7166. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7166. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7166. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7184. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7184. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7184. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7184. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7192. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7192. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7192. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7192. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7192. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7218. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7218. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7218. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7218. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7276. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7276. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7276. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7276. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7276. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7289. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7289. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7289. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7289. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7304. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7304. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7304. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7304. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7321. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7321. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7321. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7321. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7340. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7340. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7340. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7340. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7361. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7361. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7361. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7361. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7384. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7384. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7384. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7384. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7384. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7409. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7409. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7409. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7409. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7409. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7436. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7436. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7436. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7436. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7465. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7465. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7465. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7465. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7496. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7496. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7496. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7496. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7529. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7529. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7529. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7529. dead port 1/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7564. dead port 2/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7564. dead port 3/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7564. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7604. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7604. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7604. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7604. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7604. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7614. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7614. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7614. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7614. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7628. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7628. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7628. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7628. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7644. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7644. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7644. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7644. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7664. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7664. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7664. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7664. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7688. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7688. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7688. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7688. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7688. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7716. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7716. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7716. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7716. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7748. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7748. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7748. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7748. dead port 1/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7784. dead port 2/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7784. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7791. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7791. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7791. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7791. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7791. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7802. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7802. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7802. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7802. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7824. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7824. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7824. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7824. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7824. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7858. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7858. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7858. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7858. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7888. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7888. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7888. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7888. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7900. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7900. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7900. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7900. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7918. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7918. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7918. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7918. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7926. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7926. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7926. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7926. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7926. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7952. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7952. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7952. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$7952. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8010. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8010. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8010. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8010. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8010. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8023. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8023. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8023. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8023. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8023. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8038. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8038. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8038. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8038. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8055. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8055. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8055. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8055. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8074. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8074. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8074. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8074. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8095. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8095. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8095. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8095. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8118. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8118. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8118. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8118. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8118. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8143. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8143. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8143. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8143. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8143. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8170. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8170. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8170. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8170. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8199. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8199. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8199. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8199. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8230. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8230. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8230. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8230. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8263. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8263. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8263. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8263. dead port 1/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8298. dead port 2/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8298. dead port 3/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8298. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8338. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8338. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8338. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8338. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8338. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8348. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8348. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8348. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8348. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8348. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8362. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8362. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8362. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8362. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8378. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8378. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8378. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8378. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8398. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8398. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8398. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8398. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8422. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8422. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8422. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8422. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8422. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8450. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8450. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8450. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8450. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8482. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8482. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8482. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8482. dead port 1/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8518. dead port 2/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8518. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8525. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8525. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8525. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8525. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8525. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8536. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8536. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8536. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8536. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8536. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8558. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8558. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8558. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8558. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8558. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8592. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8592. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8592. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8592. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8622. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8622. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8622. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8622. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8634. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8634. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8634. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8634. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8634. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8652. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8652. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8652. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8652. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8660. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8660. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8660. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8660. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8660. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8686. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8686. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8686. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8686. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8744. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8744. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8744. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8744. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8744. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8757. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8757. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8757. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8757. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8757. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8772. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8772. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8772. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8772. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8789. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8789. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8789. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8789. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8808. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8808. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8808. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8808. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8829. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8829. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8829. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8829. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8852. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8852. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8852. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8852. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8852. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8877. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8877. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8877. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8877. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8877. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8904. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8904. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8904. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8904. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8904. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8933. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8933. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8933. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8933. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8933. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8964. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8964. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8964. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8964. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8997. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8997. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8997. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$8997. dead port 1/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9032. dead port 2/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9032. dead port 3/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9032. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9072. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9072. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9072. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9072. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9072. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9082. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9082. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9082. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9082. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9082. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9096. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9096. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9096. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9096. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9112. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9112. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9112. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9112. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9132. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9132. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9132. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9132. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9156. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9156. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9156. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9156. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9156. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9184. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9184. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9184. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9184. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9184. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9216. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9216. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9216. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9216. dead port 1/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9252. dead port 2/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9252. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9259. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9259. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9259. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9259. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9259. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9270. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9270. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9270. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9270. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9270. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9292. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9292. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9292. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9292. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9292. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9326. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9326. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9326. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9326. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9356. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9356. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9356. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9356. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9368. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9368. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9368. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9368. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9368. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9386. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9386. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9386. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9386. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9394. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9394. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9394. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9394. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9394. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9420. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9420. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9420. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9420. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9420. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9478. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9478. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9478. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9478. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9478. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9491. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9491. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9491. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9491. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9491. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9506. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9506. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9506. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9506. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9506. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9523. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9523. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9523. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9523. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9523. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9542. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9542. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9542. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9542. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9563. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9563. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9563. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9563. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9586. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9586. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9586. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9586. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9586. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9611. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9611. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9611. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9611. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9611. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9638. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9638. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9638. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9638. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9638. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9667. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9667. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9667. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9667. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9667. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9698. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9698. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9698. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9698. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9731. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9731. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9731. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9731. dead port 1/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9766. dead port 2/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9766. dead port 3/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9766. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9806. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9806. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9806. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9806. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9806. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9816. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9816. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9816. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9816. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9816. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9830. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9830. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9830. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9830. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9830. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9846. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9846. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9846. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9846. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9846. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9866. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9866. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9866. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9866. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9890. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9890. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9890. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9890. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9890. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9918. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9918. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9918. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9918. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9918. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9950. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9950. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9950. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9950. dead port 1/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9986. dead port 2/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9986. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9993. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9993. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9993. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9993. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$9993. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10004. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10004. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10004. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10004. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10004. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10026. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10026. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10026. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10026. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10026. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10060. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10060. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10060. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10060. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10090. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10090. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10090. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10090. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10102. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10102. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10102. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10102. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10102. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10120. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10120. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10120. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10120. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10128. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10128. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10128. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10128. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10128. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10154. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10154. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10154. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10154. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10154. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10212. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10212. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10212. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10212. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10212. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10225. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10225. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10225. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10225. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10225. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10240. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10240. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10240. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10240. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10240. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10257. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10257. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10257. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10257. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10257. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10276. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10276. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10276. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10276. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10297. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10297. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10297. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10297. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10320. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10320. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10320. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10320. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10320. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10345. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10345. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10345. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10345. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10345. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10372. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10372. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10372. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10372. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10372. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10401. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10401. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10401. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10401. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10401. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10432. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10432. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10432. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10432. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10432. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10465. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10465. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10465. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10465. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10465. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10500. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10500. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10500. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10540. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10540. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10540. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10540. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10540. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10550. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10550. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10550. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10550. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10550. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10564. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10564. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10564. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10564. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10564. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10580. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10580. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10580. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10580. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10580. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10600. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10600. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10600. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10600. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10624. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10624. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10624. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10624. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10624. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10652. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10652. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10652. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10652. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10652. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10684. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10684. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10684. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10684. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10684. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10720. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10720. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10727. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10727. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10727. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10727. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10727. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10738. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10738. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10738. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10738. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10738. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10760. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10760. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10760. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10760. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10760. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10794. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10794. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10794. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10794. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10824. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10824. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10824. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10824. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10824. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10836. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10836. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10836. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10836. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10836. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10854. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10854. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10854. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10854. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10862. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10862. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10862. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10862. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10862. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10888. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10888. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10888. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10888. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10888. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10946. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10946. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10946. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10946. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10946. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10959. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10959. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10959. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10959. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10959. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10974. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10974. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10974. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10974. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10974. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10991. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10991. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10991. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10991. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10991. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11010. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11010. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11010. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11010. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11010. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11031. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11031. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11031. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11031. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11031. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11054. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11054. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11054. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11054. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11054. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11079. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11079. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11079. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11079. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11079. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11106. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11106. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11106. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11106. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11106. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11135. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11135. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11135. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11135. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11135. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11166. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11166. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11166. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11166. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11166. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11199. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11199. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11199. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11199. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11199. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11234. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11234. dead port 4/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11234. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11274. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11274. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11274. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11274. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11274. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11284. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11284. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11284. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11284. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11284. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11298. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11298. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11298. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11298. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11298. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11314. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11314. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11314. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11314. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11314. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11334. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11334. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11334. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11334. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11334. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11358. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11358. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11358. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11358. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11358. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11386. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11386. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11386. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11386. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11386. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11418. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11418. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11418. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11418. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11418. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11454. dead port 3/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11454. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11461. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11461. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11461. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11461. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11461. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11472. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11472. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11472. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11472. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11472. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11494. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11494. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11494. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11494. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11494. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11528. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11528. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11528. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11528. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11558. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11558. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11558. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11558. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11558. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11570. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11570. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11570. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11570. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11570. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11588. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11588. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11588. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11588. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11588. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11596. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11596. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11596. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11596. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11596. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11622. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11622. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11622. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11622. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11622. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5808. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5808. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5808. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5808. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5821. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5821. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5821. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5821. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5836. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5836. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5836. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5836. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5853. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5853. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5853. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5853. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5872. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5872. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5872. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5872. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5893. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5893. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5893. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5893. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5916. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5916. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5916. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5916. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5941. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5941. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5941. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5941. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5968. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5968. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5968. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5968. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5997. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5997. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5997. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5997. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6028. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6028. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6028. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6028. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6061. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6061. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6061. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6061. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6096. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6096. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6096. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6136. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6136. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6136. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6136. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6146. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6146. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6146. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6146. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6160. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6160. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6160. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6160. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6176. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6176. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6176. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6176. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6196. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6196. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6196. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6196. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6220. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6220. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6220. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6220. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6248. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6248. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6248. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6248. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6280. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6280. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6280. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6280. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6316. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6316. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6323. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6323. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6323. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6323. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6334. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6334. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6334. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6334. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6356. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6356. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6356. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6356. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6390. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6390. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6390. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6390. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6420. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6420. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6420. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6420. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6432. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6432. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6432. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6432. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6450. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6450. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6450. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6450. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6458. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6458. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6458. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6458. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6484. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6484. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6484. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6484. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6542. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6542. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6542. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6542. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6542. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6555. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6555. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6555. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6555. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6570. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6570. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6570. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6570. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6587. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6587. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6587. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6587. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6606. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6606. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6606. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6606. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6627. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6627. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6627. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6627. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6650. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6650. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6650. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6650. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6675. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6675. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6675. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6675. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6702. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6702. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6702. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6702. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6731. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6731. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6731. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6731. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6762. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6762. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6762. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6762. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6795. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6795. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6795. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6795. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6830. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6830. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6830. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6870. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6870. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6870. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6870. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6870. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6880. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6880. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6880. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6880. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6894. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6894. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6894. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6894. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6910. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6910. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6910. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6910. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6930. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6930. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6930. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6930. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6954. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6954. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6954. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6954. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6982. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6982. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6982. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6982. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7014. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7014. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7014. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7014. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7050. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7050. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7057. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7057. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7057. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7057. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7057. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7068. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7068. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7068. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7068. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7090. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7090. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7090. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7090. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7124. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7124. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7124. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7124. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7154. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7154. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7154. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7154. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7166. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7166. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7166. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7166. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7184. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7184. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7184. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7184. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7192. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7192. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7192. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7192. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7192. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7218. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7218. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7218. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7218. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7276. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7276. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7276. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7276. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7276. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7289. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7289. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7289. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7289. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7304. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7304. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7304. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7304. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7321. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7321. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7321. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7321. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7340. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7340. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7340. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7340. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7361. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7361. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7361. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7361. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7384. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7384. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7384. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7384. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7384. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7409. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7409. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7409. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7409. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7409. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7436. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7436. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7436. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7436. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7465. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7465. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7465. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7465. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7496. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7496. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7496. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7496. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7529. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7529. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7529. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7529. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7564. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7564. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7564. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7604. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7604. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7604. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7604. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7604. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7614. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7614. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7614. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7614. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7628. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7628. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7628. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7628. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7644. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7644. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7644. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7644. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7664. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7664. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7664. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7664. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7688. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7688. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7688. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7688. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7688. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7716. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7716. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7716. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7716. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7748. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7748. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7748. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7748. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7784. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7784. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7791. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7791. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7791. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7791. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7791. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7802. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7802. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7802. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7802. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7824. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7824. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7824. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7824. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7824. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7858. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7858. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7858. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7858. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7888. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7888. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7888. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7888. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7900. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7900. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7900. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7900. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7918. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7918. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7918. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7918. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7926. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7926. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7926. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7926. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7926. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7952. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7952. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7952. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7952. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8010. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8010. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8010. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8010. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8010. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8023. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8023. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8023. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8023. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8023. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8038. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8038. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8038. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8038. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8055. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8055. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8055. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8055. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8074. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8074. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8074. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8074. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8095. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8095. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8095. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8095. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8118. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8118. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8118. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8118. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8118. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8143. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8143. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8143. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8143. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8143. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8170. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8170. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8170. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8170. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8199. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8199. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8199. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8199. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8230. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8230. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8230. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8230. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8263. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8263. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8263. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8263. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8298. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8298. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8298. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8338. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8338. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8338. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8338. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8338. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8348. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8348. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8348. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8348. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8348. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8362. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8362. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8362. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8362. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8378. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8378. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8378. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8378. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8398. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8398. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8398. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8398. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8422. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8422. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8422. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8422. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8422. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8450. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8450. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8450. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8450. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8482. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8482. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8482. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8482. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8518. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8518. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8525. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8525. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8525. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8525. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8525. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8536. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8536. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8536. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8536. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8536. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8558. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8558. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8558. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8558. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8558. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8592. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8592. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8592. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8592. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8622. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8622. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8622. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8622. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8634. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8634. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8634. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8634. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8634. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8652. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8652. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8652. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8652. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8660. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8660. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8660. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8660. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8660. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8686. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8686. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8686. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8686. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8744. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8744. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8744. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8744. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8744. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8757. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8757. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8757. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8757. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8757. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8772. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8772. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8772. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8772. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8789. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8789. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8789. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8789. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8808. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8808. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8808. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8808. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8829. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8829. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8829. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8829. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8852. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8852. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8852. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8852. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8852. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8877. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8877. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8877. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8877. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8877. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8904. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8904. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8904. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8904. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8904. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8933. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8933. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8933. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8933. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8933. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8964. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8964. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8964. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8964. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8997. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8997. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8997. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8997. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9032. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9032. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9032. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9072. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9072. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9072. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9072. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9072. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9082. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9082. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9082. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9082. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9082. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9096. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9096. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9096. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9096. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9112. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9112. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9112. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9112. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9132. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9132. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9132. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9132. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9156. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9156. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9156. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9156. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9156. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9184. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9184. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9184. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9184. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9184. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9216. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9216. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9216. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9216. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9252. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9252. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9259. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9259. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9259. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9259. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9259. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9270. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9270. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9270. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9270. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9270. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9292. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9292. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9292. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9292. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9292. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9326. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9326. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9326. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9326. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9356. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9356. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9356. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9356. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9368. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9368. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9368. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9368. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9368. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9386. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9386. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9386. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9386. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9394. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9394. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9394. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9394. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9394. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9420. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9420. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9420. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9420. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9420. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9478. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9478. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9478. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9478. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9478. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9491. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9491. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9491. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9491. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9491. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9506. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9506. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9506. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9506. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9506. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9523. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9523. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9523. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9523. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9523. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9542. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9542. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9542. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9542. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9563. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9563. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9563. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9563. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9586. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9586. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9586. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9586. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9586. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9611. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9611. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9611. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9611. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9611. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9638. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9638. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9638. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9638. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9638. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9667. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9667. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9667. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9667. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9667. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9698. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9698. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9698. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9698. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9731. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9731. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9731. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9731. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9766. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9766. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9766. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9806. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9806. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9806. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9806. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9806. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9816. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9816. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9816. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9816. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9816. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9830. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9830. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9830. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9830. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9830. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9846. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9846. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9846. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9846. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9846. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9866. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9866. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9866. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9866. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9890. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9890. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9890. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9890. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9890. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9918. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9918. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9918. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9918. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9918. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9950. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9950. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9950. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9950. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9986. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9986. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9993. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9993. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9993. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9993. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9993. dead port 1/2 on $mux $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procmux$12289. dead port 2/2 on $mux $flatten\soc_I.\usb_I.$procmux$15311. dead port 1/2 on $mux $flatten\misc_I.\dfu_I.\btn_flt_I.$procmux$5634. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11963. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11965. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11967. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11974. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11976. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11982. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11990. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11992. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11999. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12008. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12010. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12018. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12028. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12030. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12039. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12049. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12062. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12065. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12068. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12070. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12072. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12085. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12088. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12090. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12092. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12105. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12107. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12109. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12121. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12123. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12134. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12146. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12159. dead port 1/2 on $mux $flatten\misc_I.\pps_flt_I.$procmux$12479. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11754. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11761. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11769. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11780. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11782. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11784. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11794. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11796. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11805. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11816. dead port 2/2 on $mux $flatten\spi_mux_I.$procmux$15498. dead port 2/2 on $mux $flatten\spi_mux_I.$procmux$15505. dead port 2/2 on $mux $flatten\spi_mux_I.$procmux$15513. dead port 2/2 on $mux $flatten\spi_mux_I.$procmux$15522. dead port 2/2 on $mux $flatten\spi_mux_I.$procmux$15532. dead port 2/2 on $mux $flatten\spi_mux_I.$procmux$15543. dead port 1/2 on $mux $flatten\spi_mux_I.$procmux$15556. dead port 2/2 on $mux $flatten\spi_mux_I.$procmux$15558. dead port 2/2 on $mux $flatten\spi_mux_I.$procmux$15570. Removed 2334 multiplexer ports. 75.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $flatten\soc_I.\e1_buf_I.$reduce_or$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:195$5286: { \soc_I.cpu_I.do_waitirq \soc_I.e1_buf_I.tx_pending [0] \soc_I.e1_buf_I.rx_pending [0] } Consolidated identical input bits for $mux cell $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$procmux$5744: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 New ports: A=1'0, B=1'1, Y=$flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] New connections: $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [7:1] = { $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13531: { \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu \soc_I.cpu_I.is_slli_srli_srai $auto$opt_reduce.cc:134:opt_mux$23564 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13713: \soc_I.cpu_I.is_sb_sh_sw New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13725: \soc_I.cpu_I.is_sb_sh_sw New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13729: { \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu $auto$opt_reduce.cc:134:opt_mux$23566 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13891: { $auto$opt_reduce.cc:134:opt_mux$23570 $auto$opt_reduce.cc:134:opt_mux$23568 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$14039: $auto$opt_reduce.cc:134:opt_mux$23572 New ctrl vector for $pmux cell $flatten\i2c_I.\core_I.$procmux$15372: { $auto$opt_reduce.cc:134:opt_mux$23576 $auto$opt_reduce.cc:134:opt_mux$23574 } New ctrl vector for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$procmux$15661: { } Consolidated identical input bits for $mux cell $flatten\soc_I.\bram_I.$procmux$15271: Old ports: A=0, B=32'11111111000000000000000000000000, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3501_EN[31:0]$3514 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3501_EN[31:0]$3514 [24] New connections: { $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3501_EN[31:0]$3514 [31:25] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3501_EN[31:0]$3514 [23:0] } = { $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3501_EN[31:0]$3514 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3501_EN[31:0]$3514 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3501_EN[31:0]$3514 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3501_EN[31:0]$3514 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3501_EN[31:0]$3514 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3501_EN[31:0]$3514 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3501_EN[31:0]$3514 [24] 24'000000000000000000000000 } New ctrl vector for $mux cell $flatten\soc_I.\cpu_I.$procmux$12614: { } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12633: { } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12651: $auto$opt_reduce.cc:134:opt_mux$23578 New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12932: { $flatten\soc_I.\cpu_I.$procmux$12646_CMP $auto$opt_reduce.cc:134:opt_mux$23580 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12945: { $auto$opt_reduce.cc:134:opt_mux$23582 $flatten\soc_I.\cpu_I.$procmux$12624_CMP } Consolidated identical input bits for $mux cell $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$procmux$5744: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 New ports: A=1'0, B=1'1, Y=$flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] New connections: $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [7:1] = { $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12958: { $flatten\soc_I.\cpu_I.$procmux$12655_CMP $auto$opt_reduce.cc:134:opt_mux$23584 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13102: { } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13106: $flatten\soc_I.\cpu_I.$procmux$12635_CMP New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13112: { } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13116: { } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13145: $auto$opt_reduce.cc:134:opt_mux$23586 New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13154: $auto$opt_reduce.cc:134:opt_mux$23588 New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13158: { $auto$opt_reduce.cc:134:opt_mux$23592 $auto$opt_reduce.cc:134:opt_mux$23590 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13184: { $flatten\soc_I.\cpu_I.$procmux$12655_CMP $flatten\soc_I.\cpu_I.$procmux$12654_CMP $flatten\soc_I.\cpu_I.$procmux$12624_CMP } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13243: { \soc_I.cpu_I.is_slli_srli_srai $auto$opt_reduce.cc:134:opt_mux$23594 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13285: { $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4064_Y $flatten\soc_I.\cpu_I.$procmux$12655_CMP } Consolidated identical input bits for $mux cell $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$procmux$5744: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] New connections: $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [7:1] = { $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] } Consolidated identical input bits for $mux cell $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$procmux$5744: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] New connections: $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [7:1] = { $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN[7:0]$5455 [0] } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.$procmux$15307: { $flatten\gps_uart_I.$eq$/build/gateware/cores/no2misc//rtl/uart_wb.v:171$3276_Y $flatten\soc_I.\iobuf_I.\dma_I.$eq$/build/gateware/common/rtl/wb_dma.v:164$5037_Y } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.\phy_I.$procmux$5710: { $auto$opt_reduce.cc:134:opt_mux$23602 $auto$opt_reduce.cc:134:opt_mux$23600 $flatten\soc_I.\usb_I.\phy_I.$procmux$5719_CMP $flatten\soc_I.\usb_I.\phy_I.$procmux$5718_CMP $auto$opt_reduce.cc:134:opt_mux$23598 $auto$opt_reduce.cc:134:opt_mux$23596 } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.\phy_I.$procmux$5727: { $auto$opt_reduce.cc:134:opt_mux$23610 $auto$opt_reduce.cc:134:opt_mux$23608 $flatten\soc_I.\usb_I.\phy_I.$procmux$5736_CMP $flatten\soc_I.\usb_I.\phy_I.$procmux$5735_CMP $auto$opt_reduce.cc:134:opt_mux$23606 $auto$opt_reduce.cc:134:opt_mux$23604 } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12173: { $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12181_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12180_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12179_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12178_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12177_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12176_CMP $auto$opt_reduce.cc:134:opt_mux$23612 } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12205: { $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12209_CMP $auto$opt_reduce.cc:134:opt_mux$23614 $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12206_CMP } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12216: { $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12223_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12222_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12221_CMP $auto$opt_reduce.cc:134:opt_mux$23616 $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12219_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12218_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12217_CMP } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13382: { $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4064_Y $flatten\soc_I.\cpu_I.$procmux$12655_CMP } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13425: { $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4064_Y $flatten\soc_I.\cpu_I.$procmux$12655_CMP $auto$opt_reduce.cc:134:opt_mux$23618 } New ctrl vector for $pmux cell $flatten\spi_mux_I.$procmux$15474: $auto$opt_reduce.cc:134:opt_mux$23620 New ctrl vector for $pmux cell $flatten\spi_mux_I.$procmux$15478: $auto$opt_reduce.cc:134:opt_mux$23622 New ctrl vector for $pmux cell $flatten\spi_mux_I.$procmux$15484: $auto$opt_reduce.cc:134:opt_mux$23624 Consolidated identical input bits for $mux cell $flatten\soc_I.\bram_I.$procmux$15253: Old ports: A=0, B=255, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3498_EN[31:0]$3505 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3498_EN[31:0]$3505 [0] New connections: $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3498_EN[31:0]$3505 [31:1] = { 24'000000000000000000000000 $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3498_EN[31:0]$3505 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3498_EN[31:0]$3505 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3498_EN[31:0]$3505 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3498_EN[31:0]$3505 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3498_EN[31:0]$3505 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3498_EN[31:0]$3505 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3498_EN[31:0]$3505 [0] } Consolidated identical input bits for $mux cell $flatten\soc_I.\bram_I.$procmux$15259: Old ports: A=0, B=65280, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3499_EN[31:0]$3508 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3499_EN[31:0]$3508 [8] New connections: { $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3499_EN[31:0]$3508 [31:9] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3499_EN[31:0]$3508 [7:0] } = { 16'0000000000000000 $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3499_EN[31:0]$3508 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3499_EN[31:0]$3508 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3499_EN[31:0]$3508 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3499_EN[31:0]$3508 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3499_EN[31:0]$3508 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3499_EN[31:0]$3508 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3499_EN[31:0]$3508 [8] 8'00000000 } Consolidated identical input bits for $mux cell $flatten\soc_I.\bram_I.$procmux$15265: Old ports: A=0, B=16711680, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3500_EN[31:0]$3511 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3500_EN[31:0]$3511 [16] New connections: { $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3500_EN[31:0]$3511 [31:17] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3500_EN[31:0]$3511 [15:0] } = { 8'00000000 $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3500_EN[31:0]$3511 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3500_EN[31:0]$3511 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3500_EN[31:0]$3511 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3500_EN[31:0]$3511 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3500_EN[31:0]$3511 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3500_EN[31:0]$3511 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3500_EN[31:0]$3511 [16] 16'0000000000000000 } New ctrl vector for $mux cell $flatten\soc_I.\cpu_I.$procmux$13106: { } New ctrl vector for $mux cell $flatten\soc_I.\cpu_I.$procmux$13130: { } Optimizing cells in module \top. Performed a total of 46 changes. 75.10.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 18 cells. 75.10.6. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$23170 ($dff) from module top. Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22697 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22630 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22563 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22496 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22429 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22218 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22007 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21796 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21585 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21374 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21163 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20952 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20741 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20530 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20319 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20108 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19897 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19686 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19475 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19264 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19053 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18842 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18631 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18420 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18209 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17998 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17787 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17576 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17365 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17154 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16943 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16732 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16521 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16310 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16147 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16032 ($dlatch) from module top (changing to combinatorial circuit). Setting constant 0-bit at position 0 on $flatten\soc_I.\cpu_I.$procdff$23293 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\cpu_I.$procdff$23254 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\cpu_I.$procdff$23254 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\cpu_I.$procdff$23253 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\cpu_I.$procdff$23253 ($dff) from module top. Setting constant 1-bit at position 0 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 1 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 2 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 3 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 4 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 5 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 6 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 7 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 8 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 9 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 10 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 11 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 12 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 13 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 14 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 15 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 16 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 17 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 18 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 19 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 20 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 21 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 22 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 23 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 24 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 25 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 26 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 27 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 28 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 29 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 30 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 31 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 32 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 33 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 34 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 35 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 36 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 37 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 38 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 39 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 40 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 41 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 42 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 43 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 44 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 45 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 46 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 47 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 48 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 49 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 50 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 51 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 52 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 53 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 54 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 55 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 56 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 57 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 58 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 59 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 60 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 61 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 62 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Setting constant 1-bit at position 63 on $flatten\soc_I.\cpu_I.$procdff$23251 ($dff) from module top. Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22764 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22697 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22630 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22563 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22496 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22429 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22218 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22007 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21796 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21585 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21374 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21163 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20952 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20741 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20530 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20319 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20108 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19897 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19686 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19475 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19264 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19053 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18842 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18631 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18420 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18209 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17998 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17787 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17576 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17365 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17154 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16943 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16732 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16521 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16310 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16147 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16032 ($dlatch) from module top (changing to combinatorial circuit). Setting constant 0-bit at position 0 on $flatten\soc_I.\e1_buf_I.$procdff$23202 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\e1_buf_I.$procdff$23202 ($dff) from module top. Setting constant 0-bit at position 2 on $flatten\soc_I.\e1_buf_I.$procdff$23202 ($dff) from module top. Setting constant 0-bit at position 3 on $flatten\soc_I.\e1_buf_I.$procdff$23202 ($dff) from module top. Setting constant 0-bit at position 4 on $flatten\soc_I.\e1_buf_I.$procdff$23202 ($dff) from module top. Setting constant 0-bit at position 5 on $flatten\soc_I.\e1_buf_I.$procdff$23202 ($dff) from module top. Setting constant 0-bit at position 6 on $flatten\soc_I.\e1_buf_I.$procdff$23202 ($dff) from module top. Setting constant 0-bit at position 7 on $flatten\soc_I.\e1_buf_I.$procdff$23202 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\e1_buf_I.$procdff$23196 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\e1_buf_I.$procdff$23196 ($dff) from module top. Setting constant 0-bit at position 2 on $flatten\soc_I.\e1_buf_I.$procdff$23196 ($dff) from module top. Setting constant 0-bit at position 3 on $flatten\soc_I.\e1_buf_I.$procdff$23196 ($dff) from module top. Setting constant 0-bit at position 4 on $flatten\soc_I.\e1_buf_I.$procdff$23196 ($dff) from module top. Setting constant 0-bit at position 5 on $flatten\soc_I.\e1_buf_I.$procdff$23196 ($dff) from module top. Setting constant 0-bit at position 6 on $flatten\soc_I.\e1_buf_I.$procdff$23196 ($dff) from module top. Setting constant 0-bit at position 7 on $flatten\soc_I.\e1_buf_I.$procdff$23196 ($dff) from module top. Setting constant 0-bit at position 8 on $flatten\soc_I.\e1_buf_I.$procdff$23196 ($dff) from module top. Setting constant 0-bit at position 9 on $flatten\soc_I.\e1_buf_I.$procdff$23196 ($dff) from module top. Setting constant 0-bit at position 10 on $flatten\soc_I.\e1_buf_I.$procdff$23196 ($dff) from module top. Setting constant 0-bit at position 11 on $flatten\soc_I.\e1_buf_I.$procdff$23196 ($dff) from module top. Setting constant 0-bit at position 12 on $flatten\soc_I.\e1_buf_I.$procdff$23196 ($dff) from module top. Setting constant 0-bit at position 13 on $flatten\soc_I.\e1_buf_I.$procdff$23196 ($dff) from module top. Setting constant 0-bit at position 14 on $flatten\soc_I.\e1_buf_I.$procdff$23196 ($dff) from module top. Setting constant 0-bit at position 15 on $flatten\soc_I.\e1_buf_I.$procdff$23196 ($dff) from module top. 75.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 31 unused cells and 686 unused wires. 75.10.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.10.9. Rerunning OPT passes. (Maybe there is more to do..) 75.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 75.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $flatten\soc_I.\e1_buf_I.$reduce_or$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:195$5286: { \soc_I.e1_buf_I.tx_pending [0] \soc_I.e1_buf_I.rx_pending [0] } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13055: $auto$opt_reduce.cc:134:opt_mux$23626 New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13072: { $flatten\soc_I.\cpu_I.$procmux$12655_CMP $auto$opt_reduce.cc:134:opt_mux$23628 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13139: { $flatten\soc_I.\cpu_I.$procmux$12635_CMP $flatten\soc_I.\cpu_I.$procmux$12634_CMP } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13490: { $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4064_Y $flatten\soc_I.\cpu_I.$procmux$12635_CMP $flatten\soc_I.\cpu_I.$procmux$12634_CMP $flatten\soc_I.\cpu_I.$procmux$12655_CMP $flatten\soc_I.\cpu_I.$procmux$12654_CMP $auto$opt_reduce.cc:134:opt_mux$23630 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$14953: { $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:364$3661_Y $auto$opt_reduce.cc:134:opt_mux$23632 } Optimizing cells in module \top. Performed a total of 6 changes. 75.10.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 2 cells. 75.10.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$23163 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 8 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 9 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 10 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 11 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 12 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 13 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 14 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 15 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 16 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 17 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 18 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 19 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 20 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 21 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 22 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 23 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 8 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 9 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 10 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 11 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 12 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 13 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 14 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 15 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 24 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 25 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 26 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 27 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 28 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 29 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 30 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 31 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$23413 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$23413 ($dff) from module top. Setting constant 0-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$23413 ($dff) from module top. Setting constant 0-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$23413 ($dff) from module top. Setting constant 0-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$23413 ($dff) from module top. Setting constant 0-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$23413 ($dff) from module top. Setting constant 0-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$23413 ($dff) from module top. Setting constant 0-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$23413 ($dff) from module top. Setting constant 0-bit at position 16 on $flatten\soc_I.\bram_I.$procdff$23413 ($dff) from module top. Setting constant 0-bit at position 17 on $flatten\soc_I.\bram_I.$procdff$23413 ($dff) from module top. Setting constant 0-bit at position 18 on $flatten\soc_I.\bram_I.$procdff$23413 ($dff) from module top. Setting constant 0-bit at position 19 on $flatten\soc_I.\bram_I.$procdff$23413 ($dff) from module top. Setting constant 0-bit at position 20 on $flatten\soc_I.\bram_I.$procdff$23413 ($dff) from module top. Setting constant 0-bit at position 21 on $flatten\soc_I.\bram_I.$procdff$23413 ($dff) from module top. Setting constant 0-bit at position 22 on $flatten\soc_I.\bram_I.$procdff$23413 ($dff) from module top. Setting constant 0-bit at position 23 on $flatten\soc_I.\bram_I.$procdff$23413 ($dff) from module top. Setting constant 0-bit at position 24 on $flatten\soc_I.\bram_I.$procdff$23413 ($dff) from module top. Setting constant 0-bit at position 25 on $flatten\soc_I.\bram_I.$procdff$23413 ($dff) from module top. Setting constant 0-bit at position 26 on $flatten\soc_I.\bram_I.$procdff$23413 ($dff) from module top. Setting constant 0-bit at position 27 on $flatten\soc_I.\bram_I.$procdff$23413 ($dff) from module top. Setting constant 0-bit at position 28 on $flatten\soc_I.\bram_I.$procdff$23413 ($dff) from module top. Setting constant 0-bit at position 29 on $flatten\soc_I.\bram_I.$procdff$23413 ($dff) from module top. Setting constant 0-bit at position 30 on $flatten\soc_I.\bram_I.$procdff$23413 ($dff) from module top. Setting constant 0-bit at position 31 on $flatten\soc_I.\bram_I.$procdff$23413 ($dff) from module top. Setting constant 0-bit at position 8 on $flatten\soc_I.\bram_I.$procdff$23410 ($dff) from module top. Setting constant 0-bit at position 9 on $flatten\soc_I.\bram_I.$procdff$23410 ($dff) from module top. Setting constant 0-bit at position 10 on $flatten\soc_I.\bram_I.$procdff$23410 ($dff) from module top. Setting constant 0-bit at position 11 on $flatten\soc_I.\bram_I.$procdff$23410 ($dff) from module top. Setting constant 0-bit at position 12 on $flatten\soc_I.\bram_I.$procdff$23410 ($dff) from module top. Setting constant 0-bit at position 13 on $flatten\soc_I.\bram_I.$procdff$23410 ($dff) from module top. Setting constant 0-bit at position 14 on $flatten\soc_I.\bram_I.$procdff$23410 ($dff) from module top. Setting constant 0-bit at position 15 on $flatten\soc_I.\bram_I.$procdff$23410 ($dff) from module top. Setting constant 0-bit at position 16 on $flatten\soc_I.\bram_I.$procdff$23410 ($dff) from module top. Setting constant 0-bit at position 17 on $flatten\soc_I.\bram_I.$procdff$23410 ($dff) from module top. Setting constant 0-bit at position 18 on $flatten\soc_I.\bram_I.$procdff$23410 ($dff) from module top. Setting constant 0-bit at position 19 on $flatten\soc_I.\bram_I.$procdff$23410 ($dff) from module top. Setting constant 0-bit at position 20 on $flatten\soc_I.\bram_I.$procdff$23410 ($dff) from module top. Setting constant 0-bit at position 21 on $flatten\soc_I.\bram_I.$procdff$23410 ($dff) from module top. Setting constant 0-bit at position 22 on $flatten\soc_I.\bram_I.$procdff$23410 ($dff) from module top. Setting constant 0-bit at position 23 on $flatten\soc_I.\bram_I.$procdff$23410 ($dff) from module top. Setting constant 0-bit at position 24 on $flatten\soc_I.\bram_I.$procdff$23410 ($dff) from module top. Setting constant 0-bit at position 25 on $flatten\soc_I.\bram_I.$procdff$23410 ($dff) from module top. Setting constant 0-bit at position 26 on $flatten\soc_I.\bram_I.$procdff$23410 ($dff) from module top. Setting constant 0-bit at position 27 on $flatten\soc_I.\bram_I.$procdff$23410 ($dff) from module top. Setting constant 0-bit at position 28 on $flatten\soc_I.\bram_I.$procdff$23410 ($dff) from module top. Setting constant 0-bit at position 29 on $flatten\soc_I.\bram_I.$procdff$23410 ($dff) from module top. Setting constant 0-bit at position 30 on $flatten\soc_I.\bram_I.$procdff$23410 ($dff) from module top. Setting constant 0-bit at position 31 on $flatten\soc_I.\bram_I.$procdff$23410 ($dff) from module top. 75.10.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 9 unused wires. 75.10.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.10.16. Rerunning OPT passes. (Maybe there is more to do..) 75.10.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 75.10.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 75.10.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.10.20. Executing OPT_DFF pass (perform DFF optimizations). 75.10.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 1 unused wires. 75.10.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.10.23. Rerunning OPT passes. (Maybe there is more to do..) 75.10.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 75.10.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 75.10.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.10.27. Executing OPT_DFF pass (perform DFF optimizations). 75.10.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.10.29. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.10.30. Finished OPT passes. (There is nothing left to do.) 75.11. Executing FSM pass (extract and optimize FSM). 75.11.1. Executing FSM_DETECT pass (finding FSMs in design). Not marking top.$flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.$flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.fsm_state. Not marking top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5451_EN as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register top.i2c_I.core_I.state. Found FSM state register top.soc_I.cpu_I.cpu_state. Not marking top.soc_I.cpu_I.mem_state as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register top.soc_I.cpu_I.mem_wordsize. Not marking top.soc_I.e1_buf_I.t_chan as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.iobuf_I.dma_I.state as FSM state register: Users of register don't seem to benefit from recoding. Circuit seems to be self-resetting. Not marking top.soc_I.iobuf_I.epbam_arb_I.sel as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.iobuf_I.spram_arb_I.sel as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.phy_I.dn_state as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.phy_I.dp_state as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.rx_ll_I.dec_eop_state_1 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.rx_ll_I.dec_rep_state_1 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.rx_ll_I.dec_sync_state_1 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.rx_ll_I.samp_cnt as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register top.soc_I.usb_I.rx_pkt_I.state. Not marking top.soc_I.usb_I.trans_I.epfw_state as FSM state register: Users of register don't seem to benefit from recoding. Circuit seems to be self-resetting. Not marking top.soc_I.usb_I.tx_ll_I.out_sym as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.tx_ll_I.state as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register top.soc_I.usb_I.tx_pkt_I.state. Not marking top.spi_mux_I.state as FSM state register: Users of register don't seem to benefit from recoding. 75.11.2. Executing FSM_EXTRACT pass (extracting FSM from design). Extracting FSM `$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.fsm_state' from module `\top'. found $dff cell for state register: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23556 root of input selection tree: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] found reset state: 3'000 (guessed from mux tree) found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$or$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:140$25_Y found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.crc_I.in_valid found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procmux$15920_CMP found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.align_mframe found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procmux$15934_CMP found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.align_frame found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:163$27_Y found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.mfa_timeout [6] found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:186$32_Y found state code: 3'100 found state code: 3'000 found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf found state code: 3'011 found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.fas_pos found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.data [6] found state code: 3'001 found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.data_match_fas found state code: 3'010 found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procmux$15934_CMP found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procmux$15920_CMP found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:378$137_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:312$71_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:312$70_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.align_mframe found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.align_frame ctrl inputs: { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.data [6] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.data_match_fas $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.fas_pos $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.mfa_timeout [6] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$or$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:140$25_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:163$27_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:186$32_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.crc_I.in_valid } ctrl outputs: { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.align_frame $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.align_mframe $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:312$70_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:312$71_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:378$137_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procmux$15920_CMP $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procmux$15934_CMP } transition: 3'000 9'-----0--0 -> 3'000 10'1000011000 transition: 3'000 9'-0---0--1 -> 3'000 10'1000011000 transition: 3'000 9'-1---0--1 -> 3'001 10'1000111000 transition: 3'000 9'-----1--- -> 3'000 10'1000011000 transition: 3'100 9'-----0--0 -> 3'100 10'0010010100 transition: 3'100 9'-----0--1 -> 3'100 10'0010010100 transition: 3'100 9'-----1--- -> 3'000 10'0000010100 transition: 3'010 9'-----0--0 -> 3'010 10'0101001000 transition: 3'010 9'-----00-1 -> 3'010 10'0101001000 transition: 3'010 9'---0001-1 -> 3'010 10'0101001000 transition: 3'010 9'---0101-1 -> 3'011 10'0101101000 transition: 3'010 9'---1-01-1 -> 3'000 10'0100001000 transition: 3'010 9'-----1--- -> 3'000 10'0100001000 transition: 3'001 9'-----0--0 -> 3'001 10'0000111001 transition: 3'001 9'-----00-1 -> 3'001 10'0000111001 transition: 3'001 9'0-0--01-1 -> 3'000 10'0000011001 transition: 3'001 9'1-0--01-1 -> 3'001 10'0000111001 transition: 3'001 9'-01--01-1 -> 3'000 10'0000011001 transition: 3'001 9'-11--01-1 -> 3'010 10'0001011001 transition: 3'001 9'-----1--- -> 3'000 10'0000011001 transition: 3'011 9'-----0--0 -> 3'011 10'0001111010 transition: 3'011 9'-----00-1 -> 3'011 10'0001111010 transition: 3'011 9'---0-0101 -> 3'011 10'0001111010 transition: 3'011 9'---0-0111 -> 3'100 10'0010011010 transition: 3'011 9'---1-01-1 -> 3'000 10'0000011010 transition: 3'011 9'-----1--- -> 3'000 10'0000011010 Extracting FSM `\i2c_I.core_I.state' from module `\top'. found $dff cell for state register: $flatten\i2c_I.\core_I.$procdff$23455 root of input selection tree: $flatten\i2c_I.\core_I.$0\state[2:0] found reset state: 3'000 (guessed from mux tree) found ctrl input: \blinker_I.rst found ctrl input: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:142$5205_Y found ctrl input: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:160$5209_Y found ctrl input: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:210$5214_Y found ctrl input: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:219$5217_Y found ctrl input: \i2c_I.ready found ctrl input: \i2c_I.core_I.cyc_cnt [4] found ctrl input: \i2c_I.core_I.bit_cnt [3] found state code: 3'010 found state code: 3'000 found ctrl input: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:109$5196_Y found state code: 3'001 found state code: 3'100 found state code: 3'011 found ctrl input: \i2c_I.core_I.stb found ctrl output: \i2c_I.ready found ctrl output: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:142$5205_Y found ctrl output: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:160$5209_Y found ctrl output: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:210$5214_Y found ctrl output: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:219$5217_Y ctrl inputs: { \blinker_I.rst $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:109$5196_Y \i2c_I.core_I.bit_cnt [3] \i2c_I.core_I.cyc_cnt [4] \i2c_I.core_I.stb } ctrl outputs: { \i2c_I.ready $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:219$5217_Y $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:210$5214_Y $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:160$5209_Y $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:142$5205_Y $flatten\i2c_I.\core_I.$0\state[2:0] } transition: 3'000 5'0---0 -> 3'000 8'10000000 transition: 3'000 5'0---1 -> 3'010 8'10000010 transition: 3'000 5'1---- -> 3'000 8'10000000 transition: 3'100 5'0--0- -> 3'100 8'00010100 transition: 3'100 5'00-1- -> 3'001 8'00010001 transition: 3'100 5'01-1- -> 3'000 8'00010000 transition: 3'100 5'1---- -> 3'000 8'00010000 transition: 3'010 5'0--0- -> 3'010 8'01000010 transition: 3'010 5'0--1- -> 3'011 8'01000011 transition: 3'010 5'1---- -> 3'000 8'01000000 transition: 3'001 5'0--0- -> 3'001 8'00001001 transition: 3'001 5'0-01- -> 3'010 8'00001010 transition: 3'001 5'0-11- -> 3'000 8'00001000 transition: 3'001 5'1---- -> 3'000 8'00001000 transition: 3'011 5'0--0- -> 3'011 8'00100011 transition: 3'011 5'0--1- -> 3'100 8'00100100 transition: 3'011 5'1---- -> 3'000 8'00100000 Extracting FSM `\soc_I.cpu_I.cpu_state' from module `\top'. found $dff cell for state register: $flatten\soc_I.\cpu_I.$procdff$23276 root of input selection tree: $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] found reset state: 8'10000000 (guessed from mux tree) found ctrl input: $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1917$4252_Y found ctrl input: \soc_I.pb_rst_n found state code: 8'01000000 found ctrl input: $auto$opt_reduce.cc:134:opt_mux$23626 found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12654_CMP found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12655_CMP found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12634_CMP found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12635_CMP found ctrl input: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4064_Y found ctrl input: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4211_Y found ctrl input: $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1851$4215_Y found ctrl input: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1810$4193_Y found ctrl input: \soc_I.cpu_I.alu_wait found ctrl input: \soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu found ctrl input: \soc_I.cpu_I.mem_done found ctrl input: \soc_I.cpu_I.is_sll_srl_sra found ctrl input: \soc_I.cpu_I.is_sb_sh_sw found state code: 8'00001000 found state code: 8'00000100 found state code: 8'00000010 found ctrl input: $auto$opt_reduce.cc:134:opt_mux$23564 found ctrl input: \soc_I.cpu_I.is_slli_srli_srai found ctrl input: \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu found state code: 8'00000001 found ctrl input: \soc_I.cpu_I.decoder_trigger found ctrl input: \soc_I.cpu_I.instr_jal found state code: 8'00100000 found state code: 8'10000000 found ctrl output: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4064_Y found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12624_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12634_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12635_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12646_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12654_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12655_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12659_CMP ctrl inputs: { $auto$opt_reduce.cc:134:opt_mux$23564 $auto$opt_reduce.cc:134:opt_mux$23626 \soc_I.pb_rst_n $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1917$4252_Y $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1851$4215_Y $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4211_Y $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1810$4193_Y \soc_I.cpu_I.alu_wait \soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu \soc_I.cpu_I.is_sll_srl_sra \soc_I.cpu_I.is_sb_sh_sw \soc_I.cpu_I.is_slli_srli_srai \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu \soc_I.cpu_I.decoder_trigger \soc_I.cpu_I.instr_jal \soc_I.cpu_I.mem_done } ctrl outputs: { $flatten\soc_I.\cpu_I.$procmux$12659_CMP $flatten\soc_I.\cpu_I.$procmux$12655_CMP $flatten\soc_I.\cpu_I.$procmux$12654_CMP $flatten\soc_I.\cpu_I.$procmux$12646_CMP $flatten\soc_I.\cpu_I.$procmux$12635_CMP $flatten\soc_I.\cpu_I.$procmux$12634_CMP $flatten\soc_I.\cpu_I.$procmux$12624_CMP $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4064_Y } transition: 8'10000000 16'--00------------ -> 8'01000000 16'1000000010000000 transition: 8'10000000 16'--10------------ -> 8'10000000 16'1000000100000000 transition: 8'10000000 16'---1------------ -> 8'10000000 16'1000000100000000 transition: 8'01000000 16'--00------------ -> 8'01000000 16'0000000010000001 transition: 8'01000000 16'--10---------0-- -> 8'01000000 16'0000000010000001 transition: 8'01000000 16'--10---------10- -> 8'00100000 16'0000000001000001 transition: 8'01000000 16'--10---------11- -> 8'01000000 16'0000000010000001 transition: 8'01000000 16'---1------------ -> 8'10000000 16'0000000100000001 transition: 8'00100000 16'--00------------ -> 8'01000000 16'0000100010000000 transition: 8'00100000 16'0-10-----0000--- -> 8'00001000 16'0000100000010000 transition: 8'00100000 16'0-10------100--- -> 8'00000010 16'0000100000000100 transition: 8'00100000 16'0-10-----1-00--- -> 8'00000100 16'0000100000001000 transition: 8'00100000 16'--10--------1--- -> 8'00000001 16'0000100000000010 transition: 8'00100000 16'--10-------1---- -> 8'00000100 16'0000100000001000 transition: 8'00100000 16'1-10------------ -> 8'00001000 16'0000100000010000 transition: 8'00100000 16'---1------------ -> 8'10000000 16'0000100100000000 transition: 8'00001000 16'--00------------ -> 8'01000000 16'0100000010000000 transition: 8'00001000 16'--10---00------- -> 8'01000000 16'0100000010000000 transition: 8'00001000 16'--10---01------0 -> 8'00001000 16'0100000000010000 transition: 8'00001000 16'--10---01------1 -> 8'01000000 16'0100000010000000 transition: 8'00001000 16'--10---1-------- -> 8'00001000 16'0100000000010000 transition: 8'00001000 16'---1------------ -> 8'10000000 16'0100000100000000 transition: 8'00000100 16'--00------------ -> 8'01000000 16'0010000010000000 transition: 8'00000100 16'--10--0--------- -> 8'00000100 16'0010000000001000 transition: 8'00000100 16'--10--1--------- -> 8'01000000 16'0010000010000000 transition: 8'00000100 16'---1------------ -> 8'10000000 16'0010000100000000 transition: 8'00000010 16'--00------------ -> 8'01000000 16'0001000010000000 transition: 8'00000010 16'--10-0---------- -> 8'00000010 16'0001000000000100 transition: 8'00000010 16'--1001---------- -> 8'00000010 16'0001000000000100 transition: 8'00000010 16'--1011---------- -> 8'01000000 16'0001000010000000 transition: 8'00000010 16'---1------------ -> 8'10000000 16'0001000100000000 transition: 8'00000001 16'--00------------ -> 8'01000000 16'0000001010000000 transition: 8'00000001 16'--10-0---------- -> 8'00000001 16'0000001000000010 transition: 8'00000001 16'--1001---------- -> 8'00000001 16'0000001000000010 transition: 8'00000001 16'--1011---------- -> 8'01000000 16'0000001010000000 transition: 8'00000001 16'---1------------ -> 8'10000000 16'0000001100000000 Extracting FSM `\soc_I.cpu_I.mem_wordsize' from module `\top'. found $dff cell for state register: $flatten\soc_I.\cpu_I.$procdff$23263 root of input selection tree: $flatten\soc_I.\cpu_I.$0\mem_wordsize[1:0] found ctrl input: \soc_I.pb_rst_n found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12624_CMP found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12646_CMP found ctrl input: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4064_Y found ctrl input: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4211_Y found ctrl input: \soc_I.cpu_I.mem_do_rdata found ctrl input: \soc_I.cpu_I.instr_lw found ctrl input: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1866$4220_Y found ctrl input: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1865$4219_Y found state code: 2'00 found state code: 2'01 found state code: 2'10 found ctrl input: \soc_I.cpu_I.mem_do_wdata found ctrl input: \soc_I.cpu_I.instr_sw found ctrl input: \soc_I.cpu_I.instr_sh found ctrl input: \soc_I.cpu_I.instr_sb found ctrl output: $flatten\soc_I.\cpu_I.$procmux$15200_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$15207_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$15212_CMP ctrl inputs: { \soc_I.pb_rst_n $flatten\soc_I.\cpu_I.$procmux$12646_CMP $flatten\soc_I.\cpu_I.$procmux$12624_CMP $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1866$4220_Y $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1865$4219_Y $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4211_Y $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4064_Y \soc_I.cpu_I.instr_sw \soc_I.cpu_I.instr_sh \soc_I.cpu_I.instr_sb \soc_I.cpu_I.instr_lw \soc_I.cpu_I.mem_do_wdata \soc_I.cpu_I.mem_do_rdata } ctrl outputs: { $flatten\soc_I.\cpu_I.$procmux$15212_CMP $flatten\soc_I.\cpu_I.$procmux$15207_CMP $flatten\soc_I.\cpu_I.$procmux$15200_CMP $flatten\soc_I.\cpu_I.$0\mem_wordsize[1:0] } transition: 2'00 13'0------------ -> 2'00 5'10000 transition: 2'00 13'100---0------ -> 2'00 5'10000 transition: 2'00 13'1-----1------ -> 2'00 5'10000 transition: 2'00 13'11---0------- -> 2'00 5'10000 transition: 2'00 13'11---1-000-0- -> INVALID_STATE(2'xx) 5'100xx transition: 2'00 13'11---1---1-0- -> 2'10 5'10010 transition: 2'00 13'11---1--1--0- -> 2'01 5'10001 transition: 2'00 13'11---1-1---0- -> 2'00 5'10000 transition: 2'00 13'11---1-----1- -> 2'00 5'10000 transition: 2'00 13'1-1--0------- -> 2'00 5'10000 transition: 2'00 13'1-1001----0-0 -> INVALID_STATE(2'xx) 5'100xx transition: 2'00 13'1-1-11------0 -> 2'10 5'10010 transition: 2'00 13'1-11-1------0 -> 2'01 5'10001 transition: 2'00 13'1-1--1----1-0 -> 2'00 5'10000 transition: 2'00 13'1-1--1------1 -> 2'00 5'10000 transition: 2'10 13'0------------ -> 2'10 5'00110 transition: 2'10 13'100---0------ -> 2'10 5'00110 transition: 2'10 13'1-----1------ -> 2'00 5'00100 transition: 2'10 13'11---0------- -> 2'10 5'00110 transition: 2'10 13'11---1-000-0- -> INVALID_STATE(2'xx) 5'001xx transition: 2'10 13'11---1---1-0- -> 2'10 5'00110 transition: 2'10 13'11---1--1--0- -> 2'01 5'00101 transition: 2'10 13'11---1-1---0- -> 2'00 5'00100 transition: 2'10 13'11---1-----1- -> 2'10 5'00110 transition: 2'10 13'1-1--0------- -> 2'10 5'00110 transition: 2'10 13'1-1001----0-0 -> INVALID_STATE(2'xx) 5'001xx transition: 2'10 13'1-1-11------0 -> 2'10 5'00110 transition: 2'10 13'1-11-1------0 -> 2'01 5'00101 transition: 2'10 13'1-1--1----1-0 -> 2'00 5'00100 transition: 2'10 13'1-1--1------1 -> 2'10 5'00110 transition: 2'01 13'0------------ -> 2'01 5'01001 transition: 2'01 13'100---0------ -> 2'01 5'01001 transition: 2'01 13'1-----1------ -> 2'00 5'01000 transition: 2'01 13'11---0------- -> 2'01 5'01001 transition: 2'01 13'11---1-000-0- -> INVALID_STATE(2'xx) 5'010xx transition: 2'01 13'11---1---1-0- -> 2'10 5'01010 transition: 2'01 13'11---1--1--0- -> 2'01 5'01001 transition: 2'01 13'11---1-1---0- -> 2'00 5'01000 transition: 2'01 13'11---1-----1- -> 2'01 5'01001 transition: 2'01 13'1-1--0------- -> 2'01 5'01001 transition: 2'01 13'1-1001----0-0 -> INVALID_STATE(2'xx) 5'010xx transition: 2'01 13'1-1-11------0 -> 2'10 5'01010 transition: 2'01 13'1-11-1------0 -> 2'01 5'01001 transition: 2'01 13'1-1--1----1-0 -> 2'00 5'01000 transition: 2'01 13'1-1--1------1 -> 2'01 5'01001 Extracting FSM `\soc_I.usb_I.rx_pkt_I.state' from module `\top'. found $adff cell for state register: $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23141 root of input selection tree: \soc_I.usb_I.rx_pkt_I.state_nxt found reset state: 4'0000 (from async reset) found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:375$1402_Y found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11993_CMP found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:341$1388_Y found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:337$1385_Y found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_error[0:0] found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12073_CMP found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:245$1339_Y found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_idle[0:0] found ctrl input: \soc_I.usb_I.rx_ll_I.dec_valid_1 found ctrl input: \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [2] found ctrl input: \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [3] found state code: 4'0011 found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:180$1320_Y found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:158$1314_Y found ctrl input: \soc_I.usb_I.rx_pkt_I.llu_byte_stb found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:173$1318_Y found state code: 4'0110 found state code: 4'0101 found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:153$1313_Y found ctrl input: \soc_I.usb_I.rx_pkt_I.pid_valid found ctrl input: \soc_I.usb_I.rx_pkt_I.pid_is_sof found ctrl input: \soc_I.usb_I.rx_pkt_I.pid_is_token found ctrl input: \soc_I.usb_I.rx_pkt_I.pid_is_data found ctrl input: \soc_I.usb_I.rx_pkt_I.pid_is_handshake found state code: 4'0111 found state code: 4'0100 found state code: 4'0010 found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:126$1309_Y found state code: 4'0001 found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12073_CMP found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11993_CMP found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:375$1402_Y found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:341$1388_Y found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:337$1385_Y found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:245$1339_Y found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_error[0:0] found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_idle[0:0] ctrl inputs: { \soc_I.usb_I.rx_pkt_I.llu_byte_stb \soc_I.usb_I.rx_pkt_I.pid_valid \soc_I.usb_I.rx_pkt_I.pid_is_sof \soc_I.usb_I.rx_pkt_I.pid_is_token \soc_I.usb_I.rx_pkt_I.pid_is_data \soc_I.usb_I.rx_pkt_I.pid_is_handshake $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:126$1309_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:153$1313_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:158$1314_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:173$1318_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:180$1320_Y \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [2] \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [3] \soc_I.usb_I.rx_ll_I.dec_valid_1 } ctrl outputs: { \soc_I.usb_I.rx_pkt_I.state_nxt $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_idle[0:0] $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_error[0:0] $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:245$1339_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:337$1385_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:341$1388_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:375$1402_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11993_CMP $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12073_CMP } transition: 4'0000 14'------0------- -> 4'0000 12'000010000000 transition: 4'0000 14'------1------- -> 4'0001 12'000110000000 transition: 4'0100 14'0-------0----- -> 4'0100 12'010000010000 transition: 4'0100 14'1-------0----- -> 4'0101 12'010100010000 transition: 4'0100 14'--------1----- -> 4'0011 12'001100010000 transition: 4'0010 14'-0------------ -> 4'0011 12'001100000001 transition: 4'0010 14'-10000-------- -> 4'0011 12'001100000001 transition: 4'0010 14'-10001-------- -> 4'0110 12'011000000001 transition: 4'0010 14'-1001--------- -> 4'0111 12'011100000001 transition: 4'0010 14'-101---------- -> 4'0100 12'010000000001 transition: 4'0010 14'-11----------- -> 4'0100 12'010000000001 transition: 4'0110 14'0-------0----- -> 4'0110 12'011000000010 transition: 4'0110 14'1-------0----- -> 4'0011 12'001100000010 transition: 4'0110 14'--------10---- -> 4'0011 12'001100000010 transition: 4'0110 14'--------11---- -> 4'0000 12'000000000010 transition: 4'0001 14'0------------- -> 4'0001 12'000100100000 transition: 4'0001 14'1------------- -> 4'0010 12'001000100000 transition: 4'0101 14'0-------0----- -> 4'0101 12'010100001000 transition: 4'0101 14'1-------0----- -> 4'0110 12'011000001000 transition: 4'0101 14'--------1----- -> 4'0011 12'001100001000 transition: 4'0011 14'-------0------ -> 4'0011 12'001101000000 transition: 4'0011 14'-------1------ -> 4'0000 12'000001000000 transition: 4'0111 14'-------------0 -> 4'0111 12'011100000100 transition: 4'0111 14'-----------001 -> 4'0111 12'011100000100 transition: 4'0111 14'-----------011 -> 4'0011 12'001100000100 transition: 4'0111 14'----------01-1 -> 4'0011 12'001100000100 transition: 4'0111 14'----------11-1 -> 4'0000 12'000000000100 Extracting FSM `\soc_I.usb_I.tx_pkt_I.state' from module `\top'. found $adff cell for state register: $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$23084 root of input selection tree: \soc_I.usb_I.tx_pkt_I.state_nxt found reset state: 4'0000 (from async reset) found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1553_Y found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11744_CMP found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:177$1552_Y found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1554_Y found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$0\ll_start[0:0] found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:203$1570_Y found ctrl input: \soc_I.usb_I.tx_pkt_I.next found state code: 4'0101 found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:112$1527_Y found state code: 4'0100 found ctrl input: \soc_I.usb_I.tx_pkt_I.pid_is_handshake found ctrl input: \soc_I.usb_I.tx_pkt_I.len [10] found state code: 4'0011 found state code: 4'0010 found ctrl input: \soc_I.usb_I.trans_I.txpkt_start_i found state code: 4'0001 found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11744_CMP found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:203$1570_Y found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1554_Y found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1553_Y found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:177$1552_Y found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$0\ll_start[0:0] ctrl inputs: { \soc_I.usb_I.trans_I.txpkt_start_i \soc_I.usb_I.tx_pkt_I.pid_is_handshake \soc_I.usb_I.tx_pkt_I.next \soc_I.usb_I.tx_pkt_I.len [10] $flatten\soc_I.\usb_I.\tx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:112$1527_Y } ctrl outputs: { \soc_I.usb_I.tx_pkt_I.state_nxt $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:177$1552_Y $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1553_Y $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1554_Y $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:203$1570_Y $flatten\soc_I.\usb_I.\tx_pkt_I.$0\ll_start[0:0] $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11744_CMP } transition: 4'0000 5'0---- -> 4'0000 10'0000000100 transition: 4'0000 5'1---- -> 4'0001 10'0001000100 transition: 4'0100 5'--0-- -> 4'0100 10'0100000001 transition: 4'0100 5'--1-- -> 4'0101 10'0101000001 transition: 4'0010 5'--0-- -> 4'0010 10'0010001000 transition: 4'0010 5'-010- -> 4'0011 10'0011001000 transition: 4'0010 5'-011- -> 4'0100 10'0100001000 transition: 4'0010 5'-11-- -> 4'0000 10'0000001000 transition: 4'0001 5'----- -> 4'0010 10'0010000010 transition: 4'0101 5'--0-- -> 4'0101 10'0101010000 transition: 4'0101 5'--1-- -> 4'0000 10'0000010000 transition: 4'0011 5'----0 -> 4'0011 10'0011100000 transition: 4'0011 5'----1 -> 4'0100 10'0100100000 75.11.3. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\soc_I.usb_I.tx_pkt_I.state$23674' from module `\top'. Optimizing FSM `$fsm$\soc_I.usb_I.rx_pkt_I.state$23664' from module `\top'. Optimizing FSM `$fsm$\soc_I.cpu_I.mem_wordsize$23659' from module `\top'. Optimizing FSM `$fsm$\soc_I.cpu_I.cpu_state$23649' from module `\top'. Removing unused input signal $auto$opt_reduce.cc:134:opt_mux$23626. Optimizing FSM `$fsm$\i2c_I.core_I.state$23642' from module `\top'. Optimizing FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.fsm_state$23633' from module `\top'. Merging pattern 9'-----0--0 and 9'-----0--1 from group (1 1 10'0010010100). Merging pattern 9'-----0--1 and 9'-----0--0 from group (1 1 10'0010010100). 75.11.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 115 unused cells and 115 unused wires. 75.11.5. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.fsm_state$23633' from module `\top'. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procmux$15934_CMP. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procmux$15920_CMP. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] [0]. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] [1]. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] [2]. Optimizing FSM `$fsm$\i2c_I.core_I.state$23642' from module `\top'. Removing unused output signal $flatten\i2c_I.\core_I.$0\state[2:0] [0]. Removing unused output signal $flatten\i2c_I.\core_I.$0\state[2:0] [1]. Removing unused output signal $flatten\i2c_I.\core_I.$0\state[2:0] [2]. Optimizing FSM `$fsm$\soc_I.cpu_I.cpu_state$23649' from module `\top'. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [0]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [1]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [2]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [3]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [4]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [5]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [6]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [7]. Optimizing FSM `$fsm$\soc_I.cpu_I.mem_wordsize$23659' from module `\top'. Removing unused output signal $flatten\soc_I.\cpu_I.$0\mem_wordsize[1:0] [0]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\mem_wordsize[1:0] [1]. Optimizing FSM `$fsm$\soc_I.usb_I.rx_pkt_I.state$23664' from module `\top'. Removing unused output signal $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12073_CMP. Removing unused output signal $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11993_CMP. Removing unused output signal \soc_I.usb_I.rx_pkt_I.state_nxt [0]. Removing unused output signal \soc_I.usb_I.rx_pkt_I.state_nxt [1]. Removing unused output signal \soc_I.usb_I.rx_pkt_I.state_nxt [2]. Removing unused output signal \soc_I.usb_I.rx_pkt_I.state_nxt [3]. Optimizing FSM `$fsm$\soc_I.usb_I.tx_pkt_I.state$23674' from module `\top'. Removing unused output signal \soc_I.usb_I.tx_pkt_I.state_nxt [0]. Removing unused output signal \soc_I.usb_I.tx_pkt_I.state_nxt [1]. Removing unused output signal \soc_I.usb_I.tx_pkt_I.state_nxt [2]. Removing unused output signal \soc_I.usb_I.tx_pkt_I.state_nxt [3]. 75.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). Recoding FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.fsm_state$23633' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 000 -> ----1 100 -> ---1- 010 -> --1-- 001 -> -1--- 011 -> 1---- Recoding FSM `$fsm$\i2c_I.core_I.state$23642' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 000 -> ----1 100 -> ---1- 010 -> --1-- 001 -> -1--- 011 -> 1---- Recoding FSM `$fsm$\soc_I.cpu_I.cpu_state$23649' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 10000000 -> ------1 01000000 -> -----1- 00100000 -> ----1-- 00001000 -> ---1--- 00000100 -> --1---- 00000010 -> -1----- 00000001 -> 1------ Recoding FSM `$fsm$\soc_I.cpu_I.mem_wordsize$23659' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 00 -> --1 10 -> -1- 01 -> 1-- Recoding FSM `$fsm$\soc_I.usb_I.rx_pkt_I.state$23664' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 0000 -> -------1 0100 -> ------1- 0010 -> -----1-- 0110 -> ----1--- 0001 -> ---1---- 0101 -> --1----- 0011 -> -1------ 0111 -> 1------- Recoding FSM `$fsm$\soc_I.usb_I.tx_pkt_I.state$23674' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 0000 -> -----1 0100 -> ----1- 0010 -> ---1-- 0001 -> --1--- 0101 -> -1---- 0011 -> 1----- 75.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells). FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.fsm_state$23633' from module `top': ------------------------------------- Information on FSM $fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.fsm_state$23633 ($flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.fsm_state): Number of input signals: 9 Number of output signals: 5 Number of state bits: 5 Input signals: 0: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.crc_I.in_valid 1: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:186$32_Y 2: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:163$27_Y 3: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$or$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:140$25_Y 4: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf 5: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.mfa_timeout [6] 6: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.fas_pos 7: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.data_match_fas 8: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.data [6] Output signals: 0: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:378$137_Y 1: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:312$71_Y 2: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:312$70_Y 3: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.align_mframe 4: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.align_frame State encoding: 0: 5'----1 1: 5'---1- 2: 5'--1-- 3: 5'-1--- 4: 5'1---- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 9'-----0--0 -> 0 5'10110 1: 0 9'-0---0--1 -> 0 5'10110 2: 0 9'-----1--- -> 0 5'10110 3: 0 9'-1---0--1 -> 3 5'10110 4: 1 9'-----1--- -> 0 5'00101 5: 1 9'-----0--- -> 1 5'00101 6: 2 9'---1-01-1 -> 0 5'01010 7: 2 9'-----1--- -> 0 5'01010 8: 2 9'-----0--0 -> 2 5'01010 9: 2 9'-----00-1 -> 2 5'01010 10: 2 9'---0001-1 -> 2 5'01010 11: 2 9'---0101-1 -> 4 5'01010 12: 3 9'0-0--01-1 -> 0 5'00110 13: 3 9'-01--01-1 -> 0 5'00110 14: 3 9'-----1--- -> 0 5'00110 15: 3 9'-11--01-1 -> 2 5'00110 16: 3 9'-----0--0 -> 3 5'00110 17: 3 9'-----00-1 -> 3 5'00110 18: 3 9'1-0--01-1 -> 3 5'00110 19: 4 9'---1-01-1 -> 0 5'00110 20: 4 9'-----1--- -> 0 5'00110 21: 4 9'---0-0111 -> 1 5'00110 22: 4 9'-----0--0 -> 4 5'00110 23: 4 9'---0-0101 -> 4 5'00110 24: 4 9'-----00-1 -> 4 5'00110 ------------------------------------- FSM `$fsm$\i2c_I.core_I.state$23642' from module `top': ------------------------------------- Information on FSM $fsm$\i2c_I.core_I.state$23642 (\i2c_I.core_I.state): Number of input signals: 5 Number of output signals: 5 Number of state bits: 5 Input signals: 0: \i2c_I.core_I.stb 1: \i2c_I.core_I.cyc_cnt [4] 2: \i2c_I.core_I.bit_cnt [3] 3: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:109$5196_Y 4: \blinker_I.rst Output signals: 0: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:142$5205_Y 1: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:160$5209_Y 2: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:210$5214_Y 3: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:219$5217_Y 4: \i2c_I.ready State encoding: 0: 5'----1 1: 5'---1- 2: 5'--1-- 3: 5'-1--- 4: 5'1---- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 5'0---0 -> 0 5'10000 1: 0 5'1---- -> 0 5'10000 2: 0 5'0---1 -> 2 5'10000 3: 1 5'01-1- -> 0 5'00010 4: 1 5'1---- -> 0 5'00010 5: 1 5'0--0- -> 1 5'00010 6: 1 5'00-1- -> 3 5'00010 7: 2 5'1---- -> 0 5'01000 8: 2 5'0--0- -> 2 5'01000 9: 2 5'0--1- -> 4 5'01000 10: 3 5'0-11- -> 0 5'00001 11: 3 5'1---- -> 0 5'00001 12: 3 5'0-01- -> 2 5'00001 13: 3 5'0--0- -> 3 5'00001 14: 4 5'1---- -> 0 5'00100 15: 4 5'0--1- -> 1 5'00100 16: 4 5'0--0- -> 4 5'00100 ------------------------------------- FSM `$fsm$\soc_I.cpu_I.cpu_state$23649' from module `top': ------------------------------------- Information on FSM $fsm$\soc_I.cpu_I.cpu_state$23649 (\soc_I.cpu_I.cpu_state): Number of input signals: 15 Number of output signals: 8 Number of state bits: 7 Input signals: 0: \soc_I.cpu_I.mem_done 1: \soc_I.cpu_I.instr_jal 2: \soc_I.cpu_I.decoder_trigger 3: \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu 4: \soc_I.cpu_I.is_slli_srli_srai 5: \soc_I.cpu_I.is_sb_sh_sw 6: \soc_I.cpu_I.is_sll_srl_sra 7: \soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu 8: \soc_I.cpu_I.alu_wait 9: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1810$4193_Y 10: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4211_Y 11: $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1851$4215_Y 12: $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1917$4252_Y 13: \soc_I.pb_rst_n 14: $auto$opt_reduce.cc:134:opt_mux$23564 Output signals: 0: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4064_Y 1: $flatten\soc_I.\cpu_I.$procmux$12624_CMP 2: $flatten\soc_I.\cpu_I.$procmux$12634_CMP 3: $flatten\soc_I.\cpu_I.$procmux$12635_CMP 4: $flatten\soc_I.\cpu_I.$procmux$12646_CMP 5: $flatten\soc_I.\cpu_I.$procmux$12654_CMP 6: $flatten\soc_I.\cpu_I.$procmux$12655_CMP 7: $flatten\soc_I.\cpu_I.$procmux$12659_CMP State encoding: 0: 7'------1 1: 7'-----1- 2: 7'----1-- 3: 7'---1--- 4: 7'--1---- 5: 7'-1----- 6: 7'1------ Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 15'-10------------ -> 0 8'10000000 1: 0 15'--1------------ -> 0 8'10000000 2: 0 15'-00------------ -> 1 8'10000000 3: 1 15'--1------------ -> 0 8'00000001 4: 1 15'-10---------11- -> 1 8'00000001 5: 1 15'-10---------0-- -> 1 8'00000001 6: 1 15'-00------------ -> 1 8'00000001 7: 1 15'-10---------10- -> 2 8'00000001 8: 2 15'--1------------ -> 0 8'00001000 9: 2 15'-00------------ -> 1 8'00001000 10: 2 15'010-----0000--- -> 3 8'00001000 11: 2 15'110------------ -> 3 8'00001000 12: 2 15'010-----1-00--- -> 4 8'00001000 13: 2 15'-10-------1---- -> 4 8'00001000 14: 2 15'010------100--- -> 5 8'00001000 15: 2 15'-10--------1--- -> 6 8'00001000 16: 3 15'--1------------ -> 0 8'01000000 17: 3 15'-10---01------1 -> 1 8'01000000 18: 3 15'-10---00------- -> 1 8'01000000 19: 3 15'-00------------ -> 1 8'01000000 20: 3 15'-10---01------0 -> 3 8'01000000 21: 3 15'-10---1-------- -> 3 8'01000000 22: 4 15'--1------------ -> 0 8'00100000 23: 4 15'-10--1--------- -> 1 8'00100000 24: 4 15'-00------------ -> 1 8'00100000 25: 4 15'-10--0--------- -> 4 8'00100000 26: 5 15'--1------------ -> 0 8'00010000 27: 5 15'-1011---------- -> 1 8'00010000 28: 5 15'-00------------ -> 1 8'00010000 29: 5 15'-10-0---------- -> 5 8'00010000 30: 5 15'-1001---------- -> 5 8'00010000 31: 6 15'--1------------ -> 0 8'00000010 32: 6 15'-1011---------- -> 1 8'00000010 33: 6 15'-00------------ -> 1 8'00000010 34: 6 15'-10-0---------- -> 6 8'00000010 35: 6 15'-1001---------- -> 6 8'00000010 ------------------------------------- FSM `$fsm$\soc_I.cpu_I.mem_wordsize$23659' from module `top': ------------------------------------- Information on FSM $fsm$\soc_I.cpu_I.mem_wordsize$23659 (\soc_I.cpu_I.mem_wordsize): Number of input signals: 13 Number of output signals: 3 Number of state bits: 3 Input signals: 0: \soc_I.cpu_I.mem_do_rdata 1: \soc_I.cpu_I.mem_do_wdata 2: \soc_I.cpu_I.instr_lw 3: \soc_I.cpu_I.instr_sb 4: \soc_I.cpu_I.instr_sh 5: \soc_I.cpu_I.instr_sw 6: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4064_Y 7: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4211_Y 8: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1865$4219_Y 9: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1866$4220_Y 10: $flatten\soc_I.\cpu_I.$procmux$12624_CMP 11: $flatten\soc_I.\cpu_I.$procmux$12646_CMP 12: \soc_I.pb_rst_n Output signals: 0: $flatten\soc_I.\cpu_I.$procmux$15200_CMP 1: $flatten\soc_I.\cpu_I.$procmux$15207_CMP 2: $flatten\soc_I.\cpu_I.$procmux$15212_CMP State encoding: 0: 3'--1 1: 3'-1- 2: 3'1-- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 13'1-1--1----1-0 -> 0 3'100 1: 0 13'1-1--1------1 -> 0 3'100 2: 0 13'11---1-1---0- -> 0 3'100 3: 0 13'11---1-----1- -> 0 3'100 4: 0 13'100---0------ -> 0 3'100 5: 0 13'1-----1------ -> 0 3'100 6: 0 13'1-1--0------- -> 0 3'100 7: 0 13'11---0------- -> 0 3'100 8: 0 13'0------------ -> 0 3'100 9: 0 13'1-1-11------0 -> 1 3'100 10: 0 13'11---1---1-0- -> 1 3'100 11: 0 13'1-11-1------0 -> 2 3'100 12: 0 13'11---1--1--0- -> 2 3'100 13: 1 13'1-1--1----1-0 -> 0 3'001 14: 1 13'11---1-1---0- -> 0 3'001 15: 1 13'1-----1------ -> 0 3'001 16: 1 13'1-1-11------0 -> 1 3'001 17: 1 13'1-1--1------1 -> 1 3'001 18: 1 13'11---1---1-0- -> 1 3'001 19: 1 13'11---1-----1- -> 1 3'001 20: 1 13'100---0------ -> 1 3'001 21: 1 13'1-1--0------- -> 1 3'001 22: 1 13'11---0------- -> 1 3'001 23: 1 13'0------------ -> 1 3'001 24: 1 13'1-11-1------0 -> 2 3'001 25: 1 13'11---1--1--0- -> 2 3'001 26: 2 13'1-1--1----1-0 -> 0 3'010 27: 2 13'11---1-1---0- -> 0 3'010 28: 2 13'1-----1------ -> 0 3'010 29: 2 13'1-1-11------0 -> 1 3'010 30: 2 13'11---1---1-0- -> 1 3'010 31: 2 13'1-11-1------0 -> 2 3'010 32: 2 13'1-1--1------1 -> 2 3'010 33: 2 13'11---1--1--0- -> 2 3'010 34: 2 13'11---1-----1- -> 2 3'010 35: 2 13'100---0------ -> 2 3'010 36: 2 13'1-1--0------- -> 2 3'010 37: 2 13'11---0------- -> 2 3'010 38: 2 13'0------------ -> 2 3'010 ------------------------------------- FSM `$fsm$\soc_I.usb_I.rx_pkt_I.state$23664' from module `top': ------------------------------------- Information on FSM $fsm$\soc_I.usb_I.rx_pkt_I.state$23664 (\soc_I.usb_I.rx_pkt_I.state): Number of input signals: 14 Number of output signals: 6 Number of state bits: 8 Input signals: 0: \soc_I.usb_I.rx_ll_I.dec_valid_1 1: \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [3] 2: \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [2] 3: $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:180$1320_Y 4: $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:173$1318_Y 5: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:158$1314_Y 6: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:153$1313_Y 7: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:126$1309_Y 8: \soc_I.usb_I.rx_pkt_I.pid_is_handshake 9: \soc_I.usb_I.rx_pkt_I.pid_is_data 10: \soc_I.usb_I.rx_pkt_I.pid_is_token 11: \soc_I.usb_I.rx_pkt_I.pid_is_sof 12: \soc_I.usb_I.rx_pkt_I.pid_valid 13: \soc_I.usb_I.rx_pkt_I.llu_byte_stb Output signals: 0: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:375$1402_Y 1: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:341$1388_Y 2: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:337$1385_Y 3: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:245$1339_Y 4: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_error[0:0] 5: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_idle[0:0] State encoding: 0: 8'-------1 1: 8'------1- 2: 8'-----1-- 3: 8'----1--- 4: 8'---1---- 5: 8'--1----- 6: 8'-1------ 7: 8'1------- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 14'------0------- -> 0 6'100000 1: 0 14'------1------- -> 4 6'100000 2: 1 14'0-------0----- -> 1 6'000100 3: 1 14'1-------0----- -> 5 6'000100 4: 1 14'--------1----- -> 6 6'000100 5: 2 14'-101---------- -> 1 6'000000 6: 2 14'-11----------- -> 1 6'000000 7: 2 14'-10001-------- -> 3 6'000000 8: 2 14'-10000-------- -> 6 6'000000 9: 2 14'-0------------ -> 6 6'000000 10: 2 14'-1001--------- -> 7 6'000000 11: 3 14'--------11---- -> 0 6'000000 12: 3 14'0-------0----- -> 3 6'000000 13: 3 14'--------10---- -> 6 6'000000 14: 3 14'1-------0----- -> 6 6'000000 15: 4 14'1------------- -> 2 6'001000 16: 4 14'0------------- -> 4 6'001000 17: 5 14'1-------0----- -> 3 6'000010 18: 5 14'0-------0----- -> 5 6'000010 19: 5 14'--------1----- -> 6 6'000010 20: 6 14'-------1------ -> 0 6'010000 21: 6 14'-------0------ -> 6 6'010000 22: 7 14'----------11-1 -> 0 6'000001 23: 7 14'-----------011 -> 6 6'000001 24: 7 14'----------01-1 -> 6 6'000001 25: 7 14'-------------0 -> 7 6'000001 26: 7 14'-----------001 -> 7 6'000001 ------------------------------------- FSM `$fsm$\soc_I.usb_I.tx_pkt_I.state$23674' from module `top': ------------------------------------- Information on FSM $fsm$\soc_I.usb_I.tx_pkt_I.state$23674 (\soc_I.usb_I.tx_pkt_I.state): Number of input signals: 5 Number of output signals: 6 Number of state bits: 6 Input signals: 0: $flatten\soc_I.\usb_I.\tx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:112$1527_Y 1: \soc_I.usb_I.tx_pkt_I.len [10] 2: \soc_I.usb_I.tx_pkt_I.next 3: \soc_I.usb_I.tx_pkt_I.pid_is_handshake 4: \soc_I.usb_I.trans_I.txpkt_start_i Output signals: 0: $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11744_CMP 1: $flatten\soc_I.\usb_I.\tx_pkt_I.$0\ll_start[0:0] 2: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:203$1570_Y 3: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1554_Y 4: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1553_Y 5: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:177$1552_Y State encoding: 0: 6'-----1 1: 6'----1- 2: 6'---1-- 3: 6'--1--- 4: 6'-1---- 5: 6'1----- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 5'0---- -> 0 6'000100 1: 0 5'1---- -> 3 6'000100 2: 1 5'--0-- -> 1 6'000001 3: 1 5'--1-- -> 4 6'000001 4: 2 5'-11-- -> 0 6'001000 5: 2 5'-011- -> 1 6'001000 6: 2 5'--0-- -> 2 6'001000 7: 2 5'-010- -> 5 6'001000 8: 3 5'----- -> 2 6'000010 9: 4 5'--1-- -> 0 6'010000 10: 4 5'--0-- -> 4 6'010000 11: 5 5'----1 -> 1 6'100000 12: 5 5'----0 -> 5 6'100000 ------------------------------------- 75.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic). Mapping FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.fsm_state$23633' from module `\top'. Mapping FSM `$fsm$\i2c_I.core_I.state$23642' from module `\top'. Mapping FSM `$fsm$\soc_I.cpu_I.cpu_state$23649' from module `\top'. Mapping FSM `$fsm$\soc_I.cpu_I.mem_wordsize$23659' from module `\top'. Mapping FSM `$fsm$\soc_I.usb_I.rx_pkt_I.state$23664' from module `\top'. Mapping FSM `$fsm$\soc_I.usb_I.tx_pkt_I.state$23674' from module `\top'. 75.12. Executing OPT pass (performing simple optimizations). 75.12.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.12.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 31 cells. 75.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 1/3 on $pmux $flatten\soc_I.\cpu_I.$procmux$13139. dead port 2/4 on $pmux $flatten\soc_I.\cpu_I.$procmux$13239. dead port 3/6 on $pmux $flatten\soc_I.\cpu_I.$procmux$13703. dead port 1/3 on $pmux $flatten\soc_I.\cpu_I.$procmux$13888. Removed 4 multiplexer ports. 75.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$23583: { \soc_I.cpu_I.cpu_state [6:4] \soc_I.cpu_I.cpu_state [2:0] } New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$23581: \soc_I.cpu_I.cpu_state [5:0] New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$23579: { \soc_I.cpu_I.cpu_state [6] \soc_I.cpu_I.cpu_state [4:0] } Optimizing cells in module \top. Performed a total of 3 changes. 75.12.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.12.6. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $flatten\sys_mgr_I.$procdff$23048 ($adff) from module top (D = $flatten\sys_mgr_I.$add$/build/gateware/icE1usb/rtl/sysmgr.v:80$1711_Y [2:0], Q = \sys_mgr_I.rst_cnt [2:0]). Adding SRST signal on $flatten\spi_mux_I.$procdff$23481 ($dff) from module top (D = \spi_mux_I.state_nxt, Q = \spi_mux_I.state, rval = 3'000). Adding EN signal on $flatten\spi_mux_I.$procdff$23472 ($dff) from module top (D = \spi_mux_I.shift_data_nxt, Q = \spi_mux_I.shift_data). Adding SRST signal on $flatten\spi_mux_I.$procdff$23469 ($dff) from module top (D = \spi_mux_I.shift_data [7], Q = \spi_mux_I.srio_dat_o, rval = 1'0). Adding EN signal on $flatten\soc_I.\wb_48m_xclk_I.$procdff$23448 ($dff) from module top (D = \soc_I.wb_48m_xclk_I.m_rdata, Q = \soc_I.wb_48m_xclk_I.m_rdata_i). Adding SRST signal on $flatten\soc_I.\wb_48m_xclk_I.$procdff$23447 ($dff) from module top (D = \soc_I.wb_48m_xclk_I.m_rdata_i, Q = \soc_I.wb_48m_xclk_I.s_rdata, rval = 16'0000000000000000). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.\crc_16_I.$procdff$23016 ($dff) from module top (D = \soc_I.usb_I.tx_pkt_I.crc_16_I.state_nxt, Q = \soc_I.usb_I.tx_pkt_I.crc_16_I.state). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$23082 ($dff) from module top (D = $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1543_Y [3:0], Q = \soc_I.usb_I.tx_pkt_I.shift_bit). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$23081 ($dff) from module top (D = $flatten\soc_I.\usb_I.\tx_pkt_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:172$1549_Y, Q = \soc_I.usb_I.tx_pkt_I.shift_data). Adding SRST signal on $auto$opt_dff.cc:764:run$24207 ($dffe) from module top (D = \soc_I.usb_I.tx_pkt_I.shift_load [7], Q = \soc_I.usb_I.tx_pkt_I.shift_data [7], rval = 1'0). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$23080 ($dff) from module top (D = $flatten\soc_I.\usb_I.\tx_pkt_I.$or$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1556_Y, Q = \soc_I.usb_I.tx_pkt_I.shift_last_byte). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$23079 ($dff) from module top (D = \soc_I.usb_I.tx_pkt_I.state [5], Q = \soc_I.usb_I.tx_pkt_I.shift_data_crc). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$23077 ($dff) from module top (D = $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1566_Y [10:0], Q = \soc_I.usb_I.tx_pkt_I.len). Adding EN signal on $flatten\soc_I.\usb_I.\tx_ll_I.$procdff$23092 ($adff) from module top (D = $flatten\soc_I.\usb_I.\tx_ll_I.$0\state[2:0], Q = \soc_I.usb_I.tx_ll_I.state). Adding EN signal on $flatten\soc_I.\usb_I.\tx_ll_I.$procdff$23090 ($adff) from module top (D = $flatten\soc_I.\usb_I.\tx_ll_I.$and$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:95$1508_Y, Q = \soc_I.usb_I.tx_ll_I.bs_now). Adding EN signal on $flatten\soc_I.\usb_I.\tx_ll_I.$procdff$23089 ($adff) from module top (D = $flatten\soc_I.\usb_I.\tx_ll_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1506_Y [2:0], Q = \soc_I.usb_I.tx_ll_I.bs_cnt). Adding SRST signal on $flatten\soc_I.\usb_I.\tx_ll_I.$procdff$23088 ($dff) from module top (D = $flatten\soc_I.\usb_I.\tx_ll_I.$xor$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:103$1514_Y, Q = \soc_I.usb_I.tx_ll_I.lvl_prev, rval = 1'1). Adding EN signal on $flatten\soc_I.\usb_I.\tx_ll_I.$procdff$23086 ($adff) from module top (D = $flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11826_Y, Q = \soc_I.usb_I.tx_ll_I.out_sym). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23116 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$procmux$11907_Y, Q = \soc_I.usb_I.trans_I.mc_a_reg). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23113 ($dff) from module top (D = \soc_I.usb_I.trans_I.cel_state_i, Q = \soc_I.usb_I.trans_I.trans_cel). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23112 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:286$1440_Y, Q = \soc_I.usb_I.trans_I.trans_dir). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23111 ($dff) from module top (D = \soc_I.usb_I.rx_pkt_I.token_data [10:7], Q = \soc_I.usb_I.trans_I.trans_endp). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23110 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:284$1439_Y, Q = \soc_I.usb_I.trans_I.trans_is_setup). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23107 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$0\bd_state[2:0], Q = \soc_I.usb_I.trans_I.bd_state). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23104 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_trans.v:363$1451_Y, Q = \soc_I.usb_I.trans_I.ep_bd_idx_cur). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23103 ($dff) from module top (D = \soc_I.usb_I.ep_status_I.p_dout_3 [5], Q = \soc_I.usb_I.trans_I.ep_bd_ctrl). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23102 ($dff) from module top (D = \soc_I.usb_I.ep_status_I.p_dout_3 [4], Q = \soc_I.usb_I.trans_I.ep_bd_dual). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23101 ($dff) from module top (D = \soc_I.usb_I.ep_status_I.p_dout_3 [2:0], Q = \soc_I.usb_I.trans_I.ep_type). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23098 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$xor$/build/gateware/cores/no2usb//rtl/usb_trans.v:401$1472_Y, Q = \soc_I.usb_I.trans_I.txpkt_pid). Adding SRST signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23095 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_trans.v:425$1482_Y, Q = \soc_I.usb_I.trans_I.bd_length, rval = 11'00000000000). Adding SRST signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23094 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:429$1484_Y, Q = \soc_I.usb_I.trans_I.xfer_length, rval = 10'0000000000). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23093 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$procmux$11851_Y, Q = \soc_I.usb_I.trans_I.pkt_pid). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.\crc_5_I.$procdff$23015 ($dff) from module top (D = \soc_I.usb_I.rx_pkt_I.crc_5_I.state_nxt, Q = \soc_I.usb_I.rx_pkt_I.crc_5_I.state). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.\crc_16_I.$procdff$23016 ($dff) from module top (D = \soc_I.usb_I.rx_pkt_I.crc_16_I.state_nxt, Q = \soc_I.usb_I.rx_pkt_I.crc_16_I.state). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23138 ($dff) from module top (D = { \soc_I.usb_I.rx_ll_I.dec_bit_1 \soc_I.usb_I.rx_pkt_I.data [7:1] }, Q = \soc_I.usb_I.rx_pkt_I.data). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23137 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11950_Y, Q = \soc_I.usb_I.rx_pkt_I.bit_cnt, rval = 4'0110). Adding EN signal on $auto$opt_dff.cc:702:run$24242 ($sdff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1334_Y [3:0], Q = \soc_I.usb_I.rx_pkt_I.bit_cnt). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23136 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11945_Y, Q = \soc_I.usb_I.rx_pkt_I.bit_eop_ok, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24244 ($sdff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:234$1337_Y, Q = \soc_I.usb_I.rx_pkt_I.bit_eop_ok). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23135 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11940_Y, Q = \soc_I.usb_I.rx_pkt_I.crc_in_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24246 ($sdff) from module top (D = 1'0, Q = \soc_I.usb_I.rx_pkt_I.crc_in_first). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23133 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11930_Y, Q = \soc_I.usb_I.rx_pkt_I.crc16_ok, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24248 ($sdff) from module top (D = \soc_I.usb_I.rx_pkt_I.crc16_match, Q = \soc_I.usb_I.rx_pkt_I.crc16_ok). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23132 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11935_Y, Q = \soc_I.usb_I.rx_pkt_I.crc5_ok, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24250 ($sdff) from module top (D = \soc_I.usb_I.rx_pkt_I.crc5_match, Q = \soc_I.usb_I.rx_pkt_I.crc5_ok). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23131 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:306$1365_Y, Q = \soc_I.usb_I.rx_pkt_I.pid_valid). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23129 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_or$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:329$1383_Y, Q = \soc_I.usb_I.rx_pkt_I.pid_is_handshake). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23128 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_or$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:328$1378_Y, Q = \soc_I.usb_I.rx_pkt_I.pid_is_data). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23127 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_or$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:327$1375_Y, Q = \soc_I.usb_I.rx_pkt_I.pid_is_token). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23126 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:307$1348_Y, Q = \soc_I.usb_I.rx_pkt_I.pid_is_sof). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23125 ($dff) from module top (D = \soc_I.usb_I.rx_pkt_I.data [4:1], Q = \soc_I.usb_I.rx_pkt_I.pid). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23124 ($dff) from module top (D = { \soc_I.usb_I.rx_ll_I.dec_bit_1 \soc_I.usb_I.rx_pkt_I.data [7:1] }, Q = \soc_I.usb_I.rx_pkt_I.token_data [7:0]). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23123 ($dff) from module top (D = \soc_I.usb_I.rx_pkt_I.data [3:1], Q = \soc_I.usb_I.rx_pkt_I.token_data [10:8]). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$23150 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12216_Y, Q = \soc_I.usb_I.rx_ll_I.samp_cnt, rval = 3'101). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$23148 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:115$1297_Y, Q = \soc_I.usb_I.rx_ll_I.dec_bit_1). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$23147 ($dff) from module top (D = { \soc_I.usb_I.phy_I.dp_state [1] \soc_I.usb_I.phy_I.dn_state [1] }, Q = \soc_I.usb_I.rx_ll_I.dec_sym_1). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$23145 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12205_Y, Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$23144 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12200_Y, Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1). Adding SRST signal on $auto$opt_dff.cc:764:run$24264 ($dffe) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12190_Y, Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1, rval = 4'0000). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$23143 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12183_Y, Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1). Adding SRST signal on $auto$opt_dff.cc:764:run$24266 ($dffe) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12173_Y, Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1, rval = 4'0000). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$23142 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:183$1304_Y, Q = \soc_I.usb_I.rx_ll_I.dec_bs_skip_1). Adding EN signal on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$23161 ($dff) from module top (D = \soc_I.usb_I.ep_status_I.dout_2, Q = \soc_I.usb_I.ep_status_I.p_dout_3). Adding EN signal on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$23160 ($dff) from module top (D = $flatten\soc_I.\usb_I.\ep_status_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:82$1270_Y, Q = \soc_I.usb_I.ep_status_I.s_dout_3). Adding SRST signal on $auto$opt_dff.cc:764:run$24270 ($dffe) from module top (D = \soc_I.usb_I.ep_status_I.dout_2, Q = \soc_I.usb_I.ep_status_I.s_dout_3, rval = 16'0000000000000000). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23443 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:413$3427_Y, Q = \soc_I.usb_I.sof_clear, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23442 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:412$3424_Y, Q = \soc_I.usb_I.rst_clear, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23441 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:414$3430_Y, Q = \soc_I.usb_I.evt_rd_ack, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23439 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:410$3418_Y, Q = \soc_I.usb_I.cr_bus_we, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23437 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:411$3421_Y, Q = \soc_I.usb_I.cel_rel, rval = 1'0). Adding EN signal on $flatten\soc_I.\usb_I.$procdff$23436 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [6:0], Q = \soc_I.usb_I.cr_addr). Adding EN signal on $flatten\soc_I.\usb_I.$procdff$23435 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [7], Q = \soc_I.usb_I.cr_addr_chk). Adding EN signal on $flatten\soc_I.\usb_I.$procdff$23434 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [12], Q = \soc_I.usb_I.cr_cel_ena). Adding EN signal on $flatten\soc_I.\usb_I.$procdff$23433 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [15], Q = \soc_I.usb_I.cr_pu_ena). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23432 ($dff) from module top (D = \soc_I.cpu_I.mem_addr [13], Q = \soc_I.usb_I.eps_bus_req, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23431 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:498$3443_Y, Q = \soc_I.usb_I.eps_bus_write, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23430 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:497$3442_Y, Q = \soc_I.usb_I.eps_bus_read, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23427 ($dff) from module top (D = $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:623$3469_Y, Q = \soc_I.usb_I.timeout_suspend, rval = 20'11011100110110000000). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23426 ($dff) from module top (D = $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:632$3473_Y, Q = \soc_I.usb_I.timeout_reset, rval = 20'10001010110100000000). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23424 ($dff) from module top (D = \soc_I.usb_I.cr_pu_ena, Q = \soc_I.usb_I.pad_pu, rval = 1'0). Adding EN signal on $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$procdff$23019 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5456_DATA, Q = \soc_I.uart_I.uart_tx_fifo_I.ram_I.rd_data). Adding EN signal on $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$procdff$23228 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4332_Y [8:0], Q = \soc_I.uart_I.uart_tx_fifo_I.ram_wr_addr). Adding EN signal on $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$procdff$23227 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4334_Y [8:0], Q = \soc_I.uart_I.uart_tx_fifo_I.ram_rd_addr). Adding EN signal on $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$procdff$23226 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$not$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:114$4337_Y, Q = \soc_I.uart_I.uart_tx_fifo_I.rd_valid). Adding SRST signal on $flatten\soc_I.\uart_I.\uart_tx_I.$procdff$23224 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5253_Y [12], Q = \soc_I.uart_I.uart_tx_I.div_cnt [12], rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.\uart_tx_I.$procdff$23223 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_I.$procmux$12443_Y, Q = \soc_I.uart_I.uart_tx_I.bit_cnt, rval = 5'01000). Adding EN signal on $auto$opt_dff.cc:702:run$24292 ($sdff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5256_Y [4:0], Q = \soc_I.uart_I.uart_tx_I.bit_cnt). Adding EN signal on $flatten\soc_I.\uart_I.\uart_tx_I.$procdff$23222 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_I.$0\shift[9:0], Q = \soc_I.uart_I.uart_tx_I.shift). Adding EN signal on $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$procdff$23019 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5456_DATA, Q = \soc_I.uart_I.uart_rx_fifo_I.ram_I.rd_data). Adding EN signal on $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$procdff$23228 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4332_Y [8:0], Q = \soc_I.uart_I.uart_rx_fifo_I.ram_wr_addr). Adding EN signal on $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$procdff$23227 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4334_Y [8:0], Q = \soc_I.uart_I.uart_rx_fifo_I.ram_rd_addr). Adding EN signal on $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$procdff$23226 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$not$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:114$4337_Y, Q = \soc_I.uart_I.uart_rx_fifo_I.rd_valid). Adding SRST signal on $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procdff$23191 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4387_Y, Q = \soc_I.uart_I.uart_rx_I.gf_I.cnt, rval = 2'11). Adding SRST signal on $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procdff$23190 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procmux$12277_Y, Q = \soc_I.uart_I.uart_rx_I.gf_I.state, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24302 ($sdff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procmux$12277_Y, Q = \soc_I.uart_I.uart_rx_I.gf_I.state). Adding SRST signal on $flatten\soc_I.\uart_I.\uart_rx_I.$procdff$23404 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_I.$procmux$15242_Y, Q = \soc_I.uart_I.uart_rx_I.bit_cnt, rval = 5'01000). Adding EN signal on $auto$opt_dff.cc:702:run$24306 ($sdff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5238_Y [4:0], Q = \soc_I.uart_I.uart_rx_I.bit_cnt). Adding EN signal on $flatten\soc_I.\uart_I.\uart_rx_I.$procdff$23403 ($dff) from module top (D = { \soc_I.uart_I.uart_rx_I.gf_I.state \soc_I.uart_I.uart_rx_I.shift [8:1] }, Q = \soc_I.uart_I.uart_rx_I.shift). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$23464 ($dff) from module top (D = $flatten\soc_I.\uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:174$3289_Y, Q = \soc_I.uart_I.ub_wr_div, rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$23463 ($dff) from module top (D = $flatten\soc_I.\uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:173$3286_Y, Q = \soc_I.uart_I.ub_wr_data, rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$23462 ($dff) from module top (D = $flatten\soc_I.\uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:172$3281_Y, Q = \soc_I.uart_I.ub_rd_ctrl, rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$23461 ($dff) from module top (D = $flatten\soc_I.\uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:171$3277_Y, Q = \soc_I.uart_I.ub_rd_data, rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$23460 ($dff) from module top (D = $flatten\soc_I.\uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:181$3296_Y, Q = \soc_I.uart_I.ub_ack, rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$23459 ($dff) from module top (D = { $flatten\soc_I.\uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3301_Y [31] $flatten\soc_I.\uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3301_Y [27:12] $flatten\soc_I.\uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3301_Y [7:0] }, Q = { \soc_I.uart_I.ub_rdata [31] \soc_I.uart_I.ub_rdata [27:12] \soc_I.uart_I.ub_rdata [7:0] }, rval = 25'0000000000000000000000000). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$23459 ($dff) from module top (D = { \soc_I.uart_I.urf_overflow \soc_I.uart_I.uart_tx_fifo_I.rd_empty \soc_I.uart_I.uart_tx_fifo_I.full \soc_I.uart_I.uart_div [11:8] }, Q = { \soc_I.uart_I.ub_rdata [30:28] \soc_I.uart_I.ub_rdata [11:8] }, rval = 7'0000000). Adding EN signal on $flatten\soc_I.\uart_I.$procdff$23458 ($dff) from module top (D = \soc_I.cpu_I.mem_wdata [11:0], Q = \soc_I.uart_I.uart_div). Adding EN signal on $flatten\soc_I.\rgb_I.$procdff$23420 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [4:0], Q = \soc_I.rgb_I.led_ctrl). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$22997 ($adff) from module top (D = \soc_I.iobuf_I.spram_arb_I.mux_wmsk, Q = \soc_I.iobuf_I.spram_arb_I.m_wmsk). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$22996 ($adff) from module top (D = $flatten\soc_I.\iobuf_I.\spram_arb_I.$reduce_or$/build/gateware/common/rtl/wb_arbiter.v:91$5134_Y, Q = \soc_I.iobuf_I.spram_arb_I.m_we). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$22995 ($adff) from module top (D = \soc_I.iobuf_I.spram_arb_I.mux_wdata, Q = \soc_I.iobuf_I.spram_arb_I.m_wdata). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$22994 ($adff) from module top (D = \soc_I.iobuf_I.spram_arb_I.mux_addr, Q = \soc_I.iobuf_I.spram_arb_I.m_addr). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$22993 ($adff) from module top (D = $flatten\soc_I.\iobuf_I.\spram_arb_I.$reduce_or$/build/gateware/common/rtl/wb_arbiter.v:121$5147_Y, Q = \soc_I.iobuf_I.spram_arb_I.busy). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$22992 ($adff) from module top (D = \soc_I.iobuf_I.spram_arb_I.sel_nxt, Q = \soc_I.iobuf_I.spram_arb_I.sel). Adding EN signal on $flatten\soc_I.\iobuf_I.\epbam_arb_I.$procdff$23003 ($adff) from module top (D = $flatten\soc_I.\iobuf_I.\epbam_arb_I.$reduce_or$/build/gateware/common/rtl/wb_arbiter.v:91$5082_Y, Q = \soc_I.iobuf_I.epbam_arb_I.m_we). Adding EN signal on $flatten\soc_I.\iobuf_I.\epbam_arb_I.$procdff$23002 ($adff) from module top (D = \soc_I.iobuf_I.epbam_arb_I.mux_wdata, Q = \soc_I.iobuf_I.epbam_arb_I.m_wdata). Adding EN signal on $flatten\soc_I.\iobuf_I.\epbam_arb_I.$procdff$23001 ($adff) from module top (D = \soc_I.iobuf_I.epbam_arb_I.mux_addr, Q = \soc_I.iobuf_I.epbam_arb_I.m_addr). Adding EN signal on $flatten\soc_I.\iobuf_I.\epbam_arb_I.$procdff$23000 ($adff) from module top (D = $flatten\soc_I.\iobuf_I.\epbam_arb_I.$reduce_or$/build/gateware/common/rtl/wb_arbiter.v:121$5093_Y, Q = \soc_I.iobuf_I.epbam_arb_I.busy). Adding EN signal on $flatten\soc_I.\iobuf_I.\epbam_arb_I.$procdff$22999 ($adff) from module top (D = \soc_I.iobuf_I.epbam_arb_I.sel_nxt, Q = \soc_I.iobuf_I.epbam_arb_I.sel). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$23013 ($adff) from module top (D = \soc_I.iobuf_I.dma_I.state_nxt, Q = \soc_I.iobuf_I.dma_I.state). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$23012 ($dff) from module top (D = $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:144$5026_Y, Q = \soc_I.iobuf_I.dma_I.data_reg). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$23011 ($dff) from module top (D = $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:155$5030_Y [13:0], Q = \soc_I.iobuf_I.dma_I.m0_addr_i). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$23010 ($dff) from module top (D = $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:159$5034_Y [8:0], Q = \soc_I.iobuf_I.dma_I.m1_addr_i). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$23009 ($dff) from module top (D = $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:176$5043_Y [12:0], Q = \soc_I.iobuf_I.dma_I.len). Adding SRST signal on $auto$opt_dff.cc:764:run$24345 ($dffe) from module top (D = $flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$5042_Y [12], Q = \soc_I.iobuf_I.dma_I.len [12], rval = 1'0). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$23008 ($dff) from module top (D = \soc_I.cpu_I.mem_wdata [14], Q = \soc_I.iobuf_I.dma_I.dir). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$23219 ($dff) from module top (D = \soc_I.e1_buf_I.t_nxt_chan, Q = \soc_I.e1_buf_I.t_chan). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$23209 ($dff) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$12391_Y, Q = \soc_I.e1_buf_I.wb_wdata_byte). Adding SRST signal on $auto$opt_dff.cc:764:run$24349 ($dffe) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$12388_Y, Q = \soc_I.e1_buf_I.wb_wdata_byte, rval = 8'00000000). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$23208 ($dff) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$12406_Y, Q = \soc_I.e1_buf_I.wb_addr_lsb). Adding SRST signal on $auto$opt_dff.cc:764:run$24351 ($dffe) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$12403_Y, Q = \soc_I.e1_buf_I.wb_addr_lsb, rval = 2'00). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$23207 ($dff) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$12421_Y, Q = \soc_I.e1_buf_I.wb_addr). Adding SRST signal on $auto$opt_dff.cc:764:run$24353 ($dffe) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$12418_Y, Q = \soc_I.e1_buf_I.wb_addr, rval = 14'00000000000000). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$23206 ($dff) from module top (D = { \soc_I.e1_buf_I.buf_rx_mf [6:0] \soc_I.e1_buf_I.buf_rx_frame [3:0] \soc_I.e1_buf_I.buf_rx_ts [4:0] }, Q = \soc_I.e1_buf_I.rx_addr_reg[0]). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$23205 ($dff) from module top (D = \soc_I.e1_buf_I.buf_rx_data [7:0], Q = \soc_I.e1_buf_I.rx_data_reg[0]). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$23200 ($dff) from module top (D = { \soc_I.e1_buf_I.buf_tx_mf [6:0] \soc_I.e1_buf_I.buf_tx_frame [3:0] \soc_I.e1_buf_I.buf_tx_ts [4:0] }, Q = \soc_I.e1_buf_I.tx_addr_reg[0]). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$23198 ($dff) from module top (D = \soc_I.e1_buf_I.wb_rdata_mux, Q = \soc_I.e1_buf_I.tx_data_reg[0]). Adding SRST signal on $flatten\soc_I.\e1_I.$procdff$23185 ($dff) from module top (D = \soc_I.e1_I.bus_rdata, Q = \soc_I.e1_I.wb_rdata, rval = 16'0000000000000000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$procdff$23486 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$procmux$15665_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.hdb3_I.vstate, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24360 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$procmux$15661_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.hdb3_I.vstate). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$procdff$23485 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$procmux$15645_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.hdb3_I.zcnt, rval = 2'00). Adding EN signal on $auto$opt_dff.cc:702:run$24364 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$procmux$15643_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.hdb3_I.zcnt). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$procdff$23484 ($dff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$procmux$15590_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$procmux$15610_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$procmux$15621_Y }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.hdb3_I.d_neg, rval = 4'0000). Adding EN signal on $auto$opt_dff.cc:702:run$24366 ($sdff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$procmux$15588_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.hdb3_I.d_neg [1:0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$procmux$15619_Y }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.hdb3_I.d_neg). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$procdff$23483 ($dff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$procmux$15601_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$procmux$15654_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$procmux$15632_Y }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.hdb3_I.d_pos, rval = 4'0000). Adding EN signal on $auto$opt_dff.cc:702:run$24368 ($sdff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$procmux$15599_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.hdb3_I.d_pos [1:0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$procmux$15630_Y }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.hdb3_I.d_pos). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$procdff$23482 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$procmux$15676_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.hdb3_I.pstate, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24370 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$procmux$15674_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.hdb3_I.pstate). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.\crc_I.$procdff$23562 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.\crc_I.$xor$/build/gateware/cores/no2e1//rtl/e1_crc4.v:40$14_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.framer_I.crc_I.out_crc4). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procdff$23508 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:117$209_Y, Q = \soc_I.e1_buf_I.buf_tx_frame [3:0]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procdff$23507 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:128$212_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.framer_I.fetch_ts_is31). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procdff$23506 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.framer_I.fetch_ts_is31, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.framer_I.fetch_ts_is0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procdff$23505 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:126$211_Y [4:0], Q = \soc_I.e1_buf_I.buf_tx_ts [4:0]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procdff$23504 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$logic_and$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:141$216_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.f_mf_last). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procdff$23503 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.f_mf_last, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.f_mf_first). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procdff$23501 ($adff) from module top (D = 1'1, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.framer_I.fetch_done). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procdff$23499 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:191$227_Y [3:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.framer_I.bit_cnt). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procdff$23498 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:198$229_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.framer_I.shift_data). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procdff$23497 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$and$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:212$241_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.framer_I.shift_at_crc). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procdff$23496 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$and$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:211$238_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.framer_I.shift_at_last). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procdff$23495 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$and$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:210$234_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.framer_I.crc_I.in_first). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procdff$23493 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$0\crc_smf[3:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.framer_I.crc_smf). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$procdff$23053 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_in_I.stage[1].l_valid, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.mf_valid). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$procdff$23050 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$procmux$11670_Y, Q = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.ll_raw_lo $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.pg_lo [3:0] }, rval = 5'00000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$procdff$23049 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$procmux$11676_Y, Q = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.ll_raw_hi $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.pg_hi [3:0] }, rval = 5'00000). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\bd_tx_out_I.$procdff$23159 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\bd_tx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4500_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_out_I.data[1]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\bd_tx_out_I.$procdff$23158 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\bd_tx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4505_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_out_I.stage[1].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\bd_tx_out_I.$procdff$23157 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\bd_tx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4511_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_out_I.data[2]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\bd_tx_out_I.$procdff$23156 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\bd_tx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4516_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_out_I.stage[2].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\bd_tx_out_I.$procdff$23155 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\bd_tx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4522_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_out_I.data[3]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\bd_tx_out_I.$procdff$23154 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\bd_tx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4527_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_out_I.stage[3].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\bd_tx_out_I.$procdff$23153 ($adff) from module top (D = \soc_I.e1_buf_I.buf_tx_mf [6:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_out_I.data[4]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\bd_tx_out_I.$procdff$23152 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\bd_tx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4538_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_out_I.stage[4].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\bd_tx_in_I.$procdff$23180 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\bd_tx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4454_Y, Q = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_in_I.data[1] [8:7] \soc_I.e1_buf_I.buf_tx_mf [6:0] }). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\bd_tx_in_I.$procdff$23179 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\bd_tx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4459_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_in_I.stage[1].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\bd_tx_in_I.$procdff$23178 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\bd_tx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4465_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_in_I.data[2]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\bd_tx_in_I.$procdff$23177 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\bd_tx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4470_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_in_I.stage[2].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\bd_tx_in_I.$procdff$23176 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\bd_tx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4476_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_in_I.data[3]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\bd_tx_in_I.$procdff$23175 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\bd_tx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4481_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_in_I.stage[3].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\bd_tx_in_I.$procdff$23174 ($adff) from module top (D = { \soc_I.cpu_I.mem_wdata [14:13] \soc_I.cpu_I.mem_wdata [6:0] }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_in_I.data[4]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\bd_tx_in_I.$procdff$23173 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\bd_tx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4492_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_in_I.stage[4].l_valid). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$procdff$23046 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:118$4566_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.ctx_clear, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$procdff$23045 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:117$4563_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$procmux$11652_CMP, rval = 1'0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$procdff$23044 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [6:5], Q = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_loopback [1] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.ctrl_loopback }). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$procdff$23043 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [4], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.alarm). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$procdff$23042 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [3], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.ctrl_time_src). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$procdff$23041 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [2:1], Q = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.ctrl_do_crc4 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_mode [0] }). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$procdff$23040 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bus_rd_tx_status [0]). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$procdff$23039 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:158$4579_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_out_I.rd_ena, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$procdff$23038 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:157$4573_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_in_I.wr_ena, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\hdb3_I.$procdff$23489 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\hdb3_I.$procmux$15687_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.hdb3_I.pstate, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24420 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\hdb3_I.$xor$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:62$439_Y [0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.hdb3_I.pstate). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\hdb3_I.$procdff$23488 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\hdb3_I.$procmux$15698_Y, Q = { \soc_I.e1_I.lb_bit [0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.hdb3_I.data [2:0] }, rval = 4'0000). Adding EN signal on $auto$opt_dff.cc:702:run$24426 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\hdb3_I.$procmux$15696_Y, Q = { \soc_I.e1_I.lb_bit [0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.hdb3_I.data [2:0] }). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$procdff$23515 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$procmux$15758_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.filter_I.cnt_lo, rval = 2'00). Adding EN signal on $auto$opt_dff.cc:702:run$24428 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$procmux$15758_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.filter_I.cnt_lo). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$procdff$23514 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$procmux$15767_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.filter_I.cnt_hi, rval = 2'00). Adding EN signal on $auto$opt_dff.cc:702:run$24432 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$procmux$15767_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.filter_I.cnt_hi). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$procdff$23513 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$procmux$15739_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.clock_I.in_stb, rval = 1'1). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$procdff$23512 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$procmux$15744_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.clock_I.in_lo, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24437 ($sdff) from module top (D = 1'0, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.clock_I.in_lo). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$procdff$23511 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$procmux$15749_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.clock_I.in_hi, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24439 ($sdff) from module top (D = 1'0, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.clock_I.in_hi). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.\crc_I.$procdff$23562 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.\crc_I.$xor$/build/gateware/cores/no2e1//rtl/e1_crc4.v:40$14_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.crc_I.out_crc4). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23559 ($dff) from module top (D = \misc_I.e1_cnt_I[0].sub_I.inc, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.crc_I.in_valid, rval = 1'0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23558 ($dff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.data [6:0] \soc_I.e1_I.lb_bit [0] }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.data). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23557 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:132$23_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.data_match_fas). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23555 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procmux$15897_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.bit_last, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24445 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:210$36_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.bit_last). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23554 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procmux$15902_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.bit_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24447 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:209$35_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.bit_first). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23553 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procmux$15907_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.bit, rval = 3'000). Adding EN signal on $auto$opt_dff.cc:702:run$24449 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:208$34_Y [2:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.bit). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23552 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procmux$15882_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.ts_is_ts31, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24451 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:222$40_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.ts_is_ts31). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23551 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procmux$15887_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.ts_is_ts0, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24453 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.ts_is_ts31, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.ts_is_ts0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23550 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procmux$15892_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.ts, rval = 5'00001). Adding EN signal on $auto$opt_dff.cc:702:run$24455 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:220$39_Y [4:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.ts). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23549 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procmux$15857_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.frame_mf_last, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24457 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:238$46_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.frame_mf_last). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23548 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procmux$15862_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.frame_mf_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24459 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.frame_mf_last, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.frame_mf_first). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23547 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procmux$15867_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.frame_smf_last, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24461 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:236$45_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.frame_smf_last). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23546 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procmux$15872_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.frame_smf_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24463 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.frame_smf_last, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.frame_smf_first). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23545 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procmux$15877_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.frame, rval = 4'0000). Adding EN signal on $auto$opt_dff.cc:702:run$24465 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:234$44_Y [3:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.frame). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23544 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$xor$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:257$52_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.fas_pos, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23543 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procmux$15849_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.mfa_timeout, rval = 7'0111111). Adding EN signal on $auto$opt_dff.cc:702:run$24468 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:265$56_Y [6:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.mfa_timeout). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23542 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procmux$15834_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_crc, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24470 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:280$62_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_crc). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23541 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procmux$15839_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24472 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:279$61_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23540 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procmux$15844_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.ts0_msbs, rval = 16'1111111111111111). Adding EN signal on $auto$opt_dff.cc:702:run$24474 ($sdff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.ts0_msbs [14:0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.data [0] }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.ts0_msbs). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23539 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.crc_I.out_crc4, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.crc_smf). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23538 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:320$84_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.ep_nfas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23537 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:321$90_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.ed_nfas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23536 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:318$75_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.ep_fas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23535 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:319$80_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.ed_fas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23534 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:335$103_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.ep_mfa, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23533 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:336$108_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.ed_mfa, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23532 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:333$95_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.ep_crc, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23531 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:334$100_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.ed_crc, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23530 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:349$125_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.ec_mfa, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23529 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:348$121_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.ec_crc, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23528 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:347$117_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.ec_nfas, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23527 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:346$113_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.ec_fas, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23525 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:378$138_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.out_valid, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23524 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:385$140_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.out_last, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23523 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:384$139_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.out_first, rval = 1'1). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23521 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.ts, Q = \soc_I.e1_buf_I.buf_rx_ts [4:0], rval = 5'00000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23520 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.frame, Q = \soc_I.e1_buf_I.buf_rx_frame [3:0], rval = 4'0000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23519 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.data, Q = \soc_I.e1_buf_I.buf_rx_data [7:0], rval = 8'00000000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$procdff$23518 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:378$137_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.aligned, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\clock_I.$procdff$23561 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\clock_I.$or$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:37$16_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.clock_I.enabled, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\clock_I.$procdff$23560 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\clock_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:49$18_Y [5], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.clock_I.cnt [5], rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\clock_I.$procdff$23560 ($dff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\clock_I.$procmux$15950_Y [4] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\clock_I.$procmux$15950_Y [0] }, Q = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.clock_I.cnt [4] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.clock_I.cnt [0] }, rval = 2'01). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\clock_I.$procdff$23560 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\clock_I.$procmux$15956_Y [3:1], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.clock_I.cnt [3:1], rval = 3'111). Adding EN signal on $auto$opt_dff.cc:702:run$24513 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\clock_I.$procmux$15956_Y [3:1], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.clock_I.cnt [3:1]). Adding EN signal on $auto$opt_dff.cc:702:run$24512 ($sdff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\clock_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:49$18_Y [4] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\clock_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:49$18_Y [0] }, Q = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.clock_I.cnt [4] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.clock_I.cnt [0] }). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\bd_rx_out_I.$procdff$23180 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\bd_rx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4454_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_out_I.data[1]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\bd_rx_out_I.$procdff$23179 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4459_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_out_I.stage[1].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\bd_rx_out_I.$procdff$23178 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\bd_rx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4465_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_out_I.data[2]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\bd_rx_out_I.$procdff$23177 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4470_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_out_I.stage[2].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\bd_rx_out_I.$procdff$23176 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\bd_rx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4476_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_out_I.data[3]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\bd_rx_out_I.$procdff$23175 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4481_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_out_I.stage[3].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\bd_rx_out_I.$procdff$23174 ($adff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_out_I.data[5] [8:7] \soc_I.e1_buf_I.buf_rx_mf [6:0] }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_out_I.data[4]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\bd_rx_out_I.$procdff$23173 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4492_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_out_I.stage[4].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\bd_rx_in_I.$procdff$23159 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\bd_rx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4500_Y, Q = \soc_I.e1_buf_I.buf_rx_mf [6:0]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\bd_rx_in_I.$procdff$23158 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4505_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_in_I.stage[1].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\bd_rx_in_I.$procdff$23157 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\bd_rx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4511_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_in_I.data[2]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\bd_rx_in_I.$procdff$23156 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4516_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_in_I.stage[2].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\bd_rx_in_I.$procdff$23155 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\bd_rx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4522_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_in_I.data[3]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\bd_rx_in_I.$procdff$23154 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4527_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_in_I.stage[3].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\bd_rx_in_I.$procdff$23153 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [6:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_in_I.data[4]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\bd_rx_in_I.$procdff$23152 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4538_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_in_I.stage[4].l_valid). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.$procdff$23035 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:114$4606_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.crx_clear, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.$procdff$23034 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:113$4603_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.$procmux$11636_CMP, rval = 1'0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.$procdff$23032 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bus_rd_rx_status [0]). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.$procdff$23031 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:149$4619_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_out_I.rd_ena, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.$procdff$23030 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:148$4613_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_in_I.wr_ena, rval = 1'0). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23399 ($dff) from module top (D = \soc_I.cpu_I.mem_rdata, Q = \soc_I.cpu_I.mem_rdata_q). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23388 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$0\mem_state[1:0], Q = \soc_I.cpu_I.mem_state). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23387 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14928_Y, Q = \soc_I.cpu_I.mem_wstrb). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23386 ($dff) from module top (D = \soc_I.cpu_I.mem_la_wdata, Q = \soc_I.cpu_I.mem_wdata). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23384 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$0\mem_valid[0:0], Q = \soc_I.cpu_I.mem_valid). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23383 ($dff) from module top (D = \soc_I.cpu_I.mem_la_addr, Q = \soc_I.cpu_I.mem_addr). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23367 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$reduce_or$/build/gateware/common/rtl/picorv32.v:846$3769_Y, Q = \soc_I.cpu_I.is_compare, rval = 1'0). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23366 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:860$3789_Y, Q = \soc_I.cpu_I.is_alu_reg_reg). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23365 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:859$3788_Y, Q = \soc_I.cpu_I.is_alu_reg_imm). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23363 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14309_Y, Q = \soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24584 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:856$3785_Y, Q = \soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23360 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$reduce_or$/build/gateware/common/rtl/picorv32.v:842$3765_Y, Q = \soc_I.cpu_I.is_lui_auipc_jal_jalr_addi_add_sub, rval = 1'0). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23359 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1091$4018_Y, Q = \soc_I.cpu_I.is_sll_srl_sra). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23358 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:858$3787_Y, Q = \soc_I.cpu_I.is_sb_sh_sw). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23357 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1082$4007_Y, Q = \soc_I.cpu_I.is_jalr_addi_slti_sltiu_xori_ori_andi). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23356 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1076$3998_Y, Q = \soc_I.cpu_I.is_slli_srli_srai). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23355 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:857$3786_Y, Q = \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23353 ($dff) from module top (D = 1'0, Q = \soc_I.cpu_I.compressed_instr). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$24592 ($dffe) from module top. Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23352 ($dff) from module top (D = { \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [19:12] \soc_I.cpu_I.mem_rdata_latched [20] \soc_I.cpu_I.mem_rdata_latched [30:21] 1'0 }, Q = \soc_I.cpu_I.decoded_imm_uj). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$24593 ($dffe) from module top. Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23351 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355_Y, Q = \soc_I.cpu_I.decoded_imm). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23350 ($dff) from module top (D = \soc_I.cpu_I.mem_rdata_latched [24:20], Q = \soc_I.cpu_I.decoded_rs2). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23349 ($dff) from module top (D = \soc_I.cpu_I.mem_rdata_latched [19:15], Q = \soc_I.cpu_I.decoded_rs1). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23348 ($dff) from module top (D = \soc_I.cpu_I.mem_rdata_latched [11:7], Q = \soc_I.cpu_I.decoded_rd). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23344 ($dff) from module top (D = 1'0, Q = \soc_I.cpu_I.instr_retirq). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$24598 ($dffe) from module top. Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23341 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1068$3965_Y, Q = \soc_I.cpu_I.instr_ecall_ebreak). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23336 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14465_Y, Q = \soc_I.cpu_I.instr_and, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24600 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1059$3934_Y, Q = \soc_I.cpu_I.instr_and). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23335 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14469_Y, Q = \soc_I.cpu_I.instr_or, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24602 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1058$3930_Y, Q = \soc_I.cpu_I.instr_or). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23334 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14473_Y, Q = \soc_I.cpu_I.instr_sra, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24604 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1057$3926_Y, Q = \soc_I.cpu_I.instr_sra). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23333 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14477_Y, Q = \soc_I.cpu_I.instr_srl, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24606 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1056$3922_Y, Q = \soc_I.cpu_I.instr_srl). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23332 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14481_Y, Q = \soc_I.cpu_I.instr_xor, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24608 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1055$3918_Y, Q = \soc_I.cpu_I.instr_xor). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23331 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14485_Y, Q = \soc_I.cpu_I.instr_sltu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24610 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1054$3914_Y, Q = \soc_I.cpu_I.instr_sltu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23330 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14489_Y, Q = \soc_I.cpu_I.instr_slt, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24612 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1053$3910_Y, Q = \soc_I.cpu_I.instr_slt). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23329 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14493_Y, Q = \soc_I.cpu_I.instr_sll, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24614 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1052$3906_Y, Q = \soc_I.cpu_I.instr_sll). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23328 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14497_Y, Q = \soc_I.cpu_I.instr_sub, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24616 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1051$3902_Y, Q = \soc_I.cpu_I.instr_sub). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23327 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14501_Y, Q = \soc_I.cpu_I.instr_add, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24618 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1050$3898_Y, Q = \soc_I.cpu_I.instr_add). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23326 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1048$3894_Y, Q = \soc_I.cpu_I.instr_srai). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23325 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1047$3890_Y, Q = \soc_I.cpu_I.instr_srli). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23324 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1046$3886_Y, Q = \soc_I.cpu_I.instr_slli). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23323 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14511_Y, Q = \soc_I.cpu_I.instr_andi, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24623 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1044$3882_Y, Q = \soc_I.cpu_I.instr_andi). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23322 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14515_Y, Q = \soc_I.cpu_I.instr_ori, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24625 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1043$3880_Y, Q = \soc_I.cpu_I.instr_ori). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23321 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14519_Y, Q = \soc_I.cpu_I.instr_xori, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24627 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1042$3878_Y, Q = \soc_I.cpu_I.instr_xori). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23320 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14523_Y, Q = \soc_I.cpu_I.instr_sltiu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24629 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1041$3876_Y, Q = \soc_I.cpu_I.instr_sltiu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23319 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14527_Y, Q = \soc_I.cpu_I.instr_slti, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24631 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1040$3874_Y, Q = \soc_I.cpu_I.instr_slti). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23318 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14531_Y, Q = \soc_I.cpu_I.instr_addi, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24633 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1039$3872_Y, Q = \soc_I.cpu_I.instr_addi). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23317 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1037$3870_Y, Q = \soc_I.cpu_I.instr_sw). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23316 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1036$3868_Y, Q = \soc_I.cpu_I.instr_sh). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23315 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1035$3866_Y, Q = \soc_I.cpu_I.instr_sb). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23314 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1033$3864_Y, Q = \soc_I.cpu_I.instr_lhu). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23313 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1032$3862_Y, Q = \soc_I.cpu_I.instr_lbu). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23312 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1031$3860_Y, Q = \soc_I.cpu_I.instr_lw). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23311 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1030$3858_Y, Q = \soc_I.cpu_I.instr_lh). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23310 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1029$3856_Y, Q = \soc_I.cpu_I.instr_lb). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23309 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14551_Y, Q = \soc_I.cpu_I.instr_bgeu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24643 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1027$3854_Y, Q = \soc_I.cpu_I.instr_bgeu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23308 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14555_Y, Q = \soc_I.cpu_I.instr_bltu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24645 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1026$3852_Y, Q = \soc_I.cpu_I.instr_bltu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23307 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14559_Y, Q = \soc_I.cpu_I.instr_bge, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24647 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1025$3850_Y, Q = \soc_I.cpu_I.instr_bge). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23306 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14563_Y, Q = \soc_I.cpu_I.instr_blt, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24649 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1024$3848_Y, Q = \soc_I.cpu_I.instr_blt). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23305 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14567_Y, Q = \soc_I.cpu_I.instr_bne, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24651 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1023$3846_Y, Q = \soc_I.cpu_I.instr_bne). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23304 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14571_Y, Q = \soc_I.cpu_I.instr_beq, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24653 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1022$3844_Y, Q = \soc_I.cpu_I.instr_beq). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23303 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:852$3776_Y, Q = \soc_I.cpu_I.instr_jalr). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23302 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:851$3773_Y, Q = \soc_I.cpu_I.instr_jal). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23301 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:850$3772_Y, Q = \soc_I.cpu_I.instr_auipc). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23300 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:849$3771_Y, Q = \soc_I.cpu_I.instr_lui). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23296 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13158_Y, Q = \soc_I.cpu_I.alu_wait, rval = 1'0). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23289 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13285_Y, Q = \soc_I.cpu_I.latched_rd, rval = 5'00010). Adding EN signal on $auto$opt_dff.cc:702:run$24662 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13285_Y, Q = \soc_I.cpu_I.latched_rd). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23288 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13311_Y, Q = \soc_I.cpu_I.latched_is_lb, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24672 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13311_Y, Q = \soc_I.cpu_I.latched_is_lb). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23287 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13324_Y, Q = \soc_I.cpu_I.latched_is_lh, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24682 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13324_Y, Q = \soc_I.cpu_I.latched_is_lh). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23286 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13337_Y, Q = \soc_I.cpu_I.latched_is_lu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24692 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13337_Y, Q = \soc_I.cpu_I.latched_is_lu). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23284 ($dff) from module top (D = \soc_I.cpu_I.compressed_instr, Q = \soc_I.cpu_I.latched_compr). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23283 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13382_Y, Q = \soc_I.cpu_I.latched_branch, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24705 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13382_Y, Q = \soc_I.cpu_I.latched_branch). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23282 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13418_Y, Q = \soc_I.cpu_I.latched_stalu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24713 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13418_Y, Q = \soc_I.cpu_I.latched_stalu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23281 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13425_Y, Q = \soc_I.cpu_I.latched_store, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24723 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13425_Y, Q = \soc_I.cpu_I.latched_store). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23270 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13051_Y, Q = \soc_I.cpu_I.decoder_pseudo_trigger, rval = 1'0). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23267 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13689_Y, Q = \soc_I.cpu_I.mem_do_wdata, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24734 ($sdff) from module top (D = 1'0, Q = \soc_I.cpu_I.mem_do_wdata). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23266 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13693_Y, Q = \soc_I.cpu_I.mem_do_rdata, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24736 ($sdff) from module top (D = 1'0, Q = \soc_I.cpu_I.mem_do_rdata). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23265 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13764_Y, Q = \soc_I.cpu_I.mem_do_rinst, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24738 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13764_Y, Q = \soc_I.cpu_I.mem_do_rinst). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23264 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13789_Y, Q = \soc_I.cpu_I.mem_do_prefetch, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24754 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1552$4147_Y, Q = \soc_I.cpu_I.mem_do_prefetch). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13184_Y, Q = \soc_I.cpu_I.reg_out, rval = 1024). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23256 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13891_Y, Q = \soc_I.cpu_I.reg_op2). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23255 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13914_Y [31], Q = \soc_I.cpu_I.reg_op1 [31]). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23255 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13914_Y [30:0], Q = \soc_I.cpu_I.reg_op1 [30:0]). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23254 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12526_Y, Q = \soc_I.cpu_I.reg_next_pc [31:2], rval = 30'000000000000000000000000000000). Adding EN signal on $auto$opt_dff.cc:702:run$24798 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12515_Y, Q = \soc_I.cpu_I.reg_next_pc [31:2]). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23253 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13962_Y, Q = \soc_I.cpu_I.reg_pc [31:2], rval = 30'000000000000000000000000000000). Adding EN signal on $auto$opt_dff.cc:702:run$24800 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$3\current_pc[31:0] [31:2], Q = \soc_I.cpu_I.reg_pc [31:2]). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23246 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13267_Y, Q = \soc_I.cpu_I.trap, rval = 1'0). Adding SRST signal on $flatten\soc_I.\bridge_I.$procdff$23023 ($dff) from module top (D = \soc_I.bridge_I.wb_rdata_or, Q = \soc_I.bridge_I.wb_rdata_reg, rval = 0). Adding SRST signal on $flatten\soc_I.\bram_I.$procdff$23415 ($dff) from module top (D = 8'xxxxxxxx, Q = $flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3500_DATA [31:24], rval = 8'00000000). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$24804 ($sdff) from module top. Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$24804 ($sdff) from module top. Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$24804 ($sdff) from module top. Setting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$24804 ($sdff) from module top. Setting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$24804 ($sdff) from module top. Setting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$24804 ($sdff) from module top. Setting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$24804 ($sdff) from module top. Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$24804 ($sdff) from module top. Adding SRST signal on $flatten\soc_I.\bram_I.$procdff$23412 ($dff) from module top (D = 16'xxxxxxxxxxxxxxxx, Q = $flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3499_DATA [31:16], rval = 16'0000000000000000). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$24805 ($sdff) from module top. Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$24805 ($sdff) from module top. Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$24805 ($sdff) from module top. Setting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$24805 ($sdff) from module top. Setting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$24805 ($sdff) from module top. Setting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$24805 ($sdff) from module top. Setting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$24805 ($sdff) from module top. Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$24805 ($sdff) from module top. Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$24805 ($sdff) from module top. Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$24805 ($sdff) from module top. Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$24805 ($sdff) from module top. Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$24805 ($sdff) from module top. Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$24805 ($sdff) from module top. Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$24805 ($sdff) from module top. Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$24805 ($sdff) from module top. Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$24805 ($sdff) from module top. Adding SRST signal on $flatten\soc_I.\bram_I.$procdff$23409 ($dff) from module top (D = 24'xxxxxxxxxxxxxxxxxxxxxxxx, Q = $flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3498_DATA [31:8], rval = 24'000000000000000000000000). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$24806 ($sdff) from module top. Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$24806 ($sdff) from module top. Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$24806 ($sdff) from module top. Setting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$24806 ($sdff) from module top. Setting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$24806 ($sdff) from module top. Setting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$24806 ($sdff) from module top. Setting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$24806 ($sdff) from module top. Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$24806 ($sdff) from module top. Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$24806 ($sdff) from module top. Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$24806 ($sdff) from module top. Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$24806 ($sdff) from module top. Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$24806 ($sdff) from module top. Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$24806 ($sdff) from module top. Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$24806 ($sdff) from module top. Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$24806 ($sdff) from module top. Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$24806 ($sdff) from module top. Setting constant 0-bit at position 16 on $auto$opt_dff.cc:702:run$24806 ($sdff) from module top. Setting constant 0-bit at position 17 on $auto$opt_dff.cc:702:run$24806 ($sdff) from module top. Setting constant 0-bit at position 18 on $auto$opt_dff.cc:702:run$24806 ($sdff) from module top. Setting constant 0-bit at position 19 on $auto$opt_dff.cc:702:run$24806 ($sdff) from module top. Setting constant 0-bit at position 20 on $auto$opt_dff.cc:702:run$24806 ($sdff) from module top. Setting constant 0-bit at position 21 on $auto$opt_dff.cc:702:run$24806 ($sdff) from module top. Setting constant 0-bit at position 22 on $auto$opt_dff.cc:702:run$24806 ($sdff) from module top. Setting constant 0-bit at position 23 on $auto$opt_dff.cc:702:run$24806 ($sdff) from module top. Adding SRST signal on $flatten\misc_I.\pps_flt_I.$procdff$23234 ($dff) from module top (D = $flatten\misc_I.\pps_flt_I.$procmux$12464_Y, Q = \misc_I.pps_flt_I.state, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24807 ($sdff) from module top (D = 1'1, Q = \misc_I.pps_flt_I.state). Adding SRST signal on $flatten\misc_I.\pdm_e1_I[1].$procdff$23244 ($dff) from module top (D = $flatten\misc_I.\pdm_e1_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4268_Y, Q = \misc_I.pdm_e1_I[1].acc, rval = 9'000000000). Adding SRST signal on $flatten\misc_I.\pdm_e1_I[0].$procdff$23244 ($dff) from module top (D = $flatten\misc_I.\pdm_e1_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4268_Y, Q = \misc_I.pdm_e1_I[0].acc, rval = 9'000000000). Adding SRST signal on $flatten\misc_I.\pdm_clk_I[1].\lfsr_I.$procdff$23456 ($dff) from module top (D = { \misc_I.pdm_clk_I[1].lfsr_I.fb \misc_I.pdm_clk_I[1].lfsr_I.out [7:1] }, Q = \misc_I.pdm_clk_I[1].lfsr_I.out, rval = 8'00000001). Adding SRST signal on $flatten\misc_I.\pdm_clk_I[1].$procdff$23243 ($dff) from module top (D = $flatten\misc_I.\pdm_clk_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4273_Y, Q = \misc_I.pdm_clk_I[1].acc, rval = 13'0000000000000). Adding SRST signal on $flatten\misc_I.\pdm_clk_I[0].\lfsr_I.$procdff$23456 ($dff) from module top (D = { \misc_I.pdm_clk_I[0].lfsr_I.fb \misc_I.pdm_clk_I[0].lfsr_I.out [7:1] }, Q = \misc_I.pdm_clk_I[0].lfsr_I.out, rval = 8'00000001). Adding SRST signal on $flatten\misc_I.\pdm_clk_I[0].$procdff$23243 ($dff) from module top (D = $flatten\misc_I.\pdm_clk_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4273_Y, Q = \misc_I.pdm_clk_I[0].acc, rval = 13'0000000000000). Adding SRST signal on $flatten\misc_I.\dfu_I.\btn_flt_I.$procdff$22989 ($dff) from module top (D = $flatten\misc_I.\dfu_I.\btn_flt_I.$procmux$5619_Y, Q = \misc_I.dfu_I.btn_flt_I.state, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24815 ($sdff) from module top (D = 1'1, Q = \misc_I.dfu_I.btn_flt_I.state). Adding EN signal on $flatten\misc_I.\dfu_I.$procdff$23238 ($adff) from module top (D = $flatten\misc_I.\dfu_I.$procmux$12490_Y, Q = \misc_I.dfu_I.wb_sel). Adding EN signal on $flatten\misc_I.\dfu_I.$procdff$23237 ($adff) from module top (D = $flatten\misc_I.\dfu_I.$procmux$12495_Y, Q = \misc_I.dfu_I.rst_req). Adding SRST signal on $flatten\misc_I.$procdff$23068 ($dff) from module top (D = { $flatten\misc_I.$eq$/build/gateware/icE1usb/rtl/misc.v:126$1628_Y $flatten\misc_I.$eq$/build/gateware/icE1usb/rtl/misc.v:125$1627_Y }, Q = \misc_I.bus_we_pdm_e1, rval = 2'00). Adding SRST signal on $flatten\misc_I.$procdff$23067 ($dff) from module top (D = { $flatten\misc_I.$eq$/build/gateware/icE1usb/rtl/misc.v:124$1626_Y $flatten\misc_I.$eq$/build/gateware/icE1usb/rtl/misc.v:123$1625_Y }, Q = \misc_I.bus_we_pdm_clk, rval = 2'00). Adding SRST signal on $flatten\misc_I.$procdff$23066 ($dff) from module top (D = $flatten\misc_I.$eq$/build/gateware/icE1usb/rtl/misc.v:122$1624_Y, Q = \misc_I.bus_we_led, rval = 1'0). Adding SRST signal on $flatten\misc_I.$procdff$23065 ($dff) from module top (D = $flatten\misc_I.$eq$/build/gateware/icE1usb/rtl/misc.v:121$1623_Y, Q = \misc_I.bus_we_gpio, rval = 1'0). Adding SRST signal on $flatten\misc_I.$procdff$23064 ($dff) from module top (D = $flatten\misc_I.$eq$/build/gateware/icE1usb/rtl/misc.v:120$1622_Y, Q = \misc_I.bus_we_boot, rval = 1'0). Adding SRST signal on $flatten\misc_I.$procdff$23063 ($dff) from module top (D = $flatten\misc_I.$procmux$11702_Y, Q = \misc_I.wb_rdata, rval = 0). Adding EN signal on $flatten\misc_I.$procdff$23062 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [3:0], Q = \misc_I.gpio_out). Adding EN signal on $flatten\misc_I.$procdff$23061 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [11:8], Q = \misc_I.gpio_oe). Adding EN signal on $flatten\misc_I.$procdff$23060 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [8:0], Q = \misc_I.e1_led). Adding EN signal on $flatten\misc_I.$procdff$23059 ($adff) from module top (D = { \soc_I.cpu_I.mem_wdata [31] \soc_I.cpu_I.mem_wdata [7:0] }, Q = \misc_I.pdm_e1[1]). Adding EN signal on $flatten\misc_I.$procdff$23058 ($adff) from module top (D = { \soc_I.cpu_I.mem_wdata [31] \soc_I.cpu_I.mem_wdata [7:0] }, Q = \misc_I.pdm_e1[0]). Adding EN signal on $flatten\misc_I.$procdff$23057 ($adff) from module top (D = { \soc_I.cpu_I.mem_wdata [31] \soc_I.cpu_I.mem_wdata [11:0] }, Q = \misc_I.pdm_clk[1]). Adding EN signal on $flatten\misc_I.$procdff$23056 ($adff) from module top (D = { \soc_I.cpu_I.mem_wdata [31] \soc_I.cpu_I.mem_wdata [11:0] }, Q = \misc_I.pdm_clk[0]). Adding EN signal on $flatten\misc_I.$procdff$23055 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [2], Q = \misc_I.boot_now). Adding EN signal on $flatten\misc_I.$procdff$23054 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [1:0], Q = \misc_I.boot_sel). Adding EN signal on $flatten\i2c_I.\core_I.$procdff$23454 ($dff) from module top (D = \soc_I.cpu_I.mem_wdata [13:12], Q = \i2c_I.core_I.cmd_cur). Adding SRST signal on $flatten\i2c_I.\core_I.$procdff$23453 ($dff) from module top (D = $flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:133$5202_Y [4:0], Q = \i2c_I.core_I.cyc_cnt, rval = 5'00000). Adding EN signal on $flatten\i2c_I.\core_I.$procdff$23452 ($dff) from module top (D = $flatten\i2c_I.\core_I.$0\bit_cnt[3:0], Q = \i2c_I.core_I.bit_cnt). Adding EN signal on $flatten\i2c_I.\core_I.$procdff$23451 ($dff) from module top (D = $flatten\i2c_I.\core_I.$0\data_reg[8:0], Q = \i2c_I.core_I.data_reg). Adding SRST signal on $flatten\i2c_I.\core_I.$procdff$23450 ($dff) from module top (D = $flatten\i2c_I.\core_I.$procmux$15362_Y, Q = \i2c_I.core_I.scl_oe, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24844 ($sdff) from module top (D = $flatten\i2c_I.\core_I.$procmux$15360_Y, Q = \i2c_I.core_I.scl_oe). Adding SRST signal on $flatten\i2c_I.\core_I.$procdff$23449 ($dff) from module top (D = $flatten\i2c_I.\core_I.$procmux$15352_Y, Q = \i2c_I.core_I.sda_oe, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24850 ($sdff) from module top (D = $flatten\i2c_I.\core_I.$procmux$15350_Y, Q = \i2c_I.core_I.sda_oe). Adding SRST signal on $flatten\i2c_I.$procdff$23466 ($dff) from module top (D = { \i2c_I.ready \i2c_I.ready \i2c_I.core_I.data_reg [0] \i2c_I.core_I.data_reg [8:1] }, Q = { \i2c_I.wb_rdata [31:30] \i2c_I.wb_rdata [8:0] }, rval = 11'00000000000). Adding EN signal on $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$procdff$23019 ($dff) from module top (D = $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5456_DATA, Q = \gps_uart_I.uart_tx_fifo_I.ram_I.rd_data). Adding EN signal on $flatten\gps_uart_I.\uart_tx_fifo_I.$procdff$23228 ($adff) from module top (D = $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4332_Y [8:0], Q = \gps_uart_I.uart_tx_fifo_I.ram_wr_addr). Adding EN signal on $flatten\gps_uart_I.\uart_tx_fifo_I.$procdff$23227 ($adff) from module top (D = $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4334_Y [8:0], Q = \gps_uart_I.uart_tx_fifo_I.ram_rd_addr). Adding EN signal on $flatten\gps_uart_I.\uart_tx_fifo_I.$procdff$23226 ($adff) from module top (D = $flatten\gps_uart_I.\uart_tx_fifo_I.$not$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:114$4337_Y, Q = \gps_uart_I.uart_tx_fifo_I.rd_valid). Adding SRST signal on $flatten\gps_uart_I.\uart_tx_I.$procdff$23224 ($dff) from module top (D = $flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5253_Y [12], Q = \gps_uart_I.uart_tx_I.div_cnt [12], rval = 1'0). Adding SRST signal on $flatten\gps_uart_I.\uart_tx_I.$procdff$23223 ($dff) from module top (D = $flatten\gps_uart_I.\uart_tx_I.$procmux$12443_Y, Q = \gps_uart_I.uart_tx_I.bit_cnt, rval = 5'01000). Adding EN signal on $auto$opt_dff.cc:702:run$24864 ($sdff) from module top (D = $flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5256_Y [4:0], Q = \gps_uart_I.uart_tx_I.bit_cnt). Adding EN signal on $flatten\gps_uart_I.\uart_tx_I.$procdff$23222 ($adff) from module top (D = $flatten\gps_uart_I.\uart_tx_I.$0\shift[9:0], Q = \gps_uart_I.uart_tx_I.shift). Adding EN signal on $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$procdff$23019 ($dff) from module top (D = $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5456_DATA, Q = \gps_uart_I.uart_rx_fifo_I.ram_I.rd_data). Adding EN signal on $flatten\gps_uart_I.\uart_rx_fifo_I.$procdff$23228 ($adff) from module top (D = $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4332_Y [8:0], Q = \gps_uart_I.uart_rx_fifo_I.ram_wr_addr). Adding EN signal on $flatten\gps_uart_I.\uart_rx_fifo_I.$procdff$23227 ($adff) from module top (D = $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4334_Y [8:0], Q = \gps_uart_I.uart_rx_fifo_I.ram_rd_addr). Adding EN signal on $flatten\gps_uart_I.\uart_rx_fifo_I.$procdff$23226 ($adff) from module top (D = $flatten\gps_uart_I.\uart_rx_fifo_I.$not$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:114$4337_Y, Q = \gps_uart_I.uart_rx_fifo_I.rd_valid). Adding SRST signal on $flatten\gps_uart_I.\uart_rx_I.\gf_I.$procdff$23191 ($dff) from module top (D = $flatten\gps_uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4387_Y, Q = \gps_uart_I.uart_rx_I.gf_I.cnt, rval = 2'11). Adding SRST signal on $flatten\gps_uart_I.\uart_rx_I.\gf_I.$procdff$23190 ($dff) from module top (D = $flatten\gps_uart_I.\uart_rx_I.\gf_I.$procmux$12277_Y, Q = \gps_uart_I.uart_rx_I.gf_I.state, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24874 ($sdff) from module top (D = $flatten\gps_uart_I.\uart_rx_I.\gf_I.$procmux$12277_Y, Q = \gps_uart_I.uart_rx_I.gf_I.state). Adding SRST signal on $flatten\gps_uart_I.\uart_rx_I.$procdff$23404 ($dff) from module top (D = $flatten\gps_uart_I.\uart_rx_I.$procmux$15242_Y, Q = \gps_uart_I.uart_rx_I.bit_cnt, rval = 5'01000). Adding EN signal on $auto$opt_dff.cc:702:run$24878 ($sdff) from module top (D = $flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5238_Y [4:0], Q = \gps_uart_I.uart_rx_I.bit_cnt). Adding EN signal on $flatten\gps_uart_I.\uart_rx_I.$procdff$23403 ($dff) from module top (D = { \gps_uart_I.uart_rx_I.gf_I.state \gps_uart_I.uart_rx_I.shift [8:1] }, Q = \gps_uart_I.uart_rx_I.shift). Adding SRST signal on $flatten\gps_uart_I.$procdff$23464 ($dff) from module top (D = $flatten\gps_uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:174$3289_Y, Q = \gps_uart_I.ub_wr_div, rval = 1'0). Adding SRST signal on $flatten\gps_uart_I.$procdff$23463 ($dff) from module top (D = $flatten\gps_uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:173$3286_Y, Q = \gps_uart_I.ub_wr_data, rval = 1'0). Adding SRST signal on $flatten\gps_uart_I.$procdff$23462 ($dff) from module top (D = $flatten\gps_uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:172$3281_Y, Q = \gps_uart_I.ub_rd_ctrl, rval = 1'0). Adding SRST signal on $flatten\gps_uart_I.$procdff$23461 ($dff) from module top (D = $flatten\gps_uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:171$3277_Y, Q = \gps_uart_I.ub_rd_data, rval = 1'0). Adding SRST signal on $flatten\gps_uart_I.$procdff$23460 ($dff) from module top (D = $flatten\gps_uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:181$3296_Y, Q = \gps_uart_I.ub_ack, rval = 1'0). Adding SRST signal on $flatten\gps_uart_I.$procdff$23459 ($dff) from module top (D = { \gps_uart_I.urf_overflow \gps_uart_I.uart_tx_fifo_I.rd_empty \gps_uart_I.uart_tx_fifo_I.full \gps_uart_I.uart_div [11:8] }, Q = { \gps_uart_I.ub_rdata [30:28] \gps_uart_I.ub_rdata [11:8] }, rval = 7'0000000). Adding SRST signal on $flatten\gps_uart_I.$procdff$23459 ($dff) from module top (D = { $flatten\gps_uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3301_Y [31] $flatten\gps_uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3301_Y [27:12] $flatten\gps_uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3301_Y [7:0] }, Q = { \gps_uart_I.ub_rdata [31] \gps_uart_I.ub_rdata [27:12] \gps_uart_I.ub_rdata [7:0] }, rval = 25'0000000000000000000000000). Adding EN signal on $flatten\gps_uart_I.$procdff$23458 ($dff) from module top (D = \soc_I.cpu_I.mem_wdata [11:0], Q = \gps_uart_I.uart_div). 75.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 477 unused cells and 545 unused wires. 75.12.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.12.9. Rerunning OPT passes. (Maybe there is more to do..) 75.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 75.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 75.12.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 27 cells. 75.12.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$24704 ($dffe) from module top. 75.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 31 unused wires. 75.12.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.12.16. Rerunning OPT passes. (Maybe there is more to do..) 75.12.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 75.12.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 75.12.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.12.20. Executing OPT_DFF pass (perform DFF optimizations). 75.12.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 1 unused wires. 75.12.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.12.23. Rerunning OPT passes. (Maybe there is more to do..) 75.12.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 75.12.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 75.12.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.12.27. Executing OPT_DFF pass (perform DFF optimizations). 75.12.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.12.29. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.12.30. Finished OPT passes. (There is nothing left to do.) 75.13. Executing WREDUCE pass (reducing word size of cells). Removed top 24 address bits (of 32) from memory init port top.$flatten\soc_I.\bram_I.$meminit$\mem$/build/gateware/common/rtl/soc_bram.v:0$3524 (soc_I.bram_I.mem). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24568 ($ne). Removed top 2 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23759 ($eq). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24678 ($ne). Removed top 2 bits (of 3) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24666 ($ne). Removed top 2 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23763 ($eq). Removed top 2 bits (of 3) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24564 ($ne). Removed top 1 bits (of 3) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24717 ($ne). Removed top 1 bits (of 6) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24742 ($ne). Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23786 ($eq). Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23782 ($eq). Removed top 1 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23767 ($eq). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24775 ($ne). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24334 ($ne). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24336 ($ne). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24338 ($ne). Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$24095 ($eq). Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$24099 ($eq). Removed top 2 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$24134 ($eq). Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$24164 ($eq). Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$24195 ($eq). Removed top 2 bits (of 4) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24543 ($ne). Removed top 2 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23705 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\e1_buf_I.$eq$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:233$5313 ($eq). Removed top 26 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_buf_I.$shiftx$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5324 ($shiftx). Removed top 3 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5331 ($shl). Removed top 3 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_buf_I.$and$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5333 ($and). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\e1_buf_I.$ne$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:253$5351 ($ne). Removed top 1 bits (of 4) from mux cell top.$flatten\soc_I.\e1_buf_I.$procmux$12303 ($mux). Removed cell top.$flatten\soc_I.\e1_buf_I.$procmux$12388 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\e1_I.$eq$/build/gateware/cores/no2e1//rtl/e1_wb.v:149$5370 ($eq). Removed top 30 bits (of 32) from mux cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$12 ($mux). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.\crc_I.$xor$/build/gateware/cores/no2e1//rtl/e1_crc4.v:40$14 ($xor). Removed top 1 bits (of 16) from FF cell top.$auto$opt_dff.cc:764:run$24475 ($sdffe). Removed top 1 bits (of 6) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23907 ($eq). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:349$125 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:348$121 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:347$117 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:346$113 ($add). Removed top 1 bits (of 6) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23894 ($eq). Removed top 3 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.\crc_I.$and$/build/gateware/cores/no2e1//rtl/e1_crc4.v:35$6 ($and). Removed top 2 bits (of 6) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:279$61 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:265$56 ($sub). Removed top 25 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:265$56 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:234$44 ($add). Removed top 28 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:234$44 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:220$39 ($add). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:220$39 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:208$34 ($add). Removed top 29 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:208$34 ($add). Removed cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$procmux$15764 ($mux). Removed cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$procmux$15755 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:64$162 ($sub). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:64$162 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:62$158 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:62$158 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:56$153 ($sub). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:56$153 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:54$149 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:54$149 ($add). Removed top 2 bits (of 6) from mux cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\clock_I.$procmux$15956 ($mux). Removed top 2 bits (of 6) from mux cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\clock_I.$procmux$15953 ($mux). Removed top 5 bits (of 6) from mux cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\clock_I.$procmux$15950 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\clock_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:49$18 ($sub). Removed top 26 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\clock_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:49$18 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\hdb3_I.$xor$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:62$439 ($xor). Removed top 31 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\hdb3_I.$xor$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:62$439 ($xor). Removed top 2 bits (of 6) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:132$22 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:101$201 ($sub). Removed top 26 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:101$201 ($sub). Removed top 30 bits (of 32) from mux cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$12 ($mux). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.\crc_I.$xor$/build/gateware/cores/no2e1//rtl/e1_crc4.v:40$14 ($xor). Removed cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procmux$15703 ($mux). Removed top 3 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.\crc_I.$and$/build/gateware/cores/no2e1//rtl/e1_crc4.v:35$6 ($and). Removed top 28 bits (of 32) from mux cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:191$227 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:191$225 ($sub). Removed top 28 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:191$225 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:126$211 ($add). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:126$211 ($add). Removed top 27 bits (of 32) from mux cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:101$203 ($mux). Removed cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$procmux$15672 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$add$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:120$456 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$add$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:120$456 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$xor$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:106$451 ($xor). Removed top 31 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$xor$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:106$451 ($xor). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$xor$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:103$450 ($xor). Removed top 31 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$xor$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:103$450 ($xor). Removed top 16 bits (of 32) from port B of cell top.$flatten\soc_I.\iobuf_I.$or$/build/gateware/common/rtl/soc_iobuf.v:250$2642 ($or). Removed cell top.$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5703 ($mux). Removed cell top.$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5700 ($mux). Removed cell top.$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5696 ($mux). Removed top 20 bits (of 32) from mux cell top.$flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:176$5043 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$5042 ($sub). Removed top 19 bits (of 32) from port Y of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$5042 ($sub). Removed top 23 bits (of 32) from mux cell top.$flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:159$5034 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$5032 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$5032 ($add). Removed top 18 bits (of 32) from mux cell top.$flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:155$5030 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$5028 ($add). Removed top 18 bits (of 32) from port Y of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$5028 ($add). Removed top 3 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5742_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5741_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5740_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5739_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5738_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5737_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5736_CMP0 ($eq). Removed top 3 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5725_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5724_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5723_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5722_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5721_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5720_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5719_CMP0 ($eq). Removed cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11845 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11829_CMP0 ($eq). Removed top 29 bits (of 32) from mux cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1506 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1504 ($add). Removed top 29 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1504 ($add). Removed top 30 bits (of 32) from port A of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1500 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1500 ($add). Removed top 29 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1500 ($add). Removed top 16 bits (of 32) from mux cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.\crc_16_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4947 ($mux). Removed top 1 bits (of 7) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23881 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1566 ($sub). Removed top 21 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1566 ($sub). Removed top 21 bits (of 32) from port A of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1566 ($sub). Removed top 21 bits (of 32) from mux cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1565 ($mux). Removed top 1 bits (of 8) from mux cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:172$1549 ($mux). Removed top 28 bits (of 32) from port A of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1543 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1543 ($sub). Removed top 28 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1543 ($sub). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:137$1530 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12223_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12222_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12221_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12208_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12197_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12196_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12195_CMP0 ($eq). Removed top 3 bits (of 4) from mux cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12188 ($mux). Removed top 2 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12180_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12179_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12178_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:98$1285 ($eq). Removed top 16 bits (of 32) from mux cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.\crc_16_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4947 ($mux). Removed top 1 bits (of 16) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.\crc_16_I.$eq$/build/gateware/cores/no2usb//rtl/usb_crc.v:44$4950 ($eq). Removed top 29 bits (of 32) from mux cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.\crc_5_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4960 ($mux). Removed top 2 bits (of 5) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.\crc_5_I.$xor$/build/gateware/cores/no2usb//rtl/usb_crc.v:38$4961 ($xor). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:313$1359 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:311$1355 ($eq). Removed top 3 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:308$1349 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:307$1348 ($eq). Removed top 29 bits (of 32) from port A of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1334 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1334 ($sub). Removed top 28 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1334 ($sub). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$procmux$11910_CMP0 ($eq). Removed top 1 bits (of 4) from mux cell top.$flatten\soc_I.\usb_I.\trans_I.$procmux$11887 ($mux). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$procmux$11885_CMP0 ($eq). Removed cell top.$flatten\soc_I.\usb_I.\trans_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_trans.v:375$1461 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:303$1443 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:207$1421 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:206$1420 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:205$1419 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:204$1418 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:203$1417 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:202$1416 ($eq). Removed top 3 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:201$1415 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:179$1414 ($add). Removed top 24 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:179$1414 ($add). Removed top 24 bits (of 32) from mux cell top.$flatten\soc_I.\uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3301 ($mux). Removed top 1 bits (of 5) from FF cell top.$auto$opt_dff.cc:764:run$24321 ($adffe). Removed top 1 bits (of 13) from mux cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$procmux$12449 ($mux). Removed cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$procmux$12438 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5256 ($sub). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5256 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5253 ($sub). Removed top 19 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5253 ($sub). Removed cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$procmux$5746 ($mux). Removed cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$procmux$5748 ($mux). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$procdff$23022 ($dff). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4334 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4334 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4332 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4332 ($add). Removed top 1 bits (of 10) from port B of cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$eq$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:81$4321 ($eq). Removed cell top.$flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procmux$12274 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5238 ($sub). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5238 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5235 ($sub). Removed top 19 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5235 ($sub). Removed top 21 bits (of 32) from port A of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5234 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5234 ($sub). Removed top 20 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5234 ($sub). Removed cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$procmux$5746 ($mux). Removed cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$procmux$5748 ($mux). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$procdff$23022 ($dff). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4334 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4334 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4332 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4332 ($add). Removed top 1 bits (of 10) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$eq$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:81$4321 ($eq). Removed cell top.$flatten\soc_I.\bram_I.$procmux$15255 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$15257 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$15261 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$15263 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$15267 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$15269 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$15273 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$15275 ($mux). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\bram_I.$procdff$23410 ($dff). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\bram_I.$procdff$23413 ($dff). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\bram_I.$procdff$23416 ($dff). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\bram_I.$procdff$23419 ($dff). Removed top 24 bits (of 32) from port A of cell top.$flatten\soc_I.\bridge_I.$or$/build/gateware/common/rtl/soc_picorv32_bridge.v:152$5419 ($or). Removed top 16 bits (of 32) from port B of cell top.$flatten\soc_I.\bridge_I.$or$/build/gateware/common/rtl/soc_picorv32_bridge.v:152$5421 ($or). Removed top 16 bits (of 32) from port B of cell top.$flatten\soc_I.\bridge_I.$or$/build/gateware/common/rtl/soc_picorv32_bridge.v:152$5425 ($or). Removed top 3 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5432 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5433 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5434 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5435 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5436 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5437 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5438 ($eq). Removed top 3 bits (of 4) from port A of cell top.$flatten\soc_I.\cpu_I.$shl$/build/gateware/common/rtl/picorv32.v:403$3693 ($shl). Removed top 30 bits (of 32) from mux cell top.$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:601$3752 ($mux). Removed top 1 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:849$3771 ($eq). Removed top 2 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:850$3772 ($eq). Removed top 5 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:857$3786 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:858$3787 ($eq). Removed top 2 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:859$3788 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:860$3789 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1023$3845 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1031$3859 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1041$3875 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1048$3893 ($eq). Removed top 29 bits (of 32) from port B of cell top.$flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1296$4066 ($add). Removed top 2 bits (of 4) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24213 ($ne). Removed top 29 bits (of 32) from port B of cell top.$flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1539$4143 ($add). Removed top 2 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23712 ($eq). Removed top 29 bits (of 32) from port B of cell top.$flatten\soc_I.\cpu_I.$ge$/build/gateware/common/rtl/picorv32.v:1814$4194 ($ge). Removed top 29 bits (of 32) from port B of cell top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4202 ($sub). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4202 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4209 ($sub). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4209 ($sub). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12913 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12916 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13180 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13182 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13187 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13237 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13257 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13280 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13283 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13307 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13309 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13320 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13322 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13333 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13335 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13380 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13413 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13416 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13432 ($mux). Removed top 1 bits (of 2) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23828 ($eq). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13701 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13706 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13713 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13729 ($pmux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13762 ($mux). Removed top 2 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23819 ($eq). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13910 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13912 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13918 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13920 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13935 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14056 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14898 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14902 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14908 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\cpu_I.$procmux$14910_CMP0 ($eq). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14911 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14917 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14951 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14961 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14963 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14967 ($mux). Removed top 24 bits (of 32) from mux cell top.$flatten\soc_I.\cpu_I.$procmux$15194 ($pmux). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\cpu_I.$procmux$15197_CMP0 ($eq). Removed top 16 bits (of 32) from mux cell top.$flatten\soc_I.\cpu_I.$procmux$15203 ($pmux). Removed top 11 bits (of 31) from FF cell top.$auto$opt_dff.cc:764:run$24593 ($dffe). Removed top 1 bits (of 8) from port B of cell top.$flatten\misc_I.\pdm_clk_I[1].\lfsr_I.$and$/build/gateware/cores/no2misc//rtl/pdm.v:130$5190 ($and). Removed top 1 bits (of 8) from port B of cell top.$flatten\misc_I.\pdm_clk_I[0].\lfsr_I.$and$/build/gateware/cores/no2misc//rtl/pdm.v:130$5190 ($and). Removed top 25 bits (of 26) from port B of cell top.$flatten\misc_I.\dfu_I.$add$/build/gateware/common/rtl/dfu_helper.v:113$4282 ($add). Removed top 3 bits (of 4) from port B of cell top.$flatten\misc_I.$procmux$11708_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\misc_I.$procmux$11707_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\misc_I.$procmux$11706_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\misc_I.$procmux$11705_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\misc_I.$procmux$11704_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\misc_I.$procmux$11703_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\misc_I.$eq$/build/gateware/icE1usb/rtl/misc.v:122$1624 ($eq). Removed top 3 bits (of 4) from port B of cell top.$flatten\misc_I.$eq$/build/gateware/icE1usb/rtl/misc.v:121$1623 ($eq). Removed top 3 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23697 ($eq). Removed top 1 bits (of 10) from port B of cell top.$flatten\gps_uart_I.\uart_rx_fifo_I.$eq$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:81$4321 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4332 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4332 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4334 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4334 ($add). Removed top 7 bits (of 8) from FF cell top.$flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$procdff$23022 ($dff). Removed cell top.$flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$procmux$5748 ($mux). Removed cell top.$flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$procmux$5746 ($mux). Removed top 21 bits (of 32) from port A of cell top.$flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5234 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5234 ($sub). Removed top 20 bits (of 32) from port Y of cell top.$flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5234 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5235 ($sub). Removed top 19 bits (of 32) from port Y of cell top.$flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5235 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5238 ($sub). Removed top 27 bits (of 32) from port Y of cell top.$flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5238 ($sub). Removed cell top.$flatten\gps_uart_I.\uart_rx_I.\gf_I.$procmux$12274 ($mux). Removed top 1 bits (of 10) from port B of cell top.$flatten\gps_uart_I.\uart_tx_fifo_I.$eq$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:81$4321 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4332 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4332 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4334 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4334 ($add). Removed top 7 bits (of 8) from FF cell top.$flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$procdff$23022 ($dff). Removed cell top.$flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$procmux$5748 ($mux). Removed cell top.$flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$procmux$5746 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5253 ($sub). Removed top 19 bits (of 32) from port Y of cell top.$flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5253 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5256 ($sub). Removed top 27 bits (of 32) from port Y of cell top.$flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5256 ($sub). Removed cell top.$flatten\gps_uart_I.\uart_tx_I.$procmux$12438 ($mux). Removed top 1 bits (of 10) from mux cell top.$flatten\gps_uart_I.\uart_tx_I.$procmux$12441 ($mux). Removed top 1 bits (of 13) from mux cell top.$flatten\gps_uart_I.\uart_tx_I.$procmux$12449 ($mux). Removed top 24 bits (of 32) from mux cell top.$flatten\gps_uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3301 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\gps_uart_I.$eq$/build/gateware/cores/no2misc//rtl/uart_wb.v:172$3280 ($eq). Removed top 3 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23729 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:109$5196 ($eq). Removed top 2 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23810 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:133$5202 ($add). Removed top 27 bits (of 32) from port Y of cell top.$flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:133$5202 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:143$5207 ($add). Removed top 28 bits (of 32) from port Y of cell top.$flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:143$5207 ($add). Removed cell top.$flatten\i2c_I.\core_I.$procmux$15342 ($mux). Removed cell top.$flatten\i2c_I.\core_I.$procmux$15345 ($mux). Removed cell top.$flatten\i2c_I.\core_I.$procmux$15357 ($mux). Removed cell top.$flatten\i2c_I.\core_I.$procmux$15367 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\i2c_I.\core_I.$procmux$15375_CMP0 ($eq). Removed cell top.$flatten\i2c_I.\core_I.$procmux$15377 ($mux). Removed top 1 bits (of 2) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23802 ($eq). Removed top 1 bits (of 11) from FF cell top.$auto$opt_dff.cc:702:run$24858 ($sdff). Removed cell top.$flatten\i2c_I.$procmux$15472 ($mux). Removed top 16 bits (of 32) from port B of cell top.$flatten\blinker_I.$and$/build/gateware/icE1usb/rtl/led_blinker.v:57$1587 ($and). Removed top 16 bits (of 32) from port Y of cell top.$flatten\blinker_I.$and$/build/gateware/icE1usb/rtl/led_blinker.v:57$1587 ($and). Removed top 16 bits (of 32) from port A of cell top.$flatten\blinker_I.$and$/build/gateware/icE1usb/rtl/led_blinker.v:57$1587 ($and). Removed top 31 bits (of 32) from port B of cell top.$flatten\blinker_I.$add$/build/gateware/icE1usb/rtl/led_blinker.v:57$1585 ($add). Removed top 16 bits (of 32) from port Y of cell top.$flatten\blinker_I.$add$/build/gateware/icE1usb/rtl/led_blinker.v:57$1585 ($add). Removed top 2 bits (of 3) from port B of cell top.$flatten\spi_mux_I.$procmux$15544_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23701 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\spi_mux_I.$procmux$15486_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\spi_mux_I.$eq$/build/gateware/icE1usb/rtl/sr_btn_if.v:277$3249 ($eq). Removed top 3 bits (of 4) from port Y of cell top.$flatten\spi_mux_I.$and$/build/gateware/icE1usb/rtl/sr_btn_if.v:247$3230 ($and). Removed top 3 bits (of 4) from port B of cell top.$flatten\spi_mux_I.$and$/build/gateware/icE1usb/rtl/sr_btn_if.v:229$3223 ($and). Removed top 3 bits (of 4) from port Y of cell top.$flatten\spi_mux_I.$and$/build/gateware/icE1usb/rtl/sr_btn_if.v:229$3223 ($and). Removed top 1 bits (of 3) from port B of cell top.$flatten\spi_mux_I.$eq$/build/gateware/icE1usb/rtl/sr_btn_if.v:229$3222 ($eq). Removed top 28 bits (of 32) from port A of cell top.$flatten\spi_mux_I.$and$/build/gateware/icE1usb/rtl/sr_btn_if.v:216$3219 ($and). Removed top 28 bits (of 32) from port Y of cell top.$flatten\spi_mux_I.$and$/build/gateware/icE1usb/rtl/sr_btn_if.v:216$3219 ($and). Removed top 28 bits (of 32) from port B of cell top.$flatten\spi_mux_I.$and$/build/gateware/icE1usb/rtl/sr_btn_if.v:216$3219 ($and). Removed top 31 bits (of 32) from port B of cell top.$flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:216$3218 ($add). Removed top 28 bits (of 32) from port Y of cell top.$flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:216$3218 ($add). Removed top 2 bits (of 3) from port B of cell top.$flatten\spi_mux_I.$eq$/build/gateware/icE1usb/rtl/sr_btn_if.v:198$3212 ($eq). Removed top 29 bits (of 32) from mux cell top.$flatten\spi_mux_I.$ternary$/build/gateware/icE1usb/rtl/sr_btn_if.v:144$3201 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\sys_mgr_I.$add$/build/gateware/icE1usb/rtl/sysmgr.v:80$1711 ($add). Removed top 28 bits (of 32) from port Y of cell top.$flatten\sys_mgr_I.$add$/build/gateware/icE1usb/rtl/sysmgr.v:80$1711 ($add). Removed top 1 bits (of 4) from port Y of cell top.$flatten\soc_I.\e1_buf_I.$or$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5334 ($or). Removed top 1 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_buf_I.$or$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5334 ($or). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\e1_buf_I.$or$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5334 ($or). Removed top 1 bits (of 6) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:101$201 ($sub). Removed top 1 bits (of 4) from port Y of cell top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5331 ($shl). Removed top 1 bits (of 4) from port Y of cell top.$flatten\soc_I.\e1_buf_I.$and$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5333 ($and). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\e1_buf_I.$and$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5333 ($and). Removed top 1 bits (of 4) from port Y of cell top.$flatten\soc_I.\e1_buf_I.$not$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5332 ($not). Removed top 1 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_buf_I.$not$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5332 ($not). Removed top 1 bits (of 4) from port Y of cell top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5330 ($shl). Removed top 16 bits (of 32) from wire top.$flatten\blinker_I.$add$/build/gateware/icE1usb/rtl/led_blinker.v:57$1585_Y. Removed top 19 bits (of 32) from wire top.$flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5234_Y. Removed top 19 bits (of 32) from wire top.$flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5235_Y. Removed top 27 bits (of 32) from wire top.$flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5238_Y. Removed top 23 bits (of 32) from wire top.$flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4334_Y. Removed top 23 bits (of 32) from wire top.$flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4332_Y. Removed top 27 bits (of 32) from wire top.$flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:133$5202_Y. Removed top 28 bits (of 32) from wire top.$flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:143$5207_Y. Removed top 24 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3498_EN[31:0]$3505. Removed top 16 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3499_DATA[31:0]$3507. Removed top 8 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3500_DATA[31:0]$3510. Removed top 8 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3500_EN[31:0]$3511. Removed top 24 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3498_DATA. Removed top 16 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3499_DATA. Removed top 8 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3500_DATA. Removed top 16 bits (of 32) from wire top.$flatten\soc_I.\cpu_I.$2\mem_rdata_word[31:0]. Removed top 24 bits (of 32) from wire top.$flatten\soc_I.\cpu_I.$3\mem_rdata_word[31:0]. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4202_Y. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4209_Y. Removed top 2 bits (of 6) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\clock_I.$procmux$15950_Y. Removed top 2 bits (of 6) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\clock_I.$procmux$15953_Y. Removed top 2 bits (of 6) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\clock_I.$procmux$15956_Y. Removed top 29 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:208$34_Y. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:220$39_Y. Removed top 28 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:234$44_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:346$113_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:347$117_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:348$121_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:349$125_Y. Removed top 25 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:265$56_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$12_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:54$149_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:62$158_Y. Removed top 3 bits (of 16) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bus_rd_rx_status. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:126$211_Y. Removed top 28 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:191$225_Y. Removed top 28 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:191$227_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$12_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$add$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:120$456_Y. Removed top 3 bits (of 16) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bus_rd_tx_status. Removed top 1 bits (of 4) from wire top.$flatten\soc_I.\e1_buf_I.$and$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5333_Y. Removed top 1 bits (of 4) from wire top.$flatten\soc_I.\e1_buf_I.$not$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5332_Y. Removed top 1 bits (of 4) from wire top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5330_Y. Removed top 1 bits (of 4) from wire top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5331_Y. Removed top 18 bits (of 32) from wire top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$5028_Y. Removed top 23 bits (of 32) from wire top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$5032_Y. Removed top 19 bits (of 32) from wire top.$flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$5042_Y. Removed top 18 bits (of 32) from wire top.$flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:155$5030_Y. Removed top 23 bits (of 32) from wire top.$flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:159$5034_Y. Removed top 20 bits (of 32) from wire top.$flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:176$5043_Y. Removed top 19 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5234_Y. Removed top 19 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5235_Y. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5238_Y. Removed top 23 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4334_Y. Removed top 1 bits (of 13) from wire top.$flatten\soc_I.\uart_I.\uart_tx_I.$0\div_cnt[12:0]. Removed top 1 bits (of 10) from wire top.$flatten\soc_I.\uart_I.\uart_tx_I.$procmux$12438_Y. Removed top 19 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5253_Y. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5256_Y. Removed top 23 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4334_Y. Removed top 23 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4332_Y. Removed top 3 bits (of 4) from wire top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12188_Y. Removed top 28 bits (of 32) from wire top.$flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1334_Y. Removed top 29 bits (of 32) from wire top.$flatten\soc_I.\usb_I.\rx_pkt_I.\crc_5_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4960_Y. Removed top 29 bits (of 32) from wire top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1504_Y. Removed top 29 bits (of 32) from wire top.$flatten\soc_I.\usb_I.\tx_ll_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1506_Y. Removed top 28 bits (of 32) from wire top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1543_Y. Removed top 21 bits (of 32) from wire top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1566_Y. Removed top 1 bits (of 8) from wire top.$flatten\soc_I.\usb_I.\tx_pkt_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:172$1549_Y. Removed top 21 bits (of 32) from wire top.$flatten\soc_I.\usb_I.\tx_pkt_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1565_Y. Removed top 28 bits (of 32) from wire top.$flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:216$3218_Y. Removed top 29 bits (of 32) from wire top.$flatten\spi_mux_I.$ternary$/build/gateware/icE1usb/rtl/sr_btn_if.v:144$3201_Y. Removed top 28 bits (of 32) from wire top.$flatten\sys_mgr_I.$add$/build/gateware/icE1usb/rtl/sysmgr.v:80$1711_Y. Removed top 29 bits (of 32) from wire top.wb_rdata[2]. Removed top 29 bits (of 96) from wire top.wb_rdata_flat. 75.14. Executing PEEPOPT pass (run peephole optimizers). 75.15. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 161 unused wires. 75.16. Executing SHARE pass (SAT-based resource sharing). 75.17. Executing TECHMAP pass (map to technology primitives). 75.17.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/cmp2lut.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 75.17.2. Continuing TECHMAP pass. No more expansions possible. 75.18. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.19. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 3 unused wires. 75.20. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module top: creating $macc model for $flatten\blinker_I.$add$/build/gateware/icE1usb/rtl/led_blinker.v:57$1585 ($add). creating $macc model for $flatten\blinker_I.$add$/build/gateware/icE1usb/rtl/led_blinker.v:66$1589 ($add). creating $macc model for $flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5234 ($sub). creating $macc model for $flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5235 ($sub). creating $macc model for $flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5238 ($sub). creating $macc model for $flatten\gps_uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4387 ($add). creating $macc model for $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4334 ($add). creating $macc model for $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4317 ($add). creating $macc model for $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4332 ($add). creating $macc model for $flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5253 ($sub). creating $macc model for $flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5256 ($sub). creating $macc model for $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4334 ($add). creating $macc model for $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4317 ($add). creating $macc model for $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4332 ($add). creating $macc model for $flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:133$5202 ($add). creating $macc model for $flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:143$5207 ($add). creating $macc model for $flatten\misc_I.\dfu_I.$add$/build/gateware/common/rtl/dfu_helper.v:113$4282 ($add). creating $macc model for $flatten\misc_I.\dfu_I.\btn_flt_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$5177 ($add). creating $macc model for $flatten\misc_I.\pdm_clk_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4272 ($add). creating $macc model for $flatten\misc_I.\pdm_clk_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4273 ($add). creating $macc model for $flatten\misc_I.\pdm_clk_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4272 ($add). creating $macc model for $flatten\misc_I.\pdm_clk_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4273 ($add). creating $macc model for $flatten\misc_I.\pdm_e1_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4268 ($add). creating $macc model for $flatten\misc_I.\pdm_e1_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4268 ($add). creating $macc model for $flatten\misc_I.\pps_flt_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4303 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1210$4258 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1296$4066 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1539$4143 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1548$4144 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1785$4188 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1848$4213 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1210$4257 ($sub). creating $macc model for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4202 ($sub). creating $macc model for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4209 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\clock_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:49$18 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:208$34 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:220$39 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:234$44 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:346$113 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:347$117 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:348$121 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:349$125 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:265$56 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:54$149 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:62$158 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:56$153 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:64$162 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx.v:170$4557 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx.v:171$4558 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:117$209 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:126$211 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:101$201 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:191$225 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$add$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:120$456 ($add). creating $macc model for $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$5028 ($add). creating $macc model for $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$5032 ($add). creating $macc model for $flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$5042 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5234 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5235 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5238 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4387 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4334 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4317 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4332 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5253 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5256 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4334 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4317 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4332 ($add). creating $macc model for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:540$3488 ($add). creating $macc model for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:623$3469 ($add). creating $macc model for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:632$3473 ($add). creating $macc model for $flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1334 ($sub). creating $macc model for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:179$1414 ($add). creating $macc model for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:415$1475 ($add). creating $macc model for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:429$1484 ($add). creating $macc model for $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:258$1431 ($sub). creating $macc model for $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:425$1481 ($sub). creating $macc model for $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1500 ($add). creating $macc model for $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1504 ($add). creating $macc model for $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1543 ($sub). creating $macc model for $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1566 ($sub). creating $macc model for $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:216$3218 ($add). creating $macc model for $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:229$3224 ($add). creating $macc model for $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:246$3228 ($add). creating $macc model for $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:247$3231 ($add). creating $macc model for $flatten\sys_mgr_I.$add$/build/gateware/icE1usb/rtl/sysmgr.v:80$1711 ($add). merging $macc model for $flatten\misc_I.\pdm_clk_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4272 into $flatten\misc_I.\pdm_clk_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4273. merging $macc model for $flatten\misc_I.\pdm_clk_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4272 into $flatten\misc_I.\pdm_clk_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4273. creating $alu model for $macc $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:246$3228. creating $alu model for $macc $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:229$3224. creating $alu model for $macc $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:216$3218. creating $alu model for $macc $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1566. creating $alu model for $macc $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1543. creating $alu model for $macc $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1504. creating $alu model for $macc $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1500. creating $alu model for $macc $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:425$1481. creating $alu model for $macc $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:258$1431. creating $alu model for $macc $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:429$1484. creating $alu model for $macc $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:415$1475. creating $alu model for $macc $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:179$1414. creating $alu model for $macc $flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1334. creating $alu model for $macc $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:632$3473. creating $alu model for $macc $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:623$3469. creating $alu model for $macc $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:540$3488. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4332. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4317. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4334. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5256. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5253. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4332. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4317. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4334. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4387. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5238. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5235. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5234. creating $alu model for $macc $flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$5042. creating $alu model for $macc $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$5032. creating $alu model for $macc $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$5028. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$add$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:120$456. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:191$225. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:101$201. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:126$211. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:117$209. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx.v:171$4558. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx.v:170$4557. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:64$162. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:56$153. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:62$158. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:54$149. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:265$56. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:349$125. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:348$121. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:347$117. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:346$113. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:234$44. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:220$39. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:208$34. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\clock_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:49$18. creating $alu model for $macc $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4209. creating $alu model for $macc $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4202. creating $alu model for $macc $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1210$4257. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1848$4213. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1785$4188. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1548$4144. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1539$4143. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1296$4066. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1210$4258. creating $alu model for $macc $flatten\misc_I.\pps_flt_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4303. creating $alu model for $macc $flatten\misc_I.\pdm_e1_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4268. creating $alu model for $macc $flatten\misc_I.\pdm_e1_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4268. creating $alu model for $macc $flatten\misc_I.\pdm_clk_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4273. creating $alu model for $macc $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:247$3231. creating $alu model for $macc $flatten\misc_I.\pdm_clk_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4273. creating $alu model for $macc $flatten\sys_mgr_I.$add$/build/gateware/icE1usb/rtl/sysmgr.v:80$1711. creating $alu model for $macc $flatten\misc_I.\dfu_I.\btn_flt_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$5177. creating $alu model for $macc $flatten\misc_I.\dfu_I.$add$/build/gateware/common/rtl/dfu_helper.v:113$4282. creating $alu model for $macc $flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:143$5207. creating $alu model for $macc $flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:133$5202. creating $alu model for $macc $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4332. creating $alu model for $macc $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4317. creating $alu model for $macc $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4334. creating $alu model for $macc $flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5256. creating $alu model for $macc $flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5253. creating $alu model for $macc $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4332. creating $alu model for $macc $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4317. creating $alu model for $macc $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4334. creating $alu model for $macc $flatten\gps_uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4387. creating $alu model for $macc $flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5238. creating $alu model for $macc $flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5235. creating $alu model for $macc $flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5234. creating $alu model for $macc $flatten\blinker_I.$add$/build/gateware/icE1usb/rtl/led_blinker.v:66$1589. creating $alu model for $macc $flatten\blinker_I.$add$/build/gateware/icE1usb/rtl/led_blinker.v:57$1585. creating $alu model for $flatten\soc_I.\cpu_I.$ge$/build/gateware/common/rtl/picorv32.v:1814$4194 ($ge): new $alu creating $alu model for $flatten\soc_I.\cpu_I.$lt$/build/gateware/common/rtl/picorv32.v:1212$4261 ($lt): new $alu creating $alu model for $flatten\soc_I.\cpu_I.$lt$/build/gateware/common/rtl/picorv32.v:1213$4262 ($lt): new $alu creating $alu model for $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1211$4260 ($eq): merged with $flatten\soc_I.\cpu_I.$lt$/build/gateware/common/rtl/picorv32.v:1213$4262. creating $alu cell for $flatten\soc_I.\cpu_I.$ge$/build/gateware/common/rtl/picorv32.v:1814$4194: $auto$alumacc.cc:485:replace_alu$24976 creating $alu cell for $flatten\blinker_I.$add$/build/gateware/icE1usb/rtl/led_blinker.v:57$1585: $auto$alumacc.cc:485:replace_alu$24985 creating $alu cell for $flatten\blinker_I.$add$/build/gateware/icE1usb/rtl/led_blinker.v:66$1589: $auto$alumacc.cc:485:replace_alu$24988 creating $alu cell for $flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5234: $auto$alumacc.cc:485:replace_alu$24991 creating $alu cell for $flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5235: $auto$alumacc.cc:485:replace_alu$24994 creating $alu cell for $flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5238: $auto$alumacc.cc:485:replace_alu$24997 creating $alu cell for $flatten\gps_uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4387: $auto$alumacc.cc:485:replace_alu$25000 creating $alu cell for $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4334: $auto$alumacc.cc:485:replace_alu$25003 creating $alu cell for $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4317: $auto$alumacc.cc:485:replace_alu$25006 creating $alu cell for $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4332: $auto$alumacc.cc:485:replace_alu$25009 creating $alu cell for $flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5253: $auto$alumacc.cc:485:replace_alu$25012 creating $alu cell for $flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5256: $auto$alumacc.cc:485:replace_alu$25015 creating $alu cell for $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4334: $auto$alumacc.cc:485:replace_alu$25018 creating $alu cell for $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4317: $auto$alumacc.cc:485:replace_alu$25021 creating $alu cell for $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4332: $auto$alumacc.cc:485:replace_alu$25024 creating $alu cell for $flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:133$5202: $auto$alumacc.cc:485:replace_alu$25027 creating $alu cell for $flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:143$5207: $auto$alumacc.cc:485:replace_alu$25030 creating $alu cell for $flatten\misc_I.\dfu_I.$add$/build/gateware/common/rtl/dfu_helper.v:113$4282: $auto$alumacc.cc:485:replace_alu$25033 creating $alu cell for $flatten\misc_I.\dfu_I.\btn_flt_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$5177: $auto$alumacc.cc:485:replace_alu$25036 creating $alu cell for $flatten\sys_mgr_I.$add$/build/gateware/icE1usb/rtl/sysmgr.v:80$1711: $auto$alumacc.cc:485:replace_alu$25039 creating $alu cell for $flatten\misc_I.\pdm_clk_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4273: $auto$alumacc.cc:485:replace_alu$25042 creating $alu cell for $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:247$3231: $auto$alumacc.cc:485:replace_alu$25045 creating $alu cell for $flatten\misc_I.\pdm_clk_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4273: $auto$alumacc.cc:485:replace_alu$25048 creating $alu cell for $flatten\misc_I.\pdm_e1_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4268: $auto$alumacc.cc:485:replace_alu$25051 creating $alu cell for $flatten\misc_I.\pdm_e1_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4268: $auto$alumacc.cc:485:replace_alu$25054 creating $alu cell for $flatten\misc_I.\pps_flt_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4303: $auto$alumacc.cc:485:replace_alu$25057 creating $alu cell for $flatten\soc_I.\cpu_I.$lt$/build/gateware/common/rtl/picorv32.v:1213$4262, $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1211$4260: $auto$alumacc.cc:485:replace_alu$25060 creating $alu cell for $flatten\soc_I.\cpu_I.$lt$/build/gateware/common/rtl/picorv32.v:1212$4261: $auto$alumacc.cc:485:replace_alu$25071 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1210$4258: $auto$alumacc.cc:485:replace_alu$25084 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1296$4066: $auto$alumacc.cc:485:replace_alu$25087 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1539$4143: $auto$alumacc.cc:485:replace_alu$25090 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1548$4144: $auto$alumacc.cc:485:replace_alu$25093 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1785$4188: $auto$alumacc.cc:485:replace_alu$25096 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1848$4213: $auto$alumacc.cc:485:replace_alu$25099 creating $alu cell for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1210$4257: $auto$alumacc.cc:485:replace_alu$25102 creating $alu cell for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4202: $auto$alumacc.cc:485:replace_alu$25105 creating $alu cell for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4209: $auto$alumacc.cc:485:replace_alu$25108 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\clock_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:49$18: $auto$alumacc.cc:485:replace_alu$25111 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:208$34: $auto$alumacc.cc:485:replace_alu$25114 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:220$39: $auto$alumacc.cc:485:replace_alu$25117 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:234$44: $auto$alumacc.cc:485:replace_alu$25120 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:346$113: $auto$alumacc.cc:485:replace_alu$25123 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:347$117: $auto$alumacc.cc:485:replace_alu$25126 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:348$121: $auto$alumacc.cc:485:replace_alu$25129 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:349$125: $auto$alumacc.cc:485:replace_alu$25132 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:265$56: $auto$alumacc.cc:485:replace_alu$25135 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:54$149: $auto$alumacc.cc:485:replace_alu$25138 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:62$158: $auto$alumacc.cc:485:replace_alu$25141 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:56$153: $auto$alumacc.cc:485:replace_alu$25144 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\filter_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:64$162: $auto$alumacc.cc:485:replace_alu$25147 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx.v:170$4557: $auto$alumacc.cc:485:replace_alu$25150 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx.v:171$4558: $auto$alumacc.cc:485:replace_alu$25153 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:117$209: $auto$alumacc.cc:485:replace_alu$25156 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:126$211: $auto$alumacc.cc:485:replace_alu$25159 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:101$201: $auto$alumacc.cc:485:replace_alu$25162 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:191$225: $auto$alumacc.cc:485:replace_alu$25165 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\hdb3_I.$add$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:120$456: $auto$alumacc.cc:485:replace_alu$25168 creating $alu cell for $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$5028: $auto$alumacc.cc:485:replace_alu$25171 creating $alu cell for $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$5032: $auto$alumacc.cc:485:replace_alu$25174 creating $alu cell for $flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$5042: $auto$alumacc.cc:485:replace_alu$25177 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5234: $auto$alumacc.cc:485:replace_alu$25180 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5235: $auto$alumacc.cc:485:replace_alu$25183 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5238: $auto$alumacc.cc:485:replace_alu$25186 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4387: $auto$alumacc.cc:485:replace_alu$25189 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4334: $auto$alumacc.cc:485:replace_alu$25192 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4317: $auto$alumacc.cc:485:replace_alu$25195 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4332: $auto$alumacc.cc:485:replace_alu$25198 creating $alu cell for $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5253: $auto$alumacc.cc:485:replace_alu$25201 creating $alu cell for $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5256: $auto$alumacc.cc:485:replace_alu$25204 creating $alu cell for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4334: $auto$alumacc.cc:485:replace_alu$25207 creating $alu cell for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4317: $auto$alumacc.cc:485:replace_alu$25210 creating $alu cell for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4332: $auto$alumacc.cc:485:replace_alu$25213 creating $alu cell for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:540$3488: $auto$alumacc.cc:485:replace_alu$25216 creating $alu cell for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:623$3469: $auto$alumacc.cc:485:replace_alu$25219 creating $alu cell for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:632$3473: $auto$alumacc.cc:485:replace_alu$25222 creating $alu cell for $flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1334: $auto$alumacc.cc:485:replace_alu$25225 creating $alu cell for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:179$1414: $auto$alumacc.cc:485:replace_alu$25228 creating $alu cell for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:415$1475: $auto$alumacc.cc:485:replace_alu$25231 creating $alu cell for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:429$1484: $auto$alumacc.cc:485:replace_alu$25234 creating $alu cell for $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:258$1431: $auto$alumacc.cc:485:replace_alu$25237 creating $alu cell for $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:425$1481: $auto$alumacc.cc:485:replace_alu$25240 creating $alu cell for $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1500: $auto$alumacc.cc:485:replace_alu$25243 creating $alu cell for $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1504: $auto$alumacc.cc:485:replace_alu$25246 creating $alu cell for $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1543: $auto$alumacc.cc:485:replace_alu$25249 creating $alu cell for $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1566: $auto$alumacc.cc:485:replace_alu$25252 creating $alu cell for $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:216$3218: $auto$alumacc.cc:485:replace_alu$25255 creating $alu cell for $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:229$3224: $auto$alumacc.cc:485:replace_alu$25258 creating $alu cell for $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:246$3228: $auto$alumacc.cc:485:replace_alu$25261 created 88 $alu and 0 $macc cells. 75.21. Executing OPT pass (performing simple optimizations). 75.21.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.21.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 8 cells. 75.21.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 75.21.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13703: { \soc_I.cpu_I.cpu_state [1] \soc_I.cpu_I.cpu_state [2] $auto$opt_reduce.cc:134:opt_mux$25265 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13914: { \soc_I.cpu_I.cpu_state [2] \soc_I.cpu_I.cpu_state [4] $auto$opt_reduce.cc:134:opt_mux$25267 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$14900: { $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:364$3661_Y $flatten\soc_I.\cpu_I.$procmux$14910_CMP $auto$opt_reduce.cc:134:opt_mux$25269 } Optimizing cells in module \top. Performed a total of 3 changes. 75.21.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 1 cells. 75.21.6. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 1-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 1-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 1-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 1-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 1-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 1-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 1-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 1-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 1-bit at position 8 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 1-bit at position 9 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 1-bit at position 10 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 1-bit at position 11 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 1-bit at position 12 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 1-bit at position 13 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 1-bit at position 14 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 1-bit at position 15 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 1-bit at position 16 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 1-bit at position 17 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 1-bit at position 18 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 1-bit at position 19 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 1-bit at position 20 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 1-bit at position 21 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 1-bit at position 22 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 1-bit at position 23 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 1-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$23415 ($dff) from module top. Setting constant 1-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$23415 ($dff) from module top. Setting constant 1-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$23415 ($dff) from module top. Setting constant 1-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$23415 ($dff) from module top. Setting constant 1-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$23415 ($dff) from module top. Setting constant 1-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$23415 ($dff) from module top. Setting constant 1-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$23415 ($dff) from module top. Setting constant 1-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$23415 ($dff) from module top. Setting constant 1-bit at position 8 on $flatten\soc_I.\bram_I.$procdff$23415 ($dff) from module top. Setting constant 1-bit at position 9 on $flatten\soc_I.\bram_I.$procdff$23415 ($dff) from module top. Setting constant 1-bit at position 10 on $flatten\soc_I.\bram_I.$procdff$23415 ($dff) from module top. Setting constant 1-bit at position 11 on $flatten\soc_I.\bram_I.$procdff$23415 ($dff) from module top. Setting constant 1-bit at position 12 on $flatten\soc_I.\bram_I.$procdff$23415 ($dff) from module top. Setting constant 1-bit at position 13 on $flatten\soc_I.\bram_I.$procdff$23415 ($dff) from module top. Setting constant 1-bit at position 14 on $flatten\soc_I.\bram_I.$procdff$23415 ($dff) from module top. Setting constant 1-bit at position 15 on $flatten\soc_I.\bram_I.$procdff$23415 ($dff) from module top. Setting constant 1-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$23412 ($dff) from module top. Setting constant 1-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$23412 ($dff) from module top. Setting constant 1-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$23412 ($dff) from module top. Setting constant 1-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$23412 ($dff) from module top. Setting constant 1-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$23412 ($dff) from module top. Setting constant 1-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$23412 ($dff) from module top. Setting constant 1-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$23412 ($dff) from module top. Setting constant 1-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$23412 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\i2c_I.$procdff$23466 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\i2c_I.$procdff$23466 ($dff) from module top. Setting constant 0-bit at position 2 on $flatten\i2c_I.$procdff$23466 ($dff) from module top. Setting constant 0-bit at position 3 on $flatten\i2c_I.$procdff$23466 ($dff) from module top. Setting constant 0-bit at position 4 on $flatten\i2c_I.$procdff$23466 ($dff) from module top. Setting constant 0-bit at position 5 on $flatten\i2c_I.$procdff$23466 ($dff) from module top. Setting constant 0-bit at position 6 on $flatten\i2c_I.$procdff$23466 ($dff) from module top. Setting constant 0-bit at position 7 on $flatten\i2c_I.$procdff$23466 ($dff) from module top. Setting constant 0-bit at position 8 on $flatten\i2c_I.$procdff$23466 ($dff) from module top. Setting constant 0-bit at position 9 on $flatten\i2c_I.$procdff$23466 ($dff) from module top. Setting constant 0-bit at position 10 on $flatten\i2c_I.$procdff$23466 ($dff) from module top. Setting constant 0-bit at position 11 on $flatten\i2c_I.$procdff$23466 ($dff) from module top. Setting constant 0-bit at position 12 on $flatten\i2c_I.$procdff$23466 ($dff) from module top. Setting constant 0-bit at position 13 on $flatten\i2c_I.$procdff$23466 ($dff) from module top. Setting constant 0-bit at position 14 on $flatten\i2c_I.$procdff$23466 ($dff) from module top. Setting constant 0-bit at position 15 on $flatten\i2c_I.$procdff$23466 ($dff) from module top. Setting constant 0-bit at position 16 on $flatten\i2c_I.$procdff$23466 ($dff) from module top. Setting constant 0-bit at position 17 on $flatten\i2c_I.$procdff$23466 ($dff) from module top. Setting constant 0-bit at position 18 on $flatten\i2c_I.$procdff$23466 ($dff) from module top. Setting constant 0-bit at position 19 on $flatten\i2c_I.$procdff$23466 ($dff) from module top. Setting constant 0-bit at position 20 on $flatten\i2c_I.$procdff$23466 ($dff) from module top. Setting constant 1-bit at position 9 on $auto$opt_dff.cc:764:run$24868 ($adffe) from module top. Adding SRST signal on $auto$opt_dff.cc:764:run$24571 ($dffe) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14953_Y, Q = \soc_I.cpu_I.mem_valid, rval = 1'0). Adding SRST signal on $auto$opt_dff.cc:764:run$24554 ($dffe) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14900_Y, Q = \soc_I.cpu_I.mem_state, rval = 2'00). Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$24891 ($sdff) from module top. Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$24891 ($sdff) from module top. Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$24891 ($sdff) from module top. Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$24891 ($sdff) from module top. Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$24891 ($sdff) from module top. Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$24891 ($sdff) from module top. Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$24891 ($sdff) from module top. Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$24891 ($sdff) from module top. Setting constant 0-bit at position 16 on $auto$opt_dff.cc:702:run$24891 ($sdff) from module top. Setting constant 0-bit at position 17 on $auto$opt_dff.cc:702:run$24891 ($sdff) from module top. Setting constant 0-bit at position 18 on $auto$opt_dff.cc:702:run$24891 ($sdff) from module top. Setting constant 0-bit at position 19 on $auto$opt_dff.cc:702:run$24891 ($sdff) from module top. Setting constant 0-bit at position 20 on $auto$opt_dff.cc:702:run$24891 ($sdff) from module top. Setting constant 0-bit at position 21 on $auto$opt_dff.cc:702:run$24891 ($sdff) from module top. Setting constant 0-bit at position 22 on $auto$opt_dff.cc:702:run$24891 ($sdff) from module top. Setting constant 0-bit at position 23 on $auto$opt_dff.cc:702:run$24891 ($sdff) from module top. Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$24314 ($sdff) from module top. Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$24314 ($sdff) from module top. Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$24314 ($sdff) from module top. Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$24314 ($sdff) from module top. Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$24314 ($sdff) from module top. Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$24314 ($sdff) from module top. Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$24314 ($sdff) from module top. Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$24314 ($sdff) from module top. Setting constant 0-bit at position 16 on $auto$opt_dff.cc:702:run$24314 ($sdff) from module top. Setting constant 0-bit at position 17 on $auto$opt_dff.cc:702:run$24314 ($sdff) from module top. Setting constant 0-bit at position 18 on $auto$opt_dff.cc:702:run$24314 ($sdff) from module top. Setting constant 0-bit at position 19 on $auto$opt_dff.cc:702:run$24314 ($sdff) from module top. Setting constant 0-bit at position 20 on $auto$opt_dff.cc:702:run$24314 ($sdff) from module top. Setting constant 0-bit at position 21 on $auto$opt_dff.cc:702:run$24314 ($sdff) from module top. Setting constant 0-bit at position 22 on $auto$opt_dff.cc:702:run$24314 ($sdff) from module top. Setting constant 0-bit at position 23 on $auto$opt_dff.cc:702:run$24314 ($sdff) from module top. 75.21.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 4 unused cells and 17 unused wires. 75.21.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.21.9. Rerunning OPT passes. (Maybe there is more to do..) 75.21.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 75.21.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 75.21.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.21.13. Executing OPT_DFF pass (perform DFF optimizations). 75.21.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.21.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.21.16. Finished OPT passes. (There is nothing left to do.) 75.22. Executing MEMORY pass. 75.22.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 75.22.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). Checking cell `$flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5457' in module `\top': merged $dff to cell. Checking cell `$flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5457' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3525' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3526' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3527' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3528' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5457' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5457' in module `\top': merged $dff to cell. Checking cell `$flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5456' in module `\top': merged data $dff to cell. Checking cell `$flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5456' in module `\top': merged data $dff to cell. Checking cell `$flatten\soc_I.\bram_I.$memrd$\mem$/build/gateware/common/rtl/soc_bram.v:32$3515' in module `\top': merged data $dff to cell. Checking cell `$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5456' in module `\top': merged data $dff to cell. Checking cell `$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5456' in module `\top': merged data $dff to cell. 75.22.3. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 25 unused cells and 30 unused wires. 75.22.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). Consolidating write ports of memory top.soc_I.bram_I.mem by address: New clock domain: posedge \blinker_I.clk Port 0 ($flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3525) has addr \soc_I.cpu_I.mem_addr [9:2]. Active bits: 00000000000000000000000011111111 Port 1 ($flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3526) has addr \soc_I.cpu_I.mem_addr [9:2]. Active bits: 00000000000000001111111100000000 Merging port 0 into this one. Active bits: 00000000000000001111111111111111 Port 2 ($flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3527) has addr \soc_I.cpu_I.mem_addr [9:2]. Active bits: 00000000111111110000000000000000 Merging port 1 into this one. Active bits: 00000000111111111111111111111111 Port 3 ($flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3528) has addr \soc_I.cpu_I.mem_addr [9:2]. Active bits: 11111111000000000000000000000000 Merging port 2 into this one. Active bits: 11111111111111111111111111111111 75.22.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.22.6. Executing MEMORY_COLLECT pass (generating $mem cells). Collecting $memrd, $memwr and $meminit for memory `\gps_uart_I.uart_rx_fifo_I.ram_I.ram' in module `\top': $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5457 ($memwr) $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5456 ($memrd) Collecting $memrd, $memwr and $meminit for memory `\gps_uart_I.uart_tx_fifo_I.ram_I.ram' in module `\top': $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5457 ($memwr) $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5456 ($memrd) Collecting $memrd, $memwr and $meminit for memory `\soc_I.bram_I.mem' in module `\top': $flatten\soc_I.\bram_I.$meminit$\mem$/build/gateware/common/rtl/soc_bram.v:0$3524 ($meminit) $flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3528 ($memwr) $flatten\soc_I.\bram_I.$memrd$\mem$/build/gateware/common/rtl/soc_bram.v:32$3515 ($memrd) Collecting $memrd, $memwr and $meminit for memory `\soc_I.uart_I.uart_rx_fifo_I.ram_I.ram' in module `\top': $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5457 ($memwr) $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5456 ($memrd) Collecting $memrd, $memwr and $meminit for memory `\soc_I.uart_I.uart_tx_fifo_I.ram_I.ram' in module `\top': $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5457 ($memwr) $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5456 ($memrd) 75.23. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.24. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). Processing top.gps_uart_I.uart_rx_fifo_I.ram_I.ram: Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512 Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #2 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=0 efficiency=100 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 2): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=3072 efficiency=25 Storing for later selection. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'max wports 0' not met. Selecting best of 4 rules: Efficiency for rule 4.3: efficiency=25, cells=4, acells=1 Efficiency for rule 4.2: efficiency=50, cells=2, acells=1 Efficiency for rule 4.1: efficiency=100, cells=1, acells=1 Efficiency for rule 1.1: efficiency=50, cells=2, acells=2 Selected rule 4.1 with efficiency 100. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Creating $__ICE40_RAM4K_M123 cell at grid position <0 0 0>: gps_uart_I.uart_rx_fifo_I.ram_I.ram.0.0.0 Processing top.gps_uart_I.uart_tx_fifo_I.ram_I.ram: Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512 Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #2 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=0 efficiency=100 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 2): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=3072 efficiency=25 Storing for later selection. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'max wports 0' not met. Selecting best of 4 rules: Efficiency for rule 4.3: efficiency=25, cells=4, acells=1 Efficiency for rule 4.2: efficiency=50, cells=2, acells=1 Efficiency for rule 4.1: efficiency=100, cells=1, acells=1 Efficiency for rule 1.1: efficiency=50, cells=2, acells=2 Selected rule 4.1 with efficiency 100. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Creating $__ICE40_RAM4K_M123 cell at grid position <0 0 0>: gps_uart_I.uart_tx_fifo_I.ram_I.ram.0.0.0 Processing top.soc_I.bram_I.mem: Properties: ports=2 bits=8192 rports=1 wports=1 dbits=32 abits=8 words=256 Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=0 efficiency=100 Storing for later selection. Checking rule #2 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=256 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=768 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 2): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=3072 efficiency=25 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1792 dwaste=0 bwaste=3584 waste=3584 efficiency=12 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=3584 efficiency=12 Storing for later selection. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=256 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=768 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1792 dwaste=0 bwaste=3584 waste=3584 efficiency=12 Rule for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=256 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=768 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1792 dwaste=0 bwaste=3584 waste=3584 efficiency=12 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'max wports 0' not met. Selecting best of 4 rules: Efficiency for rule 4.3: efficiency=12, cells=16, acells=1 Efficiency for rule 4.2: efficiency=25, cells=8, acells=1 Efficiency for rule 4.1: efficiency=50, cells=4, acells=1 Efficiency for rule 1.1: efficiency=100, cells=2, acells=1 Selected rule 1.1 with efficiency 100. Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Creating $__ICE40_RAM4K_M0 cell at grid position <0 0 0>: soc_I.bram_I.mem.0.0.0 Creating $__ICE40_RAM4K_M0 cell at grid position <1 0 0>: soc_I.bram_I.mem.1.0.0 Processing top.soc_I.uart_I.uart_rx_fifo_I.ram_I.ram: Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512 Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #2 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=0 efficiency=100 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 2): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=3072 efficiency=25 Storing for later selection. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'max wports 0' not met. Selecting best of 4 rules: Efficiency for rule 4.3: efficiency=25, cells=4, acells=1 Efficiency for rule 4.2: efficiency=50, cells=2, acells=1 Efficiency for rule 4.1: efficiency=100, cells=1, acells=1 Efficiency for rule 1.1: efficiency=50, cells=2, acells=2 Selected rule 4.1 with efficiency 100. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Creating $__ICE40_RAM4K_M123 cell at grid position <0 0 0>: soc_I.uart_I.uart_rx_fifo_I.ram_I.ram.0.0.0 Processing top.soc_I.uart_I.uart_tx_fifo_I.ram_I.ram: Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512 Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #2 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=0 efficiency=100 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 2): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=3072 efficiency=25 Storing for later selection. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'max wports 0' not met. Selecting best of 4 rules: Efficiency for rule 4.3: efficiency=25, cells=4, acells=1 Efficiency for rule 4.2: efficiency=50, cells=2, acells=1 Efficiency for rule 4.1: efficiency=100, cells=1, acells=1 Efficiency for rule 1.1: efficiency=50, cells=2, acells=2 Selected rule 4.1 with efficiency 100. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Creating $__ICE40_RAM4K_M123 cell at grid position <0 0 0>: soc_I.uart_I.uart_tx_fifo_I.ram_I.ram.0.0.0 75.25. Executing TECHMAP pass (map to technology primitives). 75.25.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/brams_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ICE40_RAM4K'. Generating RTLIL representation for module `\$__ICE40_RAM4K_M0'. Generating RTLIL representation for module `\$__ICE40_RAM4K_M123'. Successfully finished Verilog frontend. 75.25.2. Continuing TECHMAP pass. Using template $paramod\$__ICE40_RAM4K_M123\CFG_ABITS=9\CFG_DBITS=8\CLKPOL2=1\CLKPOL3=1 for cells of type $__ICE40_RAM4K_M123. Using template $paramod$b9e8582c288289ac723b215129f56c6fb55d152a\$__ICE40_RAM4K_M0 for cells of type $__ICE40_RAM4K_M0. Using template $paramod$4db28c01ad2f8fb3d28d8b45acd344e29c76a5e2\$__ICE40_RAM4K_M0 for cells of type $__ICE40_RAM4K_M0. Using template $paramod$604ec1e346c2dd44ad2f04f633da753d2abbf02c\$__ICE40_RAM4K for cells of type $__ICE40_RAM4K. Using template $paramod$66c3fa288a62dc560ce3ddd26d81551ab195105f\$__ICE40_RAM4K for cells of type $__ICE40_RAM4K. Using template $paramod$7577afd8fd444532bbc3532c110d9d682708035f\$__ICE40_RAM4K for cells of type $__ICE40_RAM4K. No more expansions possible. 75.26. Executing ICE40_BRAMINIT pass. Processing soc_I.usb_I.trans_I.mc_rom_I : usb_trans_mc.hex 75.27. Executing OPT pass (performing simple optimizations). 75.27.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.27.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.27.3. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23258 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$0\reg_sh[4:0] [1:0], Q = \soc_I.cpu_I.reg_sh [1:0]). 75.27.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 39 unused cells and 264 unused wires. 75.27.5. Rerunning OPT passes. (Removed registers in this run.) 75.27.6. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.27.7. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.27.8. Executing OPT_DFF pass (perform DFF optimizations). 75.27.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.27.10. Finished fast OPT passes. 75.28. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). 75.29. Executing OPT pass (performing simple optimizations). 75.29.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.29.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.29.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 75.29.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $techmap$techmap25300\soc_I.bram_I.mem.0.0.0.$reduce_or$/opt/fpga-toolchain/bin/../share/yosys/ice40/brams_map.v:222$25299: { $auto$wreduce.cc:454:run$24901 [7] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3499_EN[31:0]$3508 [15] } New input vector for $reduce_or cell $techmap$techmap25297\soc_I.bram_I.mem.1.0.0.$reduce_or$/opt/fpga-toolchain/bin/../share/yosys/ice40/brams_map.v:222$25296: { $auto$wreduce.cc:454:run$24904 [23] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3501_EN[31:0]$3514 [31] } Consolidated identical input bits for $mux cell $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1586: Old ports: A=16'1111111111111111, B=16'0000000000000000, Y=$flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1586_Y New ports: A=1'1, B=1'0, Y=$flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1586_Y [0] New connections: $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1586_Y [15:1] = { $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1586_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1586_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1586_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1586_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1586_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1586_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1586_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1586_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1586_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1586_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1586_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1586_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1586_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1586_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1586_Y [0] } Consolidated identical input bits for $mux cell $flatten\gps_uart_I.\uart_rx_I.\gf_I.$procmux$12286: Old ports: A=2'00, B=2'11, Y=$flatten\gps_uart_I.\uart_rx_I.\gf_I.$2\cnt_move[1:0] New ports: A=1'0, B=1'1, Y=$flatten\gps_uart_I.\uart_rx_I.\gf_I.$2\cnt_move[1:0] [0] New connections: $flatten\gps_uart_I.\uart_rx_I.\gf_I.$2\cnt_move[1:0] [1] = $flatten\gps_uart_I.\uart_rx_I.\gf_I.$2\cnt_move[1:0] [0] Consolidated identical input bits for $mux cell $flatten\i2c_I.\core_I.$procmux$15372: Old ports: A=4'1000, B=4'0000, Y=$flatten\i2c_I.\core_I.$procmux$15372_Y New ports: A=1'1, B=1'0, Y=$flatten\i2c_I.\core_I.$procmux$15372_Y [3] New connections: $flatten\i2c_I.\core_I.$procmux$15372_Y [2:0] = 3'000 Consolidated identical input bits for $mux cell $flatten\misc_I.\dfu_I.\btn_flt_I.$procmux$5631: Old ports: A=4'0000, B=4'1111, Y=$flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] New ports: A=1'0, B=1'1, Y=$flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] New connections: $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [3:1] = { $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] } Consolidated identical input bits for $mux cell $flatten\misc_I.\pps_flt_I.$procmux$12476: Old ports: A=2'00, B=2'11, Y=$flatten\misc_I.\pps_flt_I.$2\cnt_move[1:0] New ports: A=1'0, B=1'1, Y=$flatten\misc_I.\pps_flt_I.$2\cnt_move[1:0] [0] New connections: $flatten\misc_I.\pps_flt_I.$2\cnt_move[1:0] [1] = $flatten\misc_I.\pps_flt_I.$2\cnt_move[1:0] [0] Consolidated identical input bits for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13176: Old ports: A=\soc_I.cpu_I.mem_rdata_word, B={ \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15:0] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7:0] }, Y=$flatten\soc_I.\cpu_I.$procmux$13176_Y New ports: A=\soc_I.cpu_I.mem_rdata_word [31:8], B={ \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15:7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] }, Y=$flatten\soc_I.\cpu_I.$procmux$13176_Y [31:8] New connections: $flatten\soc_I.\cpu_I.$procmux$13176_Y [7:0] = \soc_I.cpu_I.mem_rdata_word [7:0] Consolidated identical input bits for $pmux cell $flatten\soc_I.\cpu_I.$procmux$15219: Old ports: A=\soc_I.cpu_I.reg_op2, B={ \soc_I.cpu_I.reg_op2 [15:0] \soc_I.cpu_I.reg_op2 [15:0] \soc_I.cpu_I.reg_op2 [7:0] \soc_I.cpu_I.reg_op2 [7:0] \soc_I.cpu_I.reg_op2 [7:0] \soc_I.cpu_I.reg_op2 [7:0] }, Y=\soc_I.cpu_I.mem_la_wdata New ports: A=\soc_I.cpu_I.reg_op2 [31:8], B={ \soc_I.cpu_I.reg_op2 [15:0] \soc_I.cpu_I.reg_op2 [15:0] \soc_I.cpu_I.reg_op2 [7:0] \soc_I.cpu_I.reg_op2 [7:0] }, Y=\soc_I.cpu_I.mem_la_wdata [31:8] New connections: \soc_I.cpu_I.mem_la_wdata [7:0] = \soc_I.cpu_I.reg_op2 [7:0] Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1192$4034: Old ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 2'00 }, B={ \soc_I.cpu_I.reg_out [31:1] 1'0 }, Y=\soc_I.cpu_I.next_pc New ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 1'0 }, B=\soc_I.cpu_I.reg_out [31:1], Y=\soc_I.cpu_I.next_pc [31:1] New connections: \soc_I.cpu_I.next_pc [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$4103: Old ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 2'00 }, B={ $auto$opt_expr.cc:205:group_cell_inputs$25368 1'0 }, Y=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$4103_Y New ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 1'0 }, B=$auto$opt_expr.cc:205:group_cell_inputs$25368, Y=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$4103_Y [31:1] New connections: $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$4103_Y [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1621$4156: Old ports: A={ \soc_I.cpu_I.reg_pc [31:2] 2'00 }, B=0, Y=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1621$4156_Y New ports: A=\soc_I.cpu_I.reg_pc [31:2], B=30'000000000000000000000000000000, Y=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1621$4156_Y [31:2] New connections: $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1621$4156_Y [1:0] = 2'00 Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:366$3677: Old ports: A={ \soc_I.cpu_I.reg_op1 [31:2] 2'00 }, B={ \soc_I.cpu_I.next_pc [31:2] 2'00 }, Y=\soc_I.cpu_I.mem_la_addr New ports: A=\soc_I.cpu_I.reg_op1 [31:2], B=\soc_I.cpu_I.next_pc [31:2], Y=\soc_I.cpu_I.mem_la_addr [31:2] New connections: \soc_I.cpu_I.mem_la_addr [1:0] = 2'00 Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3692: Old ports: A=4'0011, B=4'1100, Y=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3692_Y New ports: A=2'01, B=2'10, Y={ $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3692_Y [2] $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3692_Y [0] } New connections: { $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3692_Y [3] $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3692_Y [1] } = { $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3692_Y [2] $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3692_Y [0] } Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:601$3752: Old ports: A=2'11, B=2'00, Y=$flatten\soc_I.\cpu_I.$procmux$14906_Y New ports: A=1'1, B=1'0, Y=$flatten\soc_I.\cpu_I.$procmux$14906_Y [0] New connections: $flatten\soc_I.\cpu_I.$procmux$14906_Y [1] = $flatten\soc_I.\cpu_I.$procmux$14906_Y [0] Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$4621: Old ports: A={ 3'000 $auto$wreduce.cc:454:run$24926 [12] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_out_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_out_I.rd_empty $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_in_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_in_I.rd_empty 6'000000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.aligned $auto$wreduce.cc:454:run$24926 [0] }, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_out_I.stage[1].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_out_I.data[1] [8:7] 6'000000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_out_I.data[1] [6:0] }, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$4621_Y New ports: A={ 3'000 $auto$wreduce.cc:454:run$24926 [12] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_out_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_out_I.rd_empty $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_in_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_in_I.rd_empty 5'00000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.aligned $auto$wreduce.cc:454:run$24926 [0] }, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_out_I.stage[1].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_out_I.data[1] [8:7] 5'00000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_out_I.data[1] [6:0] }, Y={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$4621_Y [15:8] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$4621_Y [6:0] } New connections: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$4621_Y [7] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.\rx_I.\deframer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$12: Old ports: A=2'00, B=2'11, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [1:0] New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [0] New connections: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [1] = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [0] Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4581: Old ports: A={ 3'000 $auto$wreduce.cc:454:run$24932 [12] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_out_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_out_I.rd_empty $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_in_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_in_I.rd_empty 7'0000000 $auto$wreduce.cc:454:run$24932 [0] }, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_out_I.stage[1].l_valid 8'00000000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_out_I.data[1] }, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4581_Y New ports: A={ 1'0 $auto$wreduce.cc:454:run$24932 [12] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_out_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_out_I.rd_empty $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_in_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_in_I.rd_empty 6'000000 $auto$wreduce.cc:454:run$24932 [0] }, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_out_I.stage[1].l_valid 5'00000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_out_I.data[1] }, Y={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4581_Y [15] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4581_Y [12:8] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4581_Y [6:0] } New connections: { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4581_Y [14:13] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4581_Y [7] } = 3'000 Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:167$4555: Old ports: A=5'00000, B=5'11001, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:167$4555_Y New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:167$4555_Y [0] New connections: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:167$4555_Y [4:1] = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:167$4555_Y [0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:167$4555_Y [0] 2'00 } Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:168$4556: Old ports: A=5'00000, B=5'11001, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:168$4556_Y New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:168$4556_Y [0] New connections: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:168$4556_Y [4:1] = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:168$4556_Y [0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:168$4556_Y [0] 2'00 } Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procmux$15720: Old ports: A=8'00011011, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$shiftx$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:0$222_Y 1'1 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.alarm 5'11111 }, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procmux$15720_Y New ports: A=3'000, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$shiftx$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:0$222_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.alarm 1'1 }, Y={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procmux$15720_Y [7] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procmux$15720_Y [5] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procmux$15720_Y [2] } New connections: { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procmux$15720_Y [6] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procmux$15720_Y [4:3] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procmux$15720_Y [1:0] } = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procmux$15720_Y [2] 4'1111 } Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$12: Old ports: A=2'00, B=2'11, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.framer_I.crc_I.state_upd_mux [1:0] New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.framer_I.crc_I.state_upd_mux [0] New connections: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.framer_I.crc_I.state_upd_mux [1] = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.framer_I.crc_I.state_upd_mux [0] Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_buf_I.$procmux$12431: Old ports: A=2'00, B=2'10, Y=\soc_I.e1_buf_I.t_nxt_chan New ports: A=1'0, B=1'1, Y=\soc_I.e1_buf_I.t_nxt_chan [1] New connections: \soc_I.e1_buf_I.t_nxt_chan [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:115$5010: Old ports: A=2'10, B=2'00, Y=$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5696_Y New ports: A=1'1, B=1'0, Y=$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5696_Y [1] New connections: $flatten\soc_I.\iobuf_I.\dma_I.$procmux$5696_Y [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:205$5060: Old ports: A=16'0000000000000000, B={ \soc_I.iobuf_I.dma_I.state [1] \soc_I.iobuf_I.dma_I.dir 1'0 \soc_I.iobuf_I.dma_I.len }, Y=\soc_I.iobuf_I.wb_rdata_dma [15:0] New ports: A=15'000000000000000, B={ \soc_I.iobuf_I.dma_I.state [1] \soc_I.iobuf_I.dma_I.dir \soc_I.iobuf_I.dma_I.len }, Y={ \soc_I.iobuf_I.wb_rdata_dma [15:14] \soc_I.iobuf_I.wb_rdata_dma [12:0] } New connections: \soc_I.iobuf_I.wb_rdata_dma [13] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$5128: Old ports: A=0, B={ \soc_I.e1_buf_I.wb_wdata_byte \soc_I.e1_buf_I.wb_wdata_byte \soc_I.e1_buf_I.wb_wdata_byte \soc_I.e1_buf_I.wb_wdata_byte }, Y=$flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$5128_Y New ports: A=8'00000000, B=\soc_I.e1_buf_I.wb_wdata_byte, Y=$flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$5128_Y [7:0] New connections: $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$5128_Y [31:8] = { $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$5128_Y [7:0] $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$5128_Y [7:0] $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$5128_Y [7:0] } Consolidated identical input bits for $mux cell $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procmux$12286: Old ports: A=2'00, B=2'11, Y=$flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$2\cnt_move[1:0] New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$2\cnt_move[1:0] [0] New connections: $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$2\cnt_move[1:0] [1] = $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$2\cnt_move[1:0] [0] Consolidated identical input bits for $mux cell $flatten\soc_I.\uart_I.\uart_tx_I.$procmux$12441: Old ports: A={ 1'1 \soc_I.uart_I.uart_tx_I.shift [9:1] }, B={ 1'1 \soc_I.uart_I.uart_tx_fifo_I.ram_I.rd_data 1'0 }, Y=$flatten\soc_I.\uart_I.\uart_tx_I.$0\shift[9:0] New ports: A=\soc_I.uart_I.uart_tx_I.shift [9:1], B={ \soc_I.uart_I.uart_tx_fifo_I.ram_I.rd_data 1'0 }, Y=$flatten\soc_I.\uart_I.\uart_tx_I.$0\shift[9:0] [8:0] New connections: $flatten\soc_I.\uart_I.\uart_tx_I.$0\shift[9:0] [9] = 1'1 Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\rx_pkt_I.\crc_16_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4947: Old ports: A=16'0000000000000000, B=16'1000000000000101, Y=\soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux New ports: A=1'0, B=1'1, Y=\soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux [0] New connections: \soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux [15:1] = { \soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux [0] 12'000000000000 \soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\rx_pkt_I.\crc_5_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4960: Old ports: A=3'000, B=3'101, Y=\soc_I.usb_I.rx_pkt_I.crc_5_I.state_upd_mux [2:0] New ports: A=1'0, B=1'1, Y=\soc_I.usb_I.rx_pkt_I.crc_5_I.state_upd_mux [0] New connections: \soc_I.usb_I.rx_pkt_I.crc_5_I.state_upd_mux [2:1] = { \soc_I.usb_I.rx_pkt_I.crc_5_I.state_upd_mux [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$procmux$11887: Old ports: A=3'000, B=3'110, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11887_Y [2:0] New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11887_Y [1] New connections: { $flatten\soc_I.\usb_I.\trans_I.$procmux$11887_Y [2] $flatten\soc_I.\usb_I.\trans_I.$procmux$11887_Y [0] } = { $flatten\soc_I.\usb_I.\trans_I.$procmux$11887_Y [1] 1'0 } Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$procmux$11890: Old ports: A={ 1'0 $flatten\soc_I.\usb_I.\trans_I.$procmux$11887_Y [2:0] }, B=4'0100, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11890_Y New ports: A=$flatten\soc_I.\usb_I.\trans_I.$procmux$11887_Y [2:0], B=3'100, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11890_Y [2:0] New connections: $flatten\soc_I.\usb_I.\trans_I.$procmux$11890_Y [3] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_trans.v:340$1445: Old ports: A={ 8'00000000 \soc_I.usb_I.trans_I.ep_data_toggle \soc_I.usb_I.trans_I.ep_bd_idx_nxt \soc_I.usb_I.trans_I.ep_bd_ctrl \soc_I.usb_I.trans_I.ep_bd_dual 1'0 \soc_I.usb_I.trans_I.ep_type }, B={ \soc_I.usb_I.trans_I.bd_state \soc_I.usb_I.trans_I.trans_is_setup 2'00 \soc_I.usb_I.trans_I.xfer_length }, Y=\soc_I.usb_I.ep_status_I.p_din_0 New ports: A={ 6'000000 \soc_I.usb_I.trans_I.ep_data_toggle \soc_I.usb_I.trans_I.ep_bd_idx_nxt \soc_I.usb_I.trans_I.ep_bd_ctrl \soc_I.usb_I.trans_I.ep_bd_dual 1'0 \soc_I.usb_I.trans_I.ep_type }, B={ \soc_I.usb_I.trans_I.bd_state \soc_I.usb_I.trans_I.trans_is_setup \soc_I.usb_I.trans_I.xfer_length }, Y={ \soc_I.usb_I.ep_status_I.p_din_0 [15:12] \soc_I.usb_I.ep_status_I.p_din_0 [9:0] } New connections: \soc_I.usb_I.ep_status_I.p_din_0 [11:10] = 2'00 Consolidated identical input bits for $pmux cell $flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11838: Old ports: A=3'000, B=6'110111, Y=$flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11838_Y New ports: A=2'00, B=4'1011, Y=$flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11838_Y [1:0] New connections: $flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11838_Y [2] = $flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11838_Y [1] Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\tx_pkt_I.\crc_16_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4947: Old ports: A=16'0000000000000000, B=16'1000000000000101, Y=\soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux New ports: A=1'0, B=1'1, Y=\soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux [0] New connections: \soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux [15:1] = { \soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux [0] 12'000000000000 \soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\spi_mux_I.$ternary$/build/gateware/icE1usb/rtl/sr_btn_if.v:144$3201: Old ports: A=3'010, B=3'100, Y=$auto$wreduce.cc:454:run$24963 [2:0] New ports: A=2'01, B=2'10, Y=$auto$wreduce.cc:454:run$24963 [2:1] New connections: $auto$wreduce.cc:454:run$24963 [0] = 1'0 Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\misc_I.\dfu_I.\btn_flt_I.$procmux$5637: Old ports: A=$flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0], B=4'0001, Y=\misc_I.dfu_I.btn_flt_I.cnt_move New ports: A={ $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] }, B=2'01, Y=\misc_I.dfu_I.btn_flt_I.cnt_move [1:0] New connections: \misc_I.dfu_I.btn_flt_I.cnt_move [3:2] = { \misc_I.dfu_I.btn_flt_I.cnt_move [1] \misc_I.dfu_I.btn_flt_I.cnt_move [1] } Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$procmux$12910: Old ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 2'00 }, B=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$4103_Y, Y={ $flatten\soc_I.\cpu_I.$3\current_pc[31:0] [31:2] $auto$alumacc.cc:501:replace_alu$25091 [1:0] } New ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 1'0 }, B=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$4103_Y [31:1], Y={ $flatten\soc_I.\cpu_I.$3\current_pc[31:0] [31:2] $auto$alumacc.cc:501:replace_alu$25091 [1] } New connections: $auto$alumacc.cc:501:replace_alu$25091 [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$4622: Old ports: A=16'0000000000000000, B=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$4621_Y, Y=\soc_I.e1_I.bus_rdata_rx[0] New ports: A=15'000000000000000, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$4621_Y [15:8] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$4621_Y [6:0] }, Y={ \soc_I.e1_I.bus_rdata_rx[0] [15:8] \soc_I.e1_I.bus_rdata_rx[0] [6:0] } New connections: \soc_I.e1_I.bus_rdata_rx[0] [7] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4582: Old ports: A=16'0000000000000000, B=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4581_Y, Y=\soc_I.e1_I.bus_rdata_tx[0] New ports: A=13'0000000000000, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4581_Y [15] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4581_Y [12:8] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4581_Y [6:0] }, Y={ \soc_I.e1_I.bus_rdata_tx[0] [15] \soc_I.e1_I.bus_rdata_tx[0] [12:8] \soc_I.e1_I.bus_rdata_tx[0] [6:0] } New connections: { \soc_I.e1_I.bus_rdata_tx[0] [14:13] \soc_I.e1_I.bus_rdata_tx[0] [7] } = 3'000 Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$procmux$11890: Old ports: A=$flatten\soc_I.\usb_I.\trans_I.$procmux$11887_Y [2:0], B=3'100, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11890_Y [2:0] New ports: A={ $flatten\soc_I.\usb_I.\trans_I.$procmux$11887_Y [1] $flatten\soc_I.\usb_I.\trans_I.$procmux$11887_Y [1] }, B=2'10, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11890_Y [2:1] New connections: $flatten\soc_I.\usb_I.\trans_I.$procmux$11890_Y [0] = 1'0 Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$procmux$11893: Old ports: A=$flatten\soc_I.\usb_I.\trans_I.$procmux$11890_Y, B=4'1000, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11893_Y New ports: A={ 1'0 $flatten\soc_I.\usb_I.\trans_I.$procmux$11890_Y [2:1] }, B=3'100, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11893_Y [3:1] New connections: $flatten\soc_I.\usb_I.\trans_I.$procmux$11893_Y [0] = 1'0 Optimizing cells in module \top. Performed a total of 42 changes. 75.29.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.29.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$23167 ($dff) from module top (D = \soc_I.cpu_I.mem_wdata [11:10], Q = \soc_I.usb_I.ep_status_I.din_1 [11:10], rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procdff$23500 ($dff) from module top (D = { \soc_I.e1_buf_I.tx_data_reg[0] [4:3] \soc_I.e1_buf_I.tx_data_reg[0] [1:0] }, Q = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.framer_I.shift_data_nxt [4:3] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.framer_I.shift_data_nxt [1:0] }, rval = 4'1111). Adding SRST signal on $auto$opt_dff.cc:702:run$24394 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx.v:170$4557_Y [2:1], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.pg_hi [2:1], rval = 2'00). Adding SRST signal on $auto$opt_dff.cc:702:run$24393 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx.v:171$4558_Y [2:1], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.pg_lo [2:1], rval = 2'00). 75.29.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.29.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.29.9. Rerunning OPT passes. (Maybe there is more to do..) 75.29.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 1/2 on $mux $flatten\soc_I.\e1_buf_I.$procmux$12397. dead port 1/2 on $mux $flatten\soc_I.\e1_buf_I.$procmux$12412. Removed 2 multiplexer ports. 75.29.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 75.29.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 1 cells. 75.29.13. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$opt_dff.cc:764:run$24840 ($dffe) from module top (D = $auto$wreduce.cc:454:run$24900 [2:0], Q = \i2c_I.core_I.bit_cnt [2:0], rval = 3'000). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$24576 ($dffe) from module top. Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$24576 ($dffe) from module top. Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$24348 ($dffe) from module top. Setting constant 1-bit at position 9 on $auto$opt_dff.cc:764:run$24296 ($adffe) from module top. 75.29.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 20 unused wires. 75.29.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.29.16. Rerunning OPT passes. (Maybe there is more to do..) 75.29.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 75.29.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 75.29.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.29.20. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$24359 ($sdff) from module top. Adding SRST signal on $auto$opt_dff.cc:702:run$24359 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_out_I.data[1] [8:7], Q = \soc_I.e1_I.wb_rdata [14:13], rval = 2'00). Removing never-active SRST on $auto$opt_dff.cc:702:run$24354 ($sdffce) from module top. Removing never-active SRST on $auto$opt_dff.cc:702:run$24352 ($sdffce) from module top. Removing never-active SRST on $auto$opt_dff.cc:702:run$24350 ($sdffce) from module top. 75.29.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.29.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.29.23. Rerunning OPT passes. (Maybe there is more to do..) 75.29.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 75.29.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 75.29.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 1 cells. 75.29.27. Executing OPT_DFF pass (perform DFF optimizations). 75.29.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 3 unused wires. 75.29.29. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.29.30. Rerunning OPT passes. (Maybe there is more to do..) 75.29.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 75.29.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 75.29.33. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.29.34. Executing OPT_DFF pass (perform DFF optimizations). 75.29.35. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.29.36. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.29.37. Finished OPT passes. (There is nothing left to do.) 75.30. Executing ICE40_WRAPCARRY pass (wrap carries). 75.31. Executing TECHMAP pass (map to technology primitives). 75.31.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/techmap.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 75.31.2. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ice40_alu'. Successfully finished Verilog frontend. 75.31.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $ne. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $sdffe. Using extmapper simplemap for cells of type $reduce_bool. Using extmapper simplemap for cells of type $sdff. Using extmapper simplemap for cells of type $dffe. Using extmapper simplemap for cells of type $sdffce. Using extmapper simplemap for cells of type $xor. Using extmapper simplemap for cells of type $adffe. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $adff. Using extmapper simplemap for cells of type $mux. Using template $paramod$constmap:37b3cc4e06391b7a7ef418215dc52e2abb59f048$paramod$71443bc33ec938a4dea8c4b4bbb3a548919fd2a5\_90_shift_shiftx for cells of type $shiftx. Using template $paramod$constmap:f131a727070ba63172385ab8bc15babdfc05a11a$paramod$4d8c31a57f918e2cd1d0bc24d8284efd6d83f4a8\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=7\B_WIDTH=1\Y_WIDTH=7 for cells of type $alu. Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu. Using extmapper simplemap for cells of type $logic_and. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=1\Y_WIDTH=5 for cells of type $alu. Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=1\Y_WIDTH=2 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=3\Y_WIDTH=3 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=1\Y_WIDTH=4 for cells of type $alu. Using template $paramod$constmap:98a2574d6790db88f29c592e698ccfc2583099ee$paramod$da4b7a069bab2d2cb126ab511d2c5f5d67aa4129\_90_shift_shiftx for cells of type $shiftx. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=14\Y_WIDTH=14 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu. Using template $paramod$constmap:2a578b20caa92a5095129d48a2f94bbad08a990f$paramod$5c10e52cdc159999f3945c97d8a1bfa2ca0de2dc\_90_shift_shiftx for cells of type $shiftx. Using template $paramod\_90_pmux\WIDTH=2\S_WIDTH=3 for cells of type $pmux. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=11\B_WIDTH=1\Y_WIDTH=12 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=13\B_WIDTH=1\Y_WIDTH=13 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=9\Y_WIDTH=9 for cells of type $alu. Using extmapper simplemap for cells of type $reduce_xor. Using extmapper simplemap for cells of type $logic_or. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=20\Y_WIDTH=20 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=1\Y_WIDTH=4 for cells of type $alu. Using template $paramod\_90_pmux\WIDTH=16\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=5 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=2\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=4 for cells of type $pmux. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=11\B_WIDTH=1\Y_WIDTH=11 for cells of type $alu. Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=6 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=3 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=8 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=6 for cells of type $pmux. Using extmapper simplemap for cells of type $reduce_xnor. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=8\Y_WIDTH=8 for cells of type $alu. Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=3 for cells of type $pmux. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=9\B_WIDTH=1\Y_WIDTH=9 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=2\Y_WIDTH=3 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=10\Y_WIDTH=10 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=11\Y_WIDTH=11 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=10\B_WIDTH=10\Y_WIDTH=10 for cells of type $alu. Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu. Using template $paramod$constmap:66d421c313e4e958be776b99540ac2de3b59fdbc$paramod$9b74a473ccd678a23e1df4cc12019cbbece20051\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=30\Y_WIDTH=30 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=31\B_WIDTH=31\Y_WIDTH=31 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=30\B_WIDTH=30\Y_WIDTH=30 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=16\Y_WIDTH=16 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=6\B_WIDTH=1\Y_WIDTH=6 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=1\Y_WIDTH=3 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=1\B_SIGNED=1\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu. Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=3 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=24\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=5 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=4 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=5 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=9\B_WIDTH=9\Y_WIDTH=9 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=26\Y_WIDTH=26 for cells of type $alu. Using template $paramod$constmap:684fca2758d270a6aba8ac07bc0dd26758fbc9a0$paramod$ce139bdae4db109c6875842b953e3d257bf611b7\_90_shift_shiftx for cells of type $shiftx. Analyzing pattern of constant bits for this cell: Constant input on bit 0 of port A: 1'0 Constant input on bit 1 of port A: 1'0 Constant input on bit 2 of port A: 1'0 Constant input on bit 3 of port A: 1'0 Constant input on bit 4 of port A: 1'1 Constant input on bit 5 of port A: 1'1 Constant input on bit 6 of port A: 1'1 Constant input on bit 7 of port A: 1'1 Constant input on bit 8 of port A: 1'0 Constant input on bit 9 of port A: 1'0 Constant input on bit 10 of port A: 1'0 Constant input on bit 11 of port A: 1'0 Constant input on bit 12 of port A: 1'1 Constant input on bit 13 of port A: 1'1 Constant input on bit 14 of port A: 1'1 Constant input on bit 15 of port A: 1'1 Creating constmapped module `$paramod$constmap:8b3644844662a5df890757b6e744f94687338ba9$paramod$ce139bdae4db109c6875842b953e3d257bf611b7\_90_shift_shiftx'. 75.31.141. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod$constmap:8b3644844662a5df890757b6e744f94687338ba9$paramod$ce139bdae4db109c6875842b953e3d257bf611b7\_90_shift_shiftx.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 2/2 on $mux $procmux$36217. dead port 2/2 on $mux $procmux$36211. dead port 2/2 on $mux $procmux$36205. dead port 2/2 on $mux $procmux$36199. Removed 4 multiplexer ports. 75.31.142. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$constmap:8b3644844662a5df890757b6e744f94687338ba9$paramod$ce139bdae4db109c6875842b953e3d257bf611b7\_90_shift_shiftx. Removed 0 unused cells and 11 unused wires. Using template $paramod$constmap:8b3644844662a5df890757b6e744f94687338ba9$paramod$ce139bdae4db109c6875842b953e3d257bf611b7\_90_shift_shiftx for cells of type $shiftx. Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=7 for cells of type $pmux. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=13\B_WIDTH=13\Y_WIDTH=13 for cells of type $alu. Using extmapper simplemap for cells of type $pos. Using template $paramod\_90_lcu\WIDTH=2 for cells of type $lcu. No more expansions possible. 75.32. Executing OPT pass (performing simple optimizations). 75.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 1313 cells. 75.32.3. Executing OPT_DFF pass (perform DFF optimizations). 75.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 989 unused cells and 4654 unused wires. 75.32.5. Finished fast OPT passes. 75.33. Executing ICE40_OPT pass (performing simple optimizations). 75.33.1. Running ICE40 specific optimizations. Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24976.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24976.BB [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24985.slice[0].carry: CO=\blinker_I.tick_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24991.slice[0].carry: CO=\gps_uart_I.uart_div [1] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24991.slice[11].carry: CO=$auto$alumacc.cc:485:replace_alu$24991.C [11] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24994.slice[0].carry: CO=\gps_uart_I.uart_rx_I.div_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24997.slice[0].carry: CO=\gps_uart_I.uart_rx_I.bit_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25003.slice[0].carry: CO=\gps_uart_I.uart_rx_fifo_I.ram_rd_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25009.slice[0].carry: CO=\gps_uart_I.uart_rx_fifo_I.ram_wr_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25012.slice[0].carry: CO=\gps_uart_I.uart_tx_I.div_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25015.slice[0].carry: CO=\gps_uart_I.uart_tx_I.bit_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25018.slice[0].carry: CO=\gps_uart_I.uart_tx_fifo_I.ram_rd_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25024.slice[0].carry: CO=\gps_uart_I.uart_tx_fifo_I.ram_wr_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25027.slice[0].carry: CO=\i2c_I.core_I.cyc_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25030.slice[0].carry: CO=\i2c_I.core_I.bit_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25039.slice[0].carry: CO=\sys_mgr_I.rst_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25087.slice[0].carry: CO=\soc_I.cpu_I.reg_pc [2] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25090.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25090.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25105.slice[0].carry: CO=\soc_I.cpu_I.reg_sh [2] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25108.slice[0].carry: CO=\soc_I.cpu_I.reg_sh [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25111.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25111.A [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25114.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25114.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25117.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25117.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25120.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25120.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25135.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25135.A [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25159.slice[0].carry: CO=\soc_I.e1_buf_I.buf_tx_ts [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25162.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25162.A [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25165.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25165.A [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25171.slice[0].carry: CO=\soc_I.iobuf_I.dma_I.m0_addr_i [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25174.slice[0].carry: CO=\soc_I.iobuf_I.dma_I.m1_addr_i [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25177.slice[0].carry: CO=\soc_I.iobuf_I.dma_I.len [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25180.slice[0].carry: CO=\soc_I.uart_I.uart_div [1] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25180.slice[11].carry: CO=$auto$alumacc.cc:485:replace_alu$25180.C [11] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25183.slice[0].carry: CO=\soc_I.uart_I.uart_rx_I.div_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25186.slice[0].carry: CO=\soc_I.uart_I.uart_rx_I.bit_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25192.slice[0].carry: CO=\soc_I.uart_I.uart_rx_fifo_I.ram_rd_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25198.slice[0].carry: CO=\soc_I.uart_I.uart_rx_fifo_I.ram_wr_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25201.slice[0].carry: CO=\soc_I.uart_I.uart_tx_I.div_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25204.slice[0].carry: CO=\soc_I.uart_I.uart_tx_I.bit_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25207.slice[0].carry: CO=\soc_I.uart_I.uart_tx_fifo_I.ram_rd_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25213.slice[0].carry: CO=\soc_I.uart_I.uart_tx_fifo_I.ram_wr_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25225.slice[0].carry: CO=\soc_I.usb_I.rx_pkt_I.bit_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25225.slice[3].carry: CO=$auto$alumacc.cc:485:replace_alu$25225.C [3] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25228.slice[0].carry: CO=\soc_I.usb_I.trans_I.mc_pc [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25243.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25243.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25243.slice[2].carry: CO=1'0 Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25246.slice[0].carry: CO=\soc_I.usb_I.tx_ll_I.bs_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25249.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25249.A [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25252.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25252.A [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25255.slice[0].carry: CO=\spi_mux_I.tick_cnt [0] 75.33.2. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.33.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.33.4. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30615 ($_SDFFCE_PP0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12173.B_AND_S [3], Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [3], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30614 ($_SDFFCE_PP0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12173.Y_B [2], Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [2], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30613 ($_SDFFCE_PP0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12173.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [1], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30611 ($_SDFFCE_PN0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12190.B_AND_S [3], Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1 [3], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30610 ($_SDFFCE_PN0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12190.Y_B [2], Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1 [2], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30609 ($_SDFFCE_PN0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12190.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1 [1], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35219 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [31], Q = \misc_I.wb_rdata [31], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35218 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [30], Q = \misc_I.wb_rdata [30], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35217 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [29], Q = \misc_I.wb_rdata [29], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35216 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [28], Q = \misc_I.wb_rdata [28], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35215 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [27], Q = \misc_I.wb_rdata [27], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35214 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [26], Q = \misc_I.wb_rdata [26], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35213 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [25], Q = \misc_I.wb_rdata [25], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35212 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [24], Q = \misc_I.wb_rdata [24], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35211 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [23], Q = \misc_I.wb_rdata [23], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35210 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [22], Q = \misc_I.wb_rdata [22], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35209 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [21], Q = \misc_I.wb_rdata [21], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35208 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [20], Q = \misc_I.wb_rdata [20], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35203 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [15], Q = \misc_I.wb_rdata [15], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35202 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [14], Q = \misc_I.wb_rdata [14], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35201 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [13], Q = \misc_I.wb_rdata [13], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35200 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [12], Q = \misc_I.wb_rdata [12], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35195 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [7], Q = \misc_I.wb_rdata [7], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35194 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [6], Q = \misc_I.wb_rdata [6], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35193 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [5], Q = \misc_I.wb_rdata [5], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35192 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [4], Q = \misc_I.wb_rdata [4], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$31223 ($_SDFF_PP0_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12216.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.samp_cnt [1], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34812 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [31], Q = \soc_I.cpu_I.decoded_imm [31], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34811 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [30], Q = \soc_I.cpu_I.decoded_imm [30], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34810 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [29], Q = \soc_I.cpu_I.decoded_imm [29], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34809 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [28], Q = \soc_I.cpu_I.decoded_imm [28], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34808 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [27], Q = \soc_I.cpu_I.decoded_imm [27], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34807 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [26], Q = \soc_I.cpu_I.decoded_imm [26], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34806 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [25], Q = \soc_I.cpu_I.decoded_imm [25], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34805 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [24], Q = \soc_I.cpu_I.decoded_imm [24], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34804 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [23], Q = \soc_I.cpu_I.decoded_imm [23], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34803 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [22], Q = \soc_I.cpu_I.decoded_imm [22], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34802 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [21], Q = \soc_I.cpu_I.decoded_imm [21], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34801 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [20], Q = \soc_I.cpu_I.decoded_imm [20], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34800 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [19], Q = \soc_I.cpu_I.decoded_imm [19], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34799 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [18], Q = \soc_I.cpu_I.decoded_imm [18], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34798 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [17], Q = \soc_I.cpu_I.decoded_imm [17], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34797 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [16], Q = \soc_I.cpu_I.decoded_imm [16], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34796 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [15], Q = \soc_I.cpu_I.decoded_imm [15], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34795 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [14], Q = \soc_I.cpu_I.decoded_imm [14], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34794 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [13], Q = \soc_I.cpu_I.decoded_imm [13], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34793 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [12], Q = \soc_I.cpu_I.decoded_imm [12], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34792 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [11], Q = \soc_I.cpu_I.decoded_imm [11], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34791 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [10], Q = \soc_I.cpu_I.decoded_imm [10], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34790 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [9], Q = \soc_I.cpu_I.decoded_imm [9], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34789 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [8], Q = \soc_I.cpu_I.decoded_imm [8], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34788 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [7], Q = \soc_I.cpu_I.decoded_imm [7], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34787 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [6], Q = \soc_I.cpu_I.decoded_imm [6], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34786 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [5], Q = \soc_I.cpu_I.decoded_imm [5], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34785 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [4], Q = \soc_I.cpu_I.decoded_imm [4], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34784 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [3], Q = \soc_I.cpu_I.decoded_imm [3], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34783 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [2], Q = \soc_I.cpu_I.decoded_imm [2], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34782 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [1], Q = \soc_I.cpu_I.decoded_imm [1], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$30605 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12205.B_AND_S [2], Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [2], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$30604 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12205.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [1], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$30603 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12205.Y_B [0], Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [0], rval = 1'0). 75.33.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 62 unused cells and 32 unused wires. 75.33.6. Rerunning OPT passes. (Removed registers in this run.) 75.33.7. Running ICE40 specific optimizations. 75.33.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.33.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 44 cells. 75.33.10. Executing OPT_DFF pass (perform DFF optimizations). 75.33.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 44 unused wires. 75.33.12. Rerunning OPT passes. (Removed registers in this run.) 75.33.13. Running ICE40 specific optimizations. 75.33.14. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.33.15. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.33.16. Executing OPT_DFF pass (perform DFF optimizations). 75.33.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.33.18. Finished OPT passes. (There is nothing left to do.) 75.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 75.35. Executing TECHMAP pass (map to technology primitives). 75.35.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. Successfully finished Verilog frontend. 75.35.2. Continuing TECHMAP pass. Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_. Using template \$_DFF_PP1_ for cells of type $_DFF_PP1_. Using template \$_SDFFCE_PP0P_ for cells of type $_SDFFCE_PP0P_. Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template \$_DFF_P_ for cells of type $_DFF_P_. Using template \$_DFFE_PP0P_ for cells of type $_DFFE_PP0P_. Using template \$_DFF_PP0_ for cells of type $_DFF_PP0_. Using template \$_DFFE_PP1P_ for cells of type $_DFFE_PP1P_. Using template \$_SDFFCE_PP1P_ for cells of type $_SDFFCE_PP1P_. Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_. No more expansions possible. 75.36. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). Mapping top.$auto$alumacc.cc:485:replace_alu$24985.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24991.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24991.slice[11].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24994.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24997.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25003.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25009.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25012.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25015.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25018.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25024.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25027.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25030.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25039.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25087.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25090.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25105.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25108.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25111.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25114.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25117.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25120.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25135.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25159.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25162.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25165.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25171.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25174.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25177.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25180.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25180.slice[11].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25183.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25186.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25192.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25198.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25201.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25204.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25207.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25213.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25225.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25225.slice[3].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25228.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25243.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25243.slice[2].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25246.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25249.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25252.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25255.slice[0].carry ($lut). 75.38. Executing ICE40_OPT pass (performing simple optimizations). 75.38.1. Running ICE40 specific optimizations. 75.38.2. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.38.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 453 cells. 75.38.4. Executing OPT_DFF pass (perform DFF optimizations). 75.38.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 12111 unused wires. 75.38.6. Rerunning OPT passes. (Removed registers in this run.) 75.38.7. Running ICE40 specific optimizations. 75.38.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.38.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.38.10. Executing OPT_DFF pass (perform DFF optimizations). 75.38.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.38.12. Finished OPT passes. (There is nothing left to do.) 75.39. Executing TECHMAP pass (map to technology primitives). 75.39.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/latches_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/latches_map.v' to AST representation. Generating RTLIL representation for module `\$_DLATCH_N_'. Generating RTLIL representation for module `\$_DLATCH_P_'. Successfully finished Verilog frontend. 75.39.2. Continuing TECHMAP pass. No more expansions possible. 75.40. Executing ABC pass (technology mapping using ABC). 75.40.1. Extracting gate netlist of module `\top' to `/input.blif'.. Extracted 6543 gates and 9005 wires to a netlist network with 2460 inputs and 1837 outputs. 75.40.1.1. Executing ABC. Running ABC command: /yosys-abc -s -f /abc.script 2>&1 ABC: ABC command line: "source /abc.script". ABC: ABC: + read_blif /input.blif ABC: + read_lut /lutdefs.txt ABC: + strash ABC: + ifraig ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + strash ABC: + dch -f ABC: + if ABC: + mfs2 ABC: + lutpack -S 1 ABC: + dress ABC: Total number of equiv classes = 2230. ABC: Participating nodes from both networks = 4701. ABC: Participating nodes from the first network = 2247. ( 79.01 % of nodes) ABC: Participating nodes from the second network = 2454. ( 86.29 % of nodes) ABC: Node pairs (any polarity) = 2247. ( 79.01 % of names can be moved) ABC: Node pairs (same polarity) = 1991. ( 70.01 % of names can be moved) ABC: Total runtime = 0.11 sec ABC: + write_blif /output.blif 75.40.1.2. Re-integrating ABC results. ABC RESULTS: $lut cells: 2843 ABC RESULTS: internal signals: 4708 ABC RESULTS: input signals: 2460 ABC RESULTS: output signals: 1837 Removing temp directory. 75.41. Executing ICE40_WRAPCARRY pass (wrap carries). 75.42. Executing TECHMAP pass (map to technology primitives). 75.42.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. Successfully finished Verilog frontend. 75.42.2. Continuing TECHMAP pass. No more expansions possible. Removed 140 unused cells and 5952 unused wires. 75.43. Executing OPT_LUT pass (optimize LUTs). Discovering LUTs. Number of LUTs: 3520 1-LUT 149 2-LUT 948 3-LUT 1252 4-LUT 1171 Eliminating LUTs. Number of LUTs: 3516 1-LUT 149 2-LUT 948 3-LUT 1248 4-LUT 1171 Combining LUTs. Number of LUTs: 3261 1-LUT 148 2-LUT 629 3-LUT 1133 4-LUT 1351 Eliminated 4 LUTs. Combined 255 LUTs. 75.44. Executing TECHMAP pass (map to technology primitives). 75.44.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v' to AST representation. Generating RTLIL representation for module `\$lut'. Successfully finished Verilog frontend. 75.44.2. Continuing TECHMAP pass. Using template $paramod\$lut\WIDTH=3\LUT=8'00110101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000110000001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'1110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'1000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000011101110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001001100111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11101111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011000000110011 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101111111110011 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01010011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101110011001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101000001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'1001 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'0100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'0001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000111 for cells of type $lut. Using template $paramod\$lut\WIDTH=1\LUT=2'01 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100010000001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011101111 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'0111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00001101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100101000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101110111011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100010011110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0110100110010110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011010111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101001101011100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101110001010011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000011101110111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000101110111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10101100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010001111001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000001001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111110111011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010110000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111001111110101 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100110101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'0110 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11010100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11101000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10110010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011101100110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001000111110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111111110 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00001011 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000110011001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00010100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111100011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011000010111011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111011111110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'1011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011101110110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01001011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100101011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000111111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100111110100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00000111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100000011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100011101110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00011111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111110000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000010001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111100010001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00001110 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010101011000011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010101010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001010111111100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010110010100011 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11111110 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11110001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000011111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100010111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111010001000100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100000100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110101100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011010100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000011111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011101100001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111000001110111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101000000011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000111110001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0110000000001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111010000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000010111011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100111101000100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000100011110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001010000101000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000010111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111010001001011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110111000001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00111010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000001100001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000001110111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111111110000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010110011001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0110000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101001100110011 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11000101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1001011001101001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011011100110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101010111000011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000110000000101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011100100001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110111111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111110000001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011110011111010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101011111100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101001111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111010111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100000000000010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111010000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000110000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001010001000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000011100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100111110110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110110000110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101010100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1101000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010101111101010 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00011000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11100111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111110011111010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100101111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111100000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100111000001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111110010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111011001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000110100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000010001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10111100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01000010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100001110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1101000000110011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111110110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111011101110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0010001010001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010100000101010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000100000001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000011100001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111111111110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0010100000101000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110111111111110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001010000010100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001000101000100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010001000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100101110110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110101110111110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1001110010011100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100000100010100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111000001011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010000000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100010100110101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100001101100110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011110011001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0010000100010010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111001011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111011101000000 for cells of type $lut. No more expansions possible. Removed 0 unused cells and 6938 unused wires. 75.45. Executing AUTONAME pass. Renamed 201871 objects in module top (129 iterations). 75.46. Executing HIERARCHY pass (managing design hierarchy). 75.46.1. Analyzing design hierarchy.. Top module: \top 75.46.2. Analyzing design hierarchy.. Top module: \top Removed 0 unused modules. 75.47. Printing statistics. === top === Number of wires: 3770 Number of wire bits: 18527 Number of public wires: 3770 Number of public wire bits: 18527 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 6294 SB_CARRY 719 SB_DFF 313 SB_DFFE 575 SB_DFFER 430 SB_DFFES 44 SB_DFFESR 220 SB_DFFESS 45 SB_DFFR 131 SB_DFFS 49 SB_DFFSR 374 SB_DFFSS 31 SB_GB 2 SB_GB_IO 1 SB_IO 25 SB_LEDDA_IP 1 SB_LUT4 3300 SB_MAC16 6 SB_PLL40_CORE 1 SB_RAM40_4K 16 SB_RAM40_4KNR 4 SB_RGBA_DRV 1 SB_SPI 1 SB_SPRAM256KA 4 SB_WARMBOOT 1 75.48. Executing CHECK pass (checking for obvious problems). checking module top.. found and reported 0 problems. 75.49. Executing JSON backend. Warnings: 9 unique messages, 17 total End of script. Logfile hash: e5a62a35df, CPU: user 21.04s system 0.12s, MEM: 321.84 MB peak Yosys 0.9+3568 (open-tool-forge build) (git sha1 859e52af, gcc 9.3.0-10ubuntu2 -Os) Time spent: 20% 38x opt_expr (4 sec), 16% 31x opt_clean (3 sec), ... nextpnr-ice40 --pre-pack data/clocks.py --pre-pack data/opt.py --seed 15 --no-promote-globals --timing-allow-fail \ --up5k --package sg48 \ -l /build/gateware/icE1usb/build-tmp/icE1usb.pnr.rpt \ --json /build/gateware/icE1usb/build-tmp/icE1usb.json \ --pcf /build/gateware/icE1usb/data/top-ice1usb.pcf \ --asc /build/gateware/icE1usb/build-tmp/icE1usb.asc Info: constrained 'e1A_rx_hi_p' to bel 'X8/Y31/io0' Warning: unmatched constraint 'e1A_rx_hi_n' (on line 3) Info: constrained 'e1A_rx_lo_p' to bel 'X16/Y31/io0' Warning: unmatched constraint 'e1A_rx_lo_n' (on line 5) Info: constrained 'e1A_tx_hi' to bel 'X9/Y31/io0' Info: constrained 'e1A_tx_lo' to bel 'X9/Y31/io1' Info: constrained 'e1B_rx_hi_p' to bel 'X19/Y31/io0' Warning: unmatched constraint 'e1B_rx_hi_n' (on line 10) Info: constrained 'e1B_rx_lo_p' to bel 'X18/Y31/io0' Warning: unmatched constraint 'e1B_rx_lo_n' (on line 12) Info: constrained 'e1B_tx_hi' to bel 'X13/Y31/io1' Info: constrained 'e1B_tx_lo' to bel 'X13/Y31/io0' Info: constrained 'e1_rx_bias[0]' to bel 'X17/Y31/io0' Info: constrained 'e1_rx_bias[1]' to bel 'X12/Y31/io1' Info: constrained 'usb_dp' to bel 'X16/Y0/io0' Info: constrained 'usb_dn' to bel 'X15/Y0/io0' Info: constrained 'usb_pu' to bel 'X17/Y0/io0' Info: constrained 'flash_mosi' to bel 'X23/Y0/io0' Info: constrained 'flash_miso' to bel 'X23/Y0/io1' Info: constrained 'flash_clk' to bel 'X24/Y0/io0' Info: constrained 'flash_cs_n' to bel 'X24/Y0/io1' Info: constrained 'e1_led_rclk' to bel 'X22/Y0/io1' Info: constrained 'gps_reset_n' to bel 'X13/Y0/io1' Info: constrained 'gps_rx' to bel 'X6/Y0/io0' Info: constrained 'gps_tx' to bel 'X5/Y0/io0' Info: constrained 'gps_pps' to bel 'X8/Y0/io0' Info: constrained 'i2c_sda' to bel 'X9/Y0/io1' Info: constrained 'i2c_scl' to bel 'X9/Y0/io0' Info: constrained 'gpio[0]' to bel 'X19/Y0/io0' Info: constrained 'gpio[1]' to bel 'X19/Y0/io1' Info: constrained 'gpio[2]' to bel 'X21/Y0/io1' Info: constrained 'clk_in' to bel 'X6/Y0/io1' Info: constrained 'clk_tune_hi' to bel 'X7/Y0/io0' Info: constrained 'clk_tune_lo' to bel 'X7/Y0/io1' Info: constrained 'dbg_rx' to bel 'X18/Y0/io1' Info: constrained 'dbg_tx' to bel 'X18/Y0/io0' Info: constrained 'rgb[0]' to bel 'X4/Y31/io0' Info: constrained 'rgb[1]' to bel 'X5/Y31/io0' Info: constrained 'rgb[2]' to bel 'X6/Y31/io0' Info: constraining clock net 'clk_sys' to 30.72 MHz Info: constraining clock net 'clk_48m' to 48.00 MHz 1 247 ControlSet(rs=None, ena=None, clk='clk_sys') 5 ControlSet(rs='wb_ack[1]', ena=None, clk='clk_sys') -------------- 0 248 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='spi_mux_I.srio_dat_o_SB_DFFSR_Q_R', ena=None, clk='clk_sys') -------------- 1 253 ControlSet(rs=None, ena=None, clk='clk_sys') 5 ControlSet(rs='soc_I.wb_ack[1]', ena=None, clk='clk_sys') -------------- 0 72 ControlSet(rs=None, ena=None, clk='clk_48m') 1 ControlSet(rs='soc_I.usb_I.tx_ll_I.lvl_prev_SB_DFFSS_Q_S', ena=None, clk='clk_48m') -------------- 0 12 ControlSet(rs=None, ena='soc_I.usb_I.tx_pkt_I.shift_now', clk='clk_48m') 1 ControlSet(rs='soc_I.usb_I.tx_ll_I.ll_ack_SB_LUT4_I2_O_SB_LUT4_I2_O[1]', ena='soc_I.usb_I.tx_pkt_I.shift_now', clk='clk_48m') 1 73 ControlSet(rs=None, ena=None, clk='clk_48m') 1 ControlSet(rs='soc_I.usb_I.tx_ll_I.ll_ack_SB_LUT4_I2_O_SB_LUT4_I2_O[1]', ena='soc_I.usb_I.tx_pkt_I.shift_now', clk='clk_48m') -------------- 2 74 ControlSet(rs=None, ena=None, clk='clk_48m') 2 ControlSet(rs='soc_I.usb_I.rx_pkt_I.state[0]', ena='soc_I.usb_I.rx_pkt_I.crc5_ok_SB_DFFESR_Q_E', clk='clk_48m') -------------- 3 79 ControlSet(rs=None, ena=None, clk='clk_48m') 5 ControlSet(rs='soc_I.usb_I.rx_pkt_I.state[0]', ena='soc_I.usb_I.rx_pkt_I.bit_cnt_SB_DFFESR_Q_E', clk='clk_48m') -------------- 0 81 ControlSet(rs=None, ena=None, clk='clk_48m') 2 ControlSet(rs='soc_I.usb_I.rx_ll_I.samp_sync', ena=None, clk='clk_48m') -------------- 0 82 ControlSet(rs=None, ena=None, clk='clk_48m') 1 ControlSet(rs='soc_I.usb_I.rx_ll_I.samp_cnt_SB_DFFSR_Q_R', ena=None, clk='clk_48m') -------------- 0 83 ControlSet(rs=None, ena=None, clk='clk_48m') 1 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_sync_1_SB_LUT4_I2_O[1]', ena='soc_I.usb_I.rx_pkt_I.crc_in_first_SB_DFFESS_Q_E', clk='clk_48m') -------------- 5 15 ControlSet(rs=None, ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m') 3 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_sync_1_SB_DFFESR_Q_R', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m') 3 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_eop_1_SB_DFFESR_Q_R', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m') 1 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_rep_state_1_SB_DFFESR_Q_R', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m') 3 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_sym_same_0_SB_LUT4_I3_1_O', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m') 1 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_sym_se_0', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m') 3 86 ControlSet(rs=None, ena=None, clk='clk_48m') 3 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_sync_1_SB_DFFESR_Q_R', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m') -------------- 0 85 ControlSet(rs=None, ena=None, clk='clk_48m') 2 ControlSet(rs='soc_I.usb_I.eps_write_0', ena=None, clk='clk_48m') -------------- 0 88 ControlSet(rs=None, ena=None, clk='clk_48m') 3 ControlSet(rs='soc_I.usb_I.eps_bus_clear', ena=None, clk='clk_48m') -------------- 0 93 ControlSet(rs=None, ena=None, clk='clk_48m') 5 ControlSet(rs='soc_I.usb_I.csr_bus_clear', ena=None, clk='clk_48m') -------------- 0 260 ControlSet(rs=None, ena=None, clk='clk_sys') 7 ControlSet(rs='soc_I.uart_I.ub_rdata_SB_DFFSR_Q_9_R', ena=None, clk='clk_sys') -------------- 0 261 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.uart_I.uart_tx_I.ce_SB_LUT4_I2_O[2]', ena=None, clk='clk_sys') -------------- 4 266 ControlSet(rs=None, ena=None, clk='clk_sys') 5 ControlSet(rs='soc_I.uart_I.uart_tx_I.bit_cnt_SB_DFFESS_Q_S', ena='soc_I.uart_I.uart_tx_I.ce_SB_LUT4_I2_O[2]', clk='clk_sys') -------------- 4 271 ControlSet(rs=None, ena=None, clk='clk_sys') 5 ControlSet(rs='soc_I.uart_I.uart_rx_I.bit_cnt_SB_DFFESS_Q_S', ena='soc_I.uart_I.uart_rx_I.bit_cnt_SB_DFFESS_Q_E', clk='clk_sys') -------------- 1 272 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.latched_store_SB_DFFESS_Q_E', clk='clk_sys') -------------- 5 277 ControlSet(rs=None, ena=None, clk='clk_sys') 5 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.latched_stalu_SB_DFFESR_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_O', clk='clk_sys') -------------- 0 278 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.latched_stalu_SB_DFFESR_Q_E', clk='clk_sys') -------------- 2 280 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.latched_is_lb_SB_DFFESR_Q_E', clk='clk_sys') -------------- 1 281 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.latched_branch_SB_DFFESR_Q_E[2]', clk='clk_sys') -------------- 1 282 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu_SB_DFFESR_Q_E', clk='clk_sys') -------------- 0 13 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.len_ce', clk='clk_sys') 1 ControlSet(rs='soc_I.iobuf_I.dma_I.len_ld', ena='soc_I.iobuf_I.dma_I.len_ce', clk='clk_sys') 1 283 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.iobuf_I.dma_I.len_ld', ena='soc_I.iobuf_I.dma_I.len_ce', clk='clk_sys') -------------- 0 284 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs='soc_I.e1_buf_I.buf_rx_frame_SB_LUT4_I0_I1_SB_LUT4_O_I2_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_DFFSR_D_Q_SB_LUT4_I2_O', ena=None, clk='clk_sys') -------------- 0 286 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs='soc_I.e1_I.wb_rdata_SB_DFFSR_Q_14_R', ena=None, clk='clk_sys') -------------- 0 288 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I2_O_SB_DFFSR_D_R_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFSR_R_1_Q_SB_LUT4_I2_O', ena=None, clk='clk_sys') -------------- 0 292 ControlSet(rs=None, ena=None, clk='clk_sys') 4 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I2_O_SB_DFFSR_D_R_SB_LUT4_O_I3_SB_LUT4_I3_O', ena=None, clk='clk_sys') -------------- 0 294 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I2_O_SB_DFFSR_D_R_SB_DFFSR_R_1_Q_SB_LUT4_I2_O', ena=None, clk='clk_sys') -------------- 0 298 ControlSet(rs=None, ena=None, clk='clk_sys') 4 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I2_O_SB_DFFSR_D_R', ena=None, clk='clk_sys') -------------- 0 300 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I2_O_SB_DFFSR_D_Q_SB_LUT4_I1_1_O', ena=None, clk='clk_sys') -------------- 6 307 ControlSet(rs=None, ena=None, clk='clk_sys') 7 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I0_I3[2]', ena='soc_I.e1_buf_I.buf_rx_we_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O', clk='clk_sys') -------------- 5 314 ControlSet(rs=None, ena=None, clk='clk_sys') 7 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I0_I3[2]', ena='soc_I.e1_buf_I.buf_rx_we_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I2_O', clk='clk_sys') -------------- 4 319 ControlSet(rs=None, ena=None, clk='clk_sys') 5 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I0_I3[2]', ena='soc_I.e1_buf_I.buf_rx_we_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_DFFESR_Q_E', clk='clk_sys') -------------- 0 320 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I0_I3[2]', ena=None, clk='clk_sys') -------------- 0 324 ControlSet(rs=None, ena=None, clk='clk_sys') 4 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_I2_1_O_SB_LUT4_O_I3_SB_LUT4_I3_1_O', ena=None, clk='clk_sys') -------------- 0 328 ControlSet(rs=None, ena=None, clk='clk_sys') 4 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I1_I0_SB_LUT4_I0_O_SB_DFFR_D_Q_SB_DFF_D_Q_SB_LUT4_I3_2_O', ena=None, clk='clk_sys') -------------- 0 329 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.e1_I.lb_bit_SB_DFFESR_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_O', ena=None, clk='clk_sys') -------------- 1 331 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs='soc_I.e1_I.lb_bit_SB_DFFESR_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_I2[0]', ena='soc_I.e1_I.lb_bit_SB_DFFESR_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_DFFSR_R_Q_SB_DFFESR_Q_E', clk='clk_sys') -------------- 0 332 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_DFFESS_Q_S[2]', ena='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_DFFESS_Q_E', clk='clk_sys') -------------- 0 333 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_DFFESS_Q_S[2]', ena=None, clk='clk_sys') -------------- 0 334 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_DFFESS_Q_S[2]', ena='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_DFFESS_Q_E', clk='clk_sys') -------------- 3 19 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_buf_I.buf_tx_re_SB_LUT4_O_I3', clk='clk_sys') 1 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_I2_1_O_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_DFFER_Q_E[1]', clk='clk_sys') 4 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_LUT4_I2_O', clk='clk_sys') -------------- 1 335 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I0_SB_LUT4_I0_O_SB_DFFR_D_Q_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_DFFESR_Q_E', clk='clk_sys') -------------- 0 336 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I0_SB_LUT4_I0_O_SB_DFFR_D_Q_SB_LUT4_I2_O', clk='clk_sys') -------------- 0 340 ControlSet(rs=None, ena=None, clk='clk_sys') 4 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I0_SB_DFFER_Q_E_SB_DFFSR_Q_R', ena=None, clk='clk_sys') -------------- 0 341 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.cpu_I.mem_state_SB_DFFESR_Q_R', ena='soc_I.cpu_I.mem_valid_SB_DFFESR_Q_E', clk='clk_sys') -------------- 2 343 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs='soc_I.cpu_I.mem_state_SB_DFFESR_Q_R', ena='soc_I.cpu_I.mem_state_SB_DFFESR_Q_E', clk='clk_sys') -------------- 0 344 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.cpu_I.mem_do_wdata_SB_DFFESS_Q_S[0]', ena='soc_I.cpu_I.mem_do_wdata_SB_DFFESS_Q_E', clk='clk_sys') -------------- 0 345 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.cpu_I.mem_do_rinst_SB_DFFESS_Q_S[2]', ena='soc_I.cpu_I.mem_do_prefetch_SB_DFFESR_Q_E', clk='clk_sys') -------------- 1 346 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.cpu_I.mem_do_rinst_SB_DFFESS_Q_S[0]', ena='soc_I.cpu_I.mem_do_rinst_SB_DFFESS_Q_E', clk='clk_sys') -------------- 0 347 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.cpu_I.instr_sh_SB_LUT4_I2_O[2]', ena='soc_I.cpu_I.mem_do_rdata_SB_DFFESS_Q_E', clk='clk_sys') -------------- 0 348 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.cpu_I.instr_or_SB_DFFESR_Q_E', ena=None, clk='clk_sys') -------------- 0 349 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.cpu_I.decoder_pseudo_trigger_SB_DFFSR_Q_R', ena=None, clk='clk_sys') -------------- 0 350 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.cpu_I.alu_wait_SB_DFFSR_Q_R', ena=None, clk='clk_sys') -------------- 1 191 ControlSet(rs='rst_sys', ena=None, clk='clk_sys') 1 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_tx_fifo_I.rd_valid_SB_DFFER_Q_E[1]', clk='clk_sys') 1 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_rx_fifo_I.rd_valid_SB_DFFER_Q_E[1]', clk='clk_sys') 1 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_tx_fifo_I.rd_valid_SB_DFFER_Q_E[1]', clk='clk_sys') 3 ControlSet(rs='rst_sys', ena='misc_I.bus_we_boot', clk='clk_sys') 3 ControlSet(rs='rst_sys', ena='misc_I.dfu_I.wb_sel_SB_DFFER_Q_E', clk='clk_sys') 1 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I0_SB_DFFER_Q_E', clk='clk_sys') 7 ControlSet(rs='rst_sys', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I3_SB_DFFER_Q_E', clk='clk_sys') 2 ControlSet(rs='rst_sys', ena='soc_I.iobuf_I.dma_I.state_SB_DFFER_Q_E', clk='clk_sys') 3 ControlSet(rs='rst_sys', ena='soc_I.rgb_I.led_ctrl_SB_DFFER_Q_E', clk='clk_sys') 1 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_rx_fifo_I.rd_valid_SB_DFFER_Q_E[1]', clk='clk_sys') -------------- 0 351 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_rx_I.gf_I.state_SB_DFFESS_Q_E', clk='clk_sys') -------------- 1 352 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='rst_sys', ena='i2c_I.core_I.sda_oe_SB_DFFESR_Q_E', clk='clk_sys') -------------- 0 353 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='rst_sys', ena='i2c_I.core_I.scl_oe_SB_DFFESR_Q_E', clk='clk_sys') -------------- 0 354 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_rx_I.gf_I.state_SB_DFFESS_Q_E', clk='clk_sys') -------------- 5 67 ControlSet(rs='rst_48m', ena=None, clk='clk_48m') 3 ControlSet(rs='rst_48m', ena='soc_I.usb_I.tx_ll_I.state_SB_DFFER_Q_E', clk='clk_48m') 2 ControlSet(rs='rst_48m', ena='soc_I.usb_I.tx_ll_I.br_cnt[2]', clk='clk_48m') -------------- 0 355 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='misc_I.pps_flt_I.state_SB_LUT4_I1_O[1]', ena='misc_I.pps_flt_I.state_SB_DFFESR_Q_E', clk='clk_sys') -------------- 0 356 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='misc_I.dfu_I.btn_flt_I.fall_SB_DFF_Q_D', ena='misc_I.dfu_I.btn_flt_I.state_SB_DFFESR_Q_E', clk='clk_sys') -------------- 0 363 ControlSet(rs=None, ena=None, clk='clk_sys') 7 ControlSet(rs='misc_I.bus_we_led_SB_DFFSR_Q_R', ena=None, clk='clk_sys') -------------- 0 368 ControlSet(rs=None, ena=None, clk='clk_sys') 5 ControlSet(rs='i2c_I.core_I.cyc_cnt_SB_DFFSR_Q_R', ena=None, clk='clk_sys') -------------- 2 371 ControlSet(rs=None, ena=None, clk='clk_sys') 3 ControlSet(rs='i2c_I.core_I.bit_cnt_SB_DFFESR_Q_R[1]', ena='i2c_I.core_I.bit_last_SB_DFFE_Q_E', clk='clk_sys') -------------- 0 378 ControlSet(rs=None, ena=None, clk='clk_sys') 7 ControlSet(rs='gps_uart_I.ub_rdata_SB_DFFSR_Q_9_R', ena=None, clk='clk_sys') -------------- 0 379 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='gps_uart_I.uart_tx_I.ce_SB_LUT4_I2_O[2]', ena=None, clk='clk_sys') -------------- 4 384 ControlSet(rs=None, ena=None, clk='clk_sys') 5 ControlSet(rs='gps_uart_I.uart_tx_I.bit_cnt_SB_DFFESS_Q_S', ena='gps_uart_I.uart_tx_I.ce_SB_LUT4_I2_O[2]', clk='clk_sys') -------------- 4 389 ControlSet(rs=None, ena=None, clk='clk_sys') 5 ControlSet(rs='gps_uart_I.uart_rx_I.bit_cnt_SB_DFFESS_Q_S', ena='gps_uart_I.uart_rx_I.bit_cnt_SB_DFFESS_Q_E', clk='clk_sys') -------------- 3 392 ControlSet(rs=None, ena=None, clk='clk_sys') 3 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena='soc_I.e1_I.lb_bit_SB_DFFESR_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_DFFSR_R_Q_SB_DFFESR_Q_E', clk='clk_sys') -------------- 3 396 ControlSet(rs=None, ena=None, clk='clk_sys') 4 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena='soc_I.e1_I.lb_bit_SB_DFFESR_Q_E[0]', clk='clk_sys') -------------- 0 397 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_DFFESR_Q_E', clk='clk_sys') -------------- 1 399 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena='e1A_rx_lo_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O_SB_LUT4_I2_O', clk='clk_sys') -------------- 1 401 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O_SB_LUT4_I2_O', clk='clk_sys') -------------- 1 405 ControlSet(rs=None, ena=None, clk='clk_sys') 4 ControlSet(rs=None, ena='tick_e1_tx[0]', clk='clk_sys') -------------- 0 95 ControlSet(rs=None, ena=None, clk='clk_48m') 2 ControlSet(rs=None, ena='soc_I.usb_I.tx_pkt_I.shift_data_crc_SB_DFFE_Q_E', clk='clk_48m') -------------- 1 99 ControlSet(rs=None, ena=None, clk='clk_48m') 4 ControlSet(rs=None, ena='soc_I.usb_I.trans_I.mc_op_tx', clk='clk_48m') -------------- 4 103 ControlSet(rs=None, ena=None, clk='clk_48m') 4 ControlSet(rs=None, ena='soc_I.usb_I.trans_I.mc_op_ld', clk='clk_48m') -------------- 2 110 ControlSet(rs=None, ena=None, clk='clk_48m') 7 ControlSet(rs=None, ena='soc_I.usb_I.trans_I.epfw_issue_wb_SB_LUT4_I1_O[0]', clk='clk_48m') -------------- 1 116 ControlSet(rs=None, ena=None, clk='clk_48m') 6 ControlSet(rs=None, ena='soc_I.usb_I.trans_I.ep_bd_dual_SB_LUT4_I2_O[2]', clk='clk_48m') -------------- 3 119 ControlSet(rs=None, ena=None, clk='clk_48m') 3 ControlSet(rs=None, ena='soc_I.usb_I.trans_I.bd_state_SB_DFFE_Q_E', clk='clk_48m') -------------- 0 123 ControlSet(rs=None, ena=None, clk='clk_48m') 4 ControlSet(rs=None, ena='soc_I.usb_I.rxpkt_done_ok', clk='clk_48m') -------------- 0 126 ControlSet(rs=None, ena=None, clk='clk_48m') 3 ControlSet(rs=None, ena='soc_I.usb_I.rx_pkt_I.token_data_SB_DFFE_Q_E[1]', clk='clk_48m') -------------- 0 406 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.len_ld', clk='clk_sys') -------------- 0 410 ControlSet(rs=None, ena=None, clk='clk_sys') 4 ControlSet(rs=None, ena='soc_I.e1_buf_I.buf_rx_frame_SB_LUT4_I0_I1_SB_LUT4_O_I2_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_DFFESS_D_Q_SB_LUT4_I2_I3_SB_LUT4_I0_O[0]', clk='clk_sys') -------------- 1 414 ControlSet(rs=None, ena=None, clk='clk_sys') 4 ControlSet(rs=None, ena='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I0_I1', clk='clk_sys') -------------- 1 415 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs=None, ena='soc_I.cpu_I.reg_op1_SB_DFFE_Q_31_E', clk='clk_sys') -------------- 2 417 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs=None, ena='soc_I.cpu_I.instr_sra_SB_LUT4_I2_O[3]', clk='clk_sys') -------------- 4 421 ControlSet(rs=None, ena=None, clk='clk_sys') 4 ControlSet(rs=None, ena='soc_I.bridge_I.ram_rdy_SB_LUT4_I0_O[1]', clk='clk_sys') -------------- 0 423 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs=None, ena='i2c_I.stb', clk='clk_sys') -------------- 1 424 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs=None, ena='i2c_I.core_I.bit_last_SB_DFFE_Q_E', clk='clk_sys') -------------- Control Set Optimizer: cost 99 to reduce control sets from 208 to 99 Total control sets: 99 1 2 3 1 4 1 6 1 8 13 9 21 10 12 11 2 12 4 13 5 14 2 15 2 16 5 17 2 18 1 19 1 20 4 24 1 25 1 26 1 29 1 31 2 32 5 33 2 45 1 55 1 60 1 67 1 126 1 191 1 424 1 1 ControlSet(rs='sys_mgr_I.pll_lock_SB_LUT4_I3_O', ena=None, clk='clk_sys') 1 ControlSet(rs='sys_mgr_I.rst_30m72_i', ena=None, clk='clk_48m') 3 ControlSet(rs='sys_mgr_I.pll_lock_SB_LUT4_I3_O', ena='sys_mgr_I.rst_30m72_i', clk='clk_sys') 4 ControlSet(rs='soc_I.usb_I.txll_start', ena='soc_I.usb_I.tx_ll_I.br_cnt[2]', clk='clk_48m') 6 ControlSet(rs='rst_sys', ena=None, clk='clk_48m') 8 ControlSet(rs=None, ena='spi_mux_I.shift_ce', clk='clk_sys') 8 ControlSet(rs=None, ena='soc_I.usb_I.rx_pkt_I.token_data_SB_DFFE_Q_9_E[1]', clk='clk_48m') 8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I0_SB_LUT4_I1_O[2]', clk='clk_sys') 8 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_DFF_D_Q[2]', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_1_I0_SB_DFFR_Q_D_SB_LUT4_O_I3_SB_DFF_Q_D_SB_LUT4_O_I3_SB_LUT4_I2_I0_SB_LUT4_I1_I3_SB_DFFSR_Q_D_SB_LUT4_O_I2_SB_LUT4_I2_O', clk='clk_sys') 8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I1_SB_LUT4_I1_O[1]', clk='clk_sys') 8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I0_SB_LUT4_I1_O[1]', clk='clk_sys') 8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I0_SB_LUT4_I1_O[4]', clk='clk_sys') 8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I1_SB_LUT4_I1_O[3]', clk='clk_sys') 8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I1_SB_LUT4_I1_O[4]', clk='clk_sys') 8 ControlSet(rs='rst_sys', ena='misc_I.bus_we_gpio', clk='clk_sys') 8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I1_SB_LUT4_I1_O[2]', clk='clk_sys') 8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I0_SB_LUT4_I1_O[3]', clk='clk_sys') 8 ControlSet(rs=None, ena='soc_I.e1_buf_I.t_done[2]', clk='clk_sys') 9 ControlSet(rs=None, ena='soc_I.usb_I.rx_pkt_I.pid_cap', clk='clk_48m') 9 ControlSet(rs='soc_I.uart_I.ub_rdata_rst', ena=None, clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='soc_I.uart_I.ub_wr_data', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_tx_fifo_I.ram_rd_ena', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='dbg_tx_SB_DFFES_Q_E', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='soc_I.uart_I.urf_wren', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_rx_fifo_I.ram_rd_ena', clk='clk_sys') 9 ControlSet(rs=None, ena='soc_I.uart_I.uart_rx_I.ce', clk='clk_sys') 9 ControlSet(rs=None, ena='i2c_I.ack_out_SB_DFFE_Q_E', clk='clk_sys') 9 ControlSet(rs=None, ena='tick_e1_rx[0]', clk='clk_sys') 9 ControlSet(rs='gps_uart_I.ub_rdata_rst', ena=None, clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_tx_fifo_I.ram_rd_ena', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_rx_fifo_I.ram_rd_ena', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='misc_I.bus_we_pdm_e1[0]', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='misc_I.bus_we_pdm_e1[1]', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='gps_uart_I.ub_wr_data', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='gps_tx_SB_DFFES_Q_E', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='gps_uart_I.urf_wren', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='misc_I.bus_we_led', clk='clk_sys') 9 ControlSet(rs=None, ena='gps_uart_I.uart_rx_I.ce', clk='clk_sys') 9 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.m1_addr_ce', clk='clk_sys') 10 ControlSet(rs='soc_I.usb_I.trans_I.len_ld', ena=None, clk='clk_48m') 10 ControlSet(rs='rst_48m', ena='soc_I.usb_I.cr_bus_we', clk='clk_48m') 10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I3_SB_LUT4_I1_O[3]', clk='clk_sys') 10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I3_SB_LUT4_I1_O[2]', clk='clk_sys') 10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I2_SB_LUT4_I1_O[3]', clk='clk_sys') 10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I2_SB_LUT4_I1_O[4]', clk='clk_sys') 10 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I0_SB_LUT4_I0_O_SB_DFFR_D_Q_SB_LUT4_I3_O[2]', clk='clk_sys') 10 ControlSet(rs='i2c_I.bus_clr', ena=None, clk='clk_sys') 10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I2_SB_LUT4_I1_O[1]', clk='clk_sys') 10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I3_SB_LUT4_I1_O[1]', clk='clk_sys') 10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I2_SB_LUT4_I1_O[2]', clk='clk_sys') 10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I3_SB_LUT4_I1_O[4]', clk='clk_sys') 11 ControlSet(rs=None, ena='soc_I.usb_I.tx_pkt_I.len_dec', clk='clk_48m') 11 ControlSet(rs='soc_I.usb_I.trans_I.mc_op_zlen', ena=None, clk='clk_48m') 12 ControlSet(rs=None, ena='soc_I.usb_I.tx_pkt_I.shift_now', clk='clk_48m') 12 ControlSet(rs=None, ena='soc_I.uart_I.ub_wr_div', clk='clk_sys') 12 ControlSet(rs=None, ena='gps_uart_I.ub_wr_div', clk='clk_sys') 12 ControlSet(rs='misc_I.bus_clr', ena=None, clk='clk_sys') 13 ControlSet(rs=None, ena='soc_I.cpu_I.decoder_pseudo_trigger_SB_LUT4_I2_O[0]', clk='clk_sys') 13 ControlSet(rs='rst_sys', ena='misc_I.bus_we_pdm_clk[1]', clk='clk_sys') 13 ControlSet(rs='rst_sys', ena='misc_I.bus_we_pdm_clk[0]', clk='clk_sys') 13 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.len_ce', clk='clk_sys') 13 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_buf_I.buf_tx_ts_SB_DFFES_Q_E', clk='clk_sys') 14 ControlSet(rs=None, ena='soc_I.usb_I.ep_status_I.p_read_2', clk='clk_48m') 14 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.m0_addr_ce', clk='clk_sys') 15 ControlSet(rs=None, ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m') 15 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='tick_e1_tx[0]', clk='clk_sys') 16 ControlSet(rs='soc_I.wb_48m_xclk_I.s_cyc_SB_LUT4_I3_O', ena=None, clk='clk_sys') 16 ControlSet(rs=None, ena='soc_I.ub_ack', clk='clk_48m') 16 ControlSet(rs=None, ena='soc_I.usb_I.tx_pkt_I.crc_in_valid', clk='clk_48m') 16 ControlSet(rs='soc_I.usb_I.ep_status_I.s_zero_2', ena='soc_I.usb_I.ep_status_I.s_read_2', clk='clk_48m') 16 ControlSet(rs=None, ena='soc_I.e1_buf_tx_re[0]', clk='clk_sys') 17 ControlSet(rs='soc_I.e1_I.bus_clr', ena=None, clk='clk_sys') 17 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I0_I3[2]', ena='soc_I.e1_buf_I.buf_rx_frame_SB_LUT4_I0_I1_SB_LUT4_O_I2_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_DFFESS_D_Q_SB_LUT4_I2_I3_SB_LUT4_I0_1_O', clk='clk_sys') 18 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.instr_or_SB_DFFESR_Q_E', clk='clk_sys') 19 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena=None, clk='clk_sys') 20 ControlSet(rs='soc_I.usb_I.oob_sof_SB_LUT4_I2_O', ena=None, clk='clk_48m') 20 ControlSet(rs='soc_I.usb_I.phy_I.rx_dn_SB_LUT4_I2_O', ena=None, clk='clk_48m') 20 ControlSet(rs='misc_I.wb_ack_SB_LUT4_I2_O_SB_LUT4_I3_O', ena=None, clk='clk_sys') 20 ControlSet(rs=None, ena='soc_I.cpu_I.trap_SB_LUT4_I3_1_O', clk='clk_sys') 24 ControlSet(rs=None, ena='soc_I.e1_buf_rx_we[0]', clk='clk_sys') 25 ControlSet(rs=None, ena='soc_I.e1_buf_I.t_busy_SB_LUT4_I3_O', clk='clk_sys') 26 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena=None, clk='clk_sys') 29 ControlSet(rs=None, ena='soc_I.usb_I.rx_pkt_I.crc_in_valid', clk='clk_48m') 31 ControlSet(rs='soc_I.cpu_I.is_lui_auipc_jal_SB_DFF_Q_D_SB_LUT4_I2_1_O', ena='soc_I.cpu_I.decoder_pseudo_trigger_SB_LUT4_I2_O[0]', clk='clk_sys') 31 ControlSet(rs=None, ena='soc_I.cpu_I.alu_wait_SB_LUT4_I1_O_SB_LUT4_I1_O[3]', clk='clk_sys') 32 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.ack_rd', clk='clk_sys') 32 ControlSet(rs='soc_I.bridge_I.wb_cyc_rst', ena=None, clk='clk_sys') 32 ControlSet(rs=None, ena='soc_I.cpu_I.instr_ecall_ebreak_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I0[3]', clk='clk_sys') 32 ControlSet(rs=None, ena='soc_I.pb_rst_n_SB_LUT4_I2_O', clk='clk_sys') 32 ControlSet(rs=None, ena='soc_I.cpu_I.trap_SB_LUT4_I2_O', clk='clk_sys') 33 ControlSet(rs=None, ena='soc_I.cpu_I.cpu_state_SB_DFF_Q_3_D_SB_LUT4_O_I3_SB_LUT4_O_I0[3]', clk='clk_sys') 33 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena=None, clk='clk_sys') 45 ControlSet(rs='rst_sys', ena='soc_I.iobuf_I.epbam_arb_I.reselect', clk='clk_sys') 55 ControlSet(rs='rst_sys', ena='soc_I.iobuf_I.spram_arb_I.reselect', clk='clk_sys') 60 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.pb_rst_n_SB_LUT4_I3_1_O[0]', clk='clk_sys') 67 ControlSet(rs='rst_48m', ena=None, clk='clk_48m') 126 ControlSet(rs=None, ena=None, clk='clk_48m') 191 ControlSet(rs='rst_sys', ena=None, clk='clk_sys') 424 ControlSet(rs=None, ena=None, clk='clk_sys') LUT replication: 0 new LUTs in 0 groups Info: Packing constants.. Info: Packing IOs.. Info: clk_in feeds SB_IO sys_mgr_I.gb_in, removing $nextpnr_ibuf clk_in. Info: clk_tune_hi feeds SB_IO misc_I.pdm_clk_I[1].io_reg_I, removing $nextpnr_obuf clk_tune_hi. Info: clk_tune_lo feeds SB_IO misc_I.pdm_clk_I[0].io_reg_I, removing $nextpnr_obuf clk_tune_lo. Info: e1A_rx_hi_p feeds SB_IO e1A_rx_hi_p_SB_IO_PACKAGE_PIN, removing $nextpnr_ibuf e1A_rx_hi_p. Info: e1A_rx_lo_p feeds SB_IO e1A_rx_lo_p_SB_IO_PACKAGE_PIN, removing $nextpnr_ibuf e1A_rx_lo_p. Info: e1A_tx_hi feeds SB_IO e1A_tx_hi_SB_IO_PACKAGE_PIN, removing $nextpnr_obuf e1A_tx_hi. Info: e1A_tx_lo feeds SB_IO e1A_tx_lo_SB_IO_PACKAGE_PIN, removing $nextpnr_obuf e1A_tx_lo. Info: e1B_rx_hi_p feeds SB_IO e1_dummy_rx_I[1], removing $nextpnr_ibuf e1B_rx_hi_p. Info: e1B_rx_lo_p feeds SB_IO e1_dummy_rx_I[0], removing $nextpnr_ibuf e1B_rx_lo_p. Info: e1B_tx_hi feeds SB_IO e1_dummy_tx_I[1], removing $nextpnr_obuf e1B_tx_hi. Info: e1B_tx_lo feeds SB_IO e1_dummy_tx_I[0], removing $nextpnr_obuf e1B_tx_lo. Info: e1_led_rclk feeds SB_IO spi_mux_I.iob_I[0], removing $nextpnr_iobuf e1_led_rclk. Info: flash_clk feeds SB_IO spi_mux_I.iob_I[1], removing $nextpnr_iobuf flash_clk. Info: flash_miso feeds SB_IO spi_mux_I.iob_I[2], removing $nextpnr_iobuf flash_miso. Info: flash_mosi feeds SB_IO spi_mux_I.iob_I[3], removing $nextpnr_iobuf flash_mosi. Info: gps_pps feeds SB_IO misc_I.pps_iob_I, removing $nextpnr_ibuf gps_pps. Info: gps_reset_n feeds SB_IO misc_I.gpio_iob_I[3], removing $nextpnr_obuf gps_reset_n. Info: i2c_scl feeds SB_IO i2c_iob_I[1], removing $nextpnr_iobuf i2c_scl. Info: i2c_sda feeds SB_IO i2c_iob_I[0], removing $nextpnr_iobuf i2c_sda. Info: usb_dn feeds SB_IO soc_I.usb_I.phy_I.io_dn_I, removing $nextpnr_iobuf usb_dn. Info: usb_dp feeds SB_IO soc_I.usb_I.phy_I.io_dp_I, removing $nextpnr_iobuf usb_dp. Info: gpio[0] feeds SB_IO misc_I.gpio_iob_I[0], removing $nextpnr_iobuf gpio[0]. Info: gpio[1] feeds SB_IO misc_I.gpio_iob_I[1], removing $nextpnr_iobuf gpio[1]. Info: gpio[2] feeds SB_IO misc_I.gpio_iob_I[2], removing $nextpnr_iobuf gpio[2]. Info: e1_rx_bias[0] feeds SB_IO misc_I.pdm_e1_I[0].io_reg_I, removing $nextpnr_obuf e1_rx_bias[0]. Info: e1_rx_bias[1] feeds SB_IO misc_I.pdm_e1_I[1].io_reg_I, removing $nextpnr_obuf e1_rx_bias[1]. Info: rgb[0] use by SB_RGBA_DRV/SB_RGB_DRV soc_I.rgb_I.rgb_drv_I, not creating SB_IO Info: rgb[1] use by SB_RGBA_DRV/SB_RGB_DRV soc_I.rgb_I.rgb_drv_I, not creating SB_IO Info: rgb[2] use by SB_RGBA_DRV/SB_RGB_DRV soc_I.rgb_I.rgb_drv_I, not creating SB_IO Info: Packing LUT-FFs.. Info: 1786 LCs used as LUT4 only Info: 1701 LCs used as LUT4 and DFF Info: Packing non-LUT FFs.. Info: 511 LCs used as DFF only Info: Packing carries.. Info: 264 LCs used as CARRY only Info: Packing RAMs.. Info: Placing PLLs.. Info: constrained PLL 'sys_mgr_I.pll_I' to X12/Y31/pll_3 Info: Packing special functions.. Info: constrained SB_LEDDA_IP 'soc_I.rgb_I.led_I' to X0/Y31/ledda_ip_2 Info: constrained SB_RGBA_DRV 'soc_I.rgb_I.rgb_drv_I' to X0/Y30/rgba_drv_0 Info: constrained SB_SPI 'soc_I.spi_I.spi_I' to X0/Y0/spi_0 Info: PLL 'sys_mgr_I.pll_I' has LOCK output, need to pass all outputs via LUT Info: constrained 'sys_mgr_I.pll_lock_SB_LUT4_I3_LC' to X1/Y30/lc0 Info: Constraining chains... Info: 210 LCs used to legalise carry chains. Info: Checksum: 0x9f5b8fb2 Info: Annotating ports with timing budgets for target frequency 12.00 MHz Info: Checksum: 0xe8e3c358 Info: Device utilisation: Info: ICESTORM_LC: 4477/ 5280 84% Info: ICESTORM_RAM: 20/ 30 66% Info: SB_IO: 32/ 96 33% Info: SB_GB: 4/ 8 50% Info: ICESTORM_PLL: 1/ 1 100% Info: SB_WARMBOOT: 1/ 1 100% Info: ICESTORM_DSP: 6/ 8 75% Info: ICESTORM_HFOSC: 0/ 1 0% Info: ICESTORM_LFOSC: 0/ 1 0% Info: SB_I2C: 0/ 2 0% Info: SB_SPI: 1/ 2 50% Info: IO_I3C: 0/ 2 0% Info: SB_LEDDA_IP: 1/ 1 100% Info: SB_RGBA_DRV: 1/ 1 100% Info: ICESTORM_SPRAM: 4/ 4 100% Info: Placed 39 cells based on constraints. Info: Creating initial analytic placement for 3588 cells, random placement wirelen = 111896. Info: at initial placer iter 0, wirelen = 3713 Info: at initial placer iter 1, wirelen = 3246 Info: at initial placer iter 2, wirelen = 3248 Info: at initial placer iter 3, wirelen = 3211 Info: Running main analytical placer. Info: at iteration #1, type ALL: wirelen solved = 3243, spread = 38315, legal = 56125; time = 0.58s Info: at iteration #2, type ALL: wirelen solved = 4375, spread = 29810, legal = 49270; time = 0.45s Info: at iteration #3, type ALL: wirelen solved = 5639, spread = 28919, legal = 48764; time = 0.39s Info: at iteration #4, type ALL: wirelen solved = 6869, spread = 28448, legal = 37942; time = 0.28s Info: at iteration #5, type ALL: wirelen solved = 7693, spread = 26840, legal = 39426; time = 0.26s Info: at iteration #6, type ALL: wirelen solved = 8475, spread = 26429, legal = 41359; time = 0.37s Info: at iteration #7, type ALL: wirelen solved = 8859, spread = 26231, legal = 44945; time = 0.32s Info: at iteration #8, type ALL: wirelen solved = 9080, spread = 26159, legal = 45238; time = 0.30s Info: at iteration #9, type ALL: wirelen solved = 9623, spread = 26346, legal = 45346; time = 0.28s Info: HeAP Placer Time: 4.05s Info: of which solving equations: 1.06s Info: of which spreading cells: 0.14s Info: of which strict legalisation: 2.27s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 832, wirelen = 37942 Info: at iteration #5: temp = 0.000000, timing cost = 689, wirelen = 30498 Info: at iteration #10: temp = 0.000000, timing cost = 614, wirelen = 28933 Info: at iteration #15: temp = 0.000000, timing cost = 553, wirelen = 27931 Info: at iteration #20: temp = 0.000000, timing cost = 538, wirelen = 27235 Info: at iteration #25: temp = 0.000000, timing cost = 531, wirelen = 27009 Info: at iteration #30: temp = 0.000000, timing cost = 528, wirelen = 26956 Info: at iteration #35: temp = 0.000000, timing cost = 528, wirelen = 26923 Info: at iteration #35: temp = 0.000000, timing cost = 528, wirelen = 26923 Info: SA placement time 7.62s Info: Max frequency for clock 'clk_sys': 32.09 MHz (PASS at 30.72 MHz) Info: Max frequency for clock 'clk_48m': 52.63 MHz (PASS at 48.00 MHz) Info: Max delay -> posedge clk_sys: 7.02 ns Info: Max delay posedge clk_48m -> : 4.04 ns Info: Max delay posedge clk_48m -> posedge clk_sys: 6.84 ns Info: Max delay posedge clk_sys -> : 10.88 ns Info: Max delay posedge clk_sys -> posedge clk_48m: 14.67 ns Info: Slack histogram: Info: legend: * represents 54 endpoint(s) Info: + represents [1,54) endpoint(s) Info: [ 1388, 5328) |+ Info: [ 5328, 9268) |*****+ Info: [ 9268, 13208) |***********+ Info: [ 13208, 17148) |******************************+ Info: [ 17148, 21088) |***********************+ Info: [ 21088, 25028) |*******************************+ Info: [ 25028, 28968) |************************************************************ Info: [ 28968, 32908) |**+ Info: [ 32908, 36848) | Info: [ 36848, 40788) | Info: [ 40788, 44728) | Info: [ 44728, 48668) | Info: [ 48668, 52608) | Info: [ 52608, 56548) | Info: [ 56548, 60488) | Info: [ 60488, 64428) | Info: [ 64428, 68368) | Info: [ 68368, 72308) | Info: [ 72308, 76248) |+ Info: [ 76248, 80188) |+ Info: Checksum: 0xfdcf52fe Info: Routing.. Info: Setting up routing queue. Info: Routing 15482 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 1000 | 20 979 | 20 979 | 14510| 0.14 0.14| Info: 2000 | 36 1963 | 16 984 | 13529| 0.10 0.23| Info: 3000 | 115 2884 | 79 921 | 12630| 0.27 0.50| Info: 4000 | 265 3734 | 150 850 | 11817| 0.24 0.74| Info: 5000 | 403 4596 | 138 862 | 10996| 0.27 1.01| Info: 6000 | 600 5399 | 197 803 | 10283| 0.34 1.35| Info: 7000 | 777 6222 | 177 823 | 9548| 0.30 1.65| Info: 8000 | 1060 6939 | 283 717 | 8990| 0.28 1.94| Info: 9000 | 1368 7631 | 308 692 | 8441| 0.32 2.25| Info: 10000 | 1629 8370 | 261 739 | 7807| 0.36 2.61| Info: 11000 | 2056 8943 | 427 573 | 7520| 0.59 3.20| Info: 12000 | 2483 9516 | 427 573 | 7165| 0.52 3.72| Info: 13000 | 2985 10014 | 502 498 | 6934| 0.47 4.19| Info: 14000 | 3449 10550 | 464 536 | 6726| 0.48 4.67| Info: 15000 | 3997 11002 | 548 452 | 6609| 0.41 5.08| Info: 16000 | 4544 11455 | 547 453 | 6415| 0.45 5.54| Info: 17000 | 5053 11946 | 509 491 | 6256| 0.69 6.22| Info: 18000 | 5634 12365 | 581 419 | 6108| 0.70 6.92| Info: 19000 | 5936 13063 | 302 698 | 5569| 0.47 7.38| Info: 20000 | 6446 13553 | 510 490 | 5368| 0.81 8.19| Info: 21000 | 6739 14260 | 293 707 | 4785| 0.37 8.56| Info: 22000 | 7232 14767 | 493 507 | 4517| 0.90 9.46| Info: 23000 | 7751 15248 | 519 481 | 4399| 1.21 10.67| Info: 24000 | 8329 15670 | 578 422 | 4295| 0.60 11.27| Info: 25000 | 8925 16074 | 596 404 | 4305| 0.79 12.06| Info: 26000 | 9558 16441 | 633 367 | 4242| 1.17 13.23| Info: 27000 | 10152 16847 | 594 406 | 4169| 1.15 14.38| Info: 28000 | 10739 17260 | 587 413 | 4069| 1.01 15.39| Info: 29000 | 11330 17669 | 591 409 | 3950| 0.86 16.25| Info: 30000 | 11907 18092 | 577 423 | 3909| 0.74 16.99| Info: 31000 | 12504 18495 | 597 403 | 3842| 0.68 17.67| Info: 32000 | 13114 18885 | 610 390 | 3776| 1.37 19.04| Info: 33000 | 13750 19249 | 636 364 | 3783| 0.97 20.00| Info: 34000 | 14330 19669 | 580 420 | 3728| 0.89 20.89| Info: 35000 | 14913 20086 | 583 417 | 3640| 0.97 21.86| Info: 36000 | 15511 20488 | 598 402 | 3526| 0.62 22.49| Info: 37000 | 16054 20945 | 543 457 | 3408| 0.55 23.04| Info: 38000 | 16688 21311 | 634 366 | 3402| 0.82 23.86| Info: 39000 | 17312 21687 | 624 376 | 3376| 0.91 24.77| Info: 40000 | 17846 22153 | 534 466 | 3276| 0.77 25.54| Info: 41000 | 18444 22555 | 598 402 | 3232| 0.87 26.41| Info: 42000 | 19031 22968 | 587 413 | 3159| 0.65 27.06| Info: 43000 | 19574 23425 | 543 457 | 3064| 0.69 27.74| Info: 44000 | 20183 23816 | 609 391 | 2986| 0.77 28.51| Info: 45000 | 20760 24239 | 577 423 | 2915| 0.54 29.05| Info: 46000 | 21338 24661 | 578 422 | 2827| 0.73 29.78| Info: 47000 | 21995 25004 | 657 343 | 2813| 0.83 30.61| Info: 48000 | 22564 25435 | 569 431 | 2710| 0.74 31.36| Info: 49000 | 23153 25846 | 589 411 | 2600| 0.68 32.04| Info: 50000 | 23503 26496 | 350 650 | 2089| 0.38 32.42| Info: 51000 | 23889 27110 | 386 614 | 1581| 0.28 32.70| Info: 52000 | 24447 27552 | 558 442 | 1434| 0.71 33.41| Info: 53000 | 25049 27950 | 602 398 | 1393| 0.64 34.04| Info: 54000 | 25491 28508 | 442 558 | 1070| 0.87 34.92| Info: 55000 | 26053 28946 | 562 438 | 906| 3.35 38.27| Info: 56000 | 26554 29445 | 501 499 | 645| 4.58 42.85| Info: 57000 | 27152 29847 | 598 402 | 531| 2.53 45.38| Info: 58000 | 27604 30395 | 452 548 | 210| 1.36 46.74| Info: 58217 | 27611 30606 | 7 211 | 0| 0.06 46.79| Info: Routing complete. Info: Router1 time 46.79s Info: Checksum: 0x0fc9cf3f Info: Critical path report for clock 'clk_sys' (posedge -> posedge): Info: curr total Info: 1.4 1.4 Source soc_I.cpu_I.mem_do_rinst_SB_DFFESS_Q_conv_LC.O Info: 4.8 6.2 Net soc_I.cpu_I.mem_do_rinst budget 1.349000 ns (3,13) -> (12,18) Info: Sink soc_I.cpu_I.mem_do_rinst_SB_LUT4_I3_LC.I3 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:340.6-340.18 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: 0.9 7.1 Source soc_I.cpu_I.mem_do_rinst_SB_LUT4_I3_LC.O Info: 4.2 11.3 Net soc_I.cpu_I.mem_do_rinst_SB_LUT4_I3_O[3] budget 1.256000 ns (12,18) -> (5,12) Info: Sink soc_I.cpu_I.instr_sb_SB_LUT4_I2_I3_SB_LUT4_O_I1_SB_LUT4_O_LC.I3 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.9 12.2 Source soc_I.cpu_I.instr_sb_SB_LUT4_I2_I3_SB_LUT4_O_I1_SB_LUT4_O_LC.O Info: 1.8 13.9 Net soc_I.cpu_I.instr_sb_SB_LUT4_I2_I3_SB_LUT4_O_I1[0] budget 1.833000 ns (5,12) -> (4,11) Info: Sink soc_I.cpu_I.instr_sb_SB_LUT4_I2_I3_SB_LUT4_O_LC.I1 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 1.2 15.1 Source soc_I.cpu_I.instr_sb_SB_LUT4_I2_I3_SB_LUT4_O_LC.O Info: 1.8 16.9 Net soc_I.cpu_I.instr_sb_SB_LUT4_I2_I3[2] budget 1.350000 ns (4,11) -> (4,12) Info: Sink soc_I.cpu_I.instr_sb_SB_LUT4_I2_I3_SB_LUT4_I0_LC.I0 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 1.3 18.2 Source soc_I.cpu_I.instr_sb_SB_LUT4_I2_I3_SB_LUT4_I0_LC.O Info: 3.7 21.9 Net soc_I.cpu_I.instr_lhu_SB_LUT4_I1_O_SB_LUT4_O_I1[1] budget 3.140000 ns (4,12) -> (4,20) Info: Sink soc_I.cpu_I.alu_wait_SB_LUT4_I1_O_SB_LUT4_I1_LC.I2 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 1.2 23.1 Source soc_I.cpu_I.alu_wait_SB_LUT4_I1_O_SB_LUT4_I1_LC.O Info: 1.8 24.9 Net soc_I.cpu_I.alu_wait_SB_LUT4_I1_O_SB_LUT4_I1_O[3] budget 1.687000 ns (4,20) -> (5,19) Info: Sink soc_I.cpu_I.instr_sra_SB_LUT4_I0_LC.I3 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.9 25.7 Source soc_I.cpu_I.instr_sra_SB_LUT4_I0_LC.O Info: 5.2 31.0 Net soc_I.cpu_I.reg_op1_SB_DFFE_Q_31_E budget 1.885000 ns (5,19) -> (22,14) Info: Sink soc_I.cpu_I.reg_op1_SB_DFFE_Q_31_conv_LC.I2 Info: 1.2 32.1 Setup soc_I.cpu_I.reg_op1_SB_DFFE_Q_31_conv_LC.I2 Info: 8.9 ns logic, 23.2 ns routing Info: Critical path report for clock 'clk_48m' (posedge -> posedge): Info: curr total Info: 1.2 1.2 Source soc_I.usb_I.trans_I.mc_rom_I_RAM.RDATA_6 Info: 3.1 4.2 Net soc_I.usb_I.trans_I.mc_opcode[6] budget 1.961000 ns (19,11) -> (20,10) Info: Sink soc_I.usb_I.trans_I.mc_match_bits_SB_LUT4_O_1_LC.I1 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:91.14-91.23 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: 1.2 5.5 Source soc_I.usb_I.trans_I.mc_match_bits_SB_LUT4_O_1_LC.O Info: 1.8 7.2 Net soc_I.usb_I.trans_I.mc_match_bits[2] budget 1.305000 ns (20,10) -> (20,10) Info: Sink soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_I0_SB_LUT4_O_LC.I2 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:85.32-85.45 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: 1.2 8.4 Source soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_I0_SB_LUT4_O_LC.O Info: 1.8 10.2 Net soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_I0[0] budget 1.371000 ns (20,10) -> (20,11) Info: Sink soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_LC.I0 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 1.3 11.5 Source soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_LC.O Info: 1.8 13.2 Net soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_O[2] budget 1.305000 ns (20,11) -> (21,12) Info: Sink soc_I.usb_I.trans_I.mc_pc_SB_LUT4_O_7_LC.I2 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 1.2 14.4 Source soc_I.usb_I.trans_I.mc_pc_SB_LUT4_O_7_LC.O Info: 1.8 16.2 Net soc_I.usb_I.trans_I.mc_pc[0] budget 1.306000 ns (21,12) -> (22,11) Info: Sink $nextpnr_ICESTORM_LC_196.I1 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.7 16.9 Source $nextpnr_ICESTORM_LC_196.COUT Info: 0.0 16.9 Net $nextpnr_ICESTORM_LC_196$O budget 0.000000 ns (22,11) -> (22,11) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_6_LC.CIN Info: 0.3 17.2 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_6_LC.COUT Info: 0.0 17.2 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[2] budget 0.000000 ns (22,11) -> (22,11) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_5_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 17.4 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_5_LC.COUT Info: 0.0 17.4 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[3] budget 0.000000 ns (22,11) -> (22,11) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_4_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 17.7 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_4_LC.COUT Info: 0.0 17.7 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[4] budget 0.000000 ns (22,11) -> (22,11) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_3_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 18.0 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_3_LC.COUT Info: 0.0 18.0 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[5] budget 0.000000 ns (22,11) -> (22,11) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_2_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 18.3 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_2_LC.COUT Info: 0.0 18.3 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[6] budget 0.000000 ns (22,11) -> (22,11) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_1_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 18.5 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_1_LC.COUT Info: 0.7 19.2 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[7] budget 0.660000 ns (22,11) -> (22,11) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_LC.I3 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.8 20.0 Setup soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_LC.I3 Info: 9.3 ns logic, 10.8 ns routing Info: Critical path report for cross-domain path '' -> 'posedge clk_sys': Info: curr total Info: 0.0 0.0 Source spi_mux_I.iob_I[3].D_IN_0 Info: 8.2 8.2 Net flash_mosi_i budget 31.052000 ns (23,0) -> (0,0) Info: Sink soc_I.spi_I.spi_I.SI Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:374.4-400.3 Info: /build/gateware/icE1usb/rtl/sr_btn_if.v:28.14-28.24 Info: 1.5 9.7 Setup soc_I.spi_I.spi_I.SI Info: 1.5 ns logic, 8.2 ns routing Info: Critical path report for cross-domain path 'posedge clk_48m' -> '': Info: curr total Info: 1.4 1.4 Source soc_I.usb_I.pad_pu_SB_DFFSR_Q_DFFLC.O Info: 2.4 3.8 Net usb_pu$SB_IO_OUT budget 81.943001 ns (17,2) -> (17,0) Info: Sink usb_pu$sb_io.D_OUT_0 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:39.14-39.20 Info: 1.4 ns logic, 2.4 ns routing Info: Critical path report for cross-domain path 'posedge clk_48m' -> 'posedge clk_sys': Info: curr total Info: 1.4 1.4 Source soc_I.usb_I.sof_ind_SB_LUT4_I3_LC.O Info: 4.2 5.6 Net soc_I.sof_xclk_I.src budget 29.927999 ns (16,13) -> (14,1) Info: Sink soc_I.sof_xclk_I.dst_SB_DFFR_Q_1_DFFLC.I0 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/cores/no2misc//rtl/xclk_strobe.v:25.6-25.9 Info: /build/gateware/common/rtl/soc_base.v:421.14-427.3 Info: 1.2 6.9 Setup soc_I.sof_xclk_I.dst_SB_DFFR_Q_1_DFFLC.I0 Info: 2.6 ns logic, 4.2 ns routing Info: Critical path report for cross-domain path 'posedge clk_sys' -> '': Info: curr total Info: 1.5 1.5 Source soc_I.spi_I.spi_I.MCSNO0 Info: 8.7 10.2 Net flash_csn_o budget 40.313999 ns (0,0) -> (22,1) Info: Sink flash_cs_n_SB_LUT4_O_LC.I2 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:374.4-400.3 Info: /build/gateware/icE1usb/rtl/sr_btn_if.v:40.14-40.23 Info: 1.2 11.4 Source flash_cs_n_SB_LUT4_O_LC.O Info: 3.0 14.3 Net flash_cs_n$SB_IO_OUT budget 38.368999 ns (22,1) -> (24,0) Info: Sink flash_cs_n$sb_io.D_OUT_0 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:374.4-400.3 Info: /build/gateware/icE1usb/rtl/sr_btn_if.v:90.7-90.16 Info: 2.7 ns logic, 11.6 ns routing Info: Critical path report for cross-domain path 'posedge clk_sys' -> 'posedge clk_48m': Info: curr total Info: 1.4 1.4 Source soc_I.cpu_I.mem_wstrb_SB_DFFE_Q_conv_LC.O Info: 4.2 5.6 Net wb_wmsk[3] budget 3.604000 ns (13,26) -> (16,15) Info: Sink gps_uart_I.wb_we_SB_LUT4_O_LC.I3 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:94.18-94.25 Info: 0.9 6.5 Source gps_uart_I.wb_we_SB_LUT4_O_LC.O Info: 3.1 9.6 Net wb_we budget 5.229000 ns (16,15) -> (16,10) Info: Sink soc_I.usb_I.cr_bus_we_SB_DFFSR_Q_D_SB_LUT4_O_LC.I2 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:95.18-95.23 Info: 1.2 10.8 Source soc_I.usb_I.cr_bus_we_SB_DFFSR_Q_D_SB_LUT4_O_LC.O Info: 1.8 12.5 Net soc_I.usb_I.cr_bus_we_SB_DFFSR_Q_D[1] budget 3.679000 ns (16,10) -> (16,9) Info: Sink soc_I.usb_I.cr_bus_we_SB_DFFSR_Q_conv_LC.I3 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.8 13.4 Setup soc_I.usb_I.cr_bus_we_SB_DFFSR_Q_conv_LC.I3 Info: 4.3 ns logic, 9.1 ns routing Info: Max frequency for clock 'clk_sys': 31.14 MHz (PASS at 30.72 MHz) Info: Max frequency for clock 'clk_48m': 49.92 MHz (PASS at 48.00 MHz) Info: Max delay -> posedge clk_sys: 9.68 ns Info: Max delay posedge clk_48m -> : 3.80 ns Info: Max delay posedge clk_48m -> posedge clk_sys: 6.87 ns Info: Max delay posedge clk_sys -> : 14.34 ns Info: Max delay posedge clk_sys -> posedge clk_48m: 13.36 ns Info: Slack histogram: Info: legend: * represents 56 endpoint(s) Info: + represents [1,56) endpoint(s) Info: [ 361, 4353) |+ Info: [ 4353, 8345) |***+ Info: [ 8345, 12337) |********+ Info: [ 12337, 16329) |*********************+ Info: [ 16329, 20321) |***********************+ Info: [ 20321, 24313) |************************************+ Info: [ 24313, 28305) |************************************************************ Info: [ 28305, 32297) |*****+ Info: [ 32297, 36289) | Info: [ 36289, 40281) | Info: [ 40281, 44273) | Info: [ 44273, 48265) | Info: [ 48265, 52257) | Info: [ 52257, 56249) | Info: [ 56249, 60241) | Info: [ 60241, 64233) | Info: [ 64233, 68225) | Info: [ 68225, 72217) |+ Info: [ 72217, 76209) |+ Info: [ 76209, 80201) |+ 4 warnings, 0 errors icepack -s /build/gateware/icE1usb/build-tmp/icE1usb.asc /build/gateware/icE1usb/build-tmp/icE1usb.bin make: Leaving directory '/build/gateware/icE1usb' $ ssh-agent -k unset SSH_AUTH_SOCK; unset SSH_AGENT_PID; echo Agent pid 3816452 killed; [ssh-agent] Stopped. Archiving artifacts ‘**/core’ doesn’t match anything: ‘**’ exists but not ‘**/core’ No artifacts found that match the file pattern "**/core, **/testsuite.log, **/workspace.tar.xz". Configuration error? Finished: SUCCESS