1 .cpu arm7tdmi 2 .arch armv4t 3 .fpu softvfp 4 .eabi_attribute 20, 1 5 .eabi_attribute 21, 1 6 .eabi_attribute 23, 3 7 .eabi_attribute 24, 1 8 .eabi_attribute 25, 1 9 .eabi_attribute 26, 1 10 .eabi_attribute 30, 4 11 .eabi_attribute 34, 0 12 .eabi_attribute 18, 4 13 .file "init.c" 14 .text 15 .Ltext0: 16 .cfi_sections .debug_frame 17 .file 1 "board/fcdev3b/init.c" 18 .section .text.board_init,"ax",%progbits 19 .align 2 20 .global board_init 21 .syntax unified 22 .arm 24 board_init: 25 .LVL0: 26 .LFB63: 1:board/fcdev3b/init.c **** /* Initialization for the FreeCalypso FCDEV3B modem */ 2:board/fcdev3b/init.c **** 3:board/fcdev3b/init.c **** /* Based on board/gta0x/init.c with the following obnoxious legalese: 4:board/fcdev3b/init.c **** * 5:board/fcdev3b/init.c **** * (C) 2010 by Harald Welte 6:board/fcdev3b/init.c **** * 7:board/fcdev3b/init.c **** * All Rights Reserved 8:board/fcdev3b/init.c **** * 9:board/fcdev3b/init.c **** * This program is free software; you can redistribute it and/or modify 10:board/fcdev3b/init.c **** * it under the terms of the GNU General Public License as published by 11:board/fcdev3b/init.c **** * the Free Software Foundation; either version 2 of the License, or 12:board/fcdev3b/init.c **** * (at your option) any later version. 13:board/fcdev3b/init.c **** * 14:board/fcdev3b/init.c **** * This program is distributed in the hope that it will be useful, 15:board/fcdev3b/init.c **** * but WITHOUT ANY WARRANTY; without even the implied warranty of 16:board/fcdev3b/init.c **** * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17:board/fcdev3b/init.c **** * GNU General Public License for more details. 18:board/fcdev3b/init.c **** * 19:board/fcdev3b/init.c **** */ 20:board/fcdev3b/init.c **** 21:board/fcdev3b/init.c **** #include 22:board/fcdev3b/init.c **** #include 23:board/fcdev3b/init.c **** 24:board/fcdev3b/init.c **** #include 25:board/fcdev3b/init.c **** #include 26:board/fcdev3b/init.c **** #include 27:board/fcdev3b/init.c **** #include 28:board/fcdev3b/init.c **** #include 29:board/fcdev3b/init.c **** #include 30:board/fcdev3b/init.c **** #include 31:board/fcdev3b/init.c **** #include 32:board/fcdev3b/init.c **** 33:board/fcdev3b/init.c **** #include 34:board/fcdev3b/init.c **** #include 35:board/fcdev3b/init.c **** #include 36:board/fcdev3b/init.c **** #include 37:board/fcdev3b/init.c **** #include 38:board/fcdev3b/init.c **** #include 39:board/fcdev3b/init.c **** 40:board/fcdev3b/init.c **** #include 41:board/fcdev3b/init.c **** #include 42:board/fcdev3b/init.c **** 43:board/fcdev3b/init.c **** #include 44:board/fcdev3b/init.c **** #include 45:board/fcdev3b/init.c **** 46:board/fcdev3b/init.c **** #define ARMIO_LATCH_OUT 0xfffe4802 47:board/fcdev3b/init.c **** #define IO_CNTL_REG 0xfffe4804 48:board/fcdev3b/init.c **** #define ARM_CONF_REG 0xfffef006 49:board/fcdev3b/init.c **** #define ASIC_CONF_REG 0xfffef008 50:board/fcdev3b/init.c **** #define IO_CONF_REG 0xfffef00a 51:board/fcdev3b/init.c **** 52:board/fcdev3b/init.c **** static void board_io_init(void) 53:board/fcdev3b/init.c **** { 54:board/fcdev3b/init.c **** uint16_t reg; 55:board/fcdev3b/init.c **** 56:board/fcdev3b/init.c **** reg = readw(ASIC_CONF_REG); 57:board/fcdev3b/init.c **** /* TWL3025: Set SPI+RIF RX clock to rising edge */ 58:board/fcdev3b/init.c **** reg |= (1 << 13) | (1 << 14); 59:board/fcdev3b/init.c **** writew(reg, ASIC_CONF_REG); 60:board/fcdev3b/init.c **** 61:board/fcdev3b/init.c **** /* 62:board/fcdev3b/init.c **** * Most Calypso peripheral interface signals are unconnected 63:board/fcdev3b/init.c **** * on this modem. We configure them to be GPIOs in IO_CONF_REG, 64:board/fcdev3b/init.c **** * then configure them to be outputs in IO_CNTL_REG, then set 65:board/fcdev3b/init.c **** * the outputs to 0 in ARMIO_LATCH_OUT. 66:board/fcdev3b/init.c **** * 67:board/fcdev3b/init.c **** * Differences from Openmoko GTA0x: 68:board/fcdev3b/init.c **** * 69:board/fcdev3b/init.c **** * GPIO1 output needs to be 1 to enable the loudspeaker amplifier 70:board/fcdev3b/init.c **** * GPIO3 needs to be configured as an input 71:board/fcdev3b/init.c **** * I/O 9-12 are MCSI rather than GPIOs 72:board/fcdev3b/init.c **** */ 73:board/fcdev3b/init.c **** writew(0x0215, IO_CONF_REG); 74:board/fcdev3b/init.c **** writew(0xDC08, IO_CNTL_REG); 75:board/fcdev3b/init.c **** writew(0x0002, ARMIO_LATCH_OUT); 76:board/fcdev3b/init.c **** 77:board/fcdev3b/init.c **** /* configure ADD(22), needed for second half of flash */ 78:board/fcdev3b/init.c **** reg = readw(ARM_CONF_REG); 79:board/fcdev3b/init.c **** reg |= (1 << 3); 80:board/fcdev3b/init.c **** writew(reg, ARM_CONF_REG); 81:board/fcdev3b/init.c **** } 82:board/fcdev3b/init.c **** 83:board/fcdev3b/init.c **** void board_init(int with_irq) 84:board/fcdev3b/init.c **** { 27 .loc 1 84 1 view -0 28 .cfi_startproc 29 @ Function supports interworking. 30 @ args = 0, pretend = 0, frame = 0 31 @ frame_needed = 0, uses_anonymous_args = 0 85:board/fcdev3b/init.c **** /* Configure the memory interface */ 86:board/fcdev3b/init.c **** /* Using the same settings as the official FreeCalypso fw */ 87:board/fcdev3b/init.c **** calypso_mem_cfg(CALYPSO_nCS0, 4, CALYPSO_MEM_16bit, 1); 32 .loc 1 87 2 view .LVU1 84:board/fcdev3b/init.c **** /* Configure the memory interface */ 33 .loc 1 84 1 is_stmt 0 view .LVU2 34 0000 1F402DE9 push {r0, r1, r2, r3, r4, lr} 35 .LCFI0: 36 .cfi_def_cfa_offset 24 37 .cfi_offset 4, -8 38 .cfi_offset 14, -4 39 .loc 1 87 2 view .LVU3 40 0004 0130A0E3 mov r3, #1 84:board/fcdev3b/init.c **** /* Configure the memory interface */ 41 .loc 1 84 1 view .LVU4 42 0008 0040A0E1 mov r4, r0 43 .loc 1 87 2 view .LVU5 44 000c 0320A0E1 mov r2, r3 45 0010 0410A0E3 mov r1, #4 46 0014 0000A0E3 mov r0, #0 47 .LVL1: 48 .loc 1 87 2 view .LVU6 49 0018 FEFFFFEB bl calypso_mem_cfg 50 .LVL2: 88:board/fcdev3b/init.c **** calypso_mem_cfg(CALYPSO_nCS1, 4, CALYPSO_MEM_16bit, 1); 51 .loc 1 88 2 is_stmt 1 view .LVU7 52 001c 0130A0E3 mov r3, #1 53 0020 0410A0E3 mov r1, #4 54 0024 0320A0E1 mov r2, r3 55 0028 0200A0E3 mov r0, #2 56 002c FEFFFFEB bl calypso_mem_cfg 57 .LVL3: 89:board/fcdev3b/init.c **** calypso_mem_cfg(CALYPSO_nCS2, 4, CALYPSO_MEM_16bit, 1); 58 .loc 1 89 2 view .LVU8 59 0030 0130A0E3 mov r3, #1 60 0034 0410A0E3 mov r1, #4 61 0038 0320A0E1 mov r2, r3 62 003c 0100A0E1 mov r0, r1 63 0040 FEFFFFEB bl calypso_mem_cfg 64 .LVL4: 90:board/fcdev3b/init.c **** calypso_mem_cfg(CALYPSO_nCS3, 4, CALYPSO_MEM_16bit, 1); 65 .loc 1 90 2 view .LVU9 66 0044 0130A0E3 mov r3, #1 67 0048 0410A0E3 mov r1, #4 68 004c 0320A0E1 mov r2, r3 69 0050 0600A0E3 mov r0, #6 70 0054 FEFFFFEB bl calypso_mem_cfg 71 .LVL5: 91:board/fcdev3b/init.c **** calypso_mem_cfg(CALYPSO_CS4, 4, CALYPSO_MEM_16bit, 1); 72 .loc 1 91 2 view .LVU10 73 0058 0130A0E3 mov r3, #1 74 005c 0410A0E3 mov r1, #4 75 0060 0320A0E1 mov r2, r3 76 0064 0A00A0E3 mov r0, #10 77 0068 FEFFFFEB bl calypso_mem_cfg 78 .LVL6: 92:board/fcdev3b/init.c **** calypso_mem_cfg(CALYPSO_nCS6, 0, CALYPSO_MEM_32bit, 1); 79 .loc 1 92 2 view .LVU11 80 006c 0130A0E3 mov r3, #1 81 0070 0220A0E3 mov r2, #2 82 0074 0010A0E3 mov r1, #0 83 0078 0C00A0E3 mov r0, #12 84 007c FEFFFFEB bl calypso_mem_cfg 85 .LVL7: 93:board/fcdev3b/init.c **** calypso_mem_cfg(CALYPSO_nCS7, 0, CALYPSO_MEM_32bit, 0); 86 .loc 1 93 2 view .LVU12 87 0080 0030A0E3 mov r3, #0 88 0084 0220A0E3 mov r2, #2 89 0088 0310A0E1 mov r1, r3 90 008c 0800A0E3 mov r0, #8 91 0090 FEFFFFEB bl calypso_mem_cfg 92 .LVL8: 94:board/fcdev3b/init.c **** 95:board/fcdev3b/init.c **** /* Set VTCXO_DIV2 = 1, configure PLL for 104 MHz and give ARM half of that */ 96:board/fcdev3b/init.c **** calypso_clock_set(2, CALYPSO_PLL13_104_MHZ, ARM_MCLK_DIV_2); 93 .loc 1 96 2 view .LVU13 94 0094 0220A0E3 mov r2, #2 95 0098 021BA0E3 mov r1, #2048 96 009c 0200A0E1 mov r0, r2 97 00a0 FEFFFFEB bl calypso_clock_set 98 .LVL9: 97:board/fcdev3b/init.c **** 98:board/fcdev3b/init.c **** /* Configure the RHEA bridge with some sane default values */ 99:board/fcdev3b/init.c **** calypso_rhea_cfg(0, 0, 0xff, 0, 1, 0, 0); 99 .loc 1 99 2 view .LVU14 100 00a4 0030A0E3 mov r3, #0 101 00a8 0120A0E3 mov r2, #1 102 00ac 0310A0E1 mov r1, r3 103 00b0 0300A0E1 mov r0, r3 104 00b4 08308DE5 str r3, [sp, #8] 105 00b8 04308DE5 str r3, [sp, #4] 106 00bc 00208DE5 str r2, [sp] 107 00c0 FF20A0E3 mov r2, #255 108 00c4 FEFFFFEB bl calypso_rhea_cfg 109 .LVL10: 100:board/fcdev3b/init.c **** 101:board/fcdev3b/init.c **** /* Initialize board-specific GPIO */ 102:board/fcdev3b/init.c **** board_io_init(); 110 .loc 1 102 2 view .LVU15 111 .LBB4: 112 .LBI4: 52:board/fcdev3b/init.c **** { 113 .loc 1 52 13 view .LVU16 114 .LBB5: 54:board/fcdev3b/init.c **** 115 .loc 1 54 2 view .LVU17 56:board/fcdev3b/init.c **** /* TWL3025: Set SPI+RIF RX clock to rising edge */ 116 .loc 1 56 2 view .LVU18 56:board/fcdev3b/init.c **** /* TWL3025: Set SPI+RIF RX clock to rising edge */ 117 .loc 1 56 6 is_stmt 0 view .LVU19 118 00c8 B8309FE5 ldr r3, .L7 119 00cc B72F53E1 ldrh r2, [r3, #-247] 120 .LVL11: 58:board/fcdev3b/init.c **** writew(reg, ASIC_CONF_REG); 121 .loc 1 58 2 is_stmt 1 view .LVU20 58:board/fcdev3b/init.c **** writew(reg, ASIC_CONF_REG); 122 .loc 1 58 6 is_stmt 0 view .LVU21 123 00d0 062A82E3 orr r2, r2, #24576 124 .LVL12: 59:board/fcdev3b/init.c **** 125 .loc 1 59 2 is_stmt 1 view .LVU22 126 00d4 B72F43E1 strh r2, [r3, #-247] @ movhi 73:board/fcdev3b/init.c **** writew(0xDC08, IO_CNTL_REG); 127 .loc 1 73 2 view .LVU23 128 00d8 AC209FE5 ldr r2, .L7+4 129 .LVL13: 74:board/fcdev3b/init.c **** writew(0x0002, ARMIO_LATCH_OUT); 130 .loc 1 74 2 is_stmt 0 view .LVU24 131 00dc AC109FE5 ldr r1, .L7+8 73:board/fcdev3b/init.c **** writew(0xDC08, IO_CNTL_REG); 132 .loc 1 73 2 view .LVU25 133 00e0 B52F43E1 strh r2, [r3, #-245] @ movhi 134 .LVL14: 74:board/fcdev3b/init.c **** writew(0x0002, ARMIO_LATCH_OUT); 135 .loc 1 74 2 is_stmt 1 view .LVU26 136 00e4 A8209FE5 ldr r2, .L7+12 137 00e8 BB1F42E1 strh r1, [r2, #-251] @ movhi 75:board/fcdev3b/init.c **** 138 .loc 1 75 2 view .LVU27 139 00ec 0210A0E3 mov r1, #2 140 00f0 BD1F42E1 strh r1, [r2, #-253] @ movhi 78:board/fcdev3b/init.c **** reg |= (1 << 3); 141 .loc 1 78 2 view .LVU28 78:board/fcdev3b/init.c **** reg |= (1 << 3); 142 .loc 1 78 6 is_stmt 0 view .LVU29 143 00f4 B92F53E1 ldrh r2, [r3, #-249] 144 .LVL15: 79:board/fcdev3b/init.c **** writew(reg, ARM_CONF_REG); 145 .loc 1 79 2 is_stmt 1 view .LVU30 79:board/fcdev3b/init.c **** writew(reg, ARM_CONF_REG); 146 .loc 1 79 6 is_stmt 0 view .LVU31 147 00f8 082082E3 orr r2, r2, #8 148 .LVL16: 80:board/fcdev3b/init.c **** } 149 .loc 1 80 2 is_stmt 1 view .LVU32 150 .LBE5: 151 .LBE4: 103:board/fcdev3b/init.c **** 104:board/fcdev3b/init.c **** /* Enable bootrom mapping to route exception vectors to RAM */ 105:board/fcdev3b/init.c **** calypso_bootrom(with_irq); 152 .loc 1 105 2 is_stmt 0 view .LVU33 153 00fc 0400A0E1 mov r0, r4 154 .LBB7: 155 .LBB6: 80:board/fcdev3b/init.c **** } 156 .loc 1 80 2 view .LVU34 157 0100 B92F43E1 strh r2, [r3, #-249] @ movhi 158 .LVL17: 80:board/fcdev3b/init.c **** } 159 .loc 1 80 2 view .LVU35 160 .LBE6: 161 .LBE7: 162 .loc 1 105 2 is_stmt 1 view .LVU36 163 0104 FEFFFFEB bl calypso_bootrom 164 .LVL18: 106:board/fcdev3b/init.c **** calypso_exceptions_install(); 165 .loc 1 106 2 view .LVU37 166 0108 FEFFFFEB bl calypso_exceptions_install 167 .LVL19: 107:board/fcdev3b/init.c **** 108:board/fcdev3b/init.c **** /* Initialize interrupt controller */ 109:board/fcdev3b/init.c **** if (with_irq) 168 .loc 1 109 2 view .LVU38 169 .loc 1 109 5 is_stmt 0 view .LVU39 170 010c 000054E3 cmp r4, #0 110:board/fcdev3b/init.c **** irq_init(); 171 .loc 1 110 3 is_stmt 1 view .LVU40 172 0110 FEFFFF1B blne irq_init 173 .LVL20: 174 .L2: 111:board/fcdev3b/init.c **** 112:board/fcdev3b/init.c **** sercomm_bind_uart(UART_MODEM); 175 .loc 1 112 2 view .LVU41 176 0114 0100A0E3 mov r0, #1 177 0118 FEFFFFEB bl sercomm_bind_uart 178 .LVL21: 113:board/fcdev3b/init.c **** cons_bind_uart(UART_IRDA); 179 .loc 1 113 2 view .LVU42 114:board/fcdev3b/init.c **** 115:board/fcdev3b/init.c **** /* initialize MODEM UART to be used for sercomm */ 116:board/fcdev3b/init.c **** uart_init(UART_MODEM, with_irq); 180 .loc 1 116 2 is_stmt 0 view .LVU43 181 011c FF4004E2 and r4, r4, #255 182 .LVL22: 113:board/fcdev3b/init.c **** cons_bind_uart(UART_IRDA); 183 .loc 1 113 2 view .LVU44 184 0120 0000A0E3 mov r0, #0 185 0124 FEFFFFEB bl cons_bind_uart 186 .LVL23: 187 .loc 1 116 2 is_stmt 1 view .LVU45 188 0128 0410A0E1 mov r1, r4 189 012c 0100A0E3 mov r0, #1 190 0130 FEFFFFEB bl uart_init 191 .LVL24: 117:board/fcdev3b/init.c **** uart_baudrate(UART_MODEM, UART_115200); 192 .loc 1 117 2 view .LVU46 193 0134 0210A0E3 mov r1, #2 194 0138 0100A0E3 mov r0, #1 195 013c FEFFFFEB bl uart_baudrate 196 .LVL25: 118:board/fcdev3b/init.c **** 119:board/fcdev3b/init.c **** /* Initialize IRDA UART to be used for old-school console code. 120:board/fcdev3b/init.c **** * note: IRDA uart only accessible on C115 and C117 PCB */ 121:board/fcdev3b/init.c **** uart_init(UART_IRDA, with_irq); 197 .loc 1 121 2 view .LVU47 198 0140 0410A0E1 mov r1, r4 199 0144 0000A0E3 mov r0, #0 200 0148 FEFFFFEB bl uart_init 201 .LVL26: 122:board/fcdev3b/init.c **** uart_baudrate(UART_IRDA, UART_115200); 202 .loc 1 122 2 view .LVU48 203 014c 0210A0E3 mov r1, #2 204 0150 0000A0E3 mov r0, #0 205 0154 FEFFFFEB bl uart_baudrate 206 .LVL27: 123:board/fcdev3b/init.c **** 124:board/fcdev3b/init.c **** /* Initialize hardware timers */ 125:board/fcdev3b/init.c **** hwtimer_init(); 207 .loc 1 125 2 view .LVU49 208 0158 FEFFFFEB bl hwtimer_init 209 .LVL28: 126:board/fcdev3b/init.c **** 127:board/fcdev3b/init.c **** /* Initialize DMA controller */ 128:board/fcdev3b/init.c **** dma_init(); 210 .loc 1 128 2 view .LVU50 211 015c FEFFFFEB bl dma_init 212 .LVL29: 129:board/fcdev3b/init.c **** 130:board/fcdev3b/init.c **** /* Initialize real time clock */ 131:board/fcdev3b/init.c **** rtc_init(); 213 .loc 1 131 2 view .LVU51 214 0160 FEFFFFEB bl rtc_init 215 .LVL30: 132:board/fcdev3b/init.c **** 133:board/fcdev3b/init.c **** /* Initialize system timers (uses hwtimer 2) */ 134:board/fcdev3b/init.c **** timer_init(); 216 .loc 1 134 2 view .LVU52 217 0164 FEFFFFEB bl timer_init 218 .LVL31: 135:board/fcdev3b/init.c **** 136:board/fcdev3b/init.c **** /* Initialize ABB driver (uses SPI) */ 137:board/fcdev3b/init.c **** twl3025_init(); 219 .loc 1 137 2 view .LVU53 220 0168 FEFFFFEB bl twl3025_init 221 .LVL32: 138:board/fcdev3b/init.c **** 139:board/fcdev3b/init.c **** /* Initialize TIFFS reader (8 sectors of 256 KiB each) */ 140:board/fcdev3b/init.c **** tiffs_init(0x01800000, 0x40000, 8); 222 .loc 1 140 2 view .LVU54 223 016c 0820A0E3 mov r2, #8 224 0170 0117A0E3 mov r1, #262144 225 0174 0605A0E3 mov r0, #25165824 226 0178 FEFFFFEB bl tiffs_init 227 .LVL33: 141:board/fcdev3b/init.c **** } 228 .loc 1 141 1 is_stmt 0 view .LVU55 229 017c 10D08DE2 add sp, sp, #16 230 .LCFI1: 231 .cfi_def_cfa_offset 8 232 @ sp needed 233 0180 1040BDE8 pop {r4, lr} 234 .LCFI2: 235 .cfi_restore 14 236 .cfi_restore 4 237 .cfi_def_cfa_offset 0 238 0184 1EFF2FE1 bx lr 239 .L8: 240 .align 2 241 .L7: 242 0188 FFF0FEFF .word -69377 243 018c 15020000 .word 533 244 0190 08DCFFFF .word -9208 245 0194 FF48FEFF .word -112385 246 .cfi_endproc 247 .LFE63: 249 .text 250 .Letext0: 251 .file 2 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h" 252 .file 3 "include/calypso/clock.h" 253 .file 4 "include/uart.h" 254 .file 5 "include/abb/twl3025.h" 255 .file 6 "include/comm/timer.h" 256 .file 7 "include/calypso/rtc.h" 257 .file 8 "include/calypso/dma.h" 258 .file 9 "include/calypso/timer.h" 259 .file 10 "include/tiffs.h" 260 .file 11 "include/console.h" 261 .file 12 "include/comm/sercomm.h" 262 .file 13 "include/calypso/irq.h" DEFINED SYMBOLS *ABS*:00000000 init.c /tmp/ccvJuhmY.s:19 .text.board_init:00000000 $a /tmp/ccvJuhmY.s:24 .text.board_init:00000000 board_init /tmp/ccvJuhmY.s:242 .text.board_init:00000188 $d UNDEFINED SYMBOLS calypso_mem_cfg calypso_clock_set calypso_rhea_cfg calypso_bootrom calypso_exceptions_install irq_init sercomm_bind_uart cons_bind_uart uart_init uart_baudrate hwtimer_init dma_init rtc_init timer_init twl3025_init tiffs_init