1 .cpu arm7tdmi 2 .arch armv4t 3 .fpu softvfp 4 .eabi_attribute 20, 1 5 .eabi_attribute 21, 1 6 .eabi_attribute 23, 3 7 .eabi_attribute 24, 1 8 .eabi_attribute 25, 1 9 .eabi_attribute 26, 1 10 .eabi_attribute 30, 4 11 .eabi_attribute 34, 0 12 .eabi_attribute 18, 4 13 .file "init.c" 14 .text 15 .Ltext0: 16 .cfi_sections .debug_frame 17 .file 1 "board/pirelli_dpl10/init.c" 18 .section .text.board_init,"ax",%progbits 19 .align 2 20 .global board_init 21 .syntax unified 22 .arm 24 board_init: 25 .LVL0: 26 .LFB76: 1:board/pirelli_dpl10/init.c **** /* Initialization for the Pirelli DP-L10 */ 2:board/pirelli_dpl10/init.c **** 3:board/pirelli_dpl10/init.c **** /* (C) 2010 by Harald Welte 4:board/pirelli_dpl10/init.c **** * (C) 2011-12 by Steve Markgraf 5:board/pirelli_dpl10/init.c **** * 6:board/pirelli_dpl10/init.c **** * All Rights Reserved 7:board/pirelli_dpl10/init.c **** * 8:board/pirelli_dpl10/init.c **** * This program is free software; you can redistribute it and/or modify 9:board/pirelli_dpl10/init.c **** * it under the terms of the GNU General Public License as published by 10:board/pirelli_dpl10/init.c **** * the Free Software Foundation; either version 2 of the License, or 11:board/pirelli_dpl10/init.c **** * (at your option) any later version. 12:board/pirelli_dpl10/init.c **** * 13:board/pirelli_dpl10/init.c **** * This program is distributed in the hope that it will be useful, 14:board/pirelli_dpl10/init.c **** * but WITHOUT ANY WARRANTY; without even the implied warranty of 15:board/pirelli_dpl10/init.c **** * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16:board/pirelli_dpl10/init.c **** * GNU General Public License for more details. 17:board/pirelli_dpl10/init.c **** * 18:board/pirelli_dpl10/init.c **** */ 19:board/pirelli_dpl10/init.c **** 20:board/pirelli_dpl10/init.c **** #include 21:board/pirelli_dpl10/init.c **** #include 22:board/pirelli_dpl10/init.c **** 23:board/pirelli_dpl10/init.c **** #include 24:board/pirelli_dpl10/init.c **** #include 25:board/pirelli_dpl10/init.c **** #include 26:board/pirelli_dpl10/init.c **** #include 27:board/pirelli_dpl10/init.c **** #include 28:board/pirelli_dpl10/init.c **** #include 29:board/pirelli_dpl10/init.c **** #include 30:board/pirelli_dpl10/init.c **** #include 31:board/pirelli_dpl10/init.c **** 32:board/pirelli_dpl10/init.c **** #include 33:board/pirelli_dpl10/init.c **** #include 34:board/pirelli_dpl10/init.c **** #include 35:board/pirelli_dpl10/init.c **** #include 36:board/pirelli_dpl10/init.c **** #include 37:board/pirelli_dpl10/init.c **** #include 38:board/pirelli_dpl10/init.c **** #include 39:board/pirelli_dpl10/init.c **** 40:board/pirelli_dpl10/init.c **** #include 41:board/pirelli_dpl10/init.c **** #include 42:board/pirelli_dpl10/init.c **** 43:board/pirelli_dpl10/init.c **** #include 44:board/pirelli_dpl10/init.c **** #include 45:board/pirelli_dpl10/init.c **** 46:board/pirelli_dpl10/init.c **** #include 47:board/pirelli_dpl10/init.c **** #include "keymap.h" 48:board/pirelli_dpl10/init.c **** 49:board/pirelli_dpl10/init.c **** #define ARMIO_LATCH_OUT 0xfffe4802 50:board/pirelli_dpl10/init.c **** #define IO_CNTL_REG 0xfffe4804 51:board/pirelli_dpl10/init.c **** #define ARM_CONF_REG 0xfffef006 52:board/pirelli_dpl10/init.c **** #define ASIC_CONF_REG 0xfffef008 53:board/pirelli_dpl10/init.c **** #define IO_CONF_REG 0xfffef00a 54:board/pirelli_dpl10/init.c **** 55:board/pirelli_dpl10/init.c **** static void board_io_init(void) 56:board/pirelli_dpl10/init.c **** { 57:board/pirelli_dpl10/init.c **** uint16_t reg; 58:board/pirelli_dpl10/init.c **** 59:board/pirelli_dpl10/init.c **** reg = readw(ASIC_CONF_REG); 60:board/pirelli_dpl10/init.c **** /* Set LPG and PWL pin mux like Pirelli's fw does */ 61:board/pirelli_dpl10/init.c **** reg |= (1 << 6) | (1 << 4); 62:board/pirelli_dpl10/init.c **** /* TWL3025: Set SPI+RIF RX clock to rising edge */ 63:board/pirelli_dpl10/init.c **** reg |= (1 << 13) | (1 << 14); 64:board/pirelli_dpl10/init.c **** reg &= ~(1 << 1); 65:board/pirelli_dpl10/init.c **** writew(reg, ASIC_CONF_REG); 66:board/pirelli_dpl10/init.c **** 67:board/pirelli_dpl10/init.c **** /* enable IO functionality */ 68:board/pirelli_dpl10/init.c **** reg = readw(IO_CONF_REG); 69:board/pirelli_dpl10/init.c **** reg |= (1 << 9) | (1 << 4) | (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0); 70:board/pirelli_dpl10/init.c **** writew(reg, IO_CONF_REG); 71:board/pirelli_dpl10/init.c **** 72:board/pirelli_dpl10/init.c **** /* set IO directions */ 73:board/pirelli_dpl10/init.c **** reg = readw(IO_CNTL_REG); 74:board/pirelli_dpl10/init.c **** reg &= ~((1 << 7) | (1 << 4) | (1 << 1)); 75:board/pirelli_dpl10/init.c **** writew(reg, IO_CNTL_REG); 76:board/pirelli_dpl10/init.c **** 77:board/pirelli_dpl10/init.c **** /* reset display controller, disable bypass mode, set nCS4 to display */ 78:board/pirelli_dpl10/init.c **** reg = readw(ARMIO_LATCH_OUT); 79:board/pirelli_dpl10/init.c **** reg &= ~(1 << 4); 80:board/pirelli_dpl10/init.c **** writew(reg, ARMIO_LATCH_OUT); 81:board/pirelli_dpl10/init.c **** reg &= ~(1 << 7); 82:board/pirelli_dpl10/init.c **** reg |= (1 << 4) | (1 << 1); 83:board/pirelli_dpl10/init.c **** writew(reg, ARMIO_LATCH_OUT); 84:board/pirelli_dpl10/init.c **** 85:board/pirelli_dpl10/init.c **** /* configure ADD(22), needed for second half of flash */ 86:board/pirelli_dpl10/init.c **** reg = readw(ARM_CONF_REG); 87:board/pirelli_dpl10/init.c **** reg |= (1 << 3); 88:board/pirelli_dpl10/init.c **** writew(reg, ARM_CONF_REG); 89:board/pirelli_dpl10/init.c **** } 90:board/pirelli_dpl10/init.c **** 91:board/pirelli_dpl10/init.c **** void board_init(int with_irq) 92:board/pirelli_dpl10/init.c **** { 27 .loc 1 92 1 view -0 28 .cfi_startproc 29 @ Function supports interworking. 30 @ args = 0, pretend = 0, frame = 0 31 @ frame_needed = 0, uses_anonymous_args = 0 93:board/pirelli_dpl10/init.c **** /* Configure the memory interface */ 94:board/pirelli_dpl10/init.c **** calypso_mem_cfg(CALYPSO_nCS0, 4, CALYPSO_MEM_16bit, 1); 32 .loc 1 94 2 view .LVU1 92:board/pirelli_dpl10/init.c **** /* Configure the memory interface */ 33 .loc 1 92 1 is_stmt 0 view .LVU2 34 0000 1F402DE9 push {r0, r1, r2, r3, r4, lr} 35 .LCFI0: 36 .cfi_def_cfa_offset 24 37 .cfi_offset 4, -8 38 .cfi_offset 14, -4 39 .loc 1 94 2 view .LVU3 40 0004 0130A0E3 mov r3, #1 92:board/pirelli_dpl10/init.c **** /* Configure the memory interface */ 41 .loc 1 92 1 view .LVU4 42 0008 0040A0E1 mov r4, r0 43 .loc 1 94 2 view .LVU5 44 000c 0320A0E1 mov r2, r3 45 0010 0410A0E3 mov r1, #4 46 0014 0000A0E3 mov r0, #0 47 .LVL1: 48 .loc 1 94 2 view .LVU6 49 0018 FEFFFFEB bl calypso_mem_cfg 50 .LVL2: 95:board/pirelli_dpl10/init.c **** calypso_mem_cfg(CALYPSO_nCS1, 4, CALYPSO_MEM_16bit, 1); 51 .loc 1 95 2 is_stmt 1 view .LVU7 52 001c 0130A0E3 mov r3, #1 53 0020 0410A0E3 mov r1, #4 54 0024 0320A0E1 mov r2, r3 55 0028 0200A0E3 mov r0, #2 56 002c FEFFFFEB bl calypso_mem_cfg 57 .LVL3: 96:board/pirelli_dpl10/init.c **** calypso_mem_cfg(CALYPSO_nCS2, 5, CALYPSO_MEM_16bit, 1); 58 .loc 1 96 2 view .LVU8 59 0030 0130A0E3 mov r3, #1 60 0034 0510A0E3 mov r1, #5 61 0038 0320A0E1 mov r2, r3 62 003c 0400A0E3 mov r0, #4 63 0040 FEFFFFEB bl calypso_mem_cfg 64 .LVL4: 97:board/pirelli_dpl10/init.c **** calypso_mem_cfg(CALYPSO_nCS3, 4, CALYPSO_MEM_16bit, 1); 65 .loc 1 97 2 view .LVU9 66 0044 0130A0E3 mov r3, #1 67 0048 0410A0E3 mov r1, #4 68 004c 0320A0E1 mov r2, r3 69 0050 0600A0E3 mov r0, #6 70 0054 FEFFFFEB bl calypso_mem_cfg 71 .LVL5: 98:board/pirelli_dpl10/init.c **** calypso_mem_cfg(CALYPSO_CS4, 7, CALYPSO_MEM_16bit, 1); 72 .loc 1 98 2 view .LVU10 73 0058 0130A0E3 mov r3, #1 74 005c 0710A0E3 mov r1, #7 75 0060 0320A0E1 mov r2, r3 76 0064 0A00A0E3 mov r0, #10 77 0068 FEFFFFEB bl calypso_mem_cfg 78 .LVL6: 99:board/pirelli_dpl10/init.c **** calypso_mem_cfg(CALYPSO_nCS6, 0, CALYPSO_MEM_32bit, 1); 79 .loc 1 99 2 view .LVU11 80 006c 0130A0E3 mov r3, #1 81 0070 0220A0E3 mov r2, #2 82 0074 0010A0E3 mov r1, #0 83 0078 0C00A0E3 mov r0, #12 84 007c FEFFFFEB bl calypso_mem_cfg 85 .LVL7: 100:board/pirelli_dpl10/init.c **** calypso_mem_cfg(CALYPSO_nCS7, 0, CALYPSO_MEM_32bit, 0); 86 .loc 1 100 2 view .LVU12 87 0080 0030A0E3 mov r3, #0 88 0084 0220A0E3 mov r2, #2 89 0088 0310A0E1 mov r1, r3 90 008c 0800A0E3 mov r0, #8 91 0090 FEFFFFEB bl calypso_mem_cfg 92 .LVL8: 101:board/pirelli_dpl10/init.c **** 102:board/pirelli_dpl10/init.c **** /* Set VTCXO_DIV2 = 1, configure PLL for 104 MHz and give ARM half of that */ 103:board/pirelli_dpl10/init.c **** calypso_clock_set(2, CALYPSO_PLL13_104_MHZ, ARM_MCLK_DIV_2); 93 .loc 1 103 2 view .LVU13 94 0094 0220A0E3 mov r2, #2 95 0098 021BA0E3 mov r1, #2048 96 009c 0200A0E1 mov r0, r2 97 00a0 FEFFFFEB bl calypso_clock_set 98 .LVL9: 104:board/pirelli_dpl10/init.c **** 105:board/pirelli_dpl10/init.c **** /* Configure the RHEA bridge with some sane default values */ 106:board/pirelli_dpl10/init.c **** calypso_rhea_cfg(0, 0, 0xff, 0, 1, 0, 0); 99 .loc 1 106 2 view .LVU14 100 00a4 0030A0E3 mov r3, #0 101 00a8 0120A0E3 mov r2, #1 102 00ac 0310A0E1 mov r1, r3 103 00b0 0300A0E1 mov r0, r3 104 00b4 08308DE5 str r3, [sp, #8] 105 00b8 04308DE5 str r3, [sp, #4] 106 00bc 00208DE5 str r2, [sp] 107 00c0 FF20A0E3 mov r2, #255 108 00c4 FEFFFFEB bl calypso_rhea_cfg 109 .LVL10: 107:board/pirelli_dpl10/init.c **** 108:board/pirelli_dpl10/init.c **** /* Initialize board-specific GPIO */ 109:board/pirelli_dpl10/init.c **** board_io_init(); 110 .loc 1 109 2 view .LVU15 111 .LBB6: 112 .LBI6: 55:board/pirelli_dpl10/init.c **** { 113 .loc 1 55 13 view .LVU16 114 .LBB7: 57:board/pirelli_dpl10/init.c **** 115 .loc 1 57 2 view .LVU17 59:board/pirelli_dpl10/init.c **** /* Set LPG and PWL pin mux like Pirelli's fw does */ 116 .loc 1 59 2 view .LVU18 59:board/pirelli_dpl10/init.c **** /* Set LPG and PWL pin mux like Pirelli's fw does */ 117 .loc 1 59 6 is_stmt 0 view .LVU19 118 00c8 18219FE5 ldr r2, .L7 119 00cc B73F52E1 ldrh r3, [r2, #-247] 120 .LVL11: 61:board/pirelli_dpl10/init.c **** /* TWL3025: Set SPI+RIF RX clock to rising edge */ 121 .loc 1 61 2 is_stmt 1 view .LVU20 63:board/pirelli_dpl10/init.c **** reg &= ~(1 << 1); 122 .loc 1 63 2 view .LVU21 64:board/pirelli_dpl10/init.c **** writew(reg, ASIC_CONF_REG); 123 .loc 1 64 2 view .LVU22 124 00d0 0230C3E3 bic r3, r3, #2 125 .LVL12: 64:board/pirelli_dpl10/init.c **** writew(reg, ASIC_CONF_REG); 126 .loc 1 64 6 is_stmt 0 view .LVU23 127 00d4 063A83E3 orr r3, r3, #24576 128 00d8 503083E3 orr r3, r3, #80 129 .LVL13: 65:board/pirelli_dpl10/init.c **** 130 .loc 1 65 2 is_stmt 1 view .LVU24 131 00dc B73F42E1 strh r3, [r2, #-247] @ movhi 68:board/pirelli_dpl10/init.c **** reg |= (1 << 9) | (1 << 4) | (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0); 132 .loc 1 68 2 view .LVU25 68:board/pirelli_dpl10/init.c **** reg |= (1 << 9) | (1 << 4) | (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0); 133 .loc 1 68 6 is_stmt 0 view .LVU26 134 00e0 B53F52E1 ldrh r3, [r2, #-245] 135 .LVL14: 69:board/pirelli_dpl10/init.c **** writew(reg, IO_CONF_REG); 136 .loc 1 69 2 is_stmt 1 view .LVU27 69:board/pirelli_dpl10/init.c **** writew(reg, IO_CONF_REG); 137 .loc 1 69 6 is_stmt 0 view .LVU28 138 00e4 873F83E3 orr r3, r3, #540 139 .LVL15: 69:board/pirelli_dpl10/init.c **** writew(reg, IO_CONF_REG); 140 .loc 1 69 6 view .LVU29 141 00e8 033083E3 orr r3, r3, #3 142 .LVL16: 70:board/pirelli_dpl10/init.c **** 143 .loc 1 70 2 is_stmt 1 view .LVU30 144 00ec B53F42E1 strh r3, [r2, #-245] @ movhi 73:board/pirelli_dpl10/init.c **** reg &= ~((1 << 7) | (1 << 4) | (1 << 1)); 145 .loc 1 73 2 view .LVU31 73:board/pirelli_dpl10/init.c **** reg &= ~((1 << 7) | (1 << 4) | (1 << 1)); 146 .loc 1 73 6 is_stmt 0 view .LVU32 147 00f0 F4109FE5 ldr r1, .L7+4 148 00f4 BB3F51E1 ldrh r3, [r1, #-251] 149 .LVL17: 74:board/pirelli_dpl10/init.c **** writew(reg, IO_CNTL_REG); 150 .loc 1 74 2 is_stmt 1 view .LVU33 74:board/pirelli_dpl10/init.c **** writew(reg, IO_CNTL_REG); 151 .loc 1 74 6 is_stmt 0 view .LVU34 152 00f8 9230C3E3 bic r3, r3, #146 153 .LVL18: 75:board/pirelli_dpl10/init.c **** 154 .loc 1 75 2 is_stmt 1 view .LVU35 155 00fc BB3F41E1 strh r3, [r1, #-251] @ movhi 78:board/pirelli_dpl10/init.c **** reg &= ~(1 << 4); 156 .loc 1 78 2 view .LVU36 78:board/pirelli_dpl10/init.c **** reg &= ~(1 << 4); 157 .loc 1 78 6 is_stmt 0 view .LVU37 158 0100 BD3F51E1 ldrh r3, [r1, #-253] 159 .LVL19: 79:board/pirelli_dpl10/init.c **** writew(reg, ARMIO_LATCH_OUT); 160 .loc 1 79 2 is_stmt 1 view .LVU38 79:board/pirelli_dpl10/init.c **** writew(reg, ARMIO_LATCH_OUT); 161 .loc 1 79 6 is_stmt 0 view .LVU39 162 0104 1000C3E3 bic r0, r3, #16 163 .LVL20: 80:board/pirelli_dpl10/init.c **** reg &= ~(1 << 7); 164 .loc 1 80 2 is_stmt 1 view .LVU40 81:board/pirelli_dpl10/init.c **** reg |= (1 << 4) | (1 << 1); 165 .loc 1 81 6 is_stmt 0 view .LVU41 166 0108 9030C3E3 bic r3, r3, #144 82:board/pirelli_dpl10/init.c **** writew(reg, ARMIO_LATCH_OUT); 167 .loc 1 82 6 view .LVU42 168 010c 123083E3 orr r3, r3, #18 80:board/pirelli_dpl10/init.c **** reg &= ~(1 << 7); 169 .loc 1 80 2 view .LVU43 170 0110 BD0F41E1 strh r0, [r1, #-253] @ movhi 81:board/pirelli_dpl10/init.c **** reg |= (1 << 4) | (1 << 1); 171 .loc 1 81 2 is_stmt 1 view .LVU44 172 .LVL21: 82:board/pirelli_dpl10/init.c **** writew(reg, ARMIO_LATCH_OUT); 173 .loc 1 82 2 view .LVU45 83:board/pirelli_dpl10/init.c **** 174 .loc 1 83 2 view .LVU46 175 0114 BD3F41E1 strh r3, [r1, #-253] @ movhi 86:board/pirelli_dpl10/init.c **** reg |= (1 << 3); 176 .loc 1 86 2 view .LVU47 86:board/pirelli_dpl10/init.c **** reg |= (1 << 3); 177 .loc 1 86 6 is_stmt 0 view .LVU48 178 0118 B93F52E1 ldrh r3, [r2, #-249] 179 .LVL22: 87:board/pirelli_dpl10/init.c **** writew(reg, ARM_CONF_REG); 180 .loc 1 87 2 is_stmt 1 view .LVU49 87:board/pirelli_dpl10/init.c **** writew(reg, ARM_CONF_REG); 181 .loc 1 87 6 is_stmt 0 view .LVU50 182 011c 083083E3 orr r3, r3, #8 183 .LVL23: 88:board/pirelli_dpl10/init.c **** } 184 .loc 1 88 2 is_stmt 1 view .LVU51 185 .LBE7: 186 .LBE6: 110:board/pirelli_dpl10/init.c **** 111:board/pirelli_dpl10/init.c **** /* Enable bootrom mapping to route exception vectors to RAM */ 112:board/pirelli_dpl10/init.c **** calypso_bootrom(with_irq); 187 .loc 1 112 2 is_stmt 0 view .LVU52 188 0120 0400A0E1 mov r0, r4 189 .LBB9: 190 .LBB8: 88:board/pirelli_dpl10/init.c **** } 191 .loc 1 88 2 view .LVU53 192 0124 B93F42E1 strh r3, [r2, #-249] @ movhi 193 .LVL24: 88:board/pirelli_dpl10/init.c **** } 194 .loc 1 88 2 view .LVU54 195 .LBE8: 196 .LBE9: 197 .loc 1 112 2 is_stmt 1 view .LVU55 198 0128 FEFFFFEB bl calypso_bootrom 199 .LVL25: 113:board/pirelli_dpl10/init.c **** calypso_exceptions_install(); 200 .loc 1 113 2 view .LVU56 201 012c FEFFFFEB bl calypso_exceptions_install 202 .LVL26: 114:board/pirelli_dpl10/init.c **** 115:board/pirelli_dpl10/init.c **** /* Initialize interrupt controller */ 116:board/pirelli_dpl10/init.c **** if (with_irq) 203 .loc 1 116 2 view .LVU57 204 .loc 1 116 5 is_stmt 0 view .LVU58 205 0130 000054E3 cmp r4, #0 117:board/pirelli_dpl10/init.c **** irq_init(); 206 .loc 1 117 3 is_stmt 1 view .LVU59 207 0134 FEFFFF1B blne irq_init 208 .LVL27: 209 .L2: 118:board/pirelli_dpl10/init.c **** 119:board/pirelli_dpl10/init.c **** sercomm_bind_uart(UART_IRDA); 210 .loc 1 119 2 view .LVU60 211 0138 0000A0E3 mov r0, #0 212 013c FEFFFFEB bl sercomm_bind_uart 213 .LVL28: 120:board/pirelli_dpl10/init.c **** cons_bind_uart(UART_MODEM); 214 .loc 1 120 2 view .LVU61 121:board/pirelli_dpl10/init.c **** 122:board/pirelli_dpl10/init.c **** /* initialize IRDA UART to be used for sercomm */ 123:board/pirelli_dpl10/init.c **** uart_init(UART_IRDA, with_irq); 215 .loc 1 123 2 is_stmt 0 view .LVU62 216 0140 FF4004E2 and r4, r4, #255 217 .LVL29: 120:board/pirelli_dpl10/init.c **** cons_bind_uart(UART_MODEM); 218 .loc 1 120 2 view .LVU63 219 0144 0100A0E3 mov r0, #1 220 0148 FEFFFFEB bl cons_bind_uart 221 .LVL30: 222 .loc 1 123 2 is_stmt 1 view .LVU64 223 014c 0410A0E1 mov r1, r4 224 0150 0000A0E3 mov r0, #0 225 0154 FEFFFFEB bl uart_init 226 .LVL31: 124:board/pirelli_dpl10/init.c **** uart_baudrate(UART_IRDA, UART_115200); 227 .loc 1 124 2 view .LVU65 228 0158 0210A0E3 mov r1, #2 229 015c 0000A0E3 mov r0, #0 230 0160 FEFFFFEB bl uart_baudrate 231 .LVL32: 125:board/pirelli_dpl10/init.c **** 126:board/pirelli_dpl10/init.c **** /* Initialize MODEM UART to be used for old-school console code. */ 127:board/pirelli_dpl10/init.c **** uart_init(UART_MODEM, with_irq); 232 .loc 1 127 2 view .LVU66 233 0164 0410A0E1 mov r1, r4 234 0168 0100A0E3 mov r0, #1 235 016c FEFFFFEB bl uart_init 236 .LVL33: 128:board/pirelli_dpl10/init.c **** uart_baudrate(UART_MODEM, UART_115200); 237 .loc 1 128 2 view .LVU67 238 0170 0210A0E3 mov r1, #2 239 0174 0100A0E3 mov r0, #1 240 0178 FEFFFFEB bl uart_baudrate 241 .LVL34: 129:board/pirelli_dpl10/init.c **** 130:board/pirelli_dpl10/init.c **** /* Initialize hardware timers */ 131:board/pirelli_dpl10/init.c **** hwtimer_init(); 242 .loc 1 131 2 view .LVU68 243 017c FEFFFFEB bl hwtimer_init 244 .LVL35: 132:board/pirelli_dpl10/init.c **** 133:board/pirelli_dpl10/init.c **** /* Initialize DMA controller */ 134:board/pirelli_dpl10/init.c **** dma_init(); 245 .loc 1 134 2 view .LVU69 246 0180 FEFFFFEB bl dma_init 247 .LVL36: 135:board/pirelli_dpl10/init.c **** 136:board/pirelli_dpl10/init.c **** /* Initialize real time clock */ 137:board/pirelli_dpl10/init.c **** rtc_init(); 248 .loc 1 137 2 view .LVU70 249 0184 FEFFFFEB bl rtc_init 250 .LVL37: 138:board/pirelli_dpl10/init.c **** 139:board/pirelli_dpl10/init.c **** /* Initialize system timers (uses hwtimer 2) */ 140:board/pirelli_dpl10/init.c **** timer_init(); 251 .loc 1 140 2 view .LVU71 252 0188 FEFFFFEB bl timer_init 253 .LVL38: 141:board/pirelli_dpl10/init.c **** 142:board/pirelli_dpl10/init.c **** /* Initialize LCD driver and backlight (0 is max, 255 min brightness) */ 143:board/pirelli_dpl10/init.c **** bl_mode_pwl(1); 254 .loc 1 143 2 view .LVU72 255 018c 0100A0E3 mov r0, #1 256 0190 FEFFFFEB bl bl_mode_pwl 257 .LVL39: 144:board/pirelli_dpl10/init.c **** bl_level(50); 258 .loc 1 144 2 view .LVU73 259 0194 3200A0E3 mov r0, #50 260 0198 FEFFFFEB bl bl_level 261 .LVL40: 145:board/pirelli_dpl10/init.c **** 146:board/pirelli_dpl10/init.c **** fb_init(); 262 .loc 1 146 2 view .LVU74 263 .LBB10: 264 .LBI10: 265 .file 2 "include/fb/framebuffer.h" 1:include/fb/framebuffer.h **** #ifndef _FB_FRAMEBUFFER_H 2:include/fb/framebuffer.h **** #define _FB_FRAMEBUFFER_H 3:include/fb/framebuffer.h **** 4:include/fb/framebuffer.h **** #include 5:include/fb/framebuffer.h **** #include 6:include/fb/framebuffer.h **** 7:include/fb/framebuffer.h **** /* color is encoded as */ 8:include/fb/framebuffer.h **** /* if a color is "special", then the RGB components most likely 9:include/fb/framebuffer.h **** don't make sense. Use "special" colours when you have to 10:include/fb/framebuffer.h **** mask out bits with transparency or you have to encode 11:include/fb/framebuffer.h **** colours in a fixed color palette ... */ 12:include/fb/framebuffer.h **** 13:include/fb/framebuffer.h **** #define FB_COLOR_WHITE 0x00ffffffU 14:include/fb/framebuffer.h **** #define FB_COLOR_BLACK 0x00000000U 15:include/fb/framebuffer.h **** #define FB_COLOR_TRANSP 0x01ffffffU 16:include/fb/framebuffer.h **** 17:include/fb/framebuffer.h **** #define FB_COLOR_RGB(r,g,b) ((((r) & 0xff)<<16)|(((g)&0xff)<<8)|((b)&0xff)) 18:include/fb/framebuffer.h **** #define FB_COLOR_RED FB_COLOR_RGB(0xff,0x00,0x00) 19:include/fb/framebuffer.h **** #define FB_COLOR_GREEN FB_COLOR_RGB(0x00,0xff,0x00) 20:include/fb/framebuffer.h **** #define FB_COLOR_BLUE FB_COLOR_RGB(0x00,0x00,0xff) 21:include/fb/framebuffer.h **** 22:include/fb/framebuffer.h **** /* encode */ 23:include/fb/framebuffer.h **** 24:include/fb/framebuffer.h **** /* decode */ 25:include/fb/framebuffer.h **** #define FB_COLOR_IS_SPECIAL(v) (!!((v) & 0xff000000U)) 26:include/fb/framebuffer.h **** #define FB_COLOR_TO_R(v) (((v)>>16) & 0xff) 27:include/fb/framebuffer.h **** #define FB_COLOR_TO_G(v) (((v)>> 8) & 0xff) 28:include/fb/framebuffer.h **** #define FB_COLOR_TO_B(v) ( (v) & 0xff) 29:include/fb/framebuffer.h **** 30:include/fb/framebuffer.h **** struct framebuffer { 31:include/fb/framebuffer.h **** char name[8]; // keep it short! 32:include/fb/framebuffer.h **** void (*init)(); // (re)initialize 33:include/fb/framebuffer.h **** void (*clear)(); // clear display 34:include/fb/framebuffer.h **** void (*set_p)(uint16_t x,uint16_t y); // set pixel to fg color 35:include/fb/framebuffer.h **** void (*boxto)(uint16_t x,uint16_t y); // draw box to xy 36:include/fb/framebuffer.h **** void (*lineto)(uint16_t x,uint16_t y); // draw line to xy 37:include/fb/framebuffer.h **** int (*putstr)(char *c,int maxwidth); // put text in current font to fb 38:include/fb/framebuffer.h **** void (*flush)(); // flush changes 39:include/fb/framebuffer.h **** 40:include/fb/framebuffer.h **** uint16_t width,height; // width/height of fb 41:include/fb/framebuffer.h **** uint16_t cursor_x,cursor_y; // current cursor 42:include/fb/framebuffer.h **** uint32_t fg_color,bg_color; // current fg/bg color 43:include/fb/framebuffer.h **** enum fb_font_id font; // current font 44:include/fb/framebuffer.h **** }; 45:include/fb/framebuffer.h **** 46:include/fb/framebuffer.h **** /* there is a single framebuffer, the specific driver defines 47:include/fb/framebuffer.h **** the "framebuffer" symbol */ 48:include/fb/framebuffer.h **** extern struct framebuffer *framebuffer; 49:include/fb/framebuffer.h **** 50:include/fb/framebuffer.h **** static inline void 51:include/fb/framebuffer.h **** fb_init(){ 266 .loc 2 51 1 view .LVU75 267 .LBB11: 52:include/fb/framebuffer.h **** framebuffer->init(); 268 .loc 2 52 2 view .LVU76 269 .loc 2 52 13 is_stmt 0 view .LVU77 270 019c 4C309FE5 ldr r3, .L7+8 271 01a0 003093E5 ldr r3, [r3] 272 .loc 2 52 2 view .LVU78 273 01a4 083093E5 ldr r3, [r3, #8] 274 01a8 0FE0A0E1 mov lr, pc 275 01ac 13FF2FE1 bx r3 276 .LVL41: 277 .LBE11: 278 .LBE10: 147:board/pirelli_dpl10/init.c **** 148:board/pirelli_dpl10/init.c **** /* Initialize keypad driver */ 149:board/pirelli_dpl10/init.c **** keypad_init(keymap, with_irq); 279 .loc 1 149 2 is_stmt 1 view .LVU79 280 01b0 0410A0E1 mov r1, r4 281 01b4 38009FE5 ldr r0, .L7+12 282 01b8 FEFFFFEB bl keypad_init 283 .LVL42: 150:board/pirelli_dpl10/init.c **** 151:board/pirelli_dpl10/init.c **** /* Initialize ABB driver (uses SPI) */ 152:board/pirelli_dpl10/init.c **** twl3025_init(); 284 .loc 1 152 2 view .LVU80 285 01bc FEFFFFEB bl twl3025_init 286 .LVL43: 153:board/pirelli_dpl10/init.c **** 154:board/pirelli_dpl10/init.c **** /* enable LEDB driver of Iota for keypad backlight */ 155:board/pirelli_dpl10/init.c **** twl3025_reg_write(AUXLED, 0x02); 287 .loc 1 155 2 view .LVU81 288 01c0 0210A0E3 mov r1, #2 289 01c4 9800A0E3 mov r0, #152 290 01c8 FEFFFFEB bl twl3025_reg_write 291 .LVL44: 156:board/pirelli_dpl10/init.c **** 157:board/pirelli_dpl10/init.c **** /* Initialize TIFFS reader (18 sectors of 256 KiB each) */ 158:board/pirelli_dpl10/init.c **** tiffs_init(0x02000000, 0x40000, 18); 292 .loc 1 158 2 view .LVU82 293 01cc 1220A0E3 mov r2, #18 294 01d0 0117A0E3 mov r1, #262144 295 01d4 0204A0E3 mov r0, #33554432 296 01d8 FEFFFFEB bl tiffs_init 297 .LVL45: 159:board/pirelli_dpl10/init.c **** } 298 .loc 1 159 1 is_stmt 0 view .LVU83 299 01dc 10D08DE2 add sp, sp, #16 300 .LCFI1: 301 .cfi_def_cfa_offset 8 302 @ sp needed 303 01e0 1040BDE8 pop {r4, lr} 304 .LCFI2: 305 .cfi_restore 14 306 .cfi_restore 4 307 .cfi_def_cfa_offset 0 308 01e4 1EFF2FE1 bx lr 309 .L8: 310 .align 2 311 .L7: 312 01e8 FFF0FEFF .word -69377 313 01ec FF48FEFF .word -112385 314 01f0 00000000 .word framebuffer 315 01f4 00000000 .word .LANCHOR0 316 .cfi_endproc 317 .LFE76: 319 .section .rodata 320 .set .LANCHOR0,. + 0 323 keymap: 324 0000 12040302 .ascii "\022\004\003\002\011\010\007\016\015\014\023\021\000" 324 0908070E 324 0D0C1311 324 00 325 000d 01060F10 .ascii "\001\006\017\020\005\012\013\037\026\025\027" 325 050A0B1F 325 161517 326 .text 327 .Letext0: 328 .file 3 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h" 329 .file 4 "include/keypad.h" 330 .file 5 "include/calypso/clock.h" 331 .file 6 "include/uart.h" 332 .file 7 "include/abb/twl3025.h" 333 .file 8 "include/fb/font.h" 334 .file 9 "include/calypso/backlight.h" 335 .file 10 "include/comm/timer.h" 336 .file 11 "include/calypso/rtc.h" 337 .file 12 "include/calypso/dma.h" 338 .file 13 "include/calypso/timer.h" 339 .file 14 "include/tiffs.h" 340 .file 15 "include/console.h" 341 .file 16 "include/comm/sercomm.h" 342 .file 17 "include/calypso/irq.h" 343 .file 18 "board/pirelli_dpl10/keymap.h" DEFINED SYMBOLS *ABS*:00000000 init.c /tmp/ccRVjwGy.s:19 .text.board_init:00000000 $a /tmp/ccRVjwGy.s:24 .text.board_init:00000000 board_init /tmp/ccRVjwGy.s:312 .text.board_init:000001e8 $d /tmp/ccRVjwGy.s:323 .rodata:00000000 keymap UNDEFINED SYMBOLS calypso_mem_cfg calypso_clock_set calypso_rhea_cfg calypso_bootrom calypso_exceptions_install irq_init sercomm_bind_uart cons_bind_uart uart_init uart_baudrate hwtimer_init dma_init rtc_init timer_init bl_mode_pwl bl_level keypad_init twl3025_init twl3025_reg_write tiffs_init framebuffer