1 .cpu arm7tdmi 2 .arch armv4t 3 .fpu softvfp 4 .eabi_attribute 20, 1 5 .eabi_attribute 21, 1 6 .eabi_attribute 23, 3 7 .eabi_attribute 24, 1 8 .eabi_attribute 25, 1 9 .eabi_attribute 26, 1 10 .eabi_attribute 30, 4 11 .eabi_attribute 34, 0 12 .eabi_attribute 18, 4 13 .file "rffe_dpl10_triband.c" 14 .text 15 .Ltext0: 16 .cfi_sections .debug_frame 17 .file 1 "board/pirelli_dpl10/rffe_dpl10_triband.c" 18 .section .text.rffe_mode,"ax",%progbits 19 .align 2 20 .global rffe_mode 21 .syntax unified 22 .arm 24 rffe_mode: 25 .LVL0: 26 .LFB3: 1:board/pirelli_dpl10/rffe_dpl10_triband.c **** #include 2:board/pirelli_dpl10/rffe_dpl10_triband.c **** #include 3:board/pirelli_dpl10/rffe_dpl10_triband.c **** 4:board/pirelli_dpl10/rffe_dpl10_triband.c **** #include 5:board/pirelli_dpl10/rffe_dpl10_triband.c **** #include 6:board/pirelli_dpl10/rffe_dpl10_triband.c **** #include 7:board/pirelli_dpl10/rffe_dpl10_triband.c **** #include 8:board/pirelli_dpl10/rffe_dpl10_triband.c **** #include 9:board/pirelli_dpl10/rffe_dpl10_triband.c **** 10:board/pirelli_dpl10/rffe_dpl10_triband.c **** /* This is a value that has been measured on the C123 by Harald: 71dBm, 11:board/pirelli_dpl10/rffe_dpl10_triband.c **** it is the difference between the input level at the antenna and what 12:board/pirelli_dpl10/rffe_dpl10_triband.c **** the DSP reports, subtracted by the total gain of the TRF6151 */ 13:board/pirelli_dpl10/rffe_dpl10_triband.c **** #define SYSTEM_INHERENT_GAIN 71 14:board/pirelli_dpl10/rffe_dpl10_triband.c **** 15:board/pirelli_dpl10/rffe_dpl10_triband.c **** /* describe how the RF frontend is wired on the Pirelli DP-L10 */ 16:board/pirelli_dpl10/rffe_dpl10_triband.c **** 17:board/pirelli_dpl10/rffe_dpl10_triband.c **** #define RITA_RESET TSPACT(5) /* Reset of the Rita TRF6151 */ 18:board/pirelli_dpl10/rffe_dpl10_triband.c **** #define PA_ENABLE TSPACT(0) /* Enable the Power Amplifier */ 19:board/pirelli_dpl10/rffe_dpl10_triband.c **** #define GSM_TXEN TSPACT(3) /* PA GSM switch, low-active, 20:board/pirelli_dpl10/rffe_dpl10_triband.c **** * 1 for DCS1800/PCS1900 TX */ 21:board/pirelli_dpl10/rffe_dpl10_triband.c **** 22:board/pirelli_dpl10/rffe_dpl10_triband.c **** /* All VCn controls are high-active */ 23:board/pirelli_dpl10/rffe_dpl10_triband.c **** #define ASM_VC1 TSPACT(4) /* VC1 PCS1900 RX */ 24:board/pirelli_dpl10/rffe_dpl10_triband.c **** #define ASM_VC2 TSPACT(10) /* VC2 DCS1800/PCS1900 TX */ 25:board/pirelli_dpl10/rffe_dpl10_triband.c **** #define ASM_VC3 TSPACT(11) /* VC3 GSM900 TX */ 26:board/pirelli_dpl10/rffe_dpl10_triband.c **** 27:board/pirelli_dpl10/rffe_dpl10_triband.c **** #define IOTA_STROBE TSPEN(0) /* Strobe for the Iota TSP */ 28:board/pirelli_dpl10/rffe_dpl10_triband.c **** #define RITA_STROBE TSPEN(1) /* Strobe for the Rita TSP */ 29:board/pirelli_dpl10/rffe_dpl10_triband.c **** 30:board/pirelli_dpl10/rffe_dpl10_triband.c **** /* switch RF Frontend Mode */ 31:board/pirelli_dpl10/rffe_dpl10_triband.c **** void rffe_mode(enum gsm_band band, int tx) 32:board/pirelli_dpl10/rffe_dpl10_triband.c **** { 27 .loc 1 32 1 view -0 28 .cfi_startproc 29 @ Function supports interworking. 30 @ args = 0, pretend = 0, frame = 0 31 @ frame_needed = 0, uses_anonymous_args = 0 33:board/pirelli_dpl10/rffe_dpl10_triband.c **** uint16_t tspact = tsp_act_state(); 32 .loc 1 33 2 view .LVU1 32:board/pirelli_dpl10/rffe_dpl10_triband.c **** uint16_t tspact = tsp_act_state(); 33 .loc 1 32 1 is_stmt 0 view .LVU2 34 0000 10402DE9 push {r4, lr} 35 .LCFI0: 36 .cfi_def_cfa_offset 8 37 .cfi_offset 4, -8 38 .cfi_offset 14, -4 32:board/pirelli_dpl10/rffe_dpl10_triband.c **** uint16_t tspact = tsp_act_state(); 39 .loc 1 32 1 view .LVU3 40 0004 0040A0E1 mov r4, r0 41 .loc 1 33 20 view .LVU4 42 0008 FEFFFFEB bl tsp_act_state 43 .LVL1: 34:board/pirelli_dpl10/rffe_dpl10_triband.c **** 35:board/pirelli_dpl10/rffe_dpl10_triband.c **** /* First we mask off all bits from the state cache */ 36:board/pirelli_dpl10/rffe_dpl10_triband.c **** tspact &= ~(PA_ENABLE| GSM_TXEN); 44 .loc 1 36 2 is_stmt 1 view .LVU5 37:board/pirelli_dpl10/rffe_dpl10_triband.c **** tspact &= ~(ASM_VC1 | ASM_VC2 | ASM_VC3); 45 .loc 1 37 2 view .LVU6 46 .loc 1 37 9 is_stmt 0 view .LVU7 47 000c 18309FE5 ldr r3, .L4 38:board/pirelli_dpl10/rffe_dpl10_triband.c **** 39:board/pirelli_dpl10/rffe_dpl10_triband.c **** switch (band) { 48 .loc 1 39 2 view .LVU8 49 0010 080054E3 cmp r4, #8 37:board/pirelli_dpl10/rffe_dpl10_triband.c **** tspact &= ~(ASM_VC1 | ASM_VC2 | ASM_VC3); 50 .loc 1 37 9 view .LVU9 51 0014 003003E0 and r3, r3, r0 52 .LVL2: 53 .loc 1 39 2 is_stmt 1 view .LVU10 40:board/pirelli_dpl10/rffe_dpl10_triband.c **** case GSM_BAND_850: 41:board/pirelli_dpl10/rffe_dpl10_triband.c **** case GSM_BAND_900: 42:board/pirelli_dpl10/rffe_dpl10_triband.c **** case GSM_BAND_1800: 43:board/pirelli_dpl10/rffe_dpl10_triband.c **** break; 44:board/pirelli_dpl10/rffe_dpl10_triband.c **** case GSM_BAND_1900: 45:board/pirelli_dpl10/rffe_dpl10_triband.c **** tspact |= ASM_VC1; 54 .loc 1 45 3 view .LVU11 55 .loc 1 45 10 is_stmt 0 view .LVU12 56 0018 10308303 orreq r3, r3, #16 57 .LVL3: 46:board/pirelli_dpl10/rffe_dpl10_triband.c **** break; 58 .loc 1 46 3 is_stmt 1 view .LVU13 47:board/pirelli_dpl10/rffe_dpl10_triband.c **** default: 48:board/pirelli_dpl10/rffe_dpl10_triband.c **** /* TODO return/signal error here */ 49:board/pirelli_dpl10/rffe_dpl10_triband.c **** break; 50:board/pirelli_dpl10/rffe_dpl10_triband.c **** } 51:board/pirelli_dpl10/rffe_dpl10_triband.c **** 52:board/pirelli_dpl10/rffe_dpl10_triband.c **** #ifdef CONFIG_TX_ENABLE 53:board/pirelli_dpl10/rffe_dpl10_triband.c **** /* Then we selectively set the bits on, if required */ 54:board/pirelli_dpl10/rffe_dpl10_triband.c **** if (tx) { 55:board/pirelli_dpl10/rffe_dpl10_triband.c **** switch (band) { 56:board/pirelli_dpl10/rffe_dpl10_triband.c **** case GSM_BAND_850: 57:board/pirelli_dpl10/rffe_dpl10_triband.c **** case GSM_BAND_900: 58:board/pirelli_dpl10/rffe_dpl10_triband.c **** tspact |= ASM_VC3; 59:board/pirelli_dpl10/rffe_dpl10_triband.c **** break; 60:board/pirelli_dpl10/rffe_dpl10_triband.c **** case GSM_BAND_1800: 61:board/pirelli_dpl10/rffe_dpl10_triband.c **** case GSM_BAND_1900: 62:board/pirelli_dpl10/rffe_dpl10_triband.c **** tspact |= GSM_TXEN; 63:board/pirelli_dpl10/rffe_dpl10_triband.c **** tspact |= ASM_VC2; 64:board/pirelli_dpl10/rffe_dpl10_triband.c **** break; 65:board/pirelli_dpl10/rffe_dpl10_triband.c **** default: 66:board/pirelli_dpl10/rffe_dpl10_triband.c **** break; 67:board/pirelli_dpl10/rffe_dpl10_triband.c **** } 68:board/pirelli_dpl10/rffe_dpl10_triband.c **** tspact |= PA_ENABLE; 69:board/pirelli_dpl10/rffe_dpl10_triband.c **** } 70:board/pirelli_dpl10/rffe_dpl10_triband.c **** #endif /* TRANSMIT_SUPPORT */ 71:board/pirelli_dpl10/rffe_dpl10_triband.c **** 72:board/pirelli_dpl10/rffe_dpl10_triband.c **** tsp_act_update(tspact); 59 .loc 1 72 2 view .LVU14 60 001c 0300A0E1 mov r0, r3 61 0020 FEFFFFEB bl tsp_act_update 62 .LVL4: 73:board/pirelli_dpl10/rffe_dpl10_triband.c **** } 63 .loc 1 73 1 is_stmt 0 view .LVU15 64 0024 1040BDE8 pop {r4, lr} 65 .LCFI1: 66 .cfi_restore 14 67 .cfi_restore 4 68 .cfi_def_cfa_offset 0 69 .loc 1 73 1 view .LVU16 70 0028 1EFF2FE1 bx lr 71 .L5: 72 .align 2 73 .L4: 74 002c E6F30000 .word 62438 75 .cfi_endproc 76 .LFE3: 78 .section .text.rffe_get_rx_ports,"ax",%progbits 79 .align 2 80 .global rffe_get_rx_ports 81 .syntax unified 82 .arm 84 rffe_get_rx_ports: 85 .LFB4: 74:board/pirelli_dpl10/rffe_dpl10_triband.c **** 75:board/pirelli_dpl10/rffe_dpl10_triband.c **** /* Returns RF wiring */ 76:board/pirelli_dpl10/rffe_dpl10_triband.c **** uint32_t rffe_get_rx_ports(void) 77:board/pirelli_dpl10/rffe_dpl10_triband.c **** { 86 .loc 1 77 1 is_stmt 1 view -0 87 .cfi_startproc 88 @ Function supports interworking. 89 @ args = 0, pretend = 0, frame = 0 90 @ frame_needed = 0, uses_anonymous_args = 0 91 @ link register save eliminated. 78:board/pirelli_dpl10/rffe_dpl10_triband.c **** return (1 << PORT_LO) | (1 << PORT_DCS1800) | (1 << PORT_PCS1900); 92 .loc 1 78 2 view .LVU18 79:board/pirelli_dpl10/rffe_dpl10_triband.c **** } 93 .loc 1 79 1 is_stmt 0 view .LVU19 94 0000 3100A0E3 mov r0, #49 95 0004 1EFF2FE1 bx lr 96 .cfi_endproc 97 .LFE4: 99 .section .text.rffe_get_tx_ports,"ax",%progbits 100 .align 2 101 .global rffe_get_tx_ports 102 .syntax unified 103 .arm 105 rffe_get_tx_ports: 106 .LFB5: 80:board/pirelli_dpl10/rffe_dpl10_triband.c **** 81:board/pirelli_dpl10/rffe_dpl10_triband.c **** uint32_t rffe_get_tx_ports(void) 82:board/pirelli_dpl10/rffe_dpl10_triband.c **** { 107 .loc 1 82 1 is_stmt 1 view -0 108 .cfi_startproc 109 @ Function supports interworking. 110 @ args = 0, pretend = 0, frame = 0 111 @ frame_needed = 0, uses_anonymous_args = 0 112 @ link register save eliminated. 83:board/pirelli_dpl10/rffe_dpl10_triband.c **** return (1 << PORT_LO) | (1 << PORT_HI); 113 .loc 1 83 2 view .LVU21 84:board/pirelli_dpl10/rffe_dpl10_triband.c **** } 114 .loc 1 84 1 is_stmt 0 view .LVU22 115 0000 0300A0E3 mov r0, #3 116 0004 1EFF2FE1 bx lr 117 .cfi_endproc 118 .LFE5: 120 .section .text.rffe_iq_swapped,"ax",%progbits 121 .align 2 122 .global rffe_iq_swapped 123 .syntax unified 124 .arm 126 rffe_iq_swapped: 127 .LVL5: 128 .LFB6: 85:board/pirelli_dpl10/rffe_dpl10_triband.c **** 86:board/pirelli_dpl10/rffe_dpl10_triband.c **** /* Returns need for IQ swap */ 87:board/pirelli_dpl10/rffe_dpl10_triband.c **** int rffe_iq_swapped(uint16_t band_arfcn, int tx) 88:board/pirelli_dpl10/rffe_dpl10_triband.c **** { 129 .loc 1 88 1 is_stmt 1 view -0 130 .cfi_startproc 131 @ Function supports interworking. 132 @ args = 0, pretend = 0, frame = 0 133 @ frame_needed = 0, uses_anonymous_args = 0 89:board/pirelli_dpl10/rffe_dpl10_triband.c **** return trf6151_iq_swapped(band_arfcn, tx); 134 .loc 1 89 2 view .LVU24 88:board/pirelli_dpl10/rffe_dpl10_triband.c **** return trf6151_iq_swapped(band_arfcn, tx); 135 .loc 1 88 1 is_stmt 0 view .LVU25 136 0000 10402DE9 push {r4, lr} 137 .LCFI2: 138 .cfi_def_cfa_offset 8 139 .cfi_offset 4, -8 140 .cfi_offset 14, -4 141 .loc 1 89 9 view .LVU26 142 0004 FEFFFFEB bl trf6151_iq_swapped 143 .LVL6: 90:board/pirelli_dpl10/rffe_dpl10_triband.c **** } 144 .loc 1 90 1 view .LVU27 145 0008 1040BDE8 pop {r4, lr} 146 .LCFI3: 147 .cfi_restore 14 148 .cfi_restore 4 149 .cfi_def_cfa_offset 0 150 000c 1EFF2FE1 bx lr 151 .cfi_endproc 152 .LFE6: 154 .section .text.rffe_init,"ax",%progbits 155 .align 2 156 .global rffe_init 157 .syntax unified 158 .arm 160 rffe_init: 161 .LFB7: 91:board/pirelli_dpl10/rffe_dpl10_triband.c **** 92:board/pirelli_dpl10/rffe_dpl10_triband.c **** 93:board/pirelli_dpl10/rffe_dpl10_triband.c **** #define MCU_SW_TRACE 0xfffef00e 94:board/pirelli_dpl10/rffe_dpl10_triband.c **** #define ARM_CONF_REG 0xfffef006 95:board/pirelli_dpl10/rffe_dpl10_triband.c **** #define ASIC_CONF_REG 0xfffef008 96:board/pirelli_dpl10/rffe_dpl10_triband.c **** 97:board/pirelli_dpl10/rffe_dpl10_triband.c **** void rffe_init(void) 98:board/pirelli_dpl10/rffe_dpl10_triband.c **** { 162 .loc 1 98 1 is_stmt 1 view -0 163 .cfi_startproc 164 @ Function supports interworking. 165 @ args = 0, pretend = 0, frame = 0 166 @ frame_needed = 0, uses_anonymous_args = 0 99:board/pirelli_dpl10/rffe_dpl10_triband.c **** uint16_t reg; 167 .loc 1 99 2 view .LVU29 100:board/pirelli_dpl10/rffe_dpl10_triband.c **** 101:board/pirelli_dpl10/rffe_dpl10_triband.c **** reg = readw(ARM_CONF_REG); 168 .loc 1 101 2 view .LVU30 169 .loc 1 101 6 is_stmt 0 view .LVU31 170 0000 50209FE5 ldr r2, .L12 171 0004 B93F52E1 ldrh r3, [r2, #-249] 172 .LVL7: 102:board/pirelli_dpl10/rffe_dpl10_triband.c **** reg &= ~ (1 << 7); /* TSPACT4 I/O function, not nRDYMEM */ 173 .loc 1 102 2 is_stmt 1 view .LVU32 174 .loc 1 102 6 is_stmt 0 view .LVU33 175 0008 8030C3E3 bic r3, r3, #128 176 .LVL8: 103:board/pirelli_dpl10/rffe_dpl10_triband.c **** writew(reg, ARM_CONF_REG); 177 .loc 1 103 2 is_stmt 1 view .LVU34 98:board/pirelli_dpl10/rffe_dpl10_triband.c **** uint16_t reg; 178 .loc 1 98 1 is_stmt 0 view .LVU35 179 000c 10402DE9 push {r4, lr} 180 .LCFI4: 181 .cfi_def_cfa_offset 8 182 .cfi_offset 4, -8 183 .cfi_offset 14, -4 184 .loc 1 103 2 view .LVU36 185 0010 B93F42E1 strh r3, [r2, #-249] @ movhi 104:board/pirelli_dpl10/rffe_dpl10_triband.c **** 105:board/pirelli_dpl10/rffe_dpl10_triband.c **** reg = readw(ASIC_CONF_REG); 186 .loc 1 105 2 is_stmt 1 view .LVU37 187 .loc 1 105 6 is_stmt 0 view .LVU38 188 0014 B73F52E1 ldrh r3, [r2, #-247] 189 .LVL9: 106:board/pirelli_dpl10/rffe_dpl10_triband.c **** reg &= ~ (1 << 15); /* TSPACT5 I/O function, not DPLLCLK */ 190 .loc 1 106 2 is_stmt 1 view .LVU39 191 .loc 1 106 6 is_stmt 0 view .LVU40 192 0018 8338A0E1 lsl r3, r3, #17 193 .LVL10: 194 .loc 1 106 6 view .LVU41 195 001c A338A0E1 lsr r3, r3, #17 196 .LVL11: 107:board/pirelli_dpl10/rffe_dpl10_triband.c **** writew(reg, ASIC_CONF_REG); 197 .loc 1 107 2 is_stmt 1 view .LVU42 198 0020 B73F42E1 strh r3, [r2, #-247] @ movhi 108:board/pirelli_dpl10/rffe_dpl10_triband.c **** 109:board/pirelli_dpl10/rffe_dpl10_triband.c **** reg = readw(MCU_SW_TRACE); 199 .loc 1 109 2 view .LVU43 200 .loc 1 109 6 is_stmt 0 view .LVU44 201 0024 B13F52E1 ldrh r3, [r2, #-241] 202 .LVL12: 110:board/pirelli_dpl10/rffe_dpl10_triband.c **** reg &= ~(1 << 3); /* TSPACT10 I/O function, not nWAIT(1) */ 203 .loc 1 110 2 is_stmt 1 view .LVU45 111:board/pirelli_dpl10/rffe_dpl10_triband.c **** reg &= ~(1 << 2); /* TSPACT11 I/O function, not MCLK(1) */ 204 .loc 1 111 2 view .LVU46 205 .loc 1 111 6 is_stmt 0 view .LVU47 206 0028 0C30C3E3 bic r3, r3, #12 207 .LVL13: 112:board/pirelli_dpl10/rffe_dpl10_triband.c **** writew(reg, MCU_SW_TRACE); 208 .loc 1 112 2 is_stmt 1 view .LVU48 209 002c B13F42E1 strh r3, [r2, #-241] @ movhi 113:board/pirelli_dpl10/rffe_dpl10_triband.c **** 114:board/pirelli_dpl10/rffe_dpl10_triband.c **** /* Configure the TSPEN which is connected to the TWL3025 */ 115:board/pirelli_dpl10/rffe_dpl10_triband.c **** tsp_setup(IOTA_STROBE, 1, 0, 0); 210 .loc 1 115 2 view .LVU49 211 0030 0030A0E3 mov r3, #0 212 .LVL14: 213 .loc 1 115 2 is_stmt 0 view .LVU50 214 0034 0110A0E3 mov r1, #1 215 0038 0300A0E1 mov r0, r3 216 003c 0320A0E1 mov r2, r3 217 .LVL15: 218 .loc 1 115 2 view .LVU51 219 0040 FEFFFFEB bl tsp_setup 220 .LVL16: 116:board/pirelli_dpl10/rffe_dpl10_triband.c **** 117:board/pirelli_dpl10/rffe_dpl10_triband.c **** trf6151_init(RITA_STROBE, RITA_RESET); 221 .loc 1 117 2 is_stmt 1 view .LVU52 222 0044 2010A0E3 mov r1, #32 223 0048 0100A0E3 mov r0, #1 224 004c FEFFFFEB bl trf6151_init 225 .LVL17: 118:board/pirelli_dpl10/rffe_dpl10_triband.c **** } 226 .loc 1 118 1 is_stmt 0 view .LVU53 227 0050 1040BDE8 pop {r4, lr} 228 .LCFI5: 229 .cfi_restore 14 230 .cfi_restore 4 231 .cfi_def_cfa_offset 0 232 0054 1EFF2FE1 bx lr 233 .L13: 234 .align 2 235 .L12: 236 0058 FFF0FEFF .word -69377 237 .cfi_endproc 238 .LFE7: 240 .section .text.rffe_get_gain,"ax",%progbits 241 .align 2 242 .global rffe_get_gain 243 .syntax unified 244 .arm 246 rffe_get_gain: 247 .LFB8: 119:board/pirelli_dpl10/rffe_dpl10_triband.c **** 120:board/pirelli_dpl10/rffe_dpl10_triband.c **** uint8_t rffe_get_gain(void) 121:board/pirelli_dpl10/rffe_dpl10_triband.c **** { 248 .loc 1 121 1 is_stmt 1 view -0 249 .cfi_startproc 250 @ Function supports interworking. 251 @ args = 0, pretend = 0, frame = 0 252 @ frame_needed = 0, uses_anonymous_args = 0 122:board/pirelli_dpl10/rffe_dpl10_triband.c **** return trf6151_get_gain(); 253 .loc 1 122 2 view .LVU55 121:board/pirelli_dpl10/rffe_dpl10_triband.c **** return trf6151_get_gain(); 254 .loc 1 121 1 is_stmt 0 view .LVU56 255 0000 10402DE9 push {r4, lr} 256 .LCFI6: 257 .cfi_def_cfa_offset 8 258 .cfi_offset 4, -8 259 .cfi_offset 14, -4 260 .loc 1 122 9 view .LVU57 261 0004 FEFFFFEB bl trf6151_get_gain 262 .LVL18: 123:board/pirelli_dpl10/rffe_dpl10_triband.c **** } 263 .loc 1 123 1 view .LVU58 264 0008 1040BDE8 pop {r4, lr} 265 .LCFI7: 266 .cfi_restore 14 267 .cfi_restore 4 268 .cfi_def_cfa_offset 0 269 000c 1EFF2FE1 bx lr 270 .cfi_endproc 271 .LFE8: 273 .section .text.rffe_set_gain,"ax",%progbits 274 .align 2 275 .global rffe_set_gain 276 .syntax unified 277 .arm 279 rffe_set_gain: 280 .LVL19: 281 .LFB9: 124:board/pirelli_dpl10/rffe_dpl10_triband.c **** 125:board/pirelli_dpl10/rffe_dpl10_triband.c **** void rffe_set_gain(uint8_t dbm) 126:board/pirelli_dpl10/rffe_dpl10_triband.c **** { 282 .loc 1 126 1 is_stmt 1 view -0 283 .cfi_startproc 284 @ Function supports interworking. 285 @ args = 0, pretend = 0, frame = 0 286 @ frame_needed = 0, uses_anonymous_args = 0 127:board/pirelli_dpl10/rffe_dpl10_triband.c **** trf6151_set_gain(dbm); 287 .loc 1 127 2 view .LVU60 126:board/pirelli_dpl10/rffe_dpl10_triband.c **** trf6151_set_gain(dbm); 288 .loc 1 126 1 is_stmt 0 view .LVU61 289 0000 10402DE9 push {r4, lr} 290 .LCFI8: 291 .cfi_def_cfa_offset 8 292 .cfi_offset 4, -8 293 .cfi_offset 14, -4 294 .loc 1 127 2 view .LVU62 295 0004 FEFFFFEB bl trf6151_set_gain 296 .LVL20: 128:board/pirelli_dpl10/rffe_dpl10_triband.c **** } 297 .loc 1 128 1 view .LVU63 298 0008 1040BDE8 pop {r4, lr} 299 .LCFI9: 300 .cfi_restore 14 301 .cfi_restore 4 302 .cfi_def_cfa_offset 0 303 000c 1EFF2FE1 bx lr 304 .cfi_endproc 305 .LFE9: 307 .section .text.rffe_compute_gain,"ax",%progbits 308 .align 2 309 .global rffe_compute_gain 310 .syntax unified 311 .arm 313 rffe_compute_gain: 314 .LVL21: 315 .LFB10: 129:board/pirelli_dpl10/rffe_dpl10_triband.c **** 130:board/pirelli_dpl10/rffe_dpl10_triband.c **** const uint8_t system_inherent_gain = SYSTEM_INHERENT_GAIN; 131:board/pirelli_dpl10/rffe_dpl10_triband.c **** 132:board/pirelli_dpl10/rffe_dpl10_triband.c **** /* Given the expected input level of exp_inp dBm/8 and the target of target_bb 133:board/pirelli_dpl10/rffe_dpl10_triband.c **** * dBm8, configure the RF Frontend with the respective gain */ 134:board/pirelli_dpl10/rffe_dpl10_triband.c **** void rffe_compute_gain(int16_t exp_inp, int16_t target_bb) 135:board/pirelli_dpl10/rffe_dpl10_triband.c **** { 316 .loc 1 135 1 is_stmt 1 view -0 317 .cfi_startproc 318 @ Function supports interworking. 319 @ args = 0, pretend = 0, frame = 0 320 @ frame_needed = 0, uses_anonymous_args = 0 136:board/pirelli_dpl10/rffe_dpl10_triband.c **** trf6151_compute_gain(exp_inp, target_bb); 321 .loc 1 136 2 view .LVU65 135:board/pirelli_dpl10/rffe_dpl10_triband.c **** trf6151_compute_gain(exp_inp, target_bb); 322 .loc 1 135 1 is_stmt 0 view .LVU66 323 0000 10402DE9 push {r4, lr} 324 .LCFI10: 325 .cfi_def_cfa_offset 8 326 .cfi_offset 4, -8 327 .cfi_offset 14, -4 328 .loc 1 136 2 view .LVU67 329 0004 FEFFFFEB bl trf6151_compute_gain 330 .LVL22: 137:board/pirelli_dpl10/rffe_dpl10_triband.c **** } 331 .loc 1 137 1 view .LVU68 332 0008 1040BDE8 pop {r4, lr} 333 .LCFI11: 334 .cfi_restore 14 335 .cfi_restore 4 336 .cfi_def_cfa_offset 0 337 000c 1EFF2FE1 bx lr 338 .cfi_endproc 339 .LFE10: 341 .section .text.rffe_rx_win_ctrl,"ax",%progbits 342 .align 2 343 .global rffe_rx_win_ctrl 344 .syntax unified 345 .arm 347 rffe_rx_win_ctrl: 348 .LVL23: 349 .LFB11: 138:board/pirelli_dpl10/rffe_dpl10_triband.c **** 139:board/pirelli_dpl10/rffe_dpl10_triband.c **** void rffe_rx_win_ctrl(int16_t exp_inp, int16_t target_bb) 140:board/pirelli_dpl10/rffe_dpl10_triband.c **** { 350 .loc 1 140 1 is_stmt 1 view -0 351 .cfi_startproc 352 @ Function supports interworking. 353 @ args = 0, pretend = 0, frame = 0 354 @ frame_needed = 0, uses_anonymous_args = 0 355 @ link register save eliminated. 141:board/pirelli_dpl10/rffe_dpl10_triband.c **** /* FIXME */ 142:board/pirelli_dpl10/rffe_dpl10_triband.c **** } 356 .loc 1 142 1 view .LVU70 357 0000 1EFF2FE1 bx lr 358 .cfi_endproc 359 .LFE11: 361 .global system_inherent_gain 362 .section .rodata 365 system_inherent_gain: 366 0000 47 .byte 71 367 .text 368 .Letext0: 369 .file 2 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h" 370 .file 3 "../../shared/libosmocore/include/osmocom/gsm/gsm_utils.h" 371 .file 4 "include/rffe.h" 372 .file 5 "include/rf/trf6151.h" 373 .file 6 "include/calypso/tsp.h" DEFINED SYMBOLS *ABS*:00000000 rffe_dpl10_triband.c /tmp/cc1dYhhp.s:19 .text.rffe_mode:00000000 $a /tmp/cc1dYhhp.s:24 .text.rffe_mode:00000000 rffe_mode /tmp/cc1dYhhp.s:74 .text.rffe_mode:0000002c $d /tmp/cc1dYhhp.s:79 .text.rffe_get_rx_ports:00000000 $a /tmp/cc1dYhhp.s:84 .text.rffe_get_rx_ports:00000000 rffe_get_rx_ports /tmp/cc1dYhhp.s:100 .text.rffe_get_tx_ports:00000000 $a /tmp/cc1dYhhp.s:105 .text.rffe_get_tx_ports:00000000 rffe_get_tx_ports /tmp/cc1dYhhp.s:121 .text.rffe_iq_swapped:00000000 $a /tmp/cc1dYhhp.s:126 .text.rffe_iq_swapped:00000000 rffe_iq_swapped /tmp/cc1dYhhp.s:155 .text.rffe_init:00000000 $a /tmp/cc1dYhhp.s:160 .text.rffe_init:00000000 rffe_init /tmp/cc1dYhhp.s:236 .text.rffe_init:00000058 $d /tmp/cc1dYhhp.s:241 .text.rffe_get_gain:00000000 $a /tmp/cc1dYhhp.s:246 .text.rffe_get_gain:00000000 rffe_get_gain /tmp/cc1dYhhp.s:274 .text.rffe_set_gain:00000000 $a /tmp/cc1dYhhp.s:279 .text.rffe_set_gain:00000000 rffe_set_gain /tmp/cc1dYhhp.s:308 .text.rffe_compute_gain:00000000 $a /tmp/cc1dYhhp.s:313 .text.rffe_compute_gain:00000000 rffe_compute_gain /tmp/cc1dYhhp.s:342 .text.rffe_rx_win_ctrl:00000000 $a /tmp/cc1dYhhp.s:347 .text.rffe_rx_win_ctrl:00000000 rffe_rx_win_ctrl /tmp/cc1dYhhp.s:365 .rodata:00000000 system_inherent_gain UNDEFINED SYMBOLS tsp_act_state tsp_act_update trf6151_iq_swapped tsp_setup trf6151_init trf6151_get_gain trf6151_set_gain trf6151_compute_gain