1              		.cpu arm7tdmi
   2              		.arch armv4t
   3              		.fpu softvfp
   4              		.eabi_attribute 20, 1
   5              		.eabi_attribute 21, 1
   6              		.eabi_attribute 23, 3
   7              		.eabi_attribute 24, 1
   8              		.eabi_attribute 25, 1
   9              		.eabi_attribute 26, 1
  10              		.eabi_attribute 30, 4
  11              		.eabi_attribute 34, 0
  12              		.eabi_attribute 18, 4
  13              		.file	"irq.c"
  14              		.text
  15              	.Ltext0:
  16              		.cfi_sections	.debug_frame
  17              		.file 1 "calypso/irq.c"
  18              		.section	.text.irq_enable,"ax",%progbits
  19              		.align	2
  20              		.global	irq_enable
  21              		.syntax unified
  22              		.arm
  24              	irq_enable:
  25              	.LVL0:
  26              	.LFB1:
   1:calypso/irq.c **** /* Driver for Calypso IRQ controller */
   2:calypso/irq.c **** 
   3:calypso/irq.c **** /* (C) 2010 by Harald Welte <laforge@gnumonks.org>
   4:calypso/irq.c ****  *
   5:calypso/irq.c ****  * All Rights Reserved
   6:calypso/irq.c ****  *
   7:calypso/irq.c ****  * This program is free software; you can redistribute it and/or modify
   8:calypso/irq.c ****  * it under the terms of the GNU General Public License as published by
   9:calypso/irq.c ****  * the Free Software Foundation; either version 2 of the License, or
  10:calypso/irq.c ****  * (at your option) any later version.
  11:calypso/irq.c ****  *
  12:calypso/irq.c ****  * This program is distributed in the hope that it will be useful,
  13:calypso/irq.c ****  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14:calypso/irq.c ****  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15:calypso/irq.c ****  * GNU General Public License for more details.
  16:calypso/irq.c ****  *
  17:calypso/irq.c ****  */
  18:calypso/irq.c **** 
  19:calypso/irq.c **** #include <stdint.h>
  20:calypso/irq.c **** #include <stdio.h>
  21:calypso/irq.c **** 
  22:calypso/irq.c **** #include <debug.h>
  23:calypso/irq.c **** #include <memory.h>
  24:calypso/irq.c **** #include <arm.h>
  25:calypso/irq.c **** #include <calypso/irq.h>
  26:calypso/irq.c **** 
  27:calypso/irq.c **** #define BASE_ADDR_IRQ	0xfffffa00
  28:calypso/irq.c **** 
  29:calypso/irq.c **** enum irq_reg {
  30:calypso/irq.c **** 	IT_REG1		= 0x00,
  31:calypso/irq.c **** 	IT_REG2		= 0x02,
  32:calypso/irq.c **** 	MASK_IT_REG1	= 0x08,
  33:calypso/irq.c **** 	MASK_IT_REG2	= 0x0a,
  34:calypso/irq.c **** 	IRQ_NUM		= 0x10,
  35:calypso/irq.c **** 	FIQ_NUM		= 0x12,
  36:calypso/irq.c **** 	IRQ_CTRL	= 0x14,
  37:calypso/irq.c **** };
  38:calypso/irq.c **** 
  39:calypso/irq.c **** #define ILR_IRQ(x)	(0x20 + (x*2))
  40:calypso/irq.c **** #define IRQ_REG(x)	((void *)BASE_ADDR_IRQ + (x))
  41:calypso/irq.c **** 
  42:calypso/irq.c **** #define NR_IRQS	32
  43:calypso/irq.c **** 
  44:calypso/irq.c **** static uint8_t default_irq_prio[] = {
  45:calypso/irq.c **** 	[IRQ_WATCHDOG]		= 0xff,
  46:calypso/irq.c **** 	[IRQ_TIMER1]		= 0xff,
  47:calypso/irq.c **** 	[IRQ_TIMER2]		= 0xff,
  48:calypso/irq.c **** 	[IRQ_TSP_RX]		= 0,
  49:calypso/irq.c **** 	[IRQ_TPU_FRAME]		= 3,
  50:calypso/irq.c **** 	[IRQ_TPU_PAGE]		= 0xff,
  51:calypso/irq.c **** 	[IRQ_SIMCARD]		= 0xff,
  52:calypso/irq.c **** 	[IRQ_UART_MODEM]	= 8,
  53:calypso/irq.c **** 	[IRQ_KEYPAD_GPIO]	= 4,
  54:calypso/irq.c **** 	[IRQ_RTC_TIMER]		= 9,
  55:calypso/irq.c **** 	[IRQ_RTC_ALARM_I2C]	= 10,
  56:calypso/irq.c **** 	[IRQ_ULPD_GAUGING]	= 2,
  57:calypso/irq.c **** 	[IRQ_EXTERNAL]		= 12,
  58:calypso/irq.c **** 	[IRQ_SPI]		= 0xff,
  59:calypso/irq.c **** 	[IRQ_DMA]		= 0xff,
  60:calypso/irq.c **** 	[IRQ_API]		= 0xff,
  61:calypso/irq.c **** 	[IRQ_SIM_DETECT]	= 0,
  62:calypso/irq.c **** 	[IRQ_EXTERNAL_FIQ]	= 7,
  63:calypso/irq.c **** 	[IRQ_UART_IRDA]		= 2,
  64:calypso/irq.c **** 	[IRQ_ULPD_GSM_TIMER]	= 1,
  65:calypso/irq.c **** 	[IRQ_GEA]		= 0xff,
  66:calypso/irq.c **** };
  67:calypso/irq.c **** 
  68:calypso/irq.c **** static irq_handler *irq_handlers[NR_IRQS];
  69:calypso/irq.c **** 
  70:calypso/irq.c **** static void _irq_enable(enum irq_nr nr, int enable)
  71:calypso/irq.c **** {
  72:calypso/irq.c **** 	uint16_t *reg = IRQ_REG(MASK_IT_REG1);
  73:calypso/irq.c **** 	uint16_t val;
  74:calypso/irq.c **** 
  75:calypso/irq.c **** 	if (nr > 15) {
  76:calypso/irq.c **** 		reg = IRQ_REG(MASK_IT_REG2);
  77:calypso/irq.c **** 		nr -= 16;
  78:calypso/irq.c **** 	}
  79:calypso/irq.c **** 
  80:calypso/irq.c **** 	val = readw(reg);
  81:calypso/irq.c **** 	if (enable)
  82:calypso/irq.c **** 		val &= ~(1 << nr);
  83:calypso/irq.c **** 	else
  84:calypso/irq.c **** 		val |= (1 << nr);
  85:calypso/irq.c **** 	writew(val, reg);
  86:calypso/irq.c **** }
  87:calypso/irq.c **** 
  88:calypso/irq.c **** void irq_enable(enum irq_nr nr)
  89:calypso/irq.c **** {
  27              		.loc 1 89 1 view -0
  28              		.cfi_startproc
  29              		@ Function supports interworking.
  30              		@ args = 0, pretend = 0, frame = 0
  31              		@ frame_needed = 0, uses_anonymous_args = 0
  32              		@ link register save eliminated.
  90:calypso/irq.c **** 	_irq_enable(nr, 1);
  33              		.loc 1 90 2 view .LVU1
  34              	.LBB4:
  35              	.LBI4:
  70:calypso/irq.c **** {
  36              		.loc 1 70 13 view .LVU2
  37              	.LBB5:
  72:calypso/irq.c **** 	uint16_t val;
  38              		.loc 1 72 2 view .LVU3
  73:calypso/irq.c **** 
  39              		.loc 1 73 2 view .LVU4
  75:calypso/irq.c **** 		reg = IRQ_REG(MASK_IT_REG2);
  40              		.loc 1 75 2 view .LVU5
  82:calypso/irq.c **** 	else
  41              		.loc 1 82 7 is_stmt 0 view .LVU6
  42 0000 0110A0E3 		mov	r1, #1
  75:calypso/irq.c **** 		reg = IRQ_REG(MASK_IT_REG2);
  43              		.loc 1 75 5 view .LVU7
  44 0004 0F0050E3 		cmp	r0, #15
  76:calypso/irq.c **** 		nr -= 16;
  45              		.loc 1 76 3 is_stmt 1 view .LVU8
  46              	.LVL1:
  77:calypso/irq.c **** 	}
  47              		.loc 1 77 3 view .LVU9
  76:calypso/irq.c **** 		nr -= 16;
  48              		.loc 1 76 7 is_stmt 0 view .LVU10
  49 0008 18309F85 		ldrhi	r3, .L4
  72:calypso/irq.c **** 	uint16_t val;
  50              		.loc 1 72 12 view .LVU11
  51 000c 18309F95 		ldrls	r3, .L4+4
  77:calypso/irq.c **** 	}
  52              		.loc 1 77 6 view .LVU12
  53 0010 10004082 		subhi	r0, r0, #16
  54              	.LVL2:
  80:calypso/irq.c **** 	if (enable)
  55              		.loc 1 80 6 view .LVU13
  56 0014 B020D3E1 		ldrh	r2, [r3]
  77:calypso/irq.c **** 	}
  57              		.loc 1 77 6 view .LVU14
  58 0018 FF000082 		andhi	r0, r0, #255
  59              	.LVL3:
  80:calypso/irq.c **** 	if (enable)
  60              		.loc 1 80 2 is_stmt 1 view .LVU15
  81:calypso/irq.c **** 		val &= ~(1 << nr);
  61              		.loc 1 81 2 view .LVU16
  82:calypso/irq.c **** 	else
  62              		.loc 1 82 3 view .LVU17
  82:calypso/irq.c **** 	else
  63              		.loc 1 82 7 is_stmt 0 view .LVU18
  64 001c 1120C2E1 		bic	r2, r2, r1, lsl r0
  65              	.LVL4:
  85:calypso/irq.c **** }
  66              		.loc 1 85 2 is_stmt 1 view .LVU19
  67 0020 B020C3E1 		strh	r2, [r3]	@ movhi
  68              	.LVL5:
  85:calypso/irq.c **** }
  69              		.loc 1 85 2 is_stmt 0 view .LVU20
  70              	.LBE5:
  71              	.LBE4:
  91:calypso/irq.c **** }
  72              		.loc 1 91 1 view .LVU21
  73 0024 1EFF2FE1 		bx	lr
  74              	.L5:
  75              		.align	2
  76              	.L4:
  77 0028 0AFAFFFF 		.word	-1526
  78 002c 08FAFFFF 		.word	-1528
  79              		.cfi_endproc
  80              	.LFE1:
  82              		.section	.text.irq_disable,"ax",%progbits
  83              		.align	2
  84              		.global	irq_disable
  85              		.syntax unified
  86              		.arm
  88              	irq_disable:
  89              	.LVL6:
  90              	.LFB2:
  92:calypso/irq.c **** 
  93:calypso/irq.c **** void irq_disable(enum irq_nr nr)
  94:calypso/irq.c **** {
  91              		.loc 1 94 1 is_stmt 1 view -0
  92              		.cfi_startproc
  93              		@ Function supports interworking.
  94              		@ args = 0, pretend = 0, frame = 0
  95              		@ frame_needed = 0, uses_anonymous_args = 0
  96              		@ link register save eliminated.
  95:calypso/irq.c **** 	_irq_enable(nr, 0);
  97              		.loc 1 95 2 view .LVU23
  98              	.LBB8:
  99              	.LBI8:
  70:calypso/irq.c **** {
 100              		.loc 1 70 13 view .LVU24
 101              	.LBB9:
  72:calypso/irq.c **** 	uint16_t val;
 102              		.loc 1 72 2 view .LVU25
  73:calypso/irq.c **** 
 103              		.loc 1 73 2 view .LVU26
  75:calypso/irq.c **** 		reg = IRQ_REG(MASK_IT_REG2);
 104              		.loc 1 75 2 view .LVU27
  84:calypso/irq.c **** 	writew(val, reg);
 105              		.loc 1 84 7 is_stmt 0 view .LVU28
 106 0000 0110A0E3 		mov	r1, #1
  75:calypso/irq.c **** 		reg = IRQ_REG(MASK_IT_REG2);
 107              		.loc 1 75 5 view .LVU29
 108 0004 0F0050E3 		cmp	r0, #15
  76:calypso/irq.c **** 		nr -= 16;
 109              		.loc 1 76 3 is_stmt 1 view .LVU30
 110              	.LVL7:
  77:calypso/irq.c **** 	}
 111              		.loc 1 77 3 view .LVU31
  76:calypso/irq.c **** 		nr -= 16;
 112              		.loc 1 76 7 is_stmt 0 view .LVU32
 113 0008 20209F85 		ldrhi	r2, .L9
  72:calypso/irq.c **** 	uint16_t val;
 114              		.loc 1 72 12 view .LVU33
 115 000c 20209F95 		ldrls	r2, .L9+4
  77:calypso/irq.c **** 	}
 116              		.loc 1 77 6 view .LVU34
 117 0010 10004082 		subhi	r0, r0, #16
 118              	.LVL8:
  80:calypso/irq.c **** 	if (enable)
 119              		.loc 1 80 6 view .LVU35
 120 0014 B030D2E1 		ldrh	r3, [r2]
  77:calypso/irq.c **** 	}
 121              		.loc 1 77 6 view .LVU36
 122 0018 FF000082 		andhi	r0, r0, #255
 123              	.LVL9:
  80:calypso/irq.c **** 	if (enable)
 124              		.loc 1 80 2 is_stmt 1 view .LVU37
  81:calypso/irq.c **** 		val &= ~(1 << nr);
 125              		.loc 1 81 2 view .LVU38
  84:calypso/irq.c **** 	writew(val, reg);
 126              		.loc 1 84 3 view .LVU39
  84:calypso/irq.c **** 	writew(val, reg);
 127              		.loc 1 84 7 is_stmt 0 view .LVU40
 128 001c 113083E1 		orr	r3, r3, r1, lsl r0
 129              	.LVL10:
  84:calypso/irq.c **** 	writew(val, reg);
 130              		.loc 1 84 7 view .LVU41
 131 0020 0338A0E1 		lsl	r3, r3, #16
 132 0024 2338A0E1 		lsr	r3, r3, #16
 133              	.LVL11:
  85:calypso/irq.c **** }
 134              		.loc 1 85 2 is_stmt 1 view .LVU42
 135 0028 B030C2E1 		strh	r3, [r2]	@ movhi
 136              	.LVL12:
  85:calypso/irq.c **** }
 137              		.loc 1 85 2 is_stmt 0 view .LVU43
 138              	.LBE9:
 139              	.LBE8:
  96:calypso/irq.c **** }
 140              		.loc 1 96 1 view .LVU44
 141 002c 1EFF2FE1 		bx	lr
 142              	.L10:
 143              		.align	2
 144              	.L9:
 145 0030 0AFAFFFF 		.word	-1526
 146 0034 08FAFFFF 		.word	-1528
 147              		.cfi_endproc
 148              	.LFE2:
 150              		.section	.text.irq_config,"ax",%progbits
 151              		.align	2
 152              		.global	irq_config
 153              		.syntax unified
 154              		.arm
 156              	irq_config:
 157              	.LVL13:
 158              	.LFB3:
  97:calypso/irq.c **** 
  98:calypso/irq.c **** void irq_config(enum irq_nr nr, int fiq, int edge, int8_t prio)
  99:calypso/irq.c **** {
 159              		.loc 1 99 1 is_stmt 1 view -0
 160              		.cfi_startproc
 161              		@ Function supports interworking.
 162              		@ args = 0, pretend = 0, frame = 0
 163              		@ frame_needed = 0, uses_anonymous_args = 0
 164              		@ link register save eliminated.
 100:calypso/irq.c **** 	uint16_t val;
 165              		.loc 1 100 2 view .LVU46
 101:calypso/irq.c **** 
 102:calypso/irq.c **** 	if (prio == -1)
 166              		.loc 1 102 2 view .LVU47
 167              		.loc 1 102 5 is_stmt 0 view .LVU48
 168 0000 010073E3 		cmn	r3, #1
 103:calypso/irq.c **** 		prio = default_irq_prio[nr];
 169              		.loc 1 103 3 is_stmt 1 view .LVU49
 170              		.loc 1 103 26 is_stmt 0 view .LVU50
 171 0004 30309F05 		ldreq	r3, .L21
 172              	.LVL14:
 173              		.loc 1 103 8 view .LVU51
 174 0008 D0309301 		ldrsbeq	r3, [r3, r0]
 175              	.LVL15:
 104:calypso/irq.c **** 
 105:calypso/irq.c **** 	if (prio > 31)
 176              		.loc 1 105 2 is_stmt 1 view .LVU52
 106:calypso/irq.c **** 		prio = 31;
 107:calypso/irq.c **** 
 108:calypso/irq.c **** 	val = prio << 2;
 177              		.loc 1 108 2 view .LVU53
 178              		.loc 1 108 13 is_stmt 0 view .LVU54
 179 000c 1F0053E3 		cmp	r3, #31
 180 0010 1F30A0A3 		movge	r3, #31
 181              	.LVL16:
 182              		.loc 1 108 6 view .LVU55
 183 0014 0339A0E1 		lsl	r3, r3, #18
 184 0018 2338A0E1 		lsr	r3, r3, #16
 185              	.LVL17:
 109:calypso/irq.c **** 	if (edge)
 186              		.loc 1 109 2 is_stmt 1 view .LVU56
 187              		.loc 1 109 5 is_stmt 0 view .LVU57
 188 001c 000052E3 		cmp	r2, #0
 110:calypso/irq.c **** 		val |= 0x02;
 189              		.loc 1 110 3 is_stmt 1 view .LVU58
 190              		.loc 1 110 7 is_stmt 0 view .LVU59
 191 0020 02308313 		orrne	r3, r3, #2
 192              	.LVL18:
 111:calypso/irq.c **** 	if (fiq)
 193              		.loc 1 111 2 is_stmt 1 view .LVU60
 112:calypso/irq.c **** 		val |= 0x01;
 113:calypso/irq.c **** 
 114:calypso/irq.c **** 	writew(val, IRQ_REG(ILR_IRQ(nr)));
 194              		.loc 1 114 2 is_stmt 0 view .LVU61
 195 0024 8000A0E1 		lsl	r0, r0, #1
 196              	.LVL19:
 111:calypso/irq.c **** 	if (fiq)
 197              		.loc 1 111 5 view .LVU62
 198 0028 000051E3 		cmp	r1, #0
 112:calypso/irq.c **** 		val |= 0x01;
 199              		.loc 1 112 3 is_stmt 1 view .LVU63
 112:calypso/irq.c **** 		val |= 0x01;
 200              		.loc 1 112 7 is_stmt 0 view .LVU64
 201 002c 01308313 		orrne	r3, r3, #1
 202              	.LVL20:
 203              		.loc 1 114 2 is_stmt 1 view .LVU65
 204 0030 5E0E40E2 		sub	r0, r0, #1504
 205 0034 B030C0E1 		strh	r3, [r0]	@ movhi
 115:calypso/irq.c **** }
 206              		.loc 1 115 1 is_stmt 0 view .LVU66
 207 0038 1EFF2FE1 		bx	lr
 208              	.L22:
 209              		.align	2
 210              	.L21:
 211 003c 00000000 		.word	.LANCHOR0
 212              		.cfi_endproc
 213              	.LFE3:
 215              		.section	.text.irq,"ax",%progbits
 216              		.align	2
 217              		.global	irq
 218              		.syntax unified
 219              		.arm
 221              	irq:
 222              	.LFB4:
 116:calypso/irq.c **** 
 117:calypso/irq.c **** /* Entry point for interrupts */
 118:calypso/irq.c **** void irq(void)
 119:calypso/irq.c **** {
 223              		.loc 1 119 1 is_stmt 1 view -0
 224              		.cfi_startproc
 225              		@ Function supports interworking.
 226              		@ args = 0, pretend = 0, frame = 0
 227              		@ frame_needed = 0, uses_anonymous_args = 0
 120:calypso/irq.c **** 	uint8_t num, tmp;
 228              		.loc 1 120 2 view .LVU68
 121:calypso/irq.c **** 	irq_handler *handler;
 229              		.loc 1 121 2 view .LVU69
 122:calypso/irq.c **** 
 123:calypso/irq.c **** #if 1
 124:calypso/irq.c **** 	/* Hardware interrupt detection mode */
 125:calypso/irq.c **** 	num = readb(IRQ_REG(IRQ_NUM)) & 0x1f;
 230              		.loc 1 125 2 view .LVU70
 119:calypso/irq.c **** 	uint8_t num, tmp;
 231              		.loc 1 119 1 is_stmt 0 view .LVU71
 232 0000 10402DE9 		push	{r4, lr}
 233              	.LCFI0:
 234              		.cfi_def_cfa_offset 8
 235              		.cfi_offset 4, -8
 236              		.cfi_offset 14, -4
 237              		.loc 1 125 32 view .LVU72
 238 0004 054CE0E3 		mvn	r4, #1280
 239 0008 EF0054E5 		ldrb	r0, [r4, #-239]	@ zero_extendqisi2
 126:calypso/irq.c **** 
 127:calypso/irq.c **** 	printd("i%02x\n", num);
 128:calypso/irq.c **** 
 129:calypso/irq.c **** 	handler = irq_handlers[num];
 240              		.loc 1 129 10 view .LVU73
 241 000c 24309FE5 		ldr	r3, .L29
 125:calypso/irq.c **** 
 242              		.loc 1 125 6 view .LVU74
 243 0010 1F0000E2 		and	r0, r0, #31
 244              	.LVL21:
 127:calypso/irq.c **** 
 245              		.loc 1 127 24 is_stmt 1 view .LVU75
 246              		.loc 1 129 2 view .LVU76
 247              		.loc 1 129 10 is_stmt 0 view .LVU77
 248 0014 003193E7 		ldr	r3, [r3, r0, lsl #2]
 249              	.LVL22:
 130:calypso/irq.c **** 
 131:calypso/irq.c **** 	if (handler)
 250              		.loc 1 131 2 is_stmt 1 view .LVU78
 251              		.loc 1 131 5 is_stmt 0 view .LVU79
 252 0018 000053E3 		cmp	r3, #0
 132:calypso/irq.c **** 		handler(num);
 253              		.loc 1 132 3 is_stmt 1 view .LVU80
 254 001c 0FE0A011 		movne	lr, pc
 255 0020 13FF2F11 		bxne	r3
 256              	.LVL23:
 257              	.L24:
 133:calypso/irq.c **** #else
 134:calypso/irq.c **** 	/* Software interrupt detection mode */
 135:calypso/irq.c **** 	{
 136:calypso/irq.c **** 		uint16_t it_reg, mask_reg;
 137:calypso/irq.c **** 		uint32_t irqs;
 138:calypso/irq.c **** 
 139:calypso/irq.c **** 		it_reg = readw(IRQ_REG(IT_REG1));
 140:calypso/irq.c **** 		mask_reg = readw(IRQ_REG(MASK_IT_REG1));
 141:calypso/irq.c **** 		irqs = it_reg & ~mask_reg;
 142:calypso/irq.c **** 
 143:calypso/irq.c **** 		it_reg = readw(IRQ_REG(IT_REG2));
 144:calypso/irq.c **** 		mask_reg = readw(IRQ_REG(MASK_IT_REG2));
 145:calypso/irq.c **** 		irqs |= (it_reg & ~mask_reg) << 16;
 146:calypso/irq.c **** 
 147:calypso/irq.c **** 		for (num = 0; num < 32; num++) {
 148:calypso/irq.c **** 			if (irqs & (1 << num)) {
 149:calypso/irq.c **** 				printd("i%d\n", num);
 150:calypso/irq.c **** 				handler = irq_handlers[num];
 151:calypso/irq.c **** 				if (handler)
 152:calypso/irq.c **** 					handler(num);
 153:calypso/irq.c **** 				/* clear this interrupt */
 154:calypso/irq.c **** 				if (num < 16)
 155:calypso/irq.c **** 					writew(~(1 << num), IRQ_REG(IT_REG1));
 156:calypso/irq.c **** 				else
 157:calypso/irq.c **** 					writew(~(1 << (num-16)), IRQ_REG(IT_REG2));
 158:calypso/irq.c **** 			}
 159:calypso/irq.c **** 		}
 160:calypso/irq.c **** 		dputchar('\n');
 161:calypso/irq.c **** 	}
 162:calypso/irq.c **** #endif
 163:calypso/irq.c **** 	/* Start new IRQ agreement */
 164:calypso/irq.c **** 	tmp = readb(IRQ_REG(IRQ_CTRL));
 258              		.loc 1 164 2 view .LVU81
 259              		.loc 1 164 6 is_stmt 0 view .LVU82
 260 0024 EB3054E5 		ldrb	r3, [r4, #-235]	@ zero_extendqisi2
 261              	.LVL24:
 165:calypso/irq.c **** 	tmp |= 0x01;
 262              		.loc 1 165 2 is_stmt 1 view .LVU83
 263              		.loc 1 165 6 is_stmt 0 view .LVU84
 264 0028 013083E3 		orr	r3, r3, #1
 265              	.LVL25:
 166:calypso/irq.c **** 	writeb(tmp, IRQ_REG(IRQ_CTRL));
 266              		.loc 1 166 2 is_stmt 1 view .LVU85
 267 002c EB3044E5 		strb	r3, [r4, #-235]
 167:calypso/irq.c **** }
 268              		.loc 1 167 1 is_stmt 0 view .LVU86
 269 0030 1040BDE8 		pop	{r4, lr}
 270              	.LCFI1:
 271              		.cfi_restore 14
 272              		.cfi_restore 4
 273              		.cfi_def_cfa_offset 0
 274 0034 1EFF2FE1 		bx	lr
 275              	.L30:
 276              		.align	2
 277              	.L29:
 278 0038 00000000 		.word	.LANCHOR1
 279              		.cfi_endproc
 280              	.LFE4:
 282              		.section	.text.fiq,"ax",%progbits
 283              		.align	2
 284              		.global	fiq
 285              		.syntax unified
 286              		.arm
 288              	fiq:
 289              	.LFB5:
 168:calypso/irq.c **** 
 169:calypso/irq.c **** /* Entry point for FIQs */
 170:calypso/irq.c **** void fiq(void)
 171:calypso/irq.c **** {
 290              		.loc 1 171 1 is_stmt 1 view -0
 291              		.cfi_startproc
 292              		@ Function supports interworking.
 293              		@ args = 0, pretend = 0, frame = 0
 294              		@ frame_needed = 0, uses_anonymous_args = 0
 172:calypso/irq.c **** 	uint8_t num, tmp;
 295              		.loc 1 172 2 view .LVU88
 173:calypso/irq.c **** 	irq_handler *handler;
 296              		.loc 1 173 2 view .LVU89
 174:calypso/irq.c **** 
 175:calypso/irq.c **** 	num = readb(IRQ_REG(FIQ_NUM)) & 0x1f;
 297              		.loc 1 175 2 view .LVU90
 171:calypso/irq.c **** 	uint8_t num, tmp;
 298              		.loc 1 171 1 is_stmt 0 view .LVU91
 299 0000 10402DE9 		push	{r4, lr}
 300              	.LCFI2:
 301              		.cfi_def_cfa_offset 8
 302              		.cfi_offset 4, -8
 303              		.cfi_offset 14, -4
 304              		.loc 1 175 32 view .LVU92
 305 0004 054CE0E3 		mvn	r4, #1280
 306 0008 ED0054E5 		ldrb	r0, [r4, #-237]	@ zero_extendqisi2
 176:calypso/irq.c **** 	if (num) {
 177:calypso/irq.c **** 		printd("f%02x\n", num);
 178:calypso/irq.c **** 	}
 179:calypso/irq.c **** 
 180:calypso/irq.c **** 	handler = irq_handlers[num];
 307              		.loc 1 180 10 view .LVU93
 308 000c 24309FE5 		ldr	r3, .L37
 175:calypso/irq.c **** 	if (num) {
 309              		.loc 1 175 6 view .LVU94
 310 0010 1F0000E2 		and	r0, r0, #31
 311              	.LVL26:
 176:calypso/irq.c **** 	if (num) {
 312              		.loc 1 176 2 is_stmt 1 view .LVU95
 177:calypso/irq.c **** 	}
 313              		.loc 1 177 25 view .LVU96
 314              		.loc 1 180 2 view .LVU97
 315              		.loc 1 180 10 is_stmt 0 view .LVU98
 316 0014 003193E7 		ldr	r3, [r3, r0, lsl #2]
 317              	.LVL27:
 181:calypso/irq.c **** 
 182:calypso/irq.c **** 	if (handler)
 318              		.loc 1 182 2 is_stmt 1 view .LVU99
 319              		.loc 1 182 5 is_stmt 0 view .LVU100
 320 0018 000053E3 		cmp	r3, #0
 183:calypso/irq.c **** 		handler(num);
 321              		.loc 1 183 3 is_stmt 1 view .LVU101
 322 001c 0FE0A011 		movne	lr, pc
 323 0020 13FF2F11 		bxne	r3
 324              	.LVL28:
 325              	.L32:
 184:calypso/irq.c **** 
 185:calypso/irq.c **** 	/* Start new FIQ agreement */
 186:calypso/irq.c **** 	tmp = readb(IRQ_REG(IRQ_CTRL));
 326              		.loc 1 186 2 view .LVU102
 327              		.loc 1 186 6 is_stmt 0 view .LVU103
 328 0024 EB3054E5 		ldrb	r3, [r4, #-235]	@ zero_extendqisi2
 329              	.LVL29:
 187:calypso/irq.c **** 	tmp |= 0x02;
 330              		.loc 1 187 2 is_stmt 1 view .LVU104
 331              		.loc 1 187 6 is_stmt 0 view .LVU105
 332 0028 023083E3 		orr	r3, r3, #2
 333              	.LVL30:
 188:calypso/irq.c **** 	writeb(tmp, IRQ_REG(IRQ_CTRL));
 334              		.loc 1 188 2 is_stmt 1 view .LVU106
 335 002c EB3044E5 		strb	r3, [r4, #-235]
 189:calypso/irq.c **** }
 336              		.loc 1 189 1 is_stmt 0 view .LVU107
 337 0030 1040BDE8 		pop	{r4, lr}
 338              	.LCFI3:
 339              		.cfi_restore 14
 340              		.cfi_restore 4
 341              		.cfi_def_cfa_offset 0
 342 0034 1EFF2FE1 		bx	lr
 343              	.L38:
 344              		.align	2
 345              	.L37:
 346 0038 00000000 		.word	.LANCHOR1
 347              		.cfi_endproc
 348              	.LFE5:
 350              		.section	.text.irq_register_handler,"ax",%progbits
 351              		.align	2
 352              		.global	irq_register_handler
 353              		.syntax unified
 354              		.arm
 356              	irq_register_handler:
 357              	.LVL31:
 358              	.LFB6:
 190:calypso/irq.c **** 
 191:calypso/irq.c **** void irq_register_handler(enum irq_nr nr, irq_handler *handler)
 192:calypso/irq.c **** {
 359              		.loc 1 192 1 is_stmt 1 view -0
 360              		.cfi_startproc
 361              		@ Function supports interworking.
 362              		@ args = 0, pretend = 0, frame = 0
 363              		@ frame_needed = 0, uses_anonymous_args = 0
 364              		@ link register save eliminated.
 193:calypso/irq.c **** 	if (nr >= NR_IRQS)
 365              		.loc 1 193 2 view .LVU109
 366              		.loc 1 193 5 is_stmt 0 view .LVU110
 367 0000 1F0050E3 		cmp	r0, #31
 194:calypso/irq.c **** 		return;
 195:calypso/irq.c **** 
 196:calypso/irq.c **** 	irq_handlers[nr] = handler;
 368              		.loc 1 196 2 is_stmt 1 view .LVU111
 369              		.loc 1 196 19 is_stmt 0 view .LVU112
 370 0004 04309F95 		ldrls	r3, .L41
 371 0008 00118397 		strls	r1, [r3, r0, lsl #2]
 197:calypso/irq.c **** }
 372              		.loc 1 197 1 view .LVU113
 373 000c 1EFF2FE1 		bx	lr
 374              	.L42:
 375              		.align	2
 376              	.L41:
 377 0010 00000000 		.word	.LANCHOR1
 378              		.cfi_endproc
 379              	.LFE6:
 381              		.section	.text.calypso_exceptions_install,"ax",%progbits
 382              		.align	2
 383              		.global	calypso_exceptions_install
 384              		.syntax unified
 385              		.arm
 387              	calypso_exceptions_install:
 388              	.LFB7:
 198:calypso/irq.c **** 
 199:calypso/irq.c **** #define BASE_ADDR_IBOOT_EXC	0x0080001C
 200:calypso/irq.c **** extern uint32_t _exceptions;
 201:calypso/irq.c **** 
 202:calypso/irq.c **** /* Install the exception handlers to where the ROM loader jumps */
 203:calypso/irq.c **** void calypso_exceptions_install(void)
 204:calypso/irq.c **** {
 389              		.loc 1 204 1 is_stmt 1 view -0
 390              		.cfi_startproc
 391              		@ Function supports interworking.
 392              		@ args = 0, pretend = 0, frame = 0
 393              		@ frame_needed = 0, uses_anonymous_args = 0
 394              		@ link register save eliminated.
 205:calypso/irq.c **** 	uint32_t *exceptions_dst = (uint32_t *) BASE_ADDR_IBOOT_EXC;
 395              		.loc 1 205 2 view .LVU115
 396              	.LVL32:
 206:calypso/irq.c **** 	uint32_t *exceptions_src = &_exceptions;
 397              		.loc 1 206 2 view .LVU116
 207:calypso/irq.c **** 	int i;
 398              		.loc 1 207 2 view .LVU117
 208:calypso/irq.c **** 
 209:calypso/irq.c **** 	for (i = 0; i < 7; i++)
 399              		.loc 1 209 2 view .LVU118
 400              		.loc 1 209 16 view .LVU119
 206:calypso/irq.c **** 	int i;
 401              		.loc 1 206 12 is_stmt 0 view .LVU120
 402 0000 20209FE5 		ldr	r2, .L47
 205:calypso/irq.c **** 	uint32_t *exceptions_src = &_exceptions;
 403              		.loc 1 205 12 view .LVU121
 404 0004 20309FE5 		ldr	r3, .L47+4
 405              		.loc 1 209 16 view .LVU122
 406 0008 20109FE5 		ldr	r1, .L47+8
 407              	.LVL33:
 408              	.L44:
 210:calypso/irq.c **** 		*exceptions_dst++ = *exceptions_src++;
 409              		.loc 1 210 3 is_stmt 1 discriminator 3 view .LVU123
 410              		.loc 1 210 3 is_stmt 0 discriminator 3 view .LVU124
 411 000c 0300A0E1 		mov	r0, r3
 412              		.loc 1 210 23 discriminator 3 view .LVU125
 413 0010 04C092E4 		ldr	ip, [r2], #4
 414              	.LVL34:
 415              		.loc 1 210 18 discriminator 3 view .LVU126
 416 0014 043083E2 		add	r3, r3, #4
 417              	.LVL35:
 209:calypso/irq.c **** 		*exceptions_dst++ = *exceptions_src++;
 418              		.loc 1 209 16 discriminator 3 view .LVU127
 419 0018 010053E1 		cmp	r3, r1
 420              		.loc 1 210 21 discriminator 3 view .LVU128
 421 001c 00C080E5 		str	ip, [r0]
 209:calypso/irq.c **** 		*exceptions_dst++ = *exceptions_src++;
 422              		.loc 1 209 22 is_stmt 1 discriminator 3 view .LVU129
 209:calypso/irq.c **** 		*exceptions_dst++ = *exceptions_src++;
 423              		.loc 1 209 16 discriminator 3 view .LVU130
 424 0020 F9FFFF1A 		bne	.L44
 425 0024 1EFF2FE1 		bx	lr
 426              	.L48:
 427              		.align	2
 428              	.L47:
 429 0028 00000000 		.word	_exceptions
 430 002c 1C008000 		.word	8388636
 431 0030 38008000 		.word	8388664
 432              		.cfi_endproc
 433              	.LFE7:
 435              		.section	.text.irq_init,"ax",%progbits
 436              		.align	2
 437              		.global	irq_init
 438              		.syntax unified
 439              		.arm
 441              	irq_init:
 442              	.LFB10:
 211:calypso/irq.c **** 
 212:calypso/irq.c **** }
 213:calypso/irq.c **** 
 214:calypso/irq.c **** static void set_default_priorities(void)
 215:calypso/irq.c **** {
 216:calypso/irq.c **** 	unsigned int i;
 217:calypso/irq.c **** 
 218:calypso/irq.c **** 	for (i = 0; i < ARRAY_SIZE(default_irq_prio); i++) {
 219:calypso/irq.c **** 		uint16_t val;
 220:calypso/irq.c **** 		uint8_t prio = default_irq_prio[i];
 221:calypso/irq.c **** 		if (prio > 31)
 222:calypso/irq.c **** 			prio = 31;
 223:calypso/irq.c **** 
 224:calypso/irq.c **** 		val = readw(IRQ_REG(ILR_IRQ(i)));
 225:calypso/irq.c **** 		val &= ~(0x1f << 2);
 226:calypso/irq.c **** 		val |= prio << 2;
 227:calypso/irq.c **** 		writew(val, IRQ_REG(ILR_IRQ(i)));
 228:calypso/irq.c **** 	}
 229:calypso/irq.c **** }
 230:calypso/irq.c **** 
 231:calypso/irq.c **** static uint32_t irq_nest_mask;
 232:calypso/irq.c **** /* mask off all interrupts that have a lower priority than irq_nr */
 233:calypso/irq.c **** static void mask_all_lower_prio_irqs(enum irq_nr irqnr)
 234:calypso/irq.c **** {
 235:calypso/irq.c **** 	uint8_t our_prio = readb(IRQ_REG(ILR_IRQ(irqnr))) >> 2;
 236:calypso/irq.c **** 	int i;
 237:calypso/irq.c **** 
 238:calypso/irq.c **** 	for (i = 0; i < _NR_IRQ; i++) {
 239:calypso/irq.c **** 		uint8_t prio;
 240:calypso/irq.c **** 
 241:calypso/irq.c **** 		if (i == irqnr)
 242:calypso/irq.c **** 			continue;
 243:calypso/irq.c **** 
 244:calypso/irq.c **** 		prio = readb(IRQ_REG(ILR_IRQ(i))) >> 2;
 245:calypso/irq.c **** 		if (prio >= our_prio)
 246:calypso/irq.c **** 			irq_nest_mask |= (1 << i);
 247:calypso/irq.c **** 	}
 248:calypso/irq.c **** }
 249:calypso/irq.c **** 
 250:calypso/irq.c **** void irq_init(void)
 251:calypso/irq.c **** {
 443              		.loc 1 251 1 view -0
 444              		.cfi_startproc
 445              		@ Function supports interworking.
 446              		@ args = 0, pretend = 0, frame = 0
 447              		@ frame_needed = 0, uses_anonymous_args = 0
 252:calypso/irq.c **** 	/* set default priorities */
 253:calypso/irq.c **** 	set_default_priorities();
 448              		.loc 1 253 2 view .LVU132
 449              	.LBB13:
 450              	.LBI13:
 214:calypso/irq.c **** {
 451              		.loc 1 214 13 view .LVU133
 452              	.LBB14:
 216:calypso/irq.c **** 
 453              		.loc 1 216 2 view .LVU134
 218:calypso/irq.c **** 		uint16_t val;
 454              		.loc 1 218 2 view .LVU135
 455              	.LVL36:
 218:calypso/irq.c **** 		uint16_t val;
 456              		.loc 1 218 16 view .LVU136
 457              	.LBE14:
 458              	.LBE13:
 251:calypso/irq.c **** 	/* set default priorities */
 459              		.loc 1 251 1 is_stmt 0 view .LVU137
 460 0000 10402DE9 		push	{r4, lr}
 461              	.LCFI4:
 462              		.cfi_def_cfa_offset 8
 463              		.cfi_offset 4, -8
 464              		.cfi_offset 14, -4
 465 0004 50009FE5 		ldr	r0, .L53
 251:calypso/irq.c **** 	/* set default priorities */
 466              		.loc 1 251 1 view .LVU138
 467 0008 50209FE5 		ldr	r2, .L53+4
 468              	.LBB17:
 469              	.LBB16:
 218:calypso/irq.c **** 		uint16_t val;
 470              		.loc 1 218 16 view .LVU139
 471 000c 50C09FE5 		ldr	ip, .L53+8
 472              	.LVL37:
 473              	.L50:
 474              	.LBB15:
 219:calypso/irq.c **** 		uint8_t prio = default_irq_prio[i];
 475              		.loc 1 219 3 is_stmt 1 view .LVU140
 220:calypso/irq.c **** 		if (prio > 31)
 476              		.loc 1 220 3 view .LVU141
 220:calypso/irq.c **** 		if (prio > 31)
 477              		.loc 1 220 11 is_stmt 0 view .LVU142
 478 0010 0110D0E4 		ldrb	r1, [r0], #1	@ zero_extendqisi2
 479              	.LVL38:
 221:calypso/irq.c **** 			prio = 31;
 480              		.loc 1 221 3 is_stmt 1 view .LVU143
 224:calypso/irq.c **** 		val &= ~(0x1f << 2);
 481              		.loc 1 224 3 view .LVU144
 226:calypso/irq.c **** 		writew(val, IRQ_REG(ILR_IRQ(i)));
 482              		.loc 1 226 15 is_stmt 0 view .LVU145
 483 0014 1F0051E3 		cmp	r1, #31
 484 0018 1F10A023 		movcs	r1, #31
 485              	.LVL39:
 224:calypso/irq.c **** 		val &= ~(0x1f << 2);
 486              		.loc 1 224 7 view .LVU146
 487 001c B030D2E1 		ldrh	r3, [r2]
 488              	.LVL40:
 225:calypso/irq.c **** 		val |= prio << 2;
 489              		.loc 1 225 3 is_stmt 1 view .LVU147
 225:calypso/irq.c **** 		val |= prio << 2;
 490              		.loc 1 225 7 is_stmt 0 view .LVU148
 491 0020 7C30C3E3 		bic	r3, r3, #124
 492              	.LVL41:
 226:calypso/irq.c **** 		writew(val, IRQ_REG(ILR_IRQ(i)));
 493              		.loc 1 226 3 is_stmt 1 view .LVU149
 226:calypso/irq.c **** 		writew(val, IRQ_REG(ILR_IRQ(i)));
 494              		.loc 1 226 7 is_stmt 0 view .LVU150
 495 0024 013183E1 		orr	r3, r3, r1, lsl #2
 496              	.LVL42:
 227:calypso/irq.c **** 	}
 497              		.loc 1 227 3 is_stmt 1 view .LVU151
 498 0028 B230C2E0 		strh	r3, [r2], #2	@ movhi
 499              	.LVL43:
 227:calypso/irq.c **** 	}
 500              		.loc 1 227 3 is_stmt 0 view .LVU152
 501              	.LBE15:
 218:calypso/irq.c **** 		uint16_t val;
 502              		.loc 1 218 49 is_stmt 1 view .LVU153
 218:calypso/irq.c **** 		uint16_t val;
 503              		.loc 1 218 16 view .LVU154
 504 002c 0C0052E1 		cmp	r2, ip
 505 0030 F6FFFF1A 		bne	.L50
 506              	.LVL44:
 218:calypso/irq.c **** 		uint16_t val;
 507              		.loc 1 218 16 is_stmt 0 view .LVU155
 508              	.LBE16:
 509              	.LBE17:
 254:calypso/irq.c **** 	/* mask all interrupts off */
 255:calypso/irq.c **** 	writew(0xffff, IRQ_REG(MASK_IT_REG1));
 510              		.loc 1 255 2 is_stmt 1 view .LVU156
 511 0034 053CE0E3 		mvn	r3, #1280
 512 0038 0020E0E3 		mvn	r2, #0
 513 003c B72F43E1 		strh	r2, [r3, #-247]	@ movhi
 256:calypso/irq.c **** 	writew(0xffff, IRQ_REG(MASK_IT_REG2));
 514              		.loc 1 256 2 view .LVU157
 515 0040 B52F43E1 		strh	r2, [r3, #-245]	@ movhi
 257:calypso/irq.c **** 	/* clear all pending interrupts */
 258:calypso/irq.c **** 	writew(0, IRQ_REG(IT_REG1));
 516              		.loc 1 258 2 view .LVU158
 517 0044 0020A0E3 		mov	r2, #0
 518 0048 BF2F43E1 		strh	r2, [r3, #-255]	@ movhi
 259:calypso/irq.c **** 	writew(0, IRQ_REG(IT_REG2));
 519              		.loc 1 259 2 view .LVU159
 520 004c BD2F43E1 		strh	r2, [r3, #-253]	@ movhi
 260:calypso/irq.c **** 	/* enable interrupts globally to the ARM core */
 261:calypso/irq.c **** 	arm_enable_interrupts();
 521              		.loc 1 261 2 view .LVU160
 522 0050 FEFFFFEB 		bl	arm_enable_interrupts
 523              	.LVL45:
 262:calypso/irq.c **** }
 524              		.loc 1 262 1 is_stmt 0 view .LVU161
 525 0054 1040BDE8 		pop	{r4, lr}
 526              	.LCFI5:
 527              		.cfi_restore 14
 528              		.cfi_restore 4
 529              		.cfi_def_cfa_offset 0
 530 0058 1EFF2FE1 		bx	lr
 531              	.L54:
 532              		.align	2
 533              	.L53:
 534 005c 00000000 		.word	.LANCHOR0
 535 0060 20FAFFFF 		.word	-1504
 536 0064 4AFAFFFF 		.word	-1462
 537              		.cfi_endproc
 538              	.LFE10:
 540              		.section	.rodata
 541              		.set	.LANCHOR0,. + 0
 544              	default_irq_prio:
 545 0000 FFFFFF00 		.ascii	"\377\377\377\000\003\377\377\010\004\011\012\002\014"
 545      03FFFF08 
 545      04090A02 
 545      0C
 546 000d FFFFFF00 		.ascii	"\377\377\377\000\007\002\001\377"
 546      070201FF 
 547              		.bss
 548              		.align	2
 549              		.set	.LANCHOR1,. + 0
 552              	irq_handlers:
 553 0000 00000000 		.space	128
 553      00000000 
 553      00000000 
 553      00000000 
 553      00000000 
 554              		.text
 555              	.Letext0:
 556              		.file 2 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
 557              		.file 3 "include/calypso/irq.h"
 558              		.file 4 "include/arm.h"
DEFINED SYMBOLS
                            *ABS*:00000000 irq.c
     /tmp/ccOcOrNU.s:19     .text.irq_enable:00000000 $a
     /tmp/ccOcOrNU.s:24     .text.irq_enable:00000000 irq_enable
     /tmp/ccOcOrNU.s:77     .text.irq_enable:00000028 $d
     /tmp/ccOcOrNU.s:83     .text.irq_disable:00000000 $a
     /tmp/ccOcOrNU.s:88     .text.irq_disable:00000000 irq_disable
     /tmp/ccOcOrNU.s:145    .text.irq_disable:00000030 $d
     /tmp/ccOcOrNU.s:151    .text.irq_config:00000000 $a
     /tmp/ccOcOrNU.s:156    .text.irq_config:00000000 irq_config
     /tmp/ccOcOrNU.s:211    .text.irq_config:0000003c $d
     /tmp/ccOcOrNU.s:216    .text.irq:00000000 $a
     /tmp/ccOcOrNU.s:221    .text.irq:00000000 irq
     /tmp/ccOcOrNU.s:278    .text.irq:00000038 $d
     /tmp/ccOcOrNU.s:283    .text.fiq:00000000 $a
     /tmp/ccOcOrNU.s:288    .text.fiq:00000000 fiq
     /tmp/ccOcOrNU.s:346    .text.fiq:00000038 $d
     /tmp/ccOcOrNU.s:351    .text.irq_register_handler:00000000 $a
     /tmp/ccOcOrNU.s:356    .text.irq_register_handler:00000000 irq_register_handler
     /tmp/ccOcOrNU.s:377    .text.irq_register_handler:00000010 $d
     /tmp/ccOcOrNU.s:382    .text.calypso_exceptions_install:00000000 $a
     /tmp/ccOcOrNU.s:387    .text.calypso_exceptions_install:00000000 calypso_exceptions_install
     /tmp/ccOcOrNU.s:429    .text.calypso_exceptions_install:00000028 $d
     /tmp/ccOcOrNU.s:436    .text.irq_init:00000000 $a
     /tmp/ccOcOrNU.s:441    .text.irq_init:00000000 irq_init
     /tmp/ccOcOrNU.s:534    .text.irq_init:0000005c $d
     /tmp/ccOcOrNU.s:544    .rodata:00000000 default_irq_prio
     /tmp/ccOcOrNU.s:548    .bss:00000000 $d
     /tmp/ccOcOrNU.s:552    .bss:00000000 irq_handlers

UNDEFINED SYMBOLS
_exceptions
arm_enable_interrupts