1 .cpu arm7tdmi 2 .arch armv4t 3 .fpu softvfp 4 .eabi_attribute 20, 1 5 .eabi_attribute 21, 1 6 .eabi_attribute 23, 3 7 .eabi_attribute 24, 1 8 .eabi_attribute 25, 1 9 .eabi_attribute 26, 1 10 .eabi_attribute 30, 4 11 .eabi_attribute 34, 0 12 .eabi_attribute 18, 4 13 .file "uwire.c" 14 .text 15 .Ltext0: 16 .cfi_sections .debug_frame 17 .file 1 "calypso/uwire.c" 18 .section .text.uwire_init,"ax",%progbits 19 .align 2 20 .global uwire_init 21 .syntax unified 22 .arm 24 uwire_init: 25 .LFB1: 1:calypso/uwire.c **** /* Driver for uWire Master Controller inside TI Calypso */ 2:calypso/uwire.c **** 3:calypso/uwire.c **** /* (C) 2010 by Sylvain Munaut 4:calypso/uwire.c **** * 5:calypso/uwire.c **** * All Rights Reserved 6:calypso/uwire.c **** * 7:calypso/uwire.c **** * This program is free software; you can redistribute it and/or modify 8:calypso/uwire.c **** * it under the terms of the GNU General Public License as published by 9:calypso/uwire.c **** * the Free Software Foundation; either version 2 of the License, or 10:calypso/uwire.c **** * (at your option) any later version. 11:calypso/uwire.c **** * 12:calypso/uwire.c **** * This program is distributed in the hope that it will be useful, 13:calypso/uwire.c **** * but WITHOUT ANY WARRANTY; without even the implied warranty of 14:calypso/uwire.c **** * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15:calypso/uwire.c **** * GNU General Public License for more details. 16:calypso/uwire.c **** * 17:calypso/uwire.c **** */ 18:calypso/uwire.c **** 19:calypso/uwire.c **** #include 20:calypso/uwire.c **** #include 21:calypso/uwire.c **** 22:calypso/uwire.c **** //#define DEBUG 23:calypso/uwire.c **** #include 24:calypso/uwire.c **** 25:calypso/uwire.c **** #include 26:calypso/uwire.c **** #include 27:calypso/uwire.c **** #include 28:calypso/uwire.c **** 29:calypso/uwire.c **** #define BASE_ADDR_UWIRE 0xfffe4000 30:calypso/uwire.c **** #define UWIRE_REG(n) (BASE_ADDR_UWIRE+(n)) 31:calypso/uwire.c **** 32:calypso/uwire.c **** enum uwire_regs { 33:calypso/uwire.c **** REG_DATA = 0x00, 34:calypso/uwire.c **** REG_CSR = 0x02, 35:calypso/uwire.c **** REG_SR1 = 0x04, 36:calypso/uwire.c **** REG_SR2 = 0x06, 37:calypso/uwire.c **** REG_SR3 = 0x08, 38:calypso/uwire.c **** }; 39:calypso/uwire.c **** 40:calypso/uwire.c **** #define UWIRE_CSR_BITS_RD(n) (((n) & 0x1f) << 0) 41:calypso/uwire.c **** #define UWIRE_CSR_BITS_WR(n) (((n) & 0x1f) << 5) 42:calypso/uwire.c **** #define UWIRE_CSR_IDX(n) (((n) & 3) << 10) 43:calypso/uwire.c **** #define UWIRE_CSR_CS_CMD (1 << 12) 44:calypso/uwire.c **** #define UWIRE_CSR_START (1 << 13) 45:calypso/uwire.c **** #define UWIRE_CSR_CSRB (1 << 14) 46:calypso/uwire.c **** #define UWIRE_CSR_RDRB (1 << 15) 47:calypso/uwire.c **** 48:calypso/uwire.c **** #define UWIRE_CSn_EDGE_RD (1 << 0) /* 1=falling 0=rising */ 49:calypso/uwire.c **** #define UWIRE_CSn_EDGE_WR (1 << 1) /* 1=falling 0=rising */ 50:calypso/uwire.c **** #define UWIRE_CSn_CS_LVL (1 << 2) 51:calypso/uwire.c **** #define UWIRE_CSn_FRQ_DIV2 (0 << 3) 52:calypso/uwire.c **** #define UWIRE_CSn_FRQ_DIV4 (1 << 3) 53:calypso/uwire.c **** #define UWIRE_CSn_FRQ_DIV8 (2 << 3) 54:calypso/uwire.c **** #define UWIRE_CSn_CKH 55:calypso/uwire.c **** 56:calypso/uwire.c **** #define UWIRE_CSn_SHIFT(n) (((n) & 1) ? 6 : 0) 57:calypso/uwire.c **** #define UWIRE_CSn_REG(n) (((n) & 2) ? REG_SR2 : REG_SR1) 58:calypso/uwire.c **** 59:calypso/uwire.c **** #define UWIRE_SR3_CLK_EN (1 << 0) 60:calypso/uwire.c **** #define UWIRE_SR3_CLK_DIV2 (0 << 1) 61:calypso/uwire.c **** #define UWIRE_SR3_CLK_DIV4 (1 << 1) 62:calypso/uwire.c **** #define UWIRE_SR3_CLK_DIV7 (2 << 1) 63:calypso/uwire.c **** #define UWIRE_SR3_CLK_DIV10 (3 << 1) 64:calypso/uwire.c **** 65:calypso/uwire.c **** static inline void _uwire_wait(int mask, int val) 66:calypso/uwire.c **** { 67:calypso/uwire.c **** while ((readw(UWIRE_REG(REG_CSR)) & mask) != val); 68:calypso/uwire.c **** } 69:calypso/uwire.c **** 70:calypso/uwire.c **** void uwire_init(void) 71:calypso/uwire.c **** { 26 .loc 1 71 1 view -0 27 .cfi_startproc 28 @ Function supports interworking. 29 @ args = 0, pretend = 0, frame = 0 30 @ frame_needed = 0, uses_anonymous_args = 0 31 @ link register save eliminated. 72:calypso/uwire.c **** writew(UWIRE_SR3_CLK_EN | UWIRE_SR3_CLK_DIV2, UWIRE_REG(REG_SR3)); 32 .loc 1 72 2 view .LVU1 33 0000 0120A0E3 mov r2, #1 34 0004 20309FE5 ldr r3, .L5 35 0008 B72F43E1 strh r2, [r3, #-247] @ movhi 73:calypso/uwire.c **** /* FIXME only init CS0 for now */ 74:calypso/uwire.c **** writew(((UWIRE_CSn_CS_LVL | UWIRE_CSn_FRQ_DIV2) << UWIRE_CSn_SHIFT(0)), 36 .loc 1 74 2 view .LVU2 37 000c 0420A0E3 mov r2, #4 38 0010 BB2F43E1 strh r2, [r3, #-251] @ movhi 75:calypso/uwire.c **** UWIRE_REG(UWIRE_CSn_REG(0))); 76:calypso/uwire.c **** writew(UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD, UWIRE_REG(REG_CSR)); 39 .loc 1 76 2 view .LVU3 40 0014 012AA0E3 mov r2, #4096 41 0018 BD2F43E1 strh r2, [r3, #-253] @ movhi 77:calypso/uwire.c **** _uwire_wait(UWIRE_CSR_CSRB, 0); 42 .loc 1 77 2 view .LVU4 43 .LVL0: 44 .LBB4: 45 .LBI4: 65:calypso/uwire.c **** { 46 .loc 1 65 20 view .LVU5 47 .LBB5: 67:calypso/uwire.c **** } 48 .loc 1 67 2 view .LVU6 49 .L2: 67:calypso/uwire.c **** } 50 .loc 1 67 44 view .LVU7 67:calypso/uwire.c **** } 51 .loc 1 67 10 is_stmt 0 view .LVU8 52 001c BD2F53E1 ldrh r2, [r3, #-253] 67:calypso/uwire.c **** } 53 .loc 1 67 44 view .LVU9 54 0020 010912E3 tst r2, #16384 55 0024 FCFFFF1A bne .L2 56 0028 1EFF2FE1 bx lr 57 .L6: 58 .align 2 59 .L5: 60 002c FF40FEFF .word -114433 61 .LBE5: 62 .LBE4: 63 .cfi_endproc 64 .LFE1: 66 .section .text.uwire_xfer,"ax",%progbits 67 .align 2 68 .global uwire_xfer 69 .syntax unified 70 .arm 72 uwire_xfer: 73 .LVL1: 74 .LFB2: 78:calypso/uwire.c **** } 79:calypso/uwire.c **** 80:calypso/uwire.c **** int uwire_xfer(int cs, int bitlen, const void *dout, void *din) 81:calypso/uwire.c **** { 75 .loc 1 81 1 is_stmt 1 view -0 76 .cfi_startproc 77 @ Function supports interworking. 78 @ args = 0, pretend = 0, frame = 0 79 @ frame_needed = 0, uses_anonymous_args = 0 80 @ link register save eliminated. 82:calypso/uwire.c **** uint16_t tmp = 0; 81 .loc 1 82 2 view .LVU11 83:calypso/uwire.c **** 84:calypso/uwire.c **** if (bitlen <= 0 || bitlen > 16) 82 .loc 1 84 2 view .LVU12 83 .loc 1 84 18 is_stmt 0 view .LVU13 84 0000 01C041E2 sub ip, r1, #1 85 .loc 1 84 5 view .LVU14 86 0004 0F005CE3 cmp ip, #15 87 0008 3100008A bhi .L20 85:calypso/uwire.c **** return -1; 86:calypso/uwire.c **** if (cs < 0 || cs > 4) 88 .loc 1 86 2 is_stmt 1 view .LVU15 89 .loc 1 86 5 is_stmt 0 view .LVU16 90 000c 040050E3 cmp r0, #4 91 0010 2F00008A bhi .L20 87:calypso/uwire.c **** return -1; 88:calypso/uwire.c **** 89:calypso/uwire.c **** /* FIXME uwire_init always selects CS0 for now */ 90:calypso/uwire.c **** 91:calypso/uwire.c **** printd("uwire_xfer(dev_idx=%u, bitlen=%u\n", cs, bitlen); 92 .loc 1 91 58 is_stmt 1 view .LVU17 92:calypso/uwire.c **** 93:calypso/uwire.c **** /* select the chip */ 94:calypso/uwire.c **** writew(UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD, UWIRE_REG(REG_CSR)); 93 .loc 1 94 2 view .LVU18 94 0014 01CAA0E3 mov ip, #4096 95 0018 BC009FE5 ldr r0, .L31 96 .LVL2: 97 .loc 1 94 2 is_stmt 0 view .LVU19 98 001c BDCF40E1 strh ip, [r0, #-253] @ movhi 95:calypso/uwire.c **** _uwire_wait(UWIRE_CSR_CSRB, 0); 99 .loc 1 95 2 is_stmt 1 view .LVU20 100 .LVL3: 101 .LBB14: 102 .LBI14: 65:calypso/uwire.c **** { 103 .loc 1 65 20 view .LVU21 104 .LBB15: 67:calypso/uwire.c **** } 105 .loc 1 67 2 view .LVU22 106 .L9: 67:calypso/uwire.c **** } 107 .loc 1 67 44 view .LVU23 67:calypso/uwire.c **** } 108 .loc 1 67 10 is_stmt 0 view .LVU24 109 0020 BDCF50E1 ldrh ip, [r0, #-253] 67:calypso/uwire.c **** } 110 .loc 1 67 44 view .LVU25 111 0024 01091CE3 tst ip, #16384 112 0028 FCFFFF1A bne .L9 113 .LVL4: 67:calypso/uwire.c **** } 114 .loc 1 67 44 view .LVU26 115 .LBE15: 116 .LBE14: 96:calypso/uwire.c **** 97:calypso/uwire.c **** if (dout) { 117 .loc 1 97 2 is_stmt 1 view .LVU27 118 .loc 1 97 5 is_stmt 0 view .LVU28 119 002c 000052E3 cmp r2, #0 120 0030 0A00000A beq .L10 98:calypso/uwire.c **** if (bitlen <= 8) 121 .loc 1 98 3 is_stmt 1 view .LVU29 122 .loc 1 98 6 is_stmt 0 view .LVU30 123 0034 080051E3 cmp r1, #8 99:calypso/uwire.c **** tmp = *(uint8_t *)dout; 124 .loc 1 99 4 is_stmt 1 view .LVU31 125 .loc 1 99 8 is_stmt 0 view .LVU32 126 0038 0020D2D5 ldrble r2, [r2] @ zero_extendqisi2 127 .LVL5: 100:calypso/uwire.c **** else if (bitlen <= 16) 128 .loc 1 100 8 is_stmt 1 view .LVU33 101:calypso/uwire.c **** tmp = *(uint16_t *)dout; 129 .loc 1 101 4 view .LVU34 130 .loc 1 101 8 is_stmt 0 view .LVU35 131 003c B020D2C1 ldrhgt r2, [r2] 132 .LVL6: 102:calypso/uwire.c **** tmp <<= 16 - bitlen; /* align to MSB */ 133 .loc 1 102 3 is_stmt 1 view .LVU36 134 .loc 1 102 14 is_stmt 0 view .LVU37 135 0040 100061E2 rsb r0, r1, #16 136 .loc 1 102 7 view .LVU38 137 0044 1220A0E1 lsl r2, r2, r0 138 .LVL7: 139 .loc 1 102 7 view .LVU39 140 0048 0228A0E1 lsl r2, r2, #16 103:calypso/uwire.c **** writew(tmp, UWIRE_REG(REG_DATA)); 141 .loc 1 103 3 view .LVU40 142 004c 88009FE5 ldr r0, .L31 102:calypso/uwire.c **** tmp <<= 16 - bitlen; /* align to MSB */ 143 .loc 1 102 7 view .LVU41 144 0050 2228A0E1 lsr r2, r2, #16 145 .LVL8: 146 .loc 1 103 3 is_stmt 1 view .LVU42 147 0054 BF2F40E1 strh r2, [r0, #-255] @ movhi 104:calypso/uwire.c **** printd(", data_out=0x%04hx", tmp); 148 .loc 1 104 36 view .LVU43 105:calypso/uwire.c **** } 106:calypso/uwire.c **** 107:calypso/uwire.c **** tmp = (dout ? UWIRE_CSR_BITS_WR(bitlen) : 0) | 149 .loc 1 107 2 view .LVU44 150 .loc 1 107 16 is_stmt 0 view .LVU45 151 0058 812AA0E1 lsl r2, r1, #21 152 .LVL9: 153 .loc 1 107 16 view .LVU46 154 005c 4228A0E1 asr r2, r2, #16 155 .LVL10: 156 .L10: 157 .loc 1 107 47 discriminator 4 view .LVU47 158 0060 000053E3 cmp r3, #0 159 0064 0100A011 movne r0, r1 160 0068 0000A003 moveq r0, #0 161 006c 002082E1 orr r2, r2, r0 108:calypso/uwire.c **** (din ? UWIRE_CSR_BITS_RD(bitlen) : 0) | 162 .loc 1 108 42 discriminator 4 view .LVU48 163 0070 022A82E3 orr r2, r2, #8192 109:calypso/uwire.c **** UWIRE_CSR_START; 110:calypso/uwire.c **** writew(tmp, UWIRE_REG(REG_CSR)); 164 .loc 1 110 2 discriminator 4 view .LVU49 165 0074 60009FE5 ldr r0, .L31 107:calypso/uwire.c **** (din ? UWIRE_CSR_BITS_RD(bitlen) : 0) | 166 .loc 1 107 6 discriminator 4 view .LVU50 167 0078 0228A0E1 lsl r2, r2, #16 168 007c 2228A0E1 lsr r2, r2, #16 169 .LVL11: 170 .loc 1 110 2 is_stmt 1 discriminator 4 view .LVU51 171 0080 BD2F40E1 strh r2, [r0, #-253] @ movhi 111:calypso/uwire.c **** 112:calypso/uwire.c **** _uwire_wait(UWIRE_CSR_CSRB, 0); 172 .loc 1 112 2 discriminator 4 view .LVU52 173 .LVL12: 174 .LBB16: 175 .LBI16: 65:calypso/uwire.c **** { 176 .loc 1 65 20 discriminator 4 view .LVU53 177 .LBB17: 67:calypso/uwire.c **** } 178 .loc 1 67 2 discriminator 4 view .LVU54 179 .L14: 67:calypso/uwire.c **** } 180 .loc 1 67 44 view .LVU55 67:calypso/uwire.c **** } 181 .loc 1 67 10 is_stmt 0 view .LVU56 182 0084 BD2F50E1 ldrh r2, [r0, #-253] 67:calypso/uwire.c **** } 183 .loc 1 67 44 view .LVU57 184 0088 010912E3 tst r2, #16384 185 008c FCFFFF1A bne .L14 186 .LVL13: 67:calypso/uwire.c **** } 187 .loc 1 67 44 view .LVU58 188 .LBE17: 189 .LBE16: 113:calypso/uwire.c **** 114:calypso/uwire.c **** if (din) { 190 .loc 1 114 2 is_stmt 1 discriminator 8 view .LVU59 191 .loc 1 114 5 is_stmt 0 discriminator 8 view .LVU60 192 0090 000053E3 cmp r3, #0 193 0094 0700000A beq .L15 194 .LBB18: 195 .LBB19: 67:calypso/uwire.c **** } 196 .loc 1 67 10 view .LVU61 197 0098 3C209FE5 ldr r2, .L31 198 .LVL14: 199 .L16: 67:calypso/uwire.c **** } 200 .loc 1 67 44 is_stmt 1 view .LVU62 67:calypso/uwire.c **** } 201 .loc 1 67 10 is_stmt 0 view .LVU63 202 009c BD0F52E1 ldrh r0, [r2, #-253] 67:calypso/uwire.c **** } 203 .loc 1 67 44 view .LVU64 204 00a0 020910E3 tst r0, #32768 205 00a4 FCFFFF0A beq .L16 206 .LBE19: 207 .LBE18: 115:calypso/uwire.c **** _uwire_wait(UWIRE_CSR_RDRB, UWIRE_CSR_RDRB); 116:calypso/uwire.c **** 117:calypso/uwire.c **** tmp = readw(UWIRE_REG(REG_DATA)); 208 .loc 1 117 3 is_stmt 1 view .LVU65 209 .loc 1 117 7 is_stmt 0 view .LVU66 210 00a8 BF2F52E1 ldrh r2, [r2, #-255] 211 .LVL15: 118:calypso/uwire.c **** printd(", data_in=0x%08x", tmp); 212 .loc 1 118 34 is_stmt 1 view .LVU67 119:calypso/uwire.c **** 120:calypso/uwire.c **** if (bitlen <= 8) 213 .loc 1 120 3 view .LVU68 214 .loc 1 120 6 is_stmt 0 view .LVU69 215 00ac 080051E3 cmp r1, #8 121:calypso/uwire.c **** *(uint8_t *)din = tmp & 0xff; 216 .loc 1 121 4 is_stmt 1 view .LVU70 217 .loc 1 121 20 is_stmt 0 view .LVU71 218 00b0 0020C3D5 strble r2, [r3] 122:calypso/uwire.c **** else if (bitlen <= 16) 219 .loc 1 122 8 is_stmt 1 view .LVU72 123:calypso/uwire.c **** *(uint16_t *)din = tmp & 0xffff; 220 .loc 1 123 4 view .LVU73 221 .loc 1 123 21 is_stmt 0 view .LVU74 222 00b4 B020C3C1 strhgt r2, [r3] @ movhi 223 .LVL16: 224 .L15: 124:calypso/uwire.c **** } 125:calypso/uwire.c **** /* unselect the chip */ 126:calypso/uwire.c **** writew(UWIRE_CSR_IDX(0) | 0, UWIRE_REG(REG_CSR)); 225 .loc 1 126 2 is_stmt 1 view .LVU75 226 00b8 0020A0E3 mov r2, #0 227 00bc 18309FE5 ldr r3, .L31 228 .LVL17: 229 .loc 1 126 2 is_stmt 0 view .LVU76 230 00c0 BD2F43E1 strh r2, [r3, #-253] @ movhi 127:calypso/uwire.c **** _uwire_wait(UWIRE_CSR_CSRB, 0); 231 .loc 1 127 2 is_stmt 1 view .LVU77 232 .LVL18: 233 .LBB20: 234 .LBI20: 65:calypso/uwire.c **** { 235 .loc 1 65 20 view .LVU78 236 .LBB21: 67:calypso/uwire.c **** } 237 .loc 1 67 2 view .LVU79 238 .L18: 67:calypso/uwire.c **** } 239 .loc 1 67 44 view .LVU80 67:calypso/uwire.c **** } 240 .loc 1 67 10 is_stmt 0 view .LVU81 241 00c4 BD0F53E1 ldrh r0, [r3, #-253] 67:calypso/uwire.c **** } 242 .loc 1 67 44 view .LVU82 243 00c8 010910E2 ands r0, r0, #16384 244 00cc FCFFFF1A bne .L18 245 00d0 1EFF2FE1 bx lr 246 .LVL19: 247 .L20: 67:calypso/uwire.c **** } 248 .loc 1 67 44 view .LVU83 249 .LBE21: 250 .LBE20: 85:calypso/uwire.c **** if (cs < 0 || cs > 4) 251 .loc 1 85 10 view .LVU84 252 00d4 0000E0E3 mvn r0, #0 253 .LVL20: 128:calypso/uwire.c **** 129:calypso/uwire.c **** printd(")\n"); 130:calypso/uwire.c **** 131:calypso/uwire.c **** return 0; 132:calypso/uwire.c **** } 254 .loc 1 132 1 view .LVU85 255 00d8 1EFF2FE1 bx lr 256 .L32: 257 .align 2 258 .L31: 259 00dc FF40FEFF .word -114433 260 .cfi_endproc 261 .LFE2: 263 .text 264 .Letext0: 265 .file 2 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h" DEFINED SYMBOLS *ABS*:00000000 uwire.c /tmp/ccEw3F6P.s:19 .text.uwire_init:00000000 $a /tmp/ccEw3F6P.s:24 .text.uwire_init:00000000 uwire_init /tmp/ccEw3F6P.s:60 .text.uwire_init:0000002c $d /tmp/ccEw3F6P.s:67 .text.uwire_xfer:00000000 $a /tmp/ccEw3F6P.s:72 .text.uwire_xfer:00000000 uwire_xfer /tmp/ccEw3F6P.s:259 .text.uwire_xfer:000000dc $d NO UNDEFINED SYMBOLS