1 # 0 "lib/clearbit.S" 2 # 0 "" 3 # 0 "" 4 # 1 "lib/clearbit.S" 1 /* 2 * linux/arch/arm/lib/clearbit.S 3 * 4 * Copyright (C) 1995-1996 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #include 1 #ifndef __ASM_LINKAGE_H 11 #include 1 /* 2 * linux/include/asm-arm/assembler.h 3 * 4 * Copyright (C) 1996-2000 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This file contains arm architecture specific defines 11 * for the different processors. 12 * 13 * Do not include any C declarations in this file - it is included by 14 * assembler source. 15 */ 16 #ifndef __ASSEMBLY__ 17 #error "Only include this from assembly code" 18 #endif 19 20 #include 1 /* 21 22 /* 23 * Endian independent macros for shifting bytes within registers. 24 */ 25 #ifndef __ARMEB__ 26 #define pull lsr 27 #define push lsl 28 #define get_byte_0 lsl #0 29 #define get_byte_1 lsr #8 30 #define get_byte_2 lsr #16 31 #define get_byte_3 lsr #24 32 #define put_byte_0 lsl #0 33 #define put_byte_1 lsl #8 34 #define put_byte_2 lsl #16 35 #define put_byte_3 lsl #24 36 #else 37 #define pull lsl 38 #define push lsr 39 #define get_byte_0 lsr #24 40 #define get_byte_1 lsr #16 41 #define get_byte_2 lsr #8 42 #define get_byte_3 lsl #0 43 #define put_byte_0 lsl #24 44 #define put_byte_1 lsl #16 45 #define put_byte_2 lsl #8 46 #define put_byte_3 lsl #0 47 #endif 48 49 #define PLD(code...) 50 51 #define MODE_USR USR_MODE 52 #define MODE_FIQ FIQ_MODE 53 #define MODE_IRQ IRQ_MODE 54 #define MODE_SVC SVC_MODE 55 56 #define DEFAULT_FIQ MODE_FIQ 57 58 /* 59 * LOADREGS - ldm with PC in register list (eg, ldmfd sp!, {pc}) 60 */ 61 #ifdef __STDC__ 62 #define LOADREGS(cond, base, reglist...)\ 63 ldm##cond base,reglist 64 #else 65 #define LOADREGS(cond, base, reglist...)\ 66 ldm/**/cond base,reglist 67 #endif 68 69 /* 70 * Build a return instruction for this processor type. 71 */ 72 #define RETINSTR(instr, regs...)\ 73 instr regs 74 75 /* 76 * Enable and disable interrupts 77 */ 78 .macro disable_irq 79 msr cpsr_c, #PSR_I_BIT | SVC_MODE 80 .endm 81 82 .macro enable_irq 83 msr cpsr_c, #SVC_MODE 84 .endm 85 86 /* 87 * Save the current IRQ state and disable IRQs. Note that this macro 88 * assumes FIQs are enabled, and that the processor is in SVC mode. 89 */ 90 .macro save_and_disable_irqs, oldcpsr 91 mrs \oldcpsr, cpsr 92 disable_irq 93 .endm 94 95 /* 96 * Restore interrupt state previously stored in a register. We don't 97 * guarantee that this will preserve the flags. 98 */ 99 .macro restore_irqs, oldcpsr 100 msr cpsr_c, \oldcpsr 101 .endm 102 103 /* 104 * These two are used to save LR/restore PC over a user-based access. 105 * The old 26-bit architecture requires that we do. On 32-bit 106 * architecture, we can safely ignore this requirement. 107 */ 108 .macro save_lr 109 .endm 110 111 .macro restore_pc 112 mov pc, lr 113 .endm 114 ... 12 #include "bitops.h" 1 .macro bitop, instr 2 and r2, r0, #7 3 mov r3, #1 4 mov r3, r3, lsl r2 5 save_and_disable_irqs ip 6 ldrb r2, [r1, r0, lsr #3] 7 \instr r2, r2, r3 8 strb r2, [r1, r0, lsr #3] 9 restore_irqs ip 10 mov pc, lr 11 .endm 12 13 /** 14 * testop - implement a test_and_xxx_bit operation. 15 * @instr: operational instruction 16 * @store: store instruction 17 * 18 * Note: we can trivially conditionalise the store instruction 19 * to avoid dirting the data cache. 20 */ 21 .macro testop, instr, store 22 add r1, r1, r0, lsr #3 23 and r3, r0, #7 24 mov r0, #1 25 save_and_disable_irqs ip 26 ldrb r2, [r1] 27 tst r2, r0, lsl r3 28 \instr r2, r2, r0, lsl r3 29 \store r2, [r1] 30 restore_irqs ip 31 moveq r0, #0 32 mov pc, lr 33 .endm 34 ... 13 .text 14 15 /* 16 * Purpose : Function to clear a bit 17 * Prototype: int clear_bit(int bit, void *addr) 18 */ 19 ENTRY(_clear_bit_be) 20 0000 180020E2 eor r0, r0, #0x18 @ big endian byte ordering 21 ENTRY(_clear_bit_le) 22 0004 072000E2 bitop bic 22 0130A0E3 22 1332A0E1 22 00C00FE1 22 93F021E3 DEFINED SYMBOLS lib/clearbit.S:19 .text:00000000 _clear_bit_be lib/clearbit.S:19 .text:00000000 $a lib/clearbit.S:21 .text:00000004 _clear_bit_le NO UNDEFINED SYMBOLS