trial-ttcn3_bts_tests:sysmo 92

Took 39 min

All Failed Tests

Name	Age	Duration
TC_chan_act_a52	2	19 sec
TC_chan_act_a53	25	20 sec
TC_chan_act_stress	2	32 sec
TC_chopped_ipa_payload	1	1 min 0 sec
TC_deact_sacch	25	50 sec
TC_encr_cmd_a52	3	22 sec
TC_encr_cmd_a53	25	20 sec
TC_ho_rach	25	18 sec
TC_meas_res_sign_sdcch4	25	16 sec
TC_meas_res_sign_sdcch8	25	17 sec
TC_meas_res_sign_tchf	25	8.9 sec
TC_meas_res_sign_tchh	25	16 sec
TC_meas_res_sign_tchh_toa256	25	16 sec
TC_paging_tmsi_200percent	2	48 sec
TC_paging_tmsi_80percent	2	43 sec
TC_rach_load_count	25	2 sec
TC_rach_load_idle_below_thresh	25	2 sec
TC_rach_load_idle_thresh0	25	2 sec
TC_rach_max_ta	25	22 sec
TC_rll_est_req_ACCH_3	25	21 sec
TC_rll_rel_ind_ACCH_0	25	21 sec
TC_rll_rel_ind_ACCH_3	25	24 sec
TC_rll_rel_req	25	30 sec
TC_rll_unit_data_req_ACCH	25	24 sec
TC_rsl_chan_initial_ms_pwr	25	17 sec
TC_rsl_chan_initial_ta	25	18 sec
TC_rsl_modify_encr	25	22 sec
TC_rsl_ms_pwr_ctrl	2	1 min 20 sec
TC_rsl_ms_pwr_dyn_active	25	21 sec
TC_rsl_ms_pwr_dyn_active2	25	12 sec
TC_rsl_ms_pwr_dyn_ass_updown	25	12 sec
TC_rsl_ms_pwr_dyn_down	25	12 sec
TC_rsl_ms_pwr_dyn_max	25	12 sec
TC_rsl_ms_pwr_dyn_up	25	12 sec
TC_sacch_chan_act	25	36 sec
TC_sacch_chan_act_ho_async	25	21 sec
TC_sacch_chan_act_ho_sync	25	13 sec
TC_sacch_filling	25	32 sec
TC_sacch_info_mod	25	32 sec
TC_sacch_multi	25	50 sec
TC_sacch_multi_chg	25	59 sec
TC_si_sched_13	2	31 sec
TC_si_sched_13_2bis_2ter_2quater	25	38 sec
TC_si_sched_2bis	2	28 sec
TC_si_sched_2quater	25	45 sec
TC_tch_sign_l2_fill_frame	25	28 sec
TC_tch_sign_l2_fill_frame_dtxd	25	24 sec
TC_tx_power_ramp_adm_state_change	25	16 sec
TC_tx_power_start_ramp_down_bcch	25	16 sec
TC_tx_power_start_ramp_up_bcch	25	15 sec

All Tests

Class	Failed	Skipped	Passed	Total	Duration
ttcn3_bts_tests	50+50	0	42+42	92 +92	39 min