trial-ttcn3_bts_tests:trx 127

108

Took 26 min

All Failed Tests

Name	Age	Duration
TC_chan_act_a51	2	12 sec
TC_chan_act_a52	2	12 sec
TC_chan_act_a53	25	12 sec
TC_chan_act_react	2	12 sec
TC_chan_act_stress	2	6.3 sec
TC_chan_act_wrong_nr	2	12 sec
TC_chan_deact_not_active	2	12 sec
TC_conn_fail_crit	3	12 sec
TC_deact_sacch	25	12 sec
TC_dyn_ipa_pdch_act_deact	2	12 sec
TC_dyn_ipa_pdch_act_tchf_act_nack	2	12 sec
TC_dyn_ipa_pdch_tchf_act	2	12 sec
TC_dyn_ipa_pdch_tchf_act_pdch_act_nack	2	12 sec
TC_dyn_osmo_pdch_act_deact	2	12 sec
TC_dyn_osmo_pdch_double_act	2	12 sec
TC_dyn_osmo_pdch_tchf_act	2	12 sec
TC_dyn_osmo_pdch_tchh_act	2	12 sec
TC_dyn_osmo_pdch_unsol_deact	2	8.6 sec
TC_encr_cmd_a51	2	12 sec
TC_encr_cmd_a52	3	12 sec
TC_encr_cmd_a53	25	12 sec
TC_err_rep_wrong_mdisc	2	12 sec
TC_err_rep_wrong_msg_type	2	12 sec
TC_err_rep_wrong_sequence	2	12 sec
TC_ho_rach	25	12 sec
TC_ipa_crcx_mdcx_dlcx_not_active	2	12 sec
TC_ipa_crcx_mdcx_mdcx_dlcx_not_active	2	12 sec
TC_ipa_crcx_sdcch_not_active	2	12 sec
TC_ipa_crcx_twice_not_active	2	12 sec
TC_ipa_dlcx_not_active	2	12 sec
TC_meas_res_sign_sdcch4	25	12 sec
TC_meas_res_sign_sdcch8	25	12 sec
TC_meas_res_sign_tchf	25	8.5 sec
TC_meas_res_sign_tchh	25	12 sec
TC_meas_res_sign_tchh_toa256	25	12 sec
TC_paging_imsi_200percent	2	12 sec
TC_paging_imsi_80percent	2	12 sec
TC_paging_tmsi_200percent	2	12 sec
TC_paging_tmsi_80percent	2	12 sec
TC_pcu_data_ind_lqual_cb	7	12 sec
TC_pcu_data_req_agch	2	12 sec
TC_pcu_data_req_imm_ass_pch	2	12 sec
TC_pcu_data_req_pch	2	12 sec
TC_pcu_ext_rach_content	7	12 sec
TC_pcu_oml_alert	7	13 sec
TC_pcu_ptcch	7	12 sec
TC_pcu_rach_content	2	12 sec
TC_pcu_rr_suspend	2	12 sec
TC_pcu_socket_connect_si3gprs	3	12 sec
TC_pcu_socket_connect_si4gprs	2	12 sec
TC_pcu_socket_disconnect_nosi3gprs	2	12 sec
TC_pcu_socket_disconnect_nosi4gprs	2	12 sec
TC_pcu_socket_noconnect_nosi3gprs	2	9.1 sec
TC_pcu_socket_noconnect_nosi4gprs	2	2.8 sec
TC_pcu_socket_nsvc_ipv4	7	2 sec
TC_pcu_socket_nsvc_ipv6	7	2 sec
TC_pcu_socket_verify_info_ind	1	12 sec
TC_rach_content	2	12 sec
TC_rach_content_emerg	2	12 sec
TC_rach_count	2	12 sec
TC_rach_load_count	25	2 sec
TC_rach_load_idle_below_thresh	25	2 sec
TC_rach_load_idle_thresh0	25	2 sec
TC_rach_max_ta	25	12 sec
TC_rll_est_ind	2	12 sec
TC_rll_est_req_ACCH_3	25	12 sec
TC_rll_est_req_DCCH_3	2	12 sec
TC_rll_rel_ind_ACCH_0	25	12 sec
TC_rll_rel_ind_ACCH_3	25	12 sec
TC_rll_rel_ind_DCCH_0	2	12 sec
TC_rll_rel_ind_DCCH_3	2	12 sec
TC_rll_rel_req	25	12 sec
TC_rll_unit_data_ind_ACCH	3	12 sec
TC_rll_unit_data_ind_DCCH	2	12 sec
TC_rll_unit_data_req_ACCH	25	12 sec
TC_rll_unit_data_req_DCCH	2	12 sec
TC_rsl_bs_pwr_static_ass	2	12 sec
TC_rsl_bs_pwr_static_power_control	2	12 sec
TC_rsl_chan_initial_ms_pwr	25	12 sec
TC_rsl_chan_initial_ta	25	12 sec
TC_rsl_modify_encr	25	12 sec
TC_rsl_ms_pwr_ctrl	2	12 sec
TC_rsl_ms_pwr_dyn_active	25	12 sec
TC_rsl_ms_pwr_dyn_active2	25	12 sec
TC_rsl_ms_pwr_dyn_ass_updown	25	12 sec
TC_rsl_ms_pwr_dyn_down	25	12 sec
TC_rsl_ms_pwr_dyn_max	25	12 sec
TC_rsl_ms_pwr_dyn_up	25	12 sec
TC_sacch_chan_act	25	6.7 sec
TC_sacch_chan_act_ho_async	25	12 sec
TC_sacch_chan_act_ho_sync	25	12 sec
TC_sacch_filling	25	12 sec
TC_sacch_info_mod	25	12 sec
TC_sacch_multi	25	12 sec
TC_sacch_multi_chg	25	12 sec
TC_si_sched_1	2	12 sec
TC_si_sched_13	2	12 sec
TC_si_sched_13_2bis_2ter_2quater	25	12 sec
TC_si_sched_2bis	2	12 sec
TC_si_sched_2quater	25	12 sec
TC_si_sched_2ter	2	12 sec
TC_si_sched_2ter_2bis	2	12 sec
TC_si_sched_default	2	12 sec
TC_tch_sign_l2_fill_frame	25	10 sec
TC_tch_sign_l2_fill_frame_dtxd	25	12 sec
TC_tx_power_ramp_adm_state_change	25	12 sec
TC_tx_power_start_ramp_down_bcch	25	12 sec
TC_tx_power_start_ramp_up_bcch	25	12 sec

All Tests

Class	Failed	Skipped	Passed	Total	Duration
ttcn3_bts_tests	108+108	0	19+19	127 +127	26 min